drivers/tty/serial/samsung.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7 */
   8
   9 /* Hote on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22 */
  23
  24 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  25 #define SUPPORT_SYSRQ
  26 #endif
  27
  28 #include <linux/dmaengine.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/module.h>
  32 #include <linux/ioport.h>
  33 #include <linux/io.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/init.h>
  36 #include <linux/sysrq.h>
  37 #include <linux/console.h>
  38 #include <linux/tty.h>
  39 #include <linux/tty_flip.h>
  40 #include <linux/serial_core.h>
  41 #include <linux/serial.h>
  42 #include <linux/serial_s3c.h>
  43 #include <linux/delay.h>
  44 #include <linux/clk.h>
  45 #include <linux/cpufreq.h>
  46 #include <linux/of.h>
  47
  48 #include <asm/irq.h>
  49
  50 #include "samsung.h"
  51
  52 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  53         !defined(MODULE)
  54
  55 extern void printascii(const char *);
  56
  57 __printf(1, 2)
  58 static void dbg(const char *fmt, ...)
  59 {
  60         va_list va;
  61         char buff[256];
  62
  63         va_start(va, fmt);
  64         vscnprintf(buff, sizeof(buff), fmt, va);
  65         va_end(va);
  66
  67         printascii(buff);
  68 }
  69
  70 #else
  71 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  72 #endif
  73
  74 /* UART name and device definitions */
  75
  76 #define S3C24XX_SERIAL_NAME     "ttySAC"
  77 #define S3C24XX_SERIAL_MAJOR    204
  78 #define S3C24XX_SERIAL_MINOR    64
  79
  80 #define S3C24XX_TX_PIO                  1
  81 #define S3C24XX_TX_DMA                  2
  82 #define S3C24XX_RX_PIO                  1
  83 #define S3C24XX_RX_DMA                  2
  84 /* macros to change one thing to another */
  85
  86 #define tx_enabled(port) ((port)->unused[0])
  87 #define rx_enabled(port) ((port)->unused[1])
  88
  89 /* flag to ignore all characters coming in */
  90 #define RXSTAT_DUMMY_READ (0x10000000)
  91
  92 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  93 {
  94         return container_of(port, struct s3c24xx_uart_port, port);
  95 }
  96
  97 /* translate a port to the device name */
  98
  99 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 100 {
 101         return to_platform_device(port->dev)->name;
 102 }
 103
 104 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 105 {
 106         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 107 }
 108
 109 /*
 110  * s3c64xx and later SoC's include the interrupt mask and status registers in
 111  * the controller itself, unlike the s3c24xx SoC's which have these registers
 112  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 113  */
 114 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 115 {
 116         return to_ourport(port)->info->type == PORT_S3C6400;
 117 }
 118
 119 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 120 {
 121         unsigned long flags;
 122         unsigned int ucon, ufcon;
 123         int count = 10000;
 124
 125         spin_lock_irqsave(&port->lock, flags);
 126
 127         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 128                 udelay(100);
 129
 130         ufcon = rd_regl(port, S3C2410_UFCON);
 131         ufcon |= S3C2410_UFCON_RESETRX;
 132         wr_regl(port, S3C2410_UFCON, ufcon);
 133
 134         ucon = rd_regl(port, S3C2410_UCON);
 135         ucon |= S3C2410_UCON_RXIRQMODE;
 136         wr_regl(port, S3C2410_UCON, ucon);
 137
 138         rx_enabled(port) = 1;
 139         spin_unlock_irqrestore(&port->lock, flags);
 140 }
 141
 142 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 143 {
 144         unsigned long flags;
 145         unsigned int ucon;
 146
 147         spin_lock_irqsave(&port->lock, flags);
 148
 149         ucon = rd_regl(port, S3C2410_UCON);
 150         ucon &= ~S3C2410_UCON_RXIRQMODE;
 151         wr_regl(port, S3C2410_UCON, ucon);
 152
 153         rx_enabled(port) = 0;
 154         spin_unlock_irqrestore(&port->lock, flags);
 155 }
 156
 157 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 158 {
 159         struct s3c24xx_uart_port *ourport = to_ourport(port);
 160         struct s3c24xx_uart_dma *dma = ourport->dma;
 161         struct circ_buf *xmit = &port->state->xmit;
 162         struct dma_tx_state state;
 163         int count;
 164
 165         if (!tx_enabled(port))
 166                 return;
 167
 168         if (s3c24xx_serial_has_interrupt_mask(port))
 169                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 170         else
 171                 disable_irq_nosync(ourport->tx_irq);
 172
 173         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 174                 dmaengine_pause(dma->tx_chan);
 175                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 176                 dmaengine_terminate_all(dma->tx_chan);
 177                 dma_sync_single_for_cpu(ourport->port.dev,
 178                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 179                 async_tx_ack(dma->tx_desc);
 180                 count = dma->tx_bytes_requested - state.residue;
 181                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 182                 port->icount.tx += count;
 183         }
 184
 185         tx_enabled(port) = 0;
 186         ourport->tx_in_progress = 0;
 187
 188         if (port->flags & UPF_CONS_FLOW)
 189                 s3c24xx_serial_rx_enable(port);
 190
 191         ourport->tx_mode = 0;
 192 }
 193
 194 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 195
 196 static void s3c24xx_serial_tx_dma_complete(void *args)
 197 {
 198         struct s3c24xx_uart_port *ourport = args;
 199         struct uart_port *port = &ourport->port;
 200         struct circ_buf *xmit = &port->state->xmit;
 201         struct s3c24xx_uart_dma *dma = ourport->dma;
 202         struct dma_tx_state state;
 203         unsigned long flags;
 204         int count;
 205
 206
 207         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 208         count = dma->tx_bytes_requested - state.residue;
 209         async_tx_ack(dma->tx_desc);
 210
 211         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 212                                 dma->tx_size, DMA_TO_DEVICE);
 213
 214         spin_lock_irqsave(&port->lock, flags);
 215
 216         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 217         port->icount.tx += count;
 218         ourport->tx_in_progress = 0;
 219
 220         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 221                 uart_write_wakeup(port);
 222
 223         s3c24xx_serial_start_next_tx(ourport);
 224         spin_unlock_irqrestore(&port->lock, flags);
 225 }
 226
 227 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 228 {
 229         struct uart_port *port = &ourport->port;
 230         u32 ucon;
 231
 232         /* Mask Tx interrupt */
 233         if (s3c24xx_serial_has_interrupt_mask(port))
 234                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 235         else
 236                 disable_irq_nosync(ourport->tx_irq);
 237
 238         /* Enable tx dma mode */
 239         ucon = rd_regl(port, S3C2410_UCON);
 240         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 241         ucon |= (dma_get_cache_alignment() >= 16) ?
 242                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 243         ucon |= S3C64XX_UCON_TXMODE_DMA;
 244         wr_regl(port,  S3C2410_UCON, ucon);
 245
 246         ourport->tx_mode = S3C24XX_TX_DMA;
 247 }
 248
 249 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 250 {
 251         struct uart_port *port = &ourport->port;
 252         u32 ucon, ufcon;
 253
 254         /* Set ufcon txtrig */
 255         ourport->tx_in_progress = S3C24XX_TX_PIO;
 256         ufcon = rd_regl(port, S3C2410_UFCON);
 257         wr_regl(port,  S3C2410_UFCON, ufcon);
 258
 259         /* Enable tx pio mode */
 260         ucon = rd_regl(port, S3C2410_UCON);
 261         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 262         ucon |= S3C64XX_UCON_TXMODE_CPU;
 263         wr_regl(port,  S3C2410_UCON, ucon);
 264
 265         /* Unmask Tx interrupt */
 266         if (s3c24xx_serial_has_interrupt_mask(port))
 267                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 268                                   S3C64XX_UINTM);
 269         else
 270                 enable_irq(ourport->tx_irq);
 271
 272         ourport->tx_mode = S3C24XX_TX_PIO;
 273 }
 274
 275 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 276 {
 277         if (ourport->tx_mode != S3C24XX_TX_PIO)
 278                 enable_tx_pio(ourport);
 279 }
 280
 281 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 282                                       unsigned int count)
 283 {
 284         struct uart_port *port = &ourport->port;
 285         struct circ_buf *xmit = &port->state->xmit;
 286         struct s3c24xx_uart_dma *dma = ourport->dma;
 287
 288
 289         if (ourport->tx_mode != S3C24XX_TX_DMA)
 290                 enable_tx_dma(ourport);
 291
 292         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 293         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 294
 295         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 296                                 dma->tx_size, DMA_TO_DEVICE);
 297
 298         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 299                                 dma->tx_transfer_addr, dma->tx_size,
 300                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 301         if (!dma->tx_desc) {
 302                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 303                 return -EIO;
 304         }
 305
 306         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 307         dma->tx_desc->callback_param = ourport;
 308         dma->tx_bytes_requested = dma->tx_size;
 309
 310         ourport->tx_in_progress = S3C24XX_TX_DMA;
 311         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 312         dma_async_issue_pending(dma->tx_chan);
 313         return 0;
 314 }
 315
 316 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 317 {
 318         struct uart_port *port = &ourport->port;
 319         struct circ_buf *xmit = &port->state->xmit;
 320         unsigned long count;
 321
 322         /* Get data size up to the end of buffer */
 323         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 324
 325         if (!count) {
 326                 s3c24xx_serial_stop_tx(port);
 327                 return;
 328         }
 329
 330         if (!ourport->dma || !ourport->dma->tx_chan ||
 331             count < ourport->min_dma_size ||
 332             xmit->tail & (dma_get_cache_alignment() - 1))
 333                 s3c24xx_serial_start_tx_pio(ourport);
 334         else
 335                 s3c24xx_serial_start_tx_dma(ourport, count);
 336 }
 337
 338 static void s3c24xx_serial_start_tx(struct uart_port *port)
 339 {
 340         struct s3c24xx_uart_port *ourport = to_ourport(port);
 341         struct circ_buf *xmit = &port->state->xmit;
 342
 343         if (!tx_enabled(port)) {
 344                 if (port->flags & UPF_CONS_FLOW)
 345                         s3c24xx_serial_rx_disable(port);
 346
 347                 tx_enabled(port) = 1;
 348                 if (!ourport->dma || !ourport->dma->tx_chan)
 349                         s3c24xx_serial_start_tx_pio(ourport);
 350         }
 351
 352         if (ourport->dma && ourport->dma->tx_chan) {
 353                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 354                         s3c24xx_serial_start_next_tx(ourport);
 355         }
 356 }
 357
 358 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 359                 struct tty_port *tty, int count)
 360 {
 361         struct s3c24xx_uart_dma *dma = ourport->dma;
 362         int copied;
 363
 364         if (!count)
 365                 return;
 366
 367         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 368                                 dma->rx_size, DMA_FROM_DEVICE);
 369
 370         ourport->port.icount.rx += count;
 371         if (!tty) {
 372                 dev_err(ourport->port.dev, "No tty port\n");
 373                 return;
 374         }
 375         copied = tty_insert_flip_string(tty,
 376                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 377         if (copied != count) {
 378                 WARN_ON(1);
 379                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 380         }
 381 }
 382
 383 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 384 {
 385         struct s3c24xx_uart_port *ourport = to_ourport(port);
 386         struct s3c24xx_uart_dma *dma = ourport->dma;
 387         struct tty_port *t = &port->state->port;
 388         struct dma_tx_state state;
 389         enum dma_status dma_status;
 390         unsigned int received;
 391
 392         if (rx_enabled(port)) {
 393                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 394                 if (s3c24xx_serial_has_interrupt_mask(port))
 395                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 396                                         S3C64XX_UINTM);
 397                 else
 398                         disable_irq_nosync(ourport->rx_irq);
 399                 rx_enabled(port) = 0;
 400         }
 401         if (dma && dma->rx_chan) {
 402                 dmaengine_pause(dma->tx_chan);
 403                 dma_status = dmaengine_tx_status(dma->rx_chan,
 404                                 dma->rx_cookie, &state);
 405                 if (dma_status == DMA_IN_PROGRESS ||
 406                         dma_status == DMA_PAUSED) {
 407                         received = dma->rx_bytes_requested - state.residue;
 408                         dmaengine_terminate_all(dma->rx_chan);
 409                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 410                 }
 411         }
 412 }
 413
 414 static inline struct s3c24xx_uart_info
 415         *s3c24xx_port_to_info(struct uart_port *port)
 416 {
 417         return to_ourport(port)->info;
 418 }
 419
 420 static inline struct s3c2410_uartcfg
 421         *s3c24xx_port_to_cfg(struct uart_port *port)
 422 {
 423         struct s3c24xx_uart_port *ourport;
 424
 425         if (port->dev == NULL)
 426                 return NULL;
 427
 428         ourport = container_of(port, struct s3c24xx_uart_port, port);
 429         return ourport->cfg;
 430 }
 431
 432 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 433                                      unsigned long ufstat)
 434 {
 435         struct s3c24xx_uart_info *info = ourport->info;
 436
 437         if (ufstat & info->rx_fifofull)
 438                 return ourport->port.fifosize;
 439
 440         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 441 }
 442
 443 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 444 static void s3c24xx_serial_rx_dma_complete(void *args)
 445 {
 446         struct s3c24xx_uart_port *ourport = args;
 447         struct uart_port *port = &ourport->port;
 448
 449         struct s3c24xx_uart_dma *dma = ourport->dma;
 450         struct tty_port *t = &port->state->port;
 451         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 452
 453         struct dma_tx_state state;
 454         unsigned long flags;
 455         int received;
 456
 457         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 458         received  = dma->rx_bytes_requested - state.residue;
 459         async_tx_ack(dma->rx_desc);
 460
 461         spin_lock_irqsave(&port->lock, flags);
 462
 463         if (received)
 464                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 465
 466         if (tty) {
 467                 tty_flip_buffer_push(t);
 468                 tty_kref_put(tty);
 469         }
 470
 471         s3c64xx_start_rx_dma(ourport);
 472
 473         spin_unlock_irqrestore(&port->lock, flags);
 474 }
 475
 476 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 477 {
 478         struct s3c24xx_uart_dma *dma = ourport->dma;
 479
 480         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 481                                 dma->rx_size, DMA_FROM_DEVICE);
 482
 483         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 484                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 485                                 DMA_PREP_INTERRUPT);
 486         if (!dma->rx_desc) {
 487                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 488                 return;
 489         }
 490
 491         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 492         dma->rx_desc->callback_param = ourport;
 493         dma->rx_bytes_requested = dma->rx_size;
 494
 495         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 496         dma_async_issue_pending(dma->rx_chan);
 497 }
 498
 499 /* ? - where has parity gone?? */
 500 #define S3C2410_UERSTAT_PARITY (0x1000)
 501
 502 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 503 {
 504         struct uart_port *port = &ourport->port;
 505         unsigned int ucon;
 506
 507         /* set Rx mode to DMA mode */
 508         ucon = rd_regl(port, S3C2410_UCON);
 509         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 510                         S3C64XX_UCON_TIMEOUT_MASK |
 511                         S3C64XX_UCON_EMPTYINT_EN |
 512                         S3C64XX_UCON_DMASUS_EN |
 513                         S3C64XX_UCON_TIMEOUT_EN |
 514                         S3C64XX_UCON_RXMODE_MASK);
 515         ucon |= S3C64XX_UCON_RXBURST_16 |
 516                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 517                         S3C64XX_UCON_EMPTYINT_EN |
 518                         S3C64XX_UCON_TIMEOUT_EN |
 519                         S3C64XX_UCON_RXMODE_DMA;
 520         wr_regl(port, S3C2410_UCON, ucon);
 521
 522         ourport->rx_mode = S3C24XX_RX_DMA;
 523 }
 524
 525 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 526 {
 527         struct uart_port *port = &ourport->port;
 528         unsigned int ucon;
 529
 530         /* set Rx mode to DMA mode */
 531         ucon = rd_regl(port, S3C2410_UCON);
 532         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 533                         S3C64XX_UCON_EMPTYINT_EN |
 534                         S3C64XX_UCON_DMASUS_EN |
 535                         S3C64XX_UCON_TIMEOUT_EN |
 536                         S3C64XX_UCON_RXMODE_MASK);
 537         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 538                         S3C64XX_UCON_TIMEOUT_EN |
 539                         S3C64XX_UCON_RXMODE_CPU;
 540         wr_regl(port, S3C2410_UCON, ucon);
 541
 542         ourport->rx_mode = S3C24XX_RX_PIO;
 543 }
 544
 545 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 546
 547 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 548 {
 549         unsigned int utrstat, ufstat, received;
 550         struct s3c24xx_uart_port *ourport = dev_id;
 551         struct uart_port *port = &ourport->port;
 552         struct s3c24xx_uart_dma *dma = ourport->dma;
 553         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 554         struct tty_port *t = &port->state->port;
 555         unsigned long flags;
 556         struct dma_tx_state state;
 557
 558         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 559         ufstat = rd_regl(port, S3C2410_UFSTAT);
 560
 561         spin_lock_irqsave(&port->lock, flags);
 562
 563         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 564                 s3c64xx_start_rx_dma(ourport);
 565                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 566                         enable_rx_dma(ourport);
 567                 goto finish;
 568         }
 569
 570         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 571                 dmaengine_pause(dma->rx_chan);
 572                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 573                 dmaengine_terminate_all(dma->rx_chan);
 574                 received = dma->rx_bytes_requested - state.residue;
 575                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 576
 577                 enable_rx_pio(ourport);
 578         }
 579
 580         s3c24xx_serial_rx_drain_fifo(ourport);
 581
 582         if (tty) {
 583                 tty_flip_buffer_push(t);
 584                 tty_kref_put(tty);
 585         }
 586
 587         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 588
 589 finish:
 590         spin_unlock_irqrestore(&port->lock, flags);
 591
 592         return IRQ_HANDLED;
 593 }
 594
 595 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 596 {
 597         struct uart_port *port = &ourport->port;
 598         unsigned int ufcon, ch, flag, ufstat, uerstat;
 599         unsigned int fifocnt = 0;
 600         int max_count = port->fifosize;
 601
 602         while (max_count-- > 0) {
 603                 /*
 604                  * Receive all characters known to be in FIFO
 605                  * before reading FIFO level again
 606                  */
 607                 if (fifocnt == 0) {
 608                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 609                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 610                         if (fifocnt == 0)
 611                                 break;
 612                 }
 613                 fifocnt--;
 614
 615                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 616                 ch = rd_regb(port, S3C2410_URXH);
 617
 618                 if (port->flags & UPF_CONS_FLOW) {
 619                         int txe = s3c24xx_serial_txempty_nofifo(port);
 620
 621                         if (rx_enabled(port)) {
 622                                 if (!txe) {
 623                                         rx_enabled(port) = 0;
 624                                         continue;
 625                                 }
 626                         } else {
 627                                 if (txe) {
 628                                         ufcon = rd_regl(port, S3C2410_UFCON);
 629                                         ufcon |= S3C2410_UFCON_RESETRX;
 630                                         wr_regl(port, S3C2410_UFCON, ufcon);
 631                                         rx_enabled(port) = 1;
 632                                         return;
 633                                 }
 634                                 continue;
 635                         }
 636                 }
 637
 638                 /* insert the character into the buffer */
 639
 640                 flag = TTY_NORMAL;
 641                 port->icount.rx++;
 642
 643                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 644                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 645                             ch, uerstat);
 646
 647                         /* check for break */
 648                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 649                                 dbg("break!\n");
 650                                 port->icount.brk++;
 651                                 if (uart_handle_break(port))
 652                                         continue; /* Ignore character */
 653                         }
 654
 655                         if (uerstat & S3C2410_UERSTAT_FRAME)
 656                                 port->icount.frame++;
 657                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 658                                 port->icount.overrun++;
 659
 660                         uerstat &= port->read_status_mask;
 661
 662                         if (uerstat & S3C2410_UERSTAT_BREAK)
 663                                 flag = TTY_BREAK;
 664                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 665                                 flag = TTY_PARITY;
 666                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 667                                             S3C2410_UERSTAT_OVERRUN))
 668                                 flag = TTY_FRAME;
 669                 }
 670
 671                 if (uart_handle_sysrq_char(port, ch))
 672                         continue; /* Ignore character */
 673
 674                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 675                                  ch, flag);
 676         }
 677
 678         tty_flip_buffer_push(&port->state->port);
 679 }
 680
 681 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 682 {
 683         struct s3c24xx_uart_port *ourport = dev_id;
 684         struct uart_port *port = &ourport->port;
 685         unsigned long flags;
 686
 687         spin_lock_irqsave(&port->lock, flags);
 688         s3c24xx_serial_rx_drain_fifo(ourport);
 689         spin_unlock_irqrestore(&port->lock, flags);
 690
 691         return IRQ_HANDLED;
 692 }
 693
 694
 695 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 696 {
 697         struct s3c24xx_uart_port *ourport = dev_id;
 698
 699         if (ourport->dma && ourport->dma->rx_chan)
 700                 return s3c24xx_serial_rx_chars_dma(dev_id);
 701         return s3c24xx_serial_rx_chars_pio(dev_id);
 702 }
 703
 704 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 705 {
 706         struct s3c24xx_uart_port *ourport = id;
 707         struct uart_port *port = &ourport->port;
 708         struct circ_buf *xmit = &port->state->xmit;
 709         unsigned long flags;
 710         int count, dma_count = 0;
 711
 712         spin_lock_irqsave(&port->lock, flags);
 713
 714         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 715
 716         if (ourport->dma && ourport->dma->tx_chan &&
 717             count >= ourport->min_dma_size) {
 718                 int align = dma_get_cache_alignment() -
 719                         (xmit->tail & (dma_get_cache_alignment() - 1));
 720                 if (count-align >= ourport->min_dma_size) {
 721                         dma_count = count-align;
 722                         count = align;
 723                 }
 724         }
 725
 726         if (port->x_char) {
 727                 wr_regb(port, S3C2410_UTXH, port->x_char);
 728                 port->icount.tx++;
 729                 port->x_char = 0;
 730                 goto out;
 731         }
 732
 733         /* if there isn't anything more to transmit, or the uart is now
 734          * stopped, disable the uart and exit
 735         */
 736
 737         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 738                 s3c24xx_serial_stop_tx(port);
 739                 goto out;
 740         }
 741
 742         /* try and drain the buffer... */
 743
 744         if (count > port->fifosize) {
 745                 count = port->fifosize;
 746                 dma_count = 0;
 747         }
 748
 749         while (!uart_circ_empty(xmit) && count > 0) {
 750                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 751                         break;
 752
 753                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 754                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 755                 port->icount.tx++;
 756                 count--;
 757         }
 758
 759         if (!count && dma_count) {
 760                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 761                 goto out;
 762         }
 763
 764         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 765                 uart_write_wakeup(port);
 766
 767         if (uart_circ_empty(xmit))
 768                 s3c24xx_serial_stop_tx(port);
 769
 770 out:
 771         spin_unlock_irqrestore(&port->lock, flags);
 772         return IRQ_HANDLED;
 773 }
 774
 775 /* interrupt handler for s3c64xx and later SoC's.*/
 776 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 777 {
 778         struct s3c24xx_uart_port *ourport = id;
 779         struct uart_port *port = &ourport->port;
 780         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 781         irqreturn_t ret = IRQ_HANDLED;
 782
 783         if (pend & S3C64XX_UINTM_RXD_MSK) {
 784                 ret = s3c24xx_serial_rx_chars(irq, id);
 785                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 786         }
 787         if (pend & S3C64XX_UINTM_TXD_MSK) {
 788                 ret = s3c24xx_serial_tx_chars(irq, id);
 789                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 790         }
 791         return ret;
 792 }
 793
 794 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 795 {
 796         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 797         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 798         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 799
 800         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 801                 if ((ufstat & info->tx_fifomask) != 0 ||
 802                     (ufstat & info->tx_fifofull))
 803                         return 0;
 804
 805                 return 1;
 806         }
 807
 808         return s3c24xx_serial_txempty_nofifo(port);
 809 }
 810
 811 /* no modem control lines */
 812 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 813 {
 814         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 815
 816         if (umstat & S3C2410_UMSTAT_CTS)
 817                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 818         else
 819                 return TIOCM_CAR | TIOCM_DSR;
 820 }
 821
 822 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 823 {
 824         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 825
 826         if (mctrl & TIOCM_RTS)
 827                 umcon |= S3C2410_UMCOM_RTS_LOW;
 828         else
 829                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 830
 831         wr_regl(port, S3C2410_UMCON, umcon);
 832 }
 833
 834 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 835 {
 836         unsigned long flags;
 837         unsigned int ucon;
 838
 839         spin_lock_irqsave(&port->lock, flags);
 840
 841         ucon = rd_regl(port, S3C2410_UCON);
 842
 843         if (break_state)
 844                 ucon |= S3C2410_UCON_SBREAK;
 845         else
 846                 ucon &= ~S3C2410_UCON_SBREAK;
 847
 848         wr_regl(port, S3C2410_UCON, ucon);
 849
 850         spin_unlock_irqrestore(&port->lock, flags);
 851 }
 852
 853 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 854 {
 855         struct s3c24xx_uart_dma *dma = p->dma;
 856         struct dma_slave_caps dma_caps;
 857         const char *reason = NULL;
 858         int ret;
 859
 860         /* Default slave configuration parameters */
 861         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 862         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 863         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 864         dma->rx_conf.src_maxburst       = 1;
 865
 866         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 867         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 868         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 869         dma->tx_conf.dst_maxburst       = 1;
 870
 871         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 872
 873         if (IS_ERR(dma->rx_chan)) {
 874                 reason = "DMA RX channel request failed";
 875                 ret = PTR_ERR(dma->rx_chan);
 876                 goto err_warn;
 877         }
 878
 879         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
 880         if (ret < 0 ||
 881             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
 882                 reason = "insufficient DMA RX engine capabilities";
 883                 ret = -EOPNOTSUPP;
 884                 goto err_release_rx;
 885         }
 886
 887         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 888
 889         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
 890         if (IS_ERR(dma->tx_chan)) {
 891                 reason = "DMA TX channel request failed";
 892                 ret = PTR_ERR(dma->tx_chan);
 893                 goto err_release_rx;
 894         }
 895
 896         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
 897         if (ret < 0 ||
 898             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
 899                 reason = "insufficient DMA TX engine capabilities";
 900                 ret = -EOPNOTSUPP;
 901                 goto err_release_tx;
 902         }
 903
 904         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 905
 906         /* RX buffer */
 907         dma->rx_size = PAGE_SIZE;
 908
 909         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 910         if (!dma->rx_buf) {
 911                 ret = -ENOMEM;
 912                 goto err_release_tx;
 913         }
 914
 915         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
 916                                 dma->rx_size, DMA_FROM_DEVICE);
 917         if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
 918                 reason = "DMA mapping error for RX buffer";
 919                 ret = -EIO;
 920                 goto err_free_rx;
 921         }
 922
 923         /* TX buffer */
 924         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
 925                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 926         if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
 927                 reason = "DMA mapping error for TX buffer";
 928                 ret = -EIO;
 929                 goto err_unmap_rx;
 930         }
 931
 932         return 0;
 933
 934 err_unmap_rx:
 935         dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
 936                          DMA_FROM_DEVICE);
 937 err_free_rx:
 938         kfree(dma->rx_buf);
 939 err_release_tx:
 940         dma_release_channel(dma->tx_chan);
 941 err_release_rx:
 942         dma_release_channel(dma->rx_chan);
 943 err_warn:
 944         if (reason)
 945                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
 946         return ret;
 947 }
 948
 949 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 950 {
 951         struct s3c24xx_uart_dma *dma = p->dma;
 952
 953         if (dma->rx_chan) {
 954                 dmaengine_terminate_all(dma->rx_chan);
 955                 dma_unmap_single(p->port.dev, dma->rx_addr,
 956                                 dma->rx_size, DMA_FROM_DEVICE);
 957                 kfree(dma->rx_buf);
 958                 dma_release_channel(dma->rx_chan);
 959                 dma->rx_chan = NULL;
 960         }
 961
 962         if (dma->tx_chan) {
 963                 dmaengine_terminate_all(dma->tx_chan);
 964                 dma_unmap_single(p->port.dev, dma->tx_addr,
 965                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 966                 dma_release_channel(dma->tx_chan);
 967                 dma->tx_chan = NULL;
 968         }
 969 }
 970
 971 static void s3c24xx_serial_shutdown(struct uart_port *port)
 972 {
 973         struct s3c24xx_uart_port *ourport = to_ourport(port);
 974
 975         if (ourport->tx_claimed) {
 976                 if (!s3c24xx_serial_has_interrupt_mask(port))
 977                         free_irq(ourport->tx_irq, ourport);
 978                 tx_enabled(port) = 0;
 979                 ourport->tx_claimed = 0;
 980                 ourport->tx_mode = 0;
 981         }
 982
 983         if (ourport->rx_claimed) {
 984                 if (!s3c24xx_serial_has_interrupt_mask(port))
 985                         free_irq(ourport->rx_irq, ourport);
 986                 ourport->rx_claimed = 0;
 987                 rx_enabled(port) = 0;
 988         }
 989
 990         /* Clear pending interrupts and mask all interrupts */
 991         if (s3c24xx_serial_has_interrupt_mask(port)) {
 992                 free_irq(port->irq, ourport);
 993
 994                 wr_regl(port, S3C64XX_UINTP, 0xf);
 995                 wr_regl(port, S3C64XX_UINTM, 0xf);
 996         }
 997
 998         if (ourport->dma)
 999                 s3c24xx_serial_release_dma(ourport);
1000
1001         ourport->tx_in_progress = 0;
1002 }
1003
1004 static int s3c24xx_serial_startup(struct uart_port *port)
1005 {
1006         struct s3c24xx_uart_port *ourport = to_ourport(port);
1007         int ret;
1008
1009         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1010             port, (unsigned long long)port->mapbase, port->membase);
1011
1012         rx_enabled(port) = 1;
1013
1014         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1015                           s3c24xx_serial_portname(port), ourport);
1016
1017         if (ret != 0) {
1018                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1019                 return ret;
1020         }
1021
1022         ourport->rx_claimed = 1;
1023
1024         dbg("requesting tx irq...\n");
1025
1026         tx_enabled(port) = 1;
1027
1028         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1029                           s3c24xx_serial_portname(port), ourport);
1030
1031         if (ret) {
1032                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1033                 goto err;
1034         }
1035
1036         ourport->tx_claimed = 1;
1037
1038         dbg("s3c24xx_serial_startup ok\n");
1039
1040         /* the port reset code should have done the correct
1041          * register setup for the port controls */
1042
1043         return ret;
1044
1045 err:
1046         s3c24xx_serial_shutdown(port);
1047         return ret;
1048 }
1049
1050 static int s3c64xx_serial_startup(struct uart_port *port)
1051 {
1052         struct s3c24xx_uart_port *ourport = to_ourport(port);
1053         unsigned long flags;
1054         unsigned int ufcon;
1055         int ret;
1056
1057         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1058             port, (unsigned long long)port->mapbase, port->membase);
1059
1060         wr_regl(port, S3C64XX_UINTM, 0xf);
1061         if (ourport->dma) {
1062                 ret = s3c24xx_serial_request_dma(ourport);
1063                 if (ret < 0) {
1064                         devm_kfree(port->dev, ourport->dma);
1065                         ourport->dma = NULL;
1066                 }
1067         }
1068
1069         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1070                           s3c24xx_serial_portname(port), ourport);
1071         if (ret) {
1072                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1073                 return ret;
1074         }
1075
1076         /* For compatibility with s3c24xx Soc's */
1077         rx_enabled(port) = 1;
1078         ourport->rx_claimed = 1;
1079         tx_enabled(port) = 0;
1080         ourport->tx_claimed = 1;
1081
1082         spin_lock_irqsave(&port->lock, flags);
1083
1084         ufcon = rd_regl(port, S3C2410_UFCON);
1085         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1086         if (!uart_console(port))
1087                 ufcon |= S3C2410_UFCON_RESETTX;
1088         wr_regl(port, S3C2410_UFCON, ufcon);
1089
1090         enable_rx_pio(ourport);
1091
1092         spin_unlock_irqrestore(&port->lock, flags);
1093
1094         /* Enable Rx Interrupt */
1095         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1096
1097         dbg("s3c64xx_serial_startup ok\n");
1098         return ret;
1099 }
1100
1101 /* power power management control */
1102
1103 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1104                               unsigned int old)
1105 {
1106         struct s3c24xx_uart_port *ourport = to_ourport(port);
1107         int timeout = 10000;
1108
1109         ourport->pm_level = level;
1110
1111         switch (level) {
1112         case 3:
1113                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1114                         udelay(100);
1115
1116                 if (!IS_ERR(ourport->baudclk))
1117                         clk_disable_unprepare(ourport->baudclk);
1118
1119                 clk_disable_unprepare(ourport->clk);
1120                 break;
1121
1122         case 0:
1123                 clk_prepare_enable(ourport->clk);
1124
1125                 if (!IS_ERR(ourport->baudclk))
1126                         clk_prepare_enable(ourport->baudclk);
1127
1128                 break;
1129         default:
1130                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1131         }
1132 }
1133
1134 /* baud rate calculation
1135  *
1136  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1137  * of different sources, including the peripheral clock ("pclk") and an
1138  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1139  * with a programmable extra divisor.
1140  *
1141  * The following code goes through the clock sources, and calculates the
1142  * baud clocks (and the resultant actual baud rates) and then tries to
1143  * pick the closest one and select that.
1144  *
1145 */
1146
1147 #define MAX_CLK_NAME_LENGTH 15
1148
1149 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1150 {
1151         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1152         unsigned int ucon;
1153
1154         if (info->num_clks == 1)
1155                 return 0;
1156
1157         ucon = rd_regl(port, S3C2410_UCON);
1158         ucon &= info->clksel_mask;
1159         return ucon >> info->clksel_shift;
1160 }
1161
1162 static void s3c24xx_serial_setsource(struct uart_port *port,
1163                         unsigned int clk_sel)
1164 {
1165         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1166         unsigned int ucon;
1167
1168         if (info->num_clks == 1)
1169                 return;
1170
1171         ucon = rd_regl(port, S3C2410_UCON);
1172         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1173                 return;
1174
1175         ucon &= ~info->clksel_mask;
1176         ucon |= clk_sel << info->clksel_shift;
1177         wr_regl(port, S3C2410_UCON, ucon);
1178 }
1179
1180 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1181                         unsigned int req_baud, struct clk **best_clk,
1182                         unsigned int *clk_num)
1183 {
1184         struct s3c24xx_uart_info *info = ourport->info;
1185         struct clk *clk;
1186         unsigned long rate;
1187         unsigned int cnt, baud, quot, best_quot = 0;
1188         char clkname[MAX_CLK_NAME_LENGTH];
1189         int calc_deviation, deviation = (1 << 30) - 1;
1190
1191         for (cnt = 0; cnt < info->num_clks; cnt++) {
1192                 /* Keep selected clock if provided */
1193                 if (ourport->cfg->clk_sel &&
1194                         !(ourport->cfg->clk_sel & (1 << cnt)))
1195                         continue;
1196
1197                 sprintf(clkname, "clk_uart_baud%d", cnt);
1198                 clk = clk_get(ourport->port.dev, clkname);
1199                 if (IS_ERR(clk))
1200                         continue;
1201
1202                 rate = clk_get_rate(clk);
1203                 if (!rate)
1204                         continue;
1205
1206                 if (ourport->info->has_divslot) {
1207                         unsigned long div = rate / req_baud;
1208
1209                         /* The UDIVSLOT register on the newer UARTs allows us to
1210                          * get a divisor adjustment of 1/16th on the baud clock.
1211                          *
1212                          * We don't keep the UDIVSLOT value (the 16ths we
1213                          * calculated by not multiplying the baud by 16) as it
1214                          * is easy enough to recalculate.
1215                          */
1216
1217                         quot = div / 16;
1218                         baud = rate / div;
1219                 } else {
1220                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1221                         baud = rate / (quot * 16);
1222                 }
1223                 quot--;
1224
1225                 calc_deviation = req_baud - baud;
1226                 if (calc_deviation < 0)
1227                         calc_deviation = -calc_deviation;
1228
1229                 if (calc_deviation < deviation) {
1230                         *best_clk = clk;
1231                         best_quot = quot;
1232                         *clk_num = cnt;
1233                         deviation = calc_deviation;
1234                 }
1235         }
1236
1237         return best_quot;
1238 }
1239
1240 /* udivslot_table[]
1241  *
1242  * This table takes the fractional value of the baud divisor and gives
1243  * the recommended setting for the UDIVSLOT register.
1244  */
1245 static u16 udivslot_table[16] = {
1246         [0] = 0x0000,
1247         [1] = 0x0080,
1248         [2] = 0x0808,
1249         [3] = 0x0888,
1250         [4] = 0x2222,
1251         [5] = 0x4924,
1252         [6] = 0x4A52,
1253         [7] = 0x54AA,
1254         [8] = 0x5555,
1255         [9] = 0xD555,
1256         [10] = 0xD5D5,
1257         [11] = 0xDDD5,
1258         [12] = 0xDDDD,
1259         [13] = 0xDFDD,
1260         [14] = 0xDFDF,
1261         [15] = 0xFFDF,
1262 };
1263
1264 static void s3c24xx_serial_set_termios(struct uart_port *port,
1265                                        struct ktermios *termios,
1266                                        struct ktermios *old)
1267 {
1268         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1269         struct s3c24xx_uart_port *ourport = to_ourport(port);
1270         struct clk *clk = ERR_PTR(-EINVAL);
1271         unsigned long flags;
1272         unsigned int baud, quot, clk_sel = 0;
1273         unsigned int ulcon;
1274         unsigned int umcon;
1275         unsigned int udivslot = 0;
1276
1277         /*
1278          * We don't support modem control lines.
1279          */
1280         termios->c_cflag &= ~(HUPCL | CMSPAR);
1281         termios->c_cflag |= CLOCAL;
1282
1283         /*
1284          * Ask the core to calculate the divisor for us.
1285          */
1286
1287         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1288         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1289         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1290                 quot = port->custom_divisor;
1291         if (IS_ERR(clk))
1292                 return;
1293
1294         /* check to see if we need  to change clock source */
1295
1296         if (ourport->baudclk != clk) {
1297                 clk_prepare_enable(clk);
1298
1299                 s3c24xx_serial_setsource(port, clk_sel);
1300
1301                 if (!IS_ERR(ourport->baudclk)) {
1302                         clk_disable_unprepare(ourport->baudclk);
1303                         ourport->baudclk = ERR_PTR(-EINVAL);
1304                 }
1305
1306                 ourport->baudclk = clk;
1307                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1308         }
1309
1310         if (ourport->info->has_divslot) {
1311                 unsigned int div = ourport->baudclk_rate / baud;
1312
1313                 if (cfg->has_fracval) {
1314                         udivslot = (div & 15);
1315                         dbg("fracval = %04x\n", udivslot);
1316                 } else {
1317                         udivslot = udivslot_table[div & 15];
1318                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1319                 }
1320         }
1321
1322         switch (termios->c_cflag & CSIZE) {
1323         case CS5:
1324                 dbg("config: 5bits/char\n");
1325                 ulcon = S3C2410_LCON_CS5;
1326                 break;
1327         case CS6:
1328                 dbg("config: 6bits/char\n");
1329                 ulcon = S3C2410_LCON_CS6;
1330                 break;
1331         case CS7:
1332                 dbg("config: 7bits/char\n");
1333                 ulcon = S3C2410_LCON_CS7;
1334                 break;
1335         case CS8:
1336         default:
1337                 dbg("config: 8bits/char\n");
1338                 ulcon = S3C2410_LCON_CS8;
1339                 break;
1340         }
1341
1342         /* preserve original lcon IR settings */
1343         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1344
1345         if (termios->c_cflag & CSTOPB)
1346                 ulcon |= S3C2410_LCON_STOPB;
1347
1348         if (termios->c_cflag & PARENB) {
1349                 if (termios->c_cflag & PARODD)
1350                         ulcon |= S3C2410_LCON_PODD;
1351                 else
1352                         ulcon |= S3C2410_LCON_PEVEN;
1353         } else {
1354                 ulcon |= S3C2410_LCON_PNONE;
1355         }
1356
1357         spin_lock_irqsave(&port->lock, flags);
1358
1359         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1360             ulcon, quot, udivslot);
1361
1362         wr_regl(port, S3C2410_ULCON, ulcon);
1363         wr_regl(port, S3C2410_UBRDIV, quot);
1364
1365         port->status &= ~UPSTAT_AUTOCTS;
1366
1367         umcon = rd_regl(port, S3C2410_UMCON);
1368         if (termios->c_cflag & CRTSCTS) {
1369                 umcon |= S3C2410_UMCOM_AFC;
1370                 /* Disable RTS when RX FIFO contains 63 bytes */
1371                 umcon &= ~S3C2412_UMCON_AFC_8;
1372                 port->status = UPSTAT_AUTOCTS;
1373         } else {
1374                 umcon &= ~S3C2410_UMCOM_AFC;
1375         }
1376         wr_regl(port, S3C2410_UMCON, umcon);
1377
1378         if (ourport->info->has_divslot)
1379                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1380
1381         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1382             rd_regl(port, S3C2410_ULCON),
1383             rd_regl(port, S3C2410_UCON),
1384             rd_regl(port, S3C2410_UFCON));
1385
1386         /*
1387          * Update the per-port timeout.
1388          */
1389         uart_update_timeout(port, termios->c_cflag, baud);
1390
1391         /*
1392          * Which character status flags are we interested in?
1393          */
1394         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1395         if (termios->c_iflag & INPCK)
1396                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1397                         S3C2410_UERSTAT_PARITY;
1398         /*
1399          * Which character status flags should we ignore?
1400          */
1401         port->ignore_status_mask = 0;
1402         if (termios->c_iflag & IGNPAR)
1403                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1404         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1405                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1406
1407         /*
1408          * Ignore all characters if CREAD is not set.
1409          */
1410         if ((termios->c_cflag & CREAD) == 0)
1411                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1412
1413         spin_unlock_irqrestore(&port->lock, flags);
1414 }
1415
1416 static const char *s3c24xx_serial_type(struct uart_port *port)
1417 {
1418         switch (port->type) {
1419         case PORT_S3C2410:
1420                 return "S3C2410";
1421         case PORT_S3C2440:
1422                 return "S3C2440";
1423         case PORT_S3C2412:
1424                 return "S3C2412";
1425         case PORT_S3C6400:
1426                 return "S3C6400/10";
1427         default:
1428                 return NULL;
1429         }
1430 }
1431
1432 #define MAP_SIZE (0x100)
1433
1434 static void s3c24xx_serial_release_port(struct uart_port *port)
1435 {
1436         release_mem_region(port->mapbase, MAP_SIZE);
1437 }
1438
1439 static int s3c24xx_serial_request_port(struct uart_port *port)
1440 {
1441         const char *name = s3c24xx_serial_portname(port);
1442         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1443 }
1444
1445 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1446 {
1447         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1448
1449         if (flags & UART_CONFIG_TYPE &&
1450             s3c24xx_serial_request_port(port) == 0)
1451                 port->type = info->type;
1452 }
1453
1454 /*
1455  * verify the new serial_struct (for TIOCSSERIAL).
1456  */
1457 static int
1458 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1459 {
1460         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1461
1462         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1463                 return -EINVAL;
1464
1465         return 0;
1466 }
1467
1468
1469 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1470
1471 static struct console s3c24xx_serial_console;
1472
1473 static int __init s3c24xx_serial_console_init(void)
1474 {
1475         register_console(&s3c24xx_serial_console);
1476         return 0;
1477 }
1478 console_initcall(s3c24xx_serial_console_init);
1479
1480 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1481 #else
1482 #define S3C24XX_SERIAL_CONSOLE NULL
1483 #endif
1484
1485 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1486 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1487 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1488                          unsigned char c);
1489 #endif
1490
1491 static struct uart_ops s3c24xx_serial_ops = {
1492         .pm             = s3c24xx_serial_pm,
1493         .tx_empty       = s3c24xx_serial_tx_empty,
1494         .get_mctrl      = s3c24xx_serial_get_mctrl,
1495         .set_mctrl      = s3c24xx_serial_set_mctrl,
1496         .stop_tx        = s3c24xx_serial_stop_tx,
1497         .start_tx       = s3c24xx_serial_start_tx,
1498         .stop_rx        = s3c24xx_serial_stop_rx,
1499         .break_ctl      = s3c24xx_serial_break_ctl,
1500         .startup        = s3c24xx_serial_startup,
1501         .shutdown       = s3c24xx_serial_shutdown,
1502         .set_termios    = s3c24xx_serial_set_termios,
1503         .type           = s3c24xx_serial_type,
1504         .release_port   = s3c24xx_serial_release_port,
1505         .request_port   = s3c24xx_serial_request_port,
1506         .config_port    = s3c24xx_serial_config_port,
1507         .verify_port    = s3c24xx_serial_verify_port,
1508 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1509         .poll_get_char = s3c24xx_serial_get_poll_char,
1510         .poll_put_char = s3c24xx_serial_put_poll_char,
1511 #endif
1512 };
1513
1514 static struct uart_driver s3c24xx_uart_drv = {
1515         .owner          = THIS_MODULE,
1516         .driver_name    = "s3c2410_serial",
1517         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1518         .cons           = S3C24XX_SERIAL_CONSOLE,
1519         .dev_name       = S3C24XX_SERIAL_NAME,
1520         .major          = S3C24XX_SERIAL_MAJOR,
1521         .minor          = S3C24XX_SERIAL_MINOR,
1522 };
1523
1524 #define __PORT_LOCK_UNLOCKED(i) \
1525         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1526 static struct s3c24xx_uart_port
1527 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1528         [0] = {
1529                 .port = {
1530                         .lock           = __PORT_LOCK_UNLOCKED(0),
1531                         .iotype         = UPIO_MEM,
1532                         .uartclk        = 0,
1533                         .fifosize       = 16,
1534                         .ops            = &s3c24xx_serial_ops,
1535                         .flags          = UPF_BOOT_AUTOCONF,
1536                         .line           = 0,
1537                 }
1538         },
1539         [1] = {
1540                 .port = {
1541                         .lock           = __PORT_LOCK_UNLOCKED(1),
1542                         .iotype         = UPIO_MEM,
1543                         .uartclk        = 0,
1544                         .fifosize       = 16,
1545                         .ops            = &s3c24xx_serial_ops,
1546                         .flags          = UPF_BOOT_AUTOCONF,
1547                         .line           = 1,
1548                 }
1549         },
1550 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1551
1552         [2] = {
1553                 .port = {
1554                         .lock           = __PORT_LOCK_UNLOCKED(2),
1555                         .iotype         = UPIO_MEM,
1556                         .uartclk        = 0,
1557                         .fifosize       = 16,
1558                         .ops            = &s3c24xx_serial_ops,
1559                         .flags          = UPF_BOOT_AUTOCONF,
1560                         .line           = 2,
1561                 }
1562         },
1563 #endif
1564 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1565         [3] = {
1566                 .port = {
1567                         .lock           = __PORT_LOCK_UNLOCKED(3),
1568                         .iotype         = UPIO_MEM,
1569                         .uartclk        = 0,
1570                         .fifosize       = 16,
1571                         .ops            = &s3c24xx_serial_ops,
1572                         .flags          = UPF_BOOT_AUTOCONF,
1573                         .line           = 3,
1574                 }
1575         }
1576 #endif
1577 };
1578 #undef __PORT_LOCK_UNLOCKED
1579
1580 /* s3c24xx_serial_resetport
1581  *
1582  * reset the fifos and other the settings.
1583 */
1584
1585 static void s3c24xx_serial_resetport(struct uart_port *port,
1586                                    struct s3c2410_uartcfg *cfg)
1587 {
1588         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1589         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1590         unsigned int ucon_mask;
1591
1592         ucon_mask = info->clksel_mask;
1593         if (info->type == PORT_S3C2440)
1594                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1595
1596         ucon &= ucon_mask;
1597         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1598
1599         /* reset both fifos */
1600         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1601         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1602
1603         /* some delay is required after fifo reset */
1604         udelay(1);
1605 }
1606
1607
1608 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1609
1610 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1611                                              unsigned long val, void *data)
1612 {
1613         struct s3c24xx_uart_port *port;
1614         struct uart_port *uport;
1615
1616         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1617         uport = &port->port;
1618
1619         /* check to see if port is enabled */
1620
1621         if (port->pm_level != 0)
1622                 return 0;
1623
1624         /* try and work out if the baudrate is changing, we can detect
1625          * a change in rate, but we do not have support for detecting
1626          * a disturbance in the clock-rate over the change.
1627          */
1628
1629         if (IS_ERR(port->baudclk))
1630                 goto exit;
1631
1632         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1633                 goto exit;
1634
1635         if (val == CPUFREQ_PRECHANGE) {
1636                 /* we should really shut the port down whilst the
1637                  * frequency change is in progress. */
1638
1639         } else if (val == CPUFREQ_POSTCHANGE) {
1640                 struct ktermios *termios;
1641                 struct tty_struct *tty;
1642
1643                 if (uport->state == NULL)
1644                         goto exit;
1645
1646                 tty = uport->state->port.tty;
1647
1648                 if (tty == NULL)
1649                         goto exit;
1650
1651                 termios = &tty->termios;
1652
1653                 if (termios == NULL) {
1654                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1655                         goto exit;
1656                 }
1657
1658                 s3c24xx_serial_set_termios(uport, termios, NULL);
1659         }
1660
1661 exit:
1662         return 0;
1663 }
1664
1665 static inline int
1666 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1667 {
1668         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1669
1670         return cpufreq_register_notifier(&port->freq_transition,
1671                                          CPUFREQ_TRANSITION_NOTIFIER);
1672 }
1673
1674 static inline void
1675 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1676 {
1677         cpufreq_unregister_notifier(&port->freq_transition,
1678                                     CPUFREQ_TRANSITION_NOTIFIER);
1679 }
1680
1681 #else
1682 static inline int
1683 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1684 {
1685         return 0;
1686 }
1687
1688 static inline void
1689 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1690 {
1691 }
1692 #endif
1693
1694 /* s3c24xx_serial_init_port
1695  *
1696  * initialise a single serial port from the platform device given
1697  */
1698
1699 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1700                                     struct platform_device *platdev)
1701 {
1702         struct uart_port *port = &ourport->port;
1703         struct s3c2410_uartcfg *cfg = ourport->cfg;
1704         struct resource *res;
1705         int ret;
1706
1707         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1708
1709         if (platdev == NULL)
1710                 return -ENODEV;
1711
1712         if (port->mapbase != 0)
1713                 return -EINVAL;
1714
1715         /* setup info for port */
1716         port->dev       = &platdev->dev;
1717
1718         /* Startup sequence is different for s3c64xx and higher SoC's */
1719         if (s3c24xx_serial_has_interrupt_mask(port))
1720                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1721
1722         port->uartclk = 1;
1723
1724         if (cfg->uart_flags & UPF_CONS_FLOW) {
1725                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1726                 port->flags |= UPF_CONS_FLOW;
1727         }
1728
1729         /* sort our the physical and virtual addresses for each UART */
1730
1731         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1732         if (res == NULL) {
1733                 dev_err(port->dev, "failed to find memory resource for uart\n");
1734                 return -EINVAL;
1735         }
1736
1737         dbg("resource %pR)\n", res);
1738
1739         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1740         if (!port->membase) {
1741                 dev_err(port->dev, "failed to remap controller address\n");
1742                 return -EBUSY;
1743         }
1744
1745         port->mapbase = res->start;
1746         ret = platform_get_irq(platdev, 0);
1747         if (ret < 0)
1748                 port->irq = 0;
1749         else {
1750                 port->irq = ret;
1751                 ourport->rx_irq = ret;
1752                 ourport->tx_irq = ret + 1;
1753         }
1754
1755         if (!s3c24xx_serial_has_interrupt_mask(port)) {
1756                 ret = platform_get_irq(platdev, 1);
1757                 if (ret > 0)
1758                         ourport->tx_irq = ret;
1759         }
1760         /*
1761          * DMA is currently supported only on DT platforms, if DMA properties
1762          * are specified.
1763          */
1764         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1765                                                      "dmas", NULL)) {
1766                 ourport->dma = devm_kzalloc(port->dev,
1767                                             sizeof(*ourport->dma),
1768                                             GFP_KERNEL);
1769                 if (!ourport->dma) {
1770                         ret = -ENOMEM;
1771                         goto err;
1772                 }
1773         }
1774
1775         ourport->clk    = clk_get(&platdev->dev, "uart");
1776         if (IS_ERR(ourport->clk)) {
1777                 pr_err("%s: Controller clock not found\n",
1778                                 dev_name(&platdev->dev));
1779                 ret = PTR_ERR(ourport->clk);
1780                 goto err;
1781         }
1782
1783         ret = clk_prepare_enable(ourport->clk);
1784         if (ret) {
1785                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1786                 clk_put(ourport->clk);
1787                 goto err;
1788         }
1789
1790         /* Keep all interrupts masked and cleared */
1791         if (s3c24xx_serial_has_interrupt_mask(port)) {
1792                 wr_regl(port, S3C64XX_UINTM, 0xf);
1793                 wr_regl(port, S3C64XX_UINTP, 0xf);
1794                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1795         }
1796
1797         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1798             &port->mapbase, port->membase, port->irq,
1799             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1800
1801         /* reset the fifos (and setup the uart) */
1802         s3c24xx_serial_resetport(port, cfg);
1803
1804         return 0;
1805
1806 err:
1807         port->mapbase = 0;
1808         return ret;
1809 }
1810
1811 /* Device driver serial port probe */
1812
1813 static const struct of_device_id s3c24xx_uart_dt_match[];
1814 static int probe_index;
1815
1816 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1817                         struct platform_device *pdev)
1818 {
1819 #ifdef CONFIG_OF
1820         if (pdev->dev.of_node) {
1821                 const struct of_device_id *match;
1822                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1823                 return (struct s3c24xx_serial_drv_data *)match->data;
1824         }
1825 #endif
1826         return (struct s3c24xx_serial_drv_data *)
1827                         platform_get_device_id(pdev)->driver_data;
1828 }
1829
1830 static int s3c24xx_serial_probe(struct platform_device *pdev)
1831 {
1832         struct device_node *np = pdev->dev.of_node;
1833         struct s3c24xx_uart_port *ourport;
1834         int index = probe_index;
1835         int ret;
1836
1837         if (np) {
1838                 ret = of_alias_get_id(np, "serial");
1839                 if (ret >= 0)
1840                         index = ret;
1841         }
1842
1843         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1844
1845         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1846                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1847                 return -EINVAL;
1848         }
1849         ourport = &s3c24xx_serial_ports[index];
1850
1851         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1852         if (!ourport->drv_data) {
1853                 dev_err(&pdev->dev, "could not find driver data\n");
1854                 return -ENODEV;
1855         }
1856
1857         ourport->baudclk = ERR_PTR(-EINVAL);
1858         ourport->info = ourport->drv_data->info;
1859         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1860                         dev_get_platdata(&pdev->dev) :
1861                         ourport->drv_data->def_cfg;
1862
1863         if (np)
1864                 of_property_read_u32(np,
1865                         "samsung,uart-fifosize", &ourport->port.fifosize);
1866
1867         if (ourport->drv_data->fifosize[index])
1868                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1869         else if (ourport->info->fifosize)
1870                 ourport->port.fifosize = ourport->info->fifosize;
1871
1872         /*
1873          * DMA transfers must be aligned at least to cache line size,
1874          * so find minimal transfer size suitable for DMA mode
1875          */
1876         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1877                                     dma_get_cache_alignment());
1878
1879         dbg("%s: initialising port %p...\n", __func__, ourport);
1880
1881         ret = s3c24xx_serial_init_port(ourport, pdev);
1882         if (ret < 0)
1883                 return ret;
1884
1885         if (!s3c24xx_uart_drv.state) {
1886                 ret = uart_register_driver(&s3c24xx_uart_drv);
1887                 if (ret < 0) {
1888                         pr_err("Failed to register Samsung UART driver\n");
1889                         return ret;
1890                 }
1891         }
1892
1893         dbg("%s: adding port\n", __func__);
1894         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1895         platform_set_drvdata(pdev, &ourport->port);
1896
1897         /*
1898          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1899          * so that a potential re-enablement through the pm-callback overlaps
1900          * and keeps the clock enabled in this case.
1901          */
1902         clk_disable_unprepare(ourport->clk);
1903
1904         ret = s3c24xx_serial_cpufreq_register(ourport);
1905         if (ret < 0)
1906                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1907
1908         probe_index++;
1909
1910         return 0;
1911 }
1912
1913 static int s3c24xx_serial_remove(struct platform_device *dev)
1914 {
1915         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1916
1917         if (port) {
1918                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1919                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1920         }
1921
1922         uart_unregister_driver(&s3c24xx_uart_drv);
1923
1924         return 0;
1925 }
1926
1927 /* UART power management code */
1928 #ifdef CONFIG_PM_SLEEP
1929 static int s3c24xx_serial_suspend(struct device *dev)
1930 {
1931         struct uart_port *port = s3c24xx_dev_to_port(dev);
1932
1933         if (port)
1934                 uart_suspend_port(&s3c24xx_uart_drv, port);
1935
1936         return 0;
1937 }
1938
1939 static int s3c24xx_serial_resume(struct device *dev)
1940 {
1941         struct uart_port *port = s3c24xx_dev_to_port(dev);
1942         struct s3c24xx_uart_port *ourport = to_ourport(port);
1943
1944         if (port) {
1945                 clk_prepare_enable(ourport->clk);
1946                 if (!IS_ERR(ourport->baudclk))
1947                         clk_prepare_enable(ourport->baudclk);
1948                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1949                 if (!IS_ERR(ourport->baudclk))
1950                         clk_disable_unprepare(ourport->baudclk);
1951                 clk_disable_unprepare(ourport->clk);
1952
1953                 uart_resume_port(&s3c24xx_uart_drv, port);
1954         }
1955
1956         return 0;
1957 }
1958
1959 static int s3c24xx_serial_resume_noirq(struct device *dev)
1960 {
1961         struct uart_port *port = s3c24xx_dev_to_port(dev);
1962         struct s3c24xx_uart_port *ourport = to_ourport(port);
1963
1964         if (port) {
1965                 /* restore IRQ mask */
1966                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1967                         unsigned int uintm = 0xf;
1968                         if (tx_enabled(port))
1969                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1970                         if (rx_enabled(port))
1971                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1972                         clk_prepare_enable(ourport->clk);
1973                         if (!IS_ERR(ourport->baudclk))
1974                                 clk_prepare_enable(ourport->baudclk);
1975                         wr_regl(port, S3C64XX_UINTM, uintm);
1976                         if (!IS_ERR(ourport->baudclk))
1977                                 clk_disable_unprepare(ourport->baudclk);
1978                         clk_disable_unprepare(ourport->clk);
1979                 }
1980         }
1981
1982         return 0;
1983 }
1984
1985 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1986         .suspend = s3c24xx_serial_suspend,
1987         .resume = s3c24xx_serial_resume,
1988         .resume_noirq = s3c24xx_serial_resume_noirq,
1989 };
1990 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1991
1992 #else /* !CONFIG_PM_SLEEP */
1993
1994 #define SERIAL_SAMSUNG_PM_OPS   NULL
1995 #endif /* CONFIG_PM_SLEEP */
1996
1997 /* Console code */
1998
1999 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2000
2001 static struct uart_port *cons_uart;
2002
2003 static int
2004 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2005 {
2006         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2007         unsigned long ufstat, utrstat;
2008
2009         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2010                 /* fifo mode - check amount of data in fifo registers... */
2011
2012                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2013                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2014         }
2015
2016         /* in non-fifo mode, we go and use the tx buffer empty */
2017
2018         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2019         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2020 }
2021
2022 static bool
2023 s3c24xx_port_configured(unsigned int ucon)
2024 {
2025         /* consider the serial port configured if the tx/rx mode set */
2026         return (ucon & 0xf) != 0;
2027 }
2028
2029 #ifdef CONFIG_CONSOLE_POLL
2030 /*
2031  * Console polling routines for writing and reading from the uart while
2032  * in an interrupt or debug context.
2033  */
2034
2035 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2036 {
2037         struct s3c24xx_uart_port *ourport = to_ourport(port);
2038         unsigned int ufstat;
2039
2040         ufstat = rd_regl(port, S3C2410_UFSTAT);
2041         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2042                 return NO_POLL_CHAR;
2043
2044         return rd_regb(port, S3C2410_URXH);
2045 }
2046
2047 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2048                 unsigned char c)
2049 {
2050         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2051         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2052
2053         /* not possible to xmit on unconfigured port */
2054         if (!s3c24xx_port_configured(ucon))
2055                 return;
2056
2057         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2058                 cpu_relax();
2059         wr_regb(port, S3C2410_UTXH, c);
2060 }
2061
2062 #endif /* CONFIG_CONSOLE_POLL */
2063
2064 static void
2065 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2066 {
2067         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2068
2069         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2070                 cpu_relax();
2071         wr_regb(port, S3C2410_UTXH, ch);
2072 }
2073
2074 static void
2075 s3c24xx_serial_console_write(struct console *co, const char *s,
2076                              unsigned int count)
2077 {
2078         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2079
2080         /* not possible to xmit on unconfigured port */
2081         if (!s3c24xx_port_configured(ucon))
2082                 return;
2083
2084         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2085 }
2086
2087 static void __init
2088 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2089                            int *parity, int *bits)
2090 {
2091         struct clk *clk;
2092         unsigned int ulcon;
2093         unsigned int ucon;
2094         unsigned int ubrdiv;
2095         unsigned long rate;
2096         unsigned int clk_sel;
2097         char clk_name[MAX_CLK_NAME_LENGTH];
2098
2099         ulcon  = rd_regl(port, S3C2410_ULCON);
2100         ucon   = rd_regl(port, S3C2410_UCON);
2101         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2102
2103         dbg("s3c24xx_serial_get_options: port=%p\n"
2104             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2105             port, ulcon, ucon, ubrdiv);
2106
2107         if (s3c24xx_port_configured(ucon)) {
2108                 switch (ulcon & S3C2410_LCON_CSMASK) {
2109                 case S3C2410_LCON_CS5:
2110                         *bits = 5;
2111                         break;
2112                 case S3C2410_LCON_CS6:
2113                         *bits = 6;
2114                         break;
2115                 case S3C2410_LCON_CS7:
2116                         *bits = 7;
2117                         break;
2118                 case S3C2410_LCON_CS8:
2119                 default:
2120                         *bits = 8;
2121                         break;
2122                 }
2123
2124                 switch (ulcon & S3C2410_LCON_PMASK) {
2125                 case S3C2410_LCON_PEVEN:
2126                         *parity = 'e';
2127                         break;
2128
2129                 case S3C2410_LCON_PODD:
2130                         *parity = 'o';
2131                         break;
2132
2133                 case S3C2410_LCON_PNONE:
2134                 default:
2135                         *parity = 'n';
2136                 }
2137
2138                 /* now calculate the baud rate */
2139
2140                 clk_sel = s3c24xx_serial_getsource(port);
2141                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2142
2143                 clk = clk_get(port->dev, clk_name);
2144                 if (!IS_ERR(clk))
2145                         rate = clk_get_rate(clk);
2146                 else
2147                         rate = 1;
2148
2149                 *baud = rate / (16 * (ubrdiv + 1));
2150                 dbg("calculated baud %d\n", *baud);
2151         }
2152
2153 }
2154
2155 static int __init
2156 s3c24xx_serial_console_setup(struct console *co, char *options)
2157 {
2158         struct uart_port *port;
2159         int baud = 9600;
2160         int bits = 8;
2161         int parity = 'n';
2162         int flow = 'n';
2163
2164         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2165             co, co->index, options);
2166
2167         /* is this a valid port */
2168
2169         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2170                 co->index = 0;
2171
2172         port = &s3c24xx_serial_ports[co->index].port;
2173
2174         /* is the port configured? */
2175
2176         if (port->mapbase == 0x0)
2177                 return -ENODEV;
2178
2179         cons_uart = port;
2180
2181         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2182
2183         /*
2184          * Check whether an invalid uart number has been specified, and
2185          * if so, search for the first available port that does have
2186          * console support.
2187          */
2188         if (options)
2189                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2190         else
2191                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2192
2193         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2194
2195         return uart_set_options(port, co, baud, parity, bits, flow);
2196 }
2197
2198 static struct console s3c24xx_serial_console = {
2199         .name           = S3C24XX_SERIAL_NAME,
2200         .device         = uart_console_device,
2201         .flags          = CON_PRINTBUFFER,
2202         .index          = -1,
2203         .write          = s3c24xx_serial_console_write,
2204         .setup          = s3c24xx_serial_console_setup,
2205         .data           = &s3c24xx_uart_drv,
2206 };
2207 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2208
2209 #ifdef CONFIG_CPU_S3C2410
2210 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2211         .info = &(struct s3c24xx_uart_info) {
2212                 .name           = "Samsung S3C2410 UART",
2213                 .type           = PORT_S3C2410,
2214                 .fifosize       = 16,
2215                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2216                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2217                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2218                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2219                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2220                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2221                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2222                 .num_clks       = 2,
2223                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2224                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2225         },
2226         .def_cfg = &(struct s3c2410_uartcfg) {
2227                 .ucon           = S3C2410_UCON_DEFAULT,
2228                 .ufcon          = S3C2410_UFCON_DEFAULT,
2229         },
2230 };
2231 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2232 #else
2233 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2234 #endif
2235
2236 #ifdef CONFIG_CPU_S3C2412
2237 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2238         .info = &(struct s3c24xx_uart_info) {
2239                 .name           = "Samsung S3C2412 UART",
2240                 .type           = PORT_S3C2412,
2241                 .fifosize       = 64,
2242                 .has_divslot    = 1,
2243                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2244                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2245                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2246                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2247                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2248                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2249                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2250                 .num_clks       = 4,
2251                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2252                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2253         },
2254         .def_cfg = &(struct s3c2410_uartcfg) {
2255                 .ucon           = S3C2410_UCON_DEFAULT,
2256                 .ufcon          = S3C2410_UFCON_DEFAULT,
2257         },
2258 };
2259 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2260 #else
2261 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2262 #endif
2263
2264 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2265         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2266 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2267         .info = &(struct s3c24xx_uart_info) {
2268                 .name           = "Samsung S3C2440 UART",
2269                 .type           = PORT_S3C2440,
2270                 .fifosize       = 64,
2271                 .has_divslot    = 1,
2272                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2273                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2274                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2275                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2276                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2277                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2278                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2279                 .num_clks       = 4,
2280                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2281                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2282         },
2283         .def_cfg = &(struct s3c2410_uartcfg) {
2284                 .ucon           = S3C2410_UCON_DEFAULT,
2285                 .ufcon          = S3C2410_UFCON_DEFAULT,
2286         },
2287 };
2288 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2289 #else
2290 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2291 #endif
2292
2293 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2294 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2295         .info = &(struct s3c24xx_uart_info) {
2296                 .name           = "Samsung S3C6400 UART",
2297                 .type           = PORT_S3C6400,
2298                 .fifosize       = 64,
2299                 .has_divslot    = 1,
2300                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2301                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2302                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2303                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2304                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2305                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2306                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2307                 .num_clks       = 4,
2308                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2309                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2310         },
2311         .def_cfg = &(struct s3c2410_uartcfg) {
2312                 .ucon           = S3C2410_UCON_DEFAULT,
2313                 .ufcon          = S3C2410_UFCON_DEFAULT,
2314         },
2315 };
2316 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2317 #else
2318 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2319 #endif
2320
2321 #ifdef CONFIG_CPU_S5PV210
2322 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2323         .info = &(struct s3c24xx_uart_info) {
2324                 .name           = "Samsung S5PV210 UART",
2325                 .type           = PORT_S3C6400,
2326                 .has_divslot    = 1,
2327                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2328                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2329                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2330                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2331                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2332                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2333                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2334                 .num_clks       = 2,
2335                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2336                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2337         },
2338         .def_cfg = &(struct s3c2410_uartcfg) {
2339                 .ucon           = S5PV210_UCON_DEFAULT,
2340                 .ufcon          = S5PV210_UFCON_DEFAULT,
2341         },
2342         .fifosize = { 256, 64, 16, 16 },
2343 };
2344 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2345 #else
2346 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2347 #endif
2348
2349 #if defined(CONFIG_ARCH_EXYNOS)
2350 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2351         .info = &(struct s3c24xx_uart_info) {                   \
2352                 .name           = "Samsung Exynos UART",        \
2353                 .type           = PORT_S3C6400,                 \
2354                 .has_divslot    = 1,                            \
2355                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2356                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2357                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2358                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2359                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2360                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2361                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2362                 .num_clks       = 1,                            \
2363                 .clksel_mask    = 0,                            \
2364                 .clksel_shift   = 0,                            \
2365         },                                                      \
2366         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2367                 .ucon           = S5PV210_UCON_DEFAULT,         \
2368                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2369                 .has_fracval    = 1,                            \
2370         }                                                       \
2371
2372 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2373         EXYNOS_COMMON_SERIAL_DRV_DATA,
2374         .fifosize = { 256, 64, 16, 16 },
2375 };
2376
2377 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2378         EXYNOS_COMMON_SERIAL_DRV_DATA,
2379         .fifosize = { 64, 256, 16, 256 },
2380 };
2381
2382 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2383 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2384 #else
2385 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2386 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2387 #endif
2388
2389 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2390         {
2391                 .name           = "s3c2410-uart",
2392                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2393         }, {
2394                 .name           = "s3c2412-uart",
2395                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2396         }, {
2397                 .name           = "s3c2440-uart",
2398                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2399         }, {
2400                 .name           = "s3c6400-uart",
2401                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2402         }, {
2403                 .name           = "s5pv210-uart",
2404                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2405         }, {
2406                 .name           = "exynos4210-uart",
2407                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2408         }, {
2409                 .name           = "exynos5433-uart",
2410                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2411         },
2412         { },
2413 };
2414 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2415
2416 #ifdef CONFIG_OF
2417 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2418         { .compatible = "samsung,s3c2410-uart",
2419                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2420         { .compatible = "samsung,s3c2412-uart",
2421                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2422         { .compatible = "samsung,s3c2440-uart",
2423                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2424         { .compatible = "samsung,s3c6400-uart",
2425                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2426         { .compatible = "samsung,s5pv210-uart",
2427                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2428         { .compatible = "samsung,exynos4210-uart",
2429                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2430         { .compatible = "samsung,exynos5433-uart",
2431                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2432         {},
2433 };
2434 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2435 #endif
2436
2437 static struct platform_driver samsung_serial_driver = {
2438         .probe          = s3c24xx_serial_probe,
2439         .remove         = s3c24xx_serial_remove,
2440         .id_table       = s3c24xx_serial_driver_ids,
2441         .driver         = {
2442                 .name   = "samsung-uart",
2443                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2444                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2445         },
2446 };
2447
2448 module_platform_driver(samsung_serial_driver);
2449
2450 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2451 /*
2452  * Early console.
2453  */
2454
2455 struct samsung_early_console_data {
2456         u32 txfull_mask;
2457 };
2458
2459 static void samsung_early_busyuart(struct uart_port *port)
2460 {
2461         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2462                 ;
2463 }
2464
2465 static void samsung_early_busyuart_fifo(struct uart_port *port)
2466 {
2467         struct samsung_early_console_data *data = port->private_data;
2468
2469         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2470                 ;
2471 }
2472
2473 static void samsung_early_putc(struct uart_port *port, int c)
2474 {
2475         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2476                 samsung_early_busyuart_fifo(port);
2477         else
2478                 samsung_early_busyuart(port);
2479
2480         writeb(c, port->membase + S3C2410_UTXH);
2481 }
2482
2483 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2484 {
2485         struct earlycon_device *dev = con->data;
2486
2487         uart_console_write(&dev->port, s, n, samsung_early_putc);
2488 }
2489
2490 static int __init samsung_early_console_setup(struct earlycon_device *device,
2491                                               const char *opt)
2492 {
2493         if (!device->port.membase)
2494                 return -ENODEV;
2495
2496         device->con->write = samsung_early_write;
2497         return 0;
2498 }
2499
2500 /* S3C2410 */
2501 static struct samsung_early_console_data s3c2410_early_console_data = {
2502         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2503 };
2504
2505 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2506                                               const char *opt)
2507 {
2508         device->port.private_data = &s3c2410_early_console_data;
2509         return samsung_early_console_setup(device, opt);
2510 }
2511 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2512                         s3c2410_early_console_setup);
2513
2514 /* S3C2412, S3C2440, S3C64xx */
2515 static struct samsung_early_console_data s3c2440_early_console_data = {
2516         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2517 };
2518
2519 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2520                                               const char *opt)
2521 {
2522         device->port.private_data = &s3c2440_early_console_data;
2523         return samsung_early_console_setup(device, opt);
2524 }
2525 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2526                         s3c2440_early_console_setup);
2527 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2528                         s3c2440_early_console_setup);
2529 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2530                         s3c2440_early_console_setup);
2531
2532 /* S5PV210, EXYNOS */
2533 static struct samsung_early_console_data s5pv210_early_console_data = {
2534         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2535 };
2536
2537 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2538                                               const char *opt)
2539 {
2540         device->port.private_data = &s5pv210_early_console_data;
2541         return samsung_early_console_setup(device, opt);
2542 }
2543 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2544                         s5pv210_early_console_setup);
2545 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2546                         s5pv210_early_console_setup);
2547 #endif
2548
2549 MODULE_ALIAS("platform:samsung-uart");
2550 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2551 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2552 MODULE_LICENSE("GPL v2");