drivers/tty/serial/samsung.c

   1 /*
   2  * Driver core for Samsung SoC onboard UARTs.
   3  *
   4  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /* Hote on 2410 error handling
  13  *
  14  * The s3c2410 manual has a love/hate affair with the contents of the
  15  * UERSTAT register in the UART blocks, and keeps marking some of the
  16  * error bits as reserved. Having checked with the s3c2410x01,
  17  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  18  * feature from the latter versions of the manual.
  19  *
  20  * If it becomes aparrent that latter versions of the 2410 remove these
  21  * bits, then action will have to be taken to differentiate the versions
  22  * and change the policy on BREAK
  23  *
  24  * BJD, 04-Nov-2004
  25 */
  26
  27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  28 #define SUPPORT_SYSRQ
  29 #endif
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/ioport.h>
  36 #include <linux/io.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/init.h>
  39 #include <linux/sysrq.h>
  40 #include <linux/console.h>
  41 #include <linux/tty.h>
  42 #include <linux/tty_flip.h>
  43 #include <linux/serial_core.h>
  44 #include <linux/serial.h>
  45 #include <linux/serial_s3c.h>
  46 #include <linux/delay.h>
  47 #include <linux/clk.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/of.h>
  50
  51 #include <asm/irq.h>
  52
  53 #include "samsung.h"
  54
  55 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  56         !defined(MODULE)
  57
  58 extern void printascii(const char *);
  59
  60 __printf(1, 2)
  61 static void dbg(const char *fmt, ...)
  62 {
  63         va_list va;
  64         char buff[256];
  65
  66         va_start(va, fmt);
  67         vscnprintf(buff, sizeof(buff), fmt, va);
  68         va_end(va);
  69
  70         printascii(buff);
  71 }
  72
  73 #else
  74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  75 #endif
  76
  77 /* UART name and device definitions */
  78
  79 #define S3C24XX_SERIAL_NAME     "ttySAC"
  80 #define S3C24XX_SERIAL_MAJOR    204
  81 #define S3C24XX_SERIAL_MINOR    64
  82
  83 #define S3C24XX_TX_PIO                  1
  84 #define S3C24XX_TX_DMA                  2
  85 #define S3C24XX_RX_PIO                  1
  86 #define S3C24XX_RX_DMA                  2
  87 /* macros to change one thing to another */
  88
  89 #define tx_enabled(port) ((port)->unused[0])
  90 #define rx_enabled(port) ((port)->unused[1])
  91
  92 /* flag to ignore all characters coming in */
  93 #define RXSTAT_DUMMY_READ (0x10000000)
  94
  95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  96 {
  97         return container_of(port, struct s3c24xx_uart_port, port);
  98 }
  99
 100 /* translate a port to the device name */
 101
 102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 103 {
 104         return to_platform_device(port->dev)->name;
 105 }
 106
 107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 108 {
 109         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 110 }
 111
 112 /*
 113  * s3c64xx and later SoC's include the interrupt mask and status registers in
 114  * the controller itself, unlike the s3c24xx SoC's which have these registers
 115  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 116  */
 117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 118 {
 119         return to_ourport(port)->info->type == PORT_S3C6400;
 120 }
 121
 122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 123 {
 124         unsigned long flags;
 125         unsigned int ucon, ufcon;
 126         int count = 10000;
 127
 128         spin_lock_irqsave(&port->lock, flags);
 129
 130         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 131                 udelay(100);
 132
 133         ufcon = rd_regl(port, S3C2410_UFCON);
 134         ufcon |= S3C2410_UFCON_RESETRX;
 135         wr_regl(port, S3C2410_UFCON, ufcon);
 136
 137         ucon = rd_regl(port, S3C2410_UCON);
 138         ucon |= S3C2410_UCON_RXIRQMODE;
 139         wr_regl(port, S3C2410_UCON, ucon);
 140
 141         rx_enabled(port) = 1;
 142         spin_unlock_irqrestore(&port->lock, flags);
 143 }
 144
 145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 146 {
 147         unsigned long flags;
 148         unsigned int ucon;
 149
 150         spin_lock_irqsave(&port->lock, flags);
 151
 152         ucon = rd_regl(port, S3C2410_UCON);
 153         ucon &= ~S3C2410_UCON_RXIRQMODE;
 154         wr_regl(port, S3C2410_UCON, ucon);
 155
 156         rx_enabled(port) = 0;
 157         spin_unlock_irqrestore(&port->lock, flags);
 158 }
 159
 160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 161 {
 162         struct s3c24xx_uart_port *ourport = to_ourport(port);
 163         struct s3c24xx_uart_dma *dma = ourport->dma;
 164         struct circ_buf *xmit = &port->state->xmit;
 165         struct dma_tx_state state;
 166         int count;
 167
 168         if (!tx_enabled(port))
 169                 return;
 170
 171         if (s3c24xx_serial_has_interrupt_mask(port))
 172                 __set_bit(S3C64XX_UINTM_TXD,
 173                         portaddrl(port, S3C64XX_UINTM));
 174         else
 175                 disable_irq_nosync(ourport->tx_irq);
 176
 177         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 178                 dmaengine_pause(dma->tx_chan);
 179                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 180                 dmaengine_terminate_all(dma->tx_chan);
 181                 dma_sync_single_for_cpu(ourport->port.dev,
 182                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 183                 async_tx_ack(dma->tx_desc);
 184                 count = dma->tx_bytes_requested - state.residue;
 185                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 186                 port->icount.tx += count;
 187         }
 188
 189         tx_enabled(port) = 0;
 190         ourport->tx_in_progress = 0;
 191
 192         if (port->flags & UPF_CONS_FLOW)
 193                 s3c24xx_serial_rx_enable(port);
 194
 195         ourport->tx_mode = 0;
 196 }
 197
 198 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 199
 200 static void s3c24xx_serial_tx_dma_complete(void *args)
 201 {
 202         struct s3c24xx_uart_port *ourport = args;
 203         struct uart_port *port = &ourport->port;
 204         struct circ_buf *xmit = &port->state->xmit;
 205         struct s3c24xx_uart_dma *dma = ourport->dma;
 206         struct dma_tx_state state;
 207         unsigned long flags;
 208         int count;
 209
 210
 211         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 212         count = dma->tx_bytes_requested - state.residue;
 213         async_tx_ack(dma->tx_desc);
 214
 215         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 216                                 dma->tx_size, DMA_TO_DEVICE);
 217
 218         spin_lock_irqsave(&port->lock, flags);
 219
 220         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 221         port->icount.tx += count;
 222         ourport->tx_in_progress = 0;
 223
 224         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 225                 uart_write_wakeup(port);
 226
 227         s3c24xx_serial_start_next_tx(ourport);
 228         spin_unlock_irqrestore(&port->lock, flags);
 229 }
 230
 231 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 232 {
 233         struct uart_port *port = &ourport->port;
 234         u32 ucon;
 235
 236         /* Mask Tx interrupt */
 237         if (s3c24xx_serial_has_interrupt_mask(port))
 238                 __set_bit(S3C64XX_UINTM_TXD,
 239                           portaddrl(port, S3C64XX_UINTM));
 240         else
 241                 disable_irq_nosync(ourport->tx_irq);
 242
 243         /* Enable tx dma mode */
 244         ucon = rd_regl(port, S3C2410_UCON);
 245         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 246         ucon |= (dma_get_cache_alignment() >= 16) ?
 247                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 248         ucon |= S3C64XX_UCON_TXMODE_DMA;
 249         wr_regl(port,  S3C2410_UCON, ucon);
 250
 251         ourport->tx_mode = S3C24XX_TX_DMA;
 252 }
 253
 254 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 255 {
 256         struct uart_port *port = &ourport->port;
 257         u32 ucon, ufcon;
 258
 259         /* Set ufcon txtrig */
 260         ourport->tx_in_progress = S3C24XX_TX_PIO;
 261         ufcon = rd_regl(port, S3C2410_UFCON);
 262         wr_regl(port,  S3C2410_UFCON, ufcon);
 263
 264         /* Enable tx pio mode */
 265         ucon = rd_regl(port, S3C2410_UCON);
 266         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 267         ucon |= S3C64XX_UCON_TXMODE_CPU;
 268         wr_regl(port,  S3C2410_UCON, ucon);
 269
 270         /* Unmask Tx interrupt */
 271         if (s3c24xx_serial_has_interrupt_mask(port))
 272                 __clear_bit(S3C64XX_UINTM_TXD,
 273                             portaddrl(port, S3C64XX_UINTM));
 274         else
 275                 enable_irq(ourport->tx_irq);
 276
 277         ourport->tx_mode = S3C24XX_TX_PIO;
 278 }
 279
 280 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 281 {
 282         if (ourport->tx_mode != S3C24XX_TX_PIO)
 283                 enable_tx_pio(ourport);
 284 }
 285
 286 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 287                                       unsigned int count)
 288 {
 289         struct uart_port *port = &ourport->port;
 290         struct circ_buf *xmit = &port->state->xmit;
 291         struct s3c24xx_uart_dma *dma = ourport->dma;
 292
 293
 294         if (ourport->tx_mode != S3C24XX_TX_DMA)
 295                 enable_tx_dma(ourport);
 296
 297         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 298         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 299
 300         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 301                                 dma->tx_size, DMA_TO_DEVICE);
 302
 303         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 304                                 dma->tx_transfer_addr, dma->tx_size,
 305                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 306         if (!dma->tx_desc) {
 307                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 308                 return -EIO;
 309         }
 310
 311         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 312         dma->tx_desc->callback_param = ourport;
 313         dma->tx_bytes_requested = dma->tx_size;
 314
 315         ourport->tx_in_progress = S3C24XX_TX_DMA;
 316         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 317         dma_async_issue_pending(dma->tx_chan);
 318         return 0;
 319 }
 320
 321 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 322 {
 323         struct uart_port *port = &ourport->port;
 324         struct circ_buf *xmit = &port->state->xmit;
 325         unsigned long count;
 326
 327         /* Get data size up to the end of buffer */
 328         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 329
 330         if (!count) {
 331                 s3c24xx_serial_stop_tx(port);
 332                 return;
 333         }
 334
 335         if (!ourport->dma || !ourport->dma->tx_chan ||
 336             count < ourport->min_dma_size ||
 337             xmit->tail & (dma_get_cache_alignment() - 1))
 338                 s3c24xx_serial_start_tx_pio(ourport);
 339         else
 340                 s3c24xx_serial_start_tx_dma(ourport, count);
 341 }
 342
 343 static void s3c24xx_serial_start_tx(struct uart_port *port)
 344 {
 345         struct s3c24xx_uart_port *ourport = to_ourport(port);
 346         struct circ_buf *xmit = &port->state->xmit;
 347
 348         if (!tx_enabled(port)) {
 349                 if (port->flags & UPF_CONS_FLOW)
 350                         s3c24xx_serial_rx_disable(port);
 351
 352                 tx_enabled(port) = 1;
 353                 if (!ourport->dma || !ourport->dma->tx_chan)
 354                         s3c24xx_serial_start_tx_pio(ourport);
 355         }
 356
 357         if (ourport->dma && ourport->dma->tx_chan) {
 358                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 359                         s3c24xx_serial_start_next_tx(ourport);
 360         }
 361 }
 362
 363 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 364                 struct tty_port *tty, int count)
 365 {
 366         struct s3c24xx_uart_dma *dma = ourport->dma;
 367         int copied;
 368
 369         if (!count)
 370                 return;
 371
 372         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 373                                 dma->rx_size, DMA_FROM_DEVICE);
 374
 375         ourport->port.icount.rx += count;
 376         if (!tty) {
 377                 dev_err(ourport->port.dev, "No tty port\n");
 378                 return;
 379         }
 380         copied = tty_insert_flip_string(tty,
 381                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 382         if (copied != count) {
 383                 WARN_ON(1);
 384                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 385         }
 386 }
 387
 388 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 389 {
 390         struct s3c24xx_uart_port *ourport = to_ourport(port);
 391         struct s3c24xx_uart_dma *dma = ourport->dma;
 392         struct tty_port *t = &port->state->port;
 393         struct dma_tx_state state;
 394         enum dma_status dma_status;
 395         unsigned int received;
 396
 397         if (rx_enabled(port)) {
 398                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 399                 if (s3c24xx_serial_has_interrupt_mask(port))
 400                         __set_bit(S3C64XX_UINTM_RXD,
 401                                 portaddrl(port, S3C64XX_UINTM));
 402                 else
 403                         disable_irq_nosync(ourport->rx_irq);
 404                 rx_enabled(port) = 0;
 405         }
 406         if (dma && dma->rx_chan) {
 407                 dmaengine_pause(dma->tx_chan);
 408                 dma_status = dmaengine_tx_status(dma->rx_chan,
 409                                 dma->rx_cookie, &state);
 410                 if (dma_status == DMA_IN_PROGRESS ||
 411                         dma_status == DMA_PAUSED) {
 412                         received = dma->rx_bytes_requested - state.residue;
 413                         dmaengine_terminate_all(dma->rx_chan);
 414                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 415                 }
 416         }
 417 }
 418
 419 static inline struct s3c24xx_uart_info
 420         *s3c24xx_port_to_info(struct uart_port *port)
 421 {
 422         return to_ourport(port)->info;
 423 }
 424
 425 static inline struct s3c2410_uartcfg
 426         *s3c24xx_port_to_cfg(struct uart_port *port)
 427 {
 428         struct s3c24xx_uart_port *ourport;
 429
 430         if (port->dev == NULL)
 431                 return NULL;
 432
 433         ourport = container_of(port, struct s3c24xx_uart_port, port);
 434         return ourport->cfg;
 435 }
 436
 437 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 438                                      unsigned long ufstat)
 439 {
 440         struct s3c24xx_uart_info *info = ourport->info;
 441
 442         if (ufstat & info->rx_fifofull)
 443                 return ourport->port.fifosize;
 444
 445         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 446 }
 447
 448 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 449 static void s3c24xx_serial_rx_dma_complete(void *args)
 450 {
 451         struct s3c24xx_uart_port *ourport = args;
 452         struct uart_port *port = &ourport->port;
 453
 454         struct s3c24xx_uart_dma *dma = ourport->dma;
 455         struct tty_port *t = &port->state->port;
 456         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 457
 458         struct dma_tx_state state;
 459         unsigned long flags;
 460         int received;
 461
 462         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 463         received  = dma->rx_bytes_requested - state.residue;
 464         async_tx_ack(dma->rx_desc);
 465
 466         spin_lock_irqsave(&port->lock, flags);
 467
 468         if (received)
 469                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 470
 471         if (tty) {
 472                 tty_flip_buffer_push(t);
 473                 tty_kref_put(tty);
 474         }
 475
 476         s3c64xx_start_rx_dma(ourport);
 477
 478         spin_unlock_irqrestore(&port->lock, flags);
 479 }
 480
 481 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 482 {
 483         struct s3c24xx_uart_dma *dma = ourport->dma;
 484
 485         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 486                                 dma->rx_size, DMA_FROM_DEVICE);
 487
 488         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 489                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 490                                 DMA_PREP_INTERRUPT);
 491         if (!dma->rx_desc) {
 492                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 493                 return;
 494         }
 495
 496         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 497         dma->rx_desc->callback_param = ourport;
 498         dma->rx_bytes_requested = dma->rx_size;
 499
 500         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 501         dma_async_issue_pending(dma->rx_chan);
 502 }
 503
 504 /* ? - where has parity gone?? */
 505 #define S3C2410_UERSTAT_PARITY (0x1000)
 506
 507 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 508 {
 509         struct uart_port *port = &ourport->port;
 510         unsigned int ucon;
 511
 512         /* set Rx mode to DMA mode */
 513         ucon = rd_regl(port, S3C2410_UCON);
 514         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 515                         S3C64XX_UCON_TIMEOUT_MASK |
 516                         S3C64XX_UCON_EMPTYINT_EN |
 517                         S3C64XX_UCON_DMASUS_EN |
 518                         S3C64XX_UCON_TIMEOUT_EN |
 519                         S3C64XX_UCON_RXMODE_MASK);
 520         ucon |= S3C64XX_UCON_RXBURST_16 |
 521                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 522                         S3C64XX_UCON_EMPTYINT_EN |
 523                         S3C64XX_UCON_TIMEOUT_EN |
 524                         S3C64XX_UCON_RXMODE_DMA;
 525         wr_regl(port, S3C2410_UCON, ucon);
 526
 527         ourport->rx_mode = S3C24XX_RX_DMA;
 528 }
 529
 530 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 531 {
 532         struct uart_port *port = &ourport->port;
 533         unsigned int ucon;
 534
 535         /* set Rx mode to DMA mode */
 536         ucon = rd_regl(port, S3C2410_UCON);
 537         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 538                         S3C64XX_UCON_EMPTYINT_EN |
 539                         S3C64XX_UCON_DMASUS_EN |
 540                         S3C64XX_UCON_TIMEOUT_EN |
 541                         S3C64XX_UCON_RXMODE_MASK);
 542         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 543                         S3C64XX_UCON_TIMEOUT_EN |
 544                         S3C64XX_UCON_RXMODE_CPU;
 545         wr_regl(port, S3C2410_UCON, ucon);
 546
 547         ourport->rx_mode = S3C24XX_RX_PIO;
 548 }
 549
 550 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 551
 552 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 553 {
 554         unsigned int utrstat, ufstat, received;
 555         struct s3c24xx_uart_port *ourport = dev_id;
 556         struct uart_port *port = &ourport->port;
 557         struct s3c24xx_uart_dma *dma = ourport->dma;
 558         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 559         struct tty_port *t = &port->state->port;
 560         unsigned long flags;
 561         struct dma_tx_state state;
 562
 563         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 564         ufstat = rd_regl(port, S3C2410_UFSTAT);
 565
 566         spin_lock_irqsave(&port->lock, flags);
 567
 568         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 569                 s3c64xx_start_rx_dma(ourport);
 570                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 571                         enable_rx_dma(ourport);
 572                 goto finish;
 573         }
 574
 575         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 576                 dmaengine_pause(dma->rx_chan);
 577                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 578                 dmaengine_terminate_all(dma->rx_chan);
 579                 received = dma->rx_bytes_requested - state.residue;
 580                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 581
 582                 enable_rx_pio(ourport);
 583         }
 584
 585         s3c24xx_serial_rx_drain_fifo(ourport);
 586
 587         if (tty) {
 588                 tty_flip_buffer_push(t);
 589                 tty_kref_put(tty);
 590         }
 591
 592         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 593
 594 finish:
 595         spin_unlock_irqrestore(&port->lock, flags);
 596
 597         return IRQ_HANDLED;
 598 }
 599
 600 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 601 {
 602         struct uart_port *port = &ourport->port;
 603         unsigned int ufcon, ch, flag, ufstat, uerstat;
 604         int max_count = port->fifosize;
 605
 606         while (max_count-- > 0) {
 607                 ufcon = rd_regl(port, S3C2410_UFCON);
 608                 ufstat = rd_regl(port, S3C2410_UFSTAT);
 609
 610                 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
 611                         break;
 612
 613                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 614                 ch = rd_regb(port, S3C2410_URXH);
 615
 616                 if (port->flags & UPF_CONS_FLOW) {
 617                         int txe = s3c24xx_serial_txempty_nofifo(port);
 618
 619                         if (rx_enabled(port)) {
 620                                 if (!txe) {
 621                                         rx_enabled(port) = 0;
 622                                         continue;
 623                                 }
 624                         } else {
 625                                 if (txe) {
 626                                         ufcon |= S3C2410_UFCON_RESETRX;
 627                                         wr_regl(port, S3C2410_UFCON, ufcon);
 628                                         rx_enabled(port) = 1;
 629                                         return;
 630                                 }
 631                                 continue;
 632                         }
 633                 }
 634
 635                 /* insert the character into the buffer */
 636
 637                 flag = TTY_NORMAL;
 638                 port->icount.rx++;
 639
 640                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 641                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 642                             ch, uerstat);
 643
 644                         /* check for break */
 645                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 646                                 dbg("break!\n");
 647                                 port->icount.brk++;
 648                                 if (uart_handle_break(port))
 649                                         continue; /* Ignore character */
 650                         }
 651
 652                         if (uerstat & S3C2410_UERSTAT_FRAME)
 653                                 port->icount.frame++;
 654                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 655                                 port->icount.overrun++;
 656
 657                         uerstat &= port->read_status_mask;
 658
 659                         if (uerstat & S3C2410_UERSTAT_BREAK)
 660                                 flag = TTY_BREAK;
 661                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 662                                 flag = TTY_PARITY;
 663                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 664                                             S3C2410_UERSTAT_OVERRUN))
 665                                 flag = TTY_FRAME;
 666                 }
 667
 668                 if (uart_handle_sysrq_char(port, ch))
 669                         continue; /* Ignore character */
 670
 671                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 672                                  ch, flag);
 673         }
 674
 675         tty_flip_buffer_push(&port->state->port);
 676 }
 677
 678 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 679 {
 680         struct s3c24xx_uart_port *ourport = dev_id;
 681         struct uart_port *port = &ourport->port;
 682         unsigned long flags;
 683
 684         spin_lock_irqsave(&port->lock, flags);
 685         s3c24xx_serial_rx_drain_fifo(ourport);
 686         spin_unlock_irqrestore(&port->lock, flags);
 687
 688         return IRQ_HANDLED;
 689 }
 690
 691
 692 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 693 {
 694         struct s3c24xx_uart_port *ourport = dev_id;
 695
 696         if (ourport->dma && ourport->dma->rx_chan)
 697                 return s3c24xx_serial_rx_chars_dma(dev_id);
 698         return s3c24xx_serial_rx_chars_pio(dev_id);
 699 }
 700
 701 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 702 {
 703         struct s3c24xx_uart_port *ourport = id;
 704         struct uart_port *port = &ourport->port;
 705         struct circ_buf *xmit = &port->state->xmit;
 706         unsigned long flags;
 707         int count, dma_count = 0;
 708
 709         spin_lock_irqsave(&port->lock, flags);
 710
 711         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 712
 713         if (ourport->dma && ourport->dma->tx_chan &&
 714             count >= ourport->min_dma_size) {
 715                 int align = dma_get_cache_alignment() -
 716                         (xmit->tail & (dma_get_cache_alignment() - 1));
 717                 if (count-align >= ourport->min_dma_size) {
 718                         dma_count = count-align;
 719                         count = align;
 720                 }
 721         }
 722
 723         if (port->x_char) {
 724                 wr_regb(port, S3C2410_UTXH, port->x_char);
 725                 port->icount.tx++;
 726                 port->x_char = 0;
 727                 goto out;
 728         }
 729
 730         /* if there isn't anything more to transmit, or the uart is now
 731          * stopped, disable the uart and exit
 732         */
 733
 734         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 735                 s3c24xx_serial_stop_tx(port);
 736                 goto out;
 737         }
 738
 739         /* try and drain the buffer... */
 740
 741         if (count > port->fifosize) {
 742                 count = port->fifosize;
 743                 dma_count = 0;
 744         }
 745
 746         while (!uart_circ_empty(xmit) && count > 0) {
 747                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 748                         break;
 749
 750                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 751                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 752                 port->icount.tx++;
 753                 count--;
 754         }
 755
 756         if (!count && dma_count) {
 757                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 758                 goto out;
 759         }
 760
 761         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 762                 spin_unlock(&port->lock);
 763                 uart_write_wakeup(port);
 764                 spin_lock(&port->lock);
 765         }
 766
 767         if (uart_circ_empty(xmit))
 768                 s3c24xx_serial_stop_tx(port);
 769
 770 out:
 771         spin_unlock_irqrestore(&port->lock, flags);
 772         return IRQ_HANDLED;
 773 }
 774
 775 /* interrupt handler for s3c64xx and later SoC's.*/
 776 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 777 {
 778         struct s3c24xx_uart_port *ourport = id;
 779         struct uart_port *port = &ourport->port;
 780         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 781         irqreturn_t ret = IRQ_HANDLED;
 782
 783         if (pend & S3C64XX_UINTM_RXD_MSK) {
 784                 ret = s3c24xx_serial_rx_chars(irq, id);
 785                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 786         }
 787         if (pend & S3C64XX_UINTM_TXD_MSK) {
 788                 ret = s3c24xx_serial_tx_chars(irq, id);
 789                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 790         }
 791         return ret;
 792 }
 793
 794 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 795 {
 796         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 797         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 798         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 799
 800         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 801                 if ((ufstat & info->tx_fifomask) != 0 ||
 802                     (ufstat & info->tx_fifofull))
 803                         return 0;
 804
 805                 return 1;
 806         }
 807
 808         return s3c24xx_serial_txempty_nofifo(port);
 809 }
 810
 811 /* no modem control lines */
 812 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 813 {
 814         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 815
 816         if (umstat & S3C2410_UMSTAT_CTS)
 817                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 818         else
 819                 return TIOCM_CAR | TIOCM_DSR;
 820 }
 821
 822 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 823 {
 824         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 825
 826         if (mctrl & TIOCM_RTS)
 827                 umcon |= S3C2410_UMCOM_RTS_LOW;
 828         else
 829                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 830
 831         wr_regl(port, S3C2410_UMCON, umcon);
 832 }
 833
 834 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 835 {
 836         unsigned long flags;
 837         unsigned int ucon;
 838
 839         spin_lock_irqsave(&port->lock, flags);
 840
 841         ucon = rd_regl(port, S3C2410_UCON);
 842
 843         if (break_state)
 844                 ucon |= S3C2410_UCON_SBREAK;
 845         else
 846                 ucon &= ~S3C2410_UCON_SBREAK;
 847
 848         wr_regl(port, S3C2410_UCON, ucon);
 849
 850         spin_unlock_irqrestore(&port->lock, flags);
 851 }
 852
 853 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 854 {
 855         struct s3c24xx_uart_dma *dma = p->dma;
 856         dma_cap_mask_t mask;
 857         unsigned long flags;
 858
 859         /* Default slave configuration parameters */
 860         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 861         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 862         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 863         dma->rx_conf.src_maxburst       = 1;
 864
 865         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 866         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 867         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 868         dma->tx_conf.dst_maxburst       = 1;
 869
 870         dma_cap_zero(mask);
 871         dma_cap_set(DMA_SLAVE, mask);
 872
 873         dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
 874                                         dma->rx_param, p->port.dev, "rx");
 875         if (!dma->rx_chan)
 876                 return -ENODEV;
 877
 878         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 879
 880         dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
 881                                         dma->tx_param, p->port.dev, "tx");
 882         if (!dma->tx_chan) {
 883                 dma_release_channel(dma->rx_chan);
 884                 return -ENODEV;
 885         }
 886
 887         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 888
 889         /* RX buffer */
 890         dma->rx_size = PAGE_SIZE;
 891
 892         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 893
 894         if (!dma->rx_buf) {
 895                 dma_release_channel(dma->rx_chan);
 896                 dma_release_channel(dma->tx_chan);
 897                 return -ENOMEM;
 898         }
 899
 900         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
 901                                 dma->rx_size, DMA_FROM_DEVICE);
 902
 903         spin_lock_irqsave(&p->port.lock, flags);
 904
 905         /* TX buffer */
 906         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
 907                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 908
 909         spin_unlock_irqrestore(&p->port.lock, flags);
 910
 911         return 0;
 912 }
 913
 914 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 915 {
 916         struct s3c24xx_uart_dma *dma = p->dma;
 917
 918         if (dma->rx_chan) {
 919                 dmaengine_terminate_all(dma->rx_chan);
 920                 dma_unmap_single(p->port.dev, dma->rx_addr,
 921                                 dma->rx_size, DMA_FROM_DEVICE);
 922                 kfree(dma->rx_buf);
 923                 dma_release_channel(dma->rx_chan);
 924                 dma->rx_chan = NULL;
 925         }
 926
 927         if (dma->tx_chan) {
 928                 dmaengine_terminate_all(dma->tx_chan);
 929                 dma_unmap_single(p->port.dev, dma->tx_addr,
 930                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 931                 dma_release_channel(dma->tx_chan);
 932                 dma->tx_chan = NULL;
 933         }
 934 }
 935
 936 static void s3c24xx_serial_shutdown(struct uart_port *port)
 937 {
 938         struct s3c24xx_uart_port *ourport = to_ourport(port);
 939
 940         if (ourport->tx_claimed) {
 941                 if (!s3c24xx_serial_has_interrupt_mask(port))
 942                         free_irq(ourport->tx_irq, ourport);
 943                 tx_enabled(port) = 0;
 944                 ourport->tx_claimed = 0;
 945                 ourport->tx_mode = 0;
 946         }
 947
 948         if (ourport->rx_claimed) {
 949                 if (!s3c24xx_serial_has_interrupt_mask(port))
 950                         free_irq(ourport->rx_irq, ourport);
 951                 ourport->rx_claimed = 0;
 952                 rx_enabled(port) = 0;
 953         }
 954
 955         /* Clear pending interrupts and mask all interrupts */
 956         if (s3c24xx_serial_has_interrupt_mask(port)) {
 957                 free_irq(port->irq, ourport);
 958
 959                 wr_regl(port, S3C64XX_UINTP, 0xf);
 960                 wr_regl(port, S3C64XX_UINTM, 0xf);
 961         }
 962
 963         if (ourport->dma)
 964                 s3c24xx_serial_release_dma(ourport);
 965
 966         ourport->tx_in_progress = 0;
 967 }
 968
 969 static int s3c24xx_serial_startup(struct uart_port *port)
 970 {
 971         struct s3c24xx_uart_port *ourport = to_ourport(port);
 972         int ret;
 973
 974         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
 975             port, (unsigned long long)port->mapbase, port->membase);
 976
 977         rx_enabled(port) = 1;
 978
 979         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
 980                           s3c24xx_serial_portname(port), ourport);
 981
 982         if (ret != 0) {
 983                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
 984                 return ret;
 985         }
 986
 987         ourport->rx_claimed = 1;
 988
 989         dbg("requesting tx irq...\n");
 990
 991         tx_enabled(port) = 1;
 992
 993         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
 994                           s3c24xx_serial_portname(port), ourport);
 995
 996         if (ret) {
 997                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
 998                 goto err;
 999         }
1000
1001         ourport->tx_claimed = 1;
1002
1003         dbg("s3c24xx_serial_startup ok\n");
1004
1005         /* the port reset code should have done the correct
1006          * register setup for the port controls */
1007
1008         return ret;
1009
1010 err:
1011         s3c24xx_serial_shutdown(port);
1012         return ret;
1013 }
1014
1015 static int s3c64xx_serial_startup(struct uart_port *port)
1016 {
1017         struct s3c24xx_uart_port *ourport = to_ourport(port);
1018         unsigned long flags;
1019         unsigned int ufcon;
1020         int ret;
1021
1022         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1023             port, (unsigned long long)port->mapbase, port->membase);
1024
1025         wr_regl(port, S3C64XX_UINTM, 0xf);
1026         if (ourport->dma) {
1027                 ret = s3c24xx_serial_request_dma(ourport);
1028                 if (ret < 0) {
1029                         dev_warn(port->dev,
1030                                  "DMA request failed, DMA will not be used\n");
1031                         devm_kfree(port->dev, ourport->dma);
1032                         ourport->dma = NULL;
1033                 }
1034         }
1035
1036         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1037                           s3c24xx_serial_portname(port), ourport);
1038         if (ret) {
1039                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1040                 return ret;
1041         }
1042
1043         /* For compatibility with s3c24xx Soc's */
1044         rx_enabled(port) = 1;
1045         ourport->rx_claimed = 1;
1046         tx_enabled(port) = 0;
1047         ourport->tx_claimed = 1;
1048
1049         spin_lock_irqsave(&port->lock, flags);
1050
1051         ufcon = rd_regl(port, S3C2410_UFCON);
1052         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1053         if (!uart_console(port))
1054                 ufcon |= S3C2410_UFCON_RESETTX;
1055         wr_regl(port, S3C2410_UFCON, ufcon);
1056
1057         enable_rx_pio(ourport);
1058
1059         spin_unlock_irqrestore(&port->lock, flags);
1060
1061         /* Enable Rx Interrupt */
1062         __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
1063
1064         dbg("s3c64xx_serial_startup ok\n");
1065         return ret;
1066 }
1067
1068 /* power power management control */
1069
1070 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1071                               unsigned int old)
1072 {
1073         struct s3c24xx_uart_port *ourport = to_ourport(port);
1074         int timeout = 10000;
1075
1076         ourport->pm_level = level;
1077
1078         switch (level) {
1079         case 3:
1080                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1081                         udelay(100);
1082
1083                 if (!IS_ERR(ourport->baudclk))
1084                         clk_disable_unprepare(ourport->baudclk);
1085
1086                 clk_disable_unprepare(ourport->clk);
1087                 break;
1088
1089         case 0:
1090                 clk_prepare_enable(ourport->clk);
1091
1092                 if (!IS_ERR(ourport->baudclk))
1093                         clk_prepare_enable(ourport->baudclk);
1094
1095                 break;
1096         default:
1097                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1098         }
1099 }
1100
1101 /* baud rate calculation
1102  *
1103  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1104  * of different sources, including the peripheral clock ("pclk") and an
1105  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1106  * with a programmable extra divisor.
1107  *
1108  * The following code goes through the clock sources, and calculates the
1109  * baud clocks (and the resultant actual baud rates) and then tries to
1110  * pick the closest one and select that.
1111  *
1112 */
1113
1114 #define MAX_CLK_NAME_LENGTH 15
1115
1116 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1117 {
1118         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1119         unsigned int ucon;
1120
1121         if (info->num_clks == 1)
1122                 return 0;
1123
1124         ucon = rd_regl(port, S3C2410_UCON);
1125         ucon &= info->clksel_mask;
1126         return ucon >> info->clksel_shift;
1127 }
1128
1129 static void s3c24xx_serial_setsource(struct uart_port *port,
1130                         unsigned int clk_sel)
1131 {
1132         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1133         unsigned int ucon;
1134
1135         if (info->num_clks == 1)
1136                 return;
1137
1138         ucon = rd_regl(port, S3C2410_UCON);
1139         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1140                 return;
1141
1142         ucon &= ~info->clksel_mask;
1143         ucon |= clk_sel << info->clksel_shift;
1144         wr_regl(port, S3C2410_UCON, ucon);
1145 }
1146
1147 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1148                         unsigned int req_baud, struct clk **best_clk,
1149                         unsigned int *clk_num)
1150 {
1151         struct s3c24xx_uart_info *info = ourport->info;
1152         struct clk *clk;
1153         unsigned long rate;
1154         unsigned int cnt, baud, quot, best_quot = 0;
1155         char clkname[MAX_CLK_NAME_LENGTH];
1156         int calc_deviation, deviation = (1 << 30) - 1;
1157
1158         for (cnt = 0; cnt < info->num_clks; cnt++) {
1159                 /* Keep selected clock if provided */
1160                 if (ourport->cfg->clk_sel &&
1161                         !(ourport->cfg->clk_sel & (1 << cnt)))
1162                         continue;
1163
1164                 sprintf(clkname, "clk_uart_baud%d", cnt);
1165                 clk = clk_get(ourport->port.dev, clkname);
1166                 if (IS_ERR(clk))
1167                         continue;
1168
1169                 rate = clk_get_rate(clk);
1170                 if (!rate)
1171                         continue;
1172
1173                 if (ourport->info->has_divslot) {
1174                         unsigned long div = rate / req_baud;
1175
1176                         /* The UDIVSLOT register on the newer UARTs allows us to
1177                          * get a divisor adjustment of 1/16th on the baud clock.
1178                          *
1179                          * We don't keep the UDIVSLOT value (the 16ths we
1180                          * calculated by not multiplying the baud by 16) as it
1181                          * is easy enough to recalculate.
1182                          */
1183
1184                         quot = div / 16;
1185                         baud = rate / div;
1186                 } else {
1187                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1188                         baud = rate / (quot * 16);
1189                 }
1190                 quot--;
1191
1192                 calc_deviation = req_baud - baud;
1193                 if (calc_deviation < 0)
1194                         calc_deviation = -calc_deviation;
1195
1196                 if (calc_deviation < deviation) {
1197                         *best_clk = clk;
1198                         best_quot = quot;
1199                         *clk_num = cnt;
1200                         deviation = calc_deviation;
1201                 }
1202         }
1203
1204         return best_quot;
1205 }
1206
1207 /* udivslot_table[]
1208  *
1209  * This table takes the fractional value of the baud divisor and gives
1210  * the recommended setting for the UDIVSLOT register.
1211  */
1212 static u16 udivslot_table[16] = {
1213         [0] = 0x0000,
1214         [1] = 0x0080,
1215         [2] = 0x0808,
1216         [3] = 0x0888,
1217         [4] = 0x2222,
1218         [5] = 0x4924,
1219         [6] = 0x4A52,
1220         [7] = 0x54AA,
1221         [8] = 0x5555,
1222         [9] = 0xD555,
1223         [10] = 0xD5D5,
1224         [11] = 0xDDD5,
1225         [12] = 0xDDDD,
1226         [13] = 0xDFDD,
1227         [14] = 0xDFDF,
1228         [15] = 0xFFDF,
1229 };
1230
1231 static void s3c24xx_serial_set_termios(struct uart_port *port,
1232                                        struct ktermios *termios,
1233                                        struct ktermios *old)
1234 {
1235         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1236         struct s3c24xx_uart_port *ourport = to_ourport(port);
1237         struct clk *clk = ERR_PTR(-EINVAL);
1238         unsigned long flags;
1239         unsigned int baud, quot, clk_sel = 0;
1240         unsigned int ulcon;
1241         unsigned int umcon;
1242         unsigned int udivslot = 0;
1243
1244         /*
1245          * We don't support modem control lines.
1246          */
1247         termios->c_cflag &= ~(HUPCL | CMSPAR);
1248         termios->c_cflag |= CLOCAL;
1249
1250         /*
1251          * Ask the core to calculate the divisor for us.
1252          */
1253
1254         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1255         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1256         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1257                 quot = port->custom_divisor;
1258         if (IS_ERR(clk))
1259                 return;
1260
1261         /* check to see if we need  to change clock source */
1262
1263         if (ourport->baudclk != clk) {
1264                 clk_prepare_enable(clk);
1265
1266                 s3c24xx_serial_setsource(port, clk_sel);
1267
1268                 if (!IS_ERR(ourport->baudclk)) {
1269                         clk_disable_unprepare(ourport->baudclk);
1270                         ourport->baudclk = ERR_PTR(-EINVAL);
1271                 }
1272
1273                 ourport->baudclk = clk;
1274                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1275         }
1276
1277         if (ourport->info->has_divslot) {
1278                 unsigned int div = ourport->baudclk_rate / baud;
1279
1280                 if (cfg->has_fracval) {
1281                         udivslot = (div & 15);
1282                         dbg("fracval = %04x\n", udivslot);
1283                 } else {
1284                         udivslot = udivslot_table[div & 15];
1285                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1286                 }
1287         }
1288
1289         switch (termios->c_cflag & CSIZE) {
1290         case CS5:
1291                 dbg("config: 5bits/char\n");
1292                 ulcon = S3C2410_LCON_CS5;
1293                 break;
1294         case CS6:
1295                 dbg("config: 6bits/char\n");
1296                 ulcon = S3C2410_LCON_CS6;
1297                 break;
1298         case CS7:
1299                 dbg("config: 7bits/char\n");
1300                 ulcon = S3C2410_LCON_CS7;
1301                 break;
1302         case CS8:
1303         default:
1304                 dbg("config: 8bits/char\n");
1305                 ulcon = S3C2410_LCON_CS8;
1306                 break;
1307         }
1308
1309         /* preserve original lcon IR settings */
1310         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1311
1312         if (termios->c_cflag & CSTOPB)
1313                 ulcon |= S3C2410_LCON_STOPB;
1314
1315         if (termios->c_cflag & PARENB) {
1316                 if (termios->c_cflag & PARODD)
1317                         ulcon |= S3C2410_LCON_PODD;
1318                 else
1319                         ulcon |= S3C2410_LCON_PEVEN;
1320         } else {
1321                 ulcon |= S3C2410_LCON_PNONE;
1322         }
1323
1324         spin_lock_irqsave(&port->lock, flags);
1325
1326         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1327             ulcon, quot, udivslot);
1328
1329         wr_regl(port, S3C2410_ULCON, ulcon);
1330         wr_regl(port, S3C2410_UBRDIV, quot);
1331
1332         port->status &= ~UPSTAT_AUTOCTS;
1333
1334         umcon = rd_regl(port, S3C2410_UMCON);
1335         if (termios->c_cflag & CRTSCTS) {
1336                 umcon |= S3C2410_UMCOM_AFC;
1337                 /* Disable RTS when RX FIFO contains 63 bytes */
1338                 umcon &= ~S3C2412_UMCON_AFC_8;
1339                 port->status = UPSTAT_AUTOCTS;
1340         } else {
1341                 umcon &= ~S3C2410_UMCOM_AFC;
1342         }
1343         wr_regl(port, S3C2410_UMCON, umcon);
1344
1345         if (ourport->info->has_divslot)
1346                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1347
1348         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1349             rd_regl(port, S3C2410_ULCON),
1350             rd_regl(port, S3C2410_UCON),
1351             rd_regl(port, S3C2410_UFCON));
1352
1353         /*
1354          * Update the per-port timeout.
1355          */
1356         uart_update_timeout(port, termios->c_cflag, baud);
1357
1358         /*
1359          * Which character status flags are we interested in?
1360          */
1361         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1362         if (termios->c_iflag & INPCK)
1363                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1364                         S3C2410_UERSTAT_PARITY;
1365         /*
1366          * Which character status flags should we ignore?
1367          */
1368         port->ignore_status_mask = 0;
1369         if (termios->c_iflag & IGNPAR)
1370                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1371         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1372                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1373
1374         /*
1375          * Ignore all characters if CREAD is not set.
1376          */
1377         if ((termios->c_cflag & CREAD) == 0)
1378                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1379
1380         spin_unlock_irqrestore(&port->lock, flags);
1381 }
1382
1383 static const char *s3c24xx_serial_type(struct uart_port *port)
1384 {
1385         switch (port->type) {
1386         case PORT_S3C2410:
1387                 return "S3C2410";
1388         case PORT_S3C2440:
1389                 return "S3C2440";
1390         case PORT_S3C2412:
1391                 return "S3C2412";
1392         case PORT_S3C6400:
1393                 return "S3C6400/10";
1394         default:
1395                 return NULL;
1396         }
1397 }
1398
1399 #define MAP_SIZE (0x100)
1400
1401 static void s3c24xx_serial_release_port(struct uart_port *port)
1402 {
1403         release_mem_region(port->mapbase, MAP_SIZE);
1404 }
1405
1406 static int s3c24xx_serial_request_port(struct uart_port *port)
1407 {
1408         const char *name = s3c24xx_serial_portname(port);
1409         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1410 }
1411
1412 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1413 {
1414         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1415
1416         if (flags & UART_CONFIG_TYPE &&
1417             s3c24xx_serial_request_port(port) == 0)
1418                 port->type = info->type;
1419 }
1420
1421 /*
1422  * verify the new serial_struct (for TIOCSSERIAL).
1423  */
1424 static int
1425 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1426 {
1427         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1428
1429         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1430                 return -EINVAL;
1431
1432         return 0;
1433 }
1434
1435
1436 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1437
1438 static struct console s3c24xx_serial_console;
1439
1440 static int __init s3c24xx_serial_console_init(void)
1441 {
1442         register_console(&s3c24xx_serial_console);
1443         return 0;
1444 }
1445 console_initcall(s3c24xx_serial_console_init);
1446
1447 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1448 #else
1449 #define S3C24XX_SERIAL_CONSOLE NULL
1450 #endif
1451
1452 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1453 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1454 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1455                          unsigned char c);
1456 #endif
1457
1458 static struct uart_ops s3c24xx_serial_ops = {
1459         .pm             = s3c24xx_serial_pm,
1460         .tx_empty       = s3c24xx_serial_tx_empty,
1461         .get_mctrl      = s3c24xx_serial_get_mctrl,
1462         .set_mctrl      = s3c24xx_serial_set_mctrl,
1463         .stop_tx        = s3c24xx_serial_stop_tx,
1464         .start_tx       = s3c24xx_serial_start_tx,
1465         .stop_rx        = s3c24xx_serial_stop_rx,
1466         .break_ctl      = s3c24xx_serial_break_ctl,
1467         .startup        = s3c24xx_serial_startup,
1468         .shutdown       = s3c24xx_serial_shutdown,
1469         .set_termios    = s3c24xx_serial_set_termios,
1470         .type           = s3c24xx_serial_type,
1471         .release_port   = s3c24xx_serial_release_port,
1472         .request_port   = s3c24xx_serial_request_port,
1473         .config_port    = s3c24xx_serial_config_port,
1474         .verify_port    = s3c24xx_serial_verify_port,
1475 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1476         .poll_get_char = s3c24xx_serial_get_poll_char,
1477         .poll_put_char = s3c24xx_serial_put_poll_char,
1478 #endif
1479 };
1480
1481 static struct uart_driver s3c24xx_uart_drv = {
1482         .owner          = THIS_MODULE,
1483         .driver_name    = "s3c2410_serial",
1484         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1485         .cons           = S3C24XX_SERIAL_CONSOLE,
1486         .dev_name       = S3C24XX_SERIAL_NAME,
1487         .major          = S3C24XX_SERIAL_MAJOR,
1488         .minor          = S3C24XX_SERIAL_MINOR,
1489 };
1490
1491 #define __PORT_LOCK_UNLOCKED(i) \
1492         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1493 static struct s3c24xx_uart_port
1494 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1495         [0] = {
1496                 .port = {
1497                         .lock           = __PORT_LOCK_UNLOCKED(0),
1498                         .iotype         = UPIO_MEM,
1499                         .uartclk        = 0,
1500                         .fifosize       = 16,
1501                         .ops            = &s3c24xx_serial_ops,
1502                         .flags          = UPF_BOOT_AUTOCONF,
1503                         .line           = 0,
1504                 }
1505         },
1506         [1] = {
1507                 .port = {
1508                         .lock           = __PORT_LOCK_UNLOCKED(1),
1509                         .iotype         = UPIO_MEM,
1510                         .uartclk        = 0,
1511                         .fifosize       = 16,
1512                         .ops            = &s3c24xx_serial_ops,
1513                         .flags          = UPF_BOOT_AUTOCONF,
1514                         .line           = 1,
1515                 }
1516         },
1517 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1518
1519         [2] = {
1520                 .port = {
1521                         .lock           = __PORT_LOCK_UNLOCKED(2),
1522                         .iotype         = UPIO_MEM,
1523                         .uartclk        = 0,
1524                         .fifosize       = 16,
1525                         .ops            = &s3c24xx_serial_ops,
1526                         .flags          = UPF_BOOT_AUTOCONF,
1527                         .line           = 2,
1528                 }
1529         },
1530 #endif
1531 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1532         [3] = {
1533                 .port = {
1534                         .lock           = __PORT_LOCK_UNLOCKED(3),
1535                         .iotype         = UPIO_MEM,
1536                         .uartclk        = 0,
1537                         .fifosize       = 16,
1538                         .ops            = &s3c24xx_serial_ops,
1539                         .flags          = UPF_BOOT_AUTOCONF,
1540                         .line           = 3,
1541                 }
1542         }
1543 #endif
1544 };
1545 #undef __PORT_LOCK_UNLOCKED
1546
1547 /* s3c24xx_serial_resetport
1548  *
1549  * reset the fifos and other the settings.
1550 */
1551
1552 static void s3c24xx_serial_resetport(struct uart_port *port,
1553                                    struct s3c2410_uartcfg *cfg)
1554 {
1555         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1556         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1557         unsigned int ucon_mask;
1558
1559         ucon_mask = info->clksel_mask;
1560         if (info->type == PORT_S3C2440)
1561                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1562
1563         ucon &= ucon_mask;
1564         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1565
1566         /* reset both fifos */
1567         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1568         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1569
1570         /* some delay is required after fifo reset */
1571         udelay(1);
1572 }
1573
1574
1575 #ifdef CONFIG_CPU_FREQ
1576
1577 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1578                                              unsigned long val, void *data)
1579 {
1580         struct s3c24xx_uart_port *port;
1581         struct uart_port *uport;
1582
1583         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1584         uport = &port->port;
1585
1586         /* check to see if port is enabled */
1587
1588         if (port->pm_level != 0)
1589                 return 0;
1590
1591         /* try and work out if the baudrate is changing, we can detect
1592          * a change in rate, but we do not have support for detecting
1593          * a disturbance in the clock-rate over the change.
1594          */
1595
1596         if (IS_ERR(port->baudclk))
1597                 goto exit;
1598
1599         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1600                 goto exit;
1601
1602         if (val == CPUFREQ_PRECHANGE) {
1603                 /* we should really shut the port down whilst the
1604                  * frequency change is in progress. */
1605
1606         } else if (val == CPUFREQ_POSTCHANGE) {
1607                 struct ktermios *termios;
1608                 struct tty_struct *tty;
1609
1610                 if (uport->state == NULL)
1611                         goto exit;
1612
1613                 tty = uport->state->port.tty;
1614
1615                 if (tty == NULL)
1616                         goto exit;
1617
1618                 termios = &tty->termios;
1619
1620                 if (termios == NULL) {
1621                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1622                         goto exit;
1623                 }
1624
1625                 s3c24xx_serial_set_termios(uport, termios, NULL);
1626         }
1627
1628 exit:
1629         return 0;
1630 }
1631
1632 static inline int
1633 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1634 {
1635         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1636
1637         return cpufreq_register_notifier(&port->freq_transition,
1638                                          CPUFREQ_TRANSITION_NOTIFIER);
1639 }
1640
1641 static inline void
1642 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1643 {
1644         cpufreq_unregister_notifier(&port->freq_transition,
1645                                     CPUFREQ_TRANSITION_NOTIFIER);
1646 }
1647
1648 #else
1649 static inline int
1650 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1651 {
1652         return 0;
1653 }
1654
1655 static inline void
1656 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1657 {
1658 }
1659 #endif
1660
1661 /* s3c24xx_serial_init_port
1662  *
1663  * initialise a single serial port from the platform device given
1664  */
1665
1666 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1667                                     struct platform_device *platdev)
1668 {
1669         struct uart_port *port = &ourport->port;
1670         struct s3c2410_uartcfg *cfg = ourport->cfg;
1671         struct resource *res;
1672         int ret;
1673
1674         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1675
1676         if (platdev == NULL)
1677                 return -ENODEV;
1678
1679         if (port->mapbase != 0)
1680                 return -EINVAL;
1681
1682         /* setup info for port */
1683         port->dev       = &platdev->dev;
1684
1685         /* Startup sequence is different for s3c64xx and higher SoC's */
1686         if (s3c24xx_serial_has_interrupt_mask(port))
1687                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1688
1689         port->uartclk = 1;
1690
1691         if (cfg->uart_flags & UPF_CONS_FLOW) {
1692                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1693                 port->flags |= UPF_CONS_FLOW;
1694         }
1695
1696         /* sort our the physical and virtual addresses for each UART */
1697
1698         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1699         if (res == NULL) {
1700                 dev_err(port->dev, "failed to find memory resource for uart\n");
1701                 return -EINVAL;
1702         }
1703
1704         dbg("resource %pR)\n", res);
1705
1706         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1707         if (!port->membase) {
1708                 dev_err(port->dev, "failed to remap controller address\n");
1709                 return -EBUSY;
1710         }
1711
1712         port->mapbase = res->start;
1713         ret = platform_get_irq(platdev, 0);
1714         if (ret < 0)
1715                 port->irq = 0;
1716         else {
1717                 port->irq = ret;
1718                 ourport->rx_irq = ret;
1719                 ourport->tx_irq = ret + 1;
1720         }
1721
1722         if (!s3c24xx_serial_has_interrupt_mask(port)) {
1723                 ret = platform_get_irq(platdev, 1);
1724                 if (ret > 0)
1725                         ourport->tx_irq = ret;
1726         }
1727         /*
1728          * DMA is currently supported only on DT platforms, if DMA properties
1729          * are specified.
1730          */
1731         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1732                                                      "dmas", NULL)) {
1733                 ourport->dma = devm_kzalloc(port->dev,
1734                                             sizeof(*ourport->dma),
1735                                             GFP_KERNEL);
1736                 if (!ourport->dma) {
1737                         ret = -ENOMEM;
1738                         goto err;
1739                 }
1740         }
1741
1742         ourport->clk    = clk_get(&platdev->dev, "uart");
1743         if (IS_ERR(ourport->clk)) {
1744                 pr_err("%s: Controller clock not found\n",
1745                                 dev_name(&platdev->dev));
1746                 ret = PTR_ERR(ourport->clk);
1747                 goto err;
1748         }
1749
1750         ret = clk_prepare_enable(ourport->clk);
1751         if (ret) {
1752                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1753                 clk_put(ourport->clk);
1754                 goto err;
1755         }
1756
1757         /* Keep all interrupts masked and cleared */
1758         if (s3c24xx_serial_has_interrupt_mask(port)) {
1759                 wr_regl(port, S3C64XX_UINTM, 0xf);
1760                 wr_regl(port, S3C64XX_UINTP, 0xf);
1761                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1762         }
1763
1764         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1765             &port->mapbase, port->membase, port->irq,
1766             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1767
1768         /* reset the fifos (and setup the uart) */
1769         s3c24xx_serial_resetport(port, cfg);
1770
1771         return 0;
1772
1773 err:
1774         port->mapbase = 0;
1775         return ret;
1776 }
1777
1778 /* Device driver serial port probe */
1779
1780 static const struct of_device_id s3c24xx_uart_dt_match[];
1781 static int probe_index;
1782
1783 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1784                         struct platform_device *pdev)
1785 {
1786 #ifdef CONFIG_OF
1787         if (pdev->dev.of_node) {
1788                 const struct of_device_id *match;
1789                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1790                 return (struct s3c24xx_serial_drv_data *)match->data;
1791         }
1792 #endif
1793         return (struct s3c24xx_serial_drv_data *)
1794                         platform_get_device_id(pdev)->driver_data;
1795 }
1796
1797 static int s3c24xx_serial_probe(struct platform_device *pdev)
1798 {
1799         struct device_node *np = pdev->dev.of_node;
1800         struct s3c24xx_uart_port *ourport;
1801         int index = probe_index;
1802         int ret;
1803
1804         if (np) {
1805                 ret = of_alias_get_id(np, "serial");
1806                 if (ret >= 0)
1807                         index = ret;
1808         }
1809
1810         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1811
1812         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1813                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1814                 return -EINVAL;
1815         }
1816         ourport = &s3c24xx_serial_ports[index];
1817
1818         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1819         if (!ourport->drv_data) {
1820                 dev_err(&pdev->dev, "could not find driver data\n");
1821                 return -ENODEV;
1822         }
1823
1824         ourport->baudclk = ERR_PTR(-EINVAL);
1825         ourport->info = ourport->drv_data->info;
1826         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1827                         dev_get_platdata(&pdev->dev) :
1828                         ourport->drv_data->def_cfg;
1829
1830         if (np)
1831                 of_property_read_u32(np,
1832                         "samsung,uart-fifosize", &ourport->port.fifosize);
1833
1834         if (ourport->drv_data->fifosize[index])
1835                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1836         else if (ourport->info->fifosize)
1837                 ourport->port.fifosize = ourport->info->fifosize;
1838
1839         /*
1840          * DMA transfers must be aligned at least to cache line size,
1841          * so find minimal transfer size suitable for DMA mode
1842          */
1843         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1844                                     dma_get_cache_alignment());
1845
1846         dbg("%s: initialising port %p...\n", __func__, ourport);
1847
1848         ret = s3c24xx_serial_init_port(ourport, pdev);
1849         if (ret < 0)
1850                 return ret;
1851
1852         if (!s3c24xx_uart_drv.state) {
1853                 ret = uart_register_driver(&s3c24xx_uart_drv);
1854                 if (ret < 0) {
1855                         pr_err("Failed to register Samsung UART driver\n");
1856                         return ret;
1857                 }
1858         }
1859
1860         dbg("%s: adding port\n", __func__);
1861         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1862         platform_set_drvdata(pdev, &ourport->port);
1863
1864         /*
1865          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1866          * so that a potential re-enablement through the pm-callback overlaps
1867          * and keeps the clock enabled in this case.
1868          */
1869         clk_disable_unprepare(ourport->clk);
1870
1871         ret = s3c24xx_serial_cpufreq_register(ourport);
1872         if (ret < 0)
1873                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1874
1875         probe_index++;
1876
1877         return 0;
1878 }
1879
1880 static int s3c24xx_serial_remove(struct platform_device *dev)
1881 {
1882         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1883
1884         if (port) {
1885                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1886                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1887         }
1888
1889         uart_unregister_driver(&s3c24xx_uart_drv);
1890
1891         return 0;
1892 }
1893
1894 /* UART power management code */
1895 #ifdef CONFIG_PM_SLEEP
1896 static int s3c24xx_serial_suspend(struct device *dev)
1897 {
1898         struct uart_port *port = s3c24xx_dev_to_port(dev);
1899
1900         if (port)
1901                 uart_suspend_port(&s3c24xx_uart_drv, port);
1902
1903         return 0;
1904 }
1905
1906 static int s3c24xx_serial_resume(struct device *dev)
1907 {
1908         struct uart_port *port = s3c24xx_dev_to_port(dev);
1909         struct s3c24xx_uart_port *ourport = to_ourport(port);
1910
1911         if (port) {
1912                 clk_prepare_enable(ourport->clk);
1913                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1914                 clk_disable_unprepare(ourport->clk);
1915
1916                 uart_resume_port(&s3c24xx_uart_drv, port);
1917         }
1918
1919         return 0;
1920 }
1921
1922 static int s3c24xx_serial_resume_noirq(struct device *dev)
1923 {
1924         struct uart_port *port = s3c24xx_dev_to_port(dev);
1925
1926         if (port) {
1927                 /* restore IRQ mask */
1928                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1929                         unsigned int uintm = 0xf;
1930                         if (tx_enabled(port))
1931                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1932                         if (rx_enabled(port))
1933                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1934                         wr_regl(port, S3C64XX_UINTM, uintm);
1935                 }
1936         }
1937
1938         return 0;
1939 }
1940
1941 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1942         .suspend = s3c24xx_serial_suspend,
1943         .resume = s3c24xx_serial_resume,
1944         .resume_noirq = s3c24xx_serial_resume_noirq,
1945 };
1946 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1947
1948 #else /* !CONFIG_PM_SLEEP */
1949
1950 #define SERIAL_SAMSUNG_PM_OPS   NULL
1951 #endif /* CONFIG_PM_SLEEP */
1952
1953 /* Console code */
1954
1955 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1956
1957 static struct uart_port *cons_uart;
1958
1959 static int
1960 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1961 {
1962         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1963         unsigned long ufstat, utrstat;
1964
1965         if (ufcon & S3C2410_UFCON_FIFOMODE) {
1966                 /* fifo mode - check amount of data in fifo registers... */
1967
1968                 ufstat = rd_regl(port, S3C2410_UFSTAT);
1969                 return (ufstat & info->tx_fifofull) ? 0 : 1;
1970         }
1971
1972         /* in non-fifo mode, we go and use the tx buffer empty */
1973
1974         utrstat = rd_regl(port, S3C2410_UTRSTAT);
1975         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1976 }
1977
1978 static bool
1979 s3c24xx_port_configured(unsigned int ucon)
1980 {
1981         /* consider the serial port configured if the tx/rx mode set */
1982         return (ucon & 0xf) != 0;
1983 }
1984
1985 #ifdef CONFIG_CONSOLE_POLL
1986 /*
1987  * Console polling routines for writing and reading from the uart while
1988  * in an interrupt or debug context.
1989  */
1990
1991 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1992 {
1993         struct s3c24xx_uart_port *ourport = to_ourport(port);
1994         unsigned int ufstat;
1995
1996         ufstat = rd_regl(port, S3C2410_UFSTAT);
1997         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1998                 return NO_POLL_CHAR;
1999
2000         return rd_regb(port, S3C2410_URXH);
2001 }
2002
2003 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2004                 unsigned char c)
2005 {
2006         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2007         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2008
2009         /* not possible to xmit on unconfigured port */
2010         if (!s3c24xx_port_configured(ucon))
2011                 return;
2012
2013         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2014                 cpu_relax();
2015         wr_regb(port, S3C2410_UTXH, c);
2016 }
2017
2018 #endif /* CONFIG_CONSOLE_POLL */
2019
2020 static void
2021 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2022 {
2023         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2024
2025         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2026                 cpu_relax();
2027         wr_regb(port, S3C2410_UTXH, ch);
2028 }
2029
2030 static void
2031 s3c24xx_serial_console_write(struct console *co, const char *s,
2032                              unsigned int count)
2033 {
2034         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2035
2036         /* not possible to xmit on unconfigured port */
2037         if (!s3c24xx_port_configured(ucon))
2038                 return;
2039
2040         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2041 }
2042
2043 static void __init
2044 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2045                            int *parity, int *bits)
2046 {
2047         struct clk *clk;
2048         unsigned int ulcon;
2049         unsigned int ucon;
2050         unsigned int ubrdiv;
2051         unsigned long rate;
2052         unsigned int clk_sel;
2053         char clk_name[MAX_CLK_NAME_LENGTH];
2054
2055         ulcon  = rd_regl(port, S3C2410_ULCON);
2056         ucon   = rd_regl(port, S3C2410_UCON);
2057         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2058
2059         dbg("s3c24xx_serial_get_options: port=%p\n"
2060             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2061             port, ulcon, ucon, ubrdiv);
2062
2063         if (s3c24xx_port_configured(ucon)) {
2064                 switch (ulcon & S3C2410_LCON_CSMASK) {
2065                 case S3C2410_LCON_CS5:
2066                         *bits = 5;
2067                         break;
2068                 case S3C2410_LCON_CS6:
2069                         *bits = 6;
2070                         break;
2071                 case S3C2410_LCON_CS7:
2072                         *bits = 7;
2073                         break;
2074                 case S3C2410_LCON_CS8:
2075                 default:
2076                         *bits = 8;
2077                         break;
2078                 }
2079
2080                 switch (ulcon & S3C2410_LCON_PMASK) {
2081                 case S3C2410_LCON_PEVEN:
2082                         *parity = 'e';
2083                         break;
2084
2085                 case S3C2410_LCON_PODD:
2086                         *parity = 'o';
2087                         break;
2088
2089                 case S3C2410_LCON_PNONE:
2090                 default:
2091                         *parity = 'n';
2092                 }
2093
2094                 /* now calculate the baud rate */
2095
2096                 clk_sel = s3c24xx_serial_getsource(port);
2097                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2098
2099                 clk = clk_get(port->dev, clk_name);
2100                 if (!IS_ERR(clk))
2101                         rate = clk_get_rate(clk);
2102                 else
2103                         rate = 1;
2104
2105                 *baud = rate / (16 * (ubrdiv + 1));
2106                 dbg("calculated baud %d\n", *baud);
2107         }
2108
2109 }
2110
2111 static int __init
2112 s3c24xx_serial_console_setup(struct console *co, char *options)
2113 {
2114         struct uart_port *port;
2115         int baud = 9600;
2116         int bits = 8;
2117         int parity = 'n';
2118         int flow = 'n';
2119
2120         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2121             co, co->index, options);
2122
2123         /* is this a valid port */
2124
2125         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2126                 co->index = 0;
2127
2128         port = &s3c24xx_serial_ports[co->index].port;
2129
2130         /* is the port configured? */
2131
2132         if (port->mapbase == 0x0)
2133                 return -ENODEV;
2134
2135         cons_uart = port;
2136
2137         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2138
2139         /*
2140          * Check whether an invalid uart number has been specified, and
2141          * if so, search for the first available port that does have
2142          * console support.
2143          */
2144         if (options)
2145                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2146         else
2147                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2148
2149         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2150
2151         return uart_set_options(port, co, baud, parity, bits, flow);
2152 }
2153
2154 static struct console s3c24xx_serial_console = {
2155         .name           = S3C24XX_SERIAL_NAME,
2156         .device         = uart_console_device,
2157         .flags          = CON_PRINTBUFFER,
2158         .index          = -1,
2159         .write          = s3c24xx_serial_console_write,
2160         .setup          = s3c24xx_serial_console_setup,
2161         .data           = &s3c24xx_uart_drv,
2162 };
2163 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2164
2165 #ifdef CONFIG_CPU_S3C2410
2166 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2167         .info = &(struct s3c24xx_uart_info) {
2168                 .name           = "Samsung S3C2410 UART",
2169                 .type           = PORT_S3C2410,
2170                 .fifosize       = 16,
2171                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2172                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2173                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2174                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2175                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2176                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2177                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2178                 .num_clks       = 2,
2179                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2180                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2181         },
2182         .def_cfg = &(struct s3c2410_uartcfg) {
2183                 .ucon           = S3C2410_UCON_DEFAULT,
2184                 .ufcon          = S3C2410_UFCON_DEFAULT,
2185         },
2186 };
2187 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2188 #else
2189 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2190 #endif
2191
2192 #ifdef CONFIG_CPU_S3C2412
2193 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2194         .info = &(struct s3c24xx_uart_info) {
2195                 .name           = "Samsung S3C2412 UART",
2196                 .type           = PORT_S3C2412,
2197                 .fifosize       = 64,
2198                 .has_divslot    = 1,
2199                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2200                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2201                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2202                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2203                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2204                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2205                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2206                 .num_clks       = 4,
2207                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2208                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2209         },
2210         .def_cfg = &(struct s3c2410_uartcfg) {
2211                 .ucon           = S3C2410_UCON_DEFAULT,
2212                 .ufcon          = S3C2410_UFCON_DEFAULT,
2213         },
2214 };
2215 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2216 #else
2217 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2218 #endif
2219
2220 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2221         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2222 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2223         .info = &(struct s3c24xx_uart_info) {
2224                 .name           = "Samsung S3C2440 UART",
2225                 .type           = PORT_S3C2440,
2226                 .fifosize       = 64,
2227                 .has_divslot    = 1,
2228                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2229                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2230                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2231                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2232                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2233                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2234                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2235                 .num_clks       = 4,
2236                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2237                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2238         },
2239         .def_cfg = &(struct s3c2410_uartcfg) {
2240                 .ucon           = S3C2410_UCON_DEFAULT,
2241                 .ufcon          = S3C2410_UFCON_DEFAULT,
2242         },
2243 };
2244 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2245 #else
2246 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2247 #endif
2248
2249 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2250 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2251         .info = &(struct s3c24xx_uart_info) {
2252                 .name           = "Samsung S3C6400 UART",
2253                 .type           = PORT_S3C6400,
2254                 .fifosize       = 64,
2255                 .has_divslot    = 1,
2256                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2257                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2258                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2259                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2260                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2261                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2262                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2263                 .num_clks       = 4,
2264                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2265                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2266         },
2267         .def_cfg = &(struct s3c2410_uartcfg) {
2268                 .ucon           = S3C2410_UCON_DEFAULT,
2269                 .ufcon          = S3C2410_UFCON_DEFAULT,
2270         },
2271 };
2272 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2273 #else
2274 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2275 #endif
2276
2277 #ifdef CONFIG_CPU_S5PV210
2278 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2279         .info = &(struct s3c24xx_uart_info) {
2280                 .name           = "Samsung S5PV210 UART",
2281                 .type           = PORT_S3C6400,
2282                 .has_divslot    = 1,
2283                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2284                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2285                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2286                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2287                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2288                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2289                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2290                 .num_clks       = 2,
2291                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2292                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2293         },
2294         .def_cfg = &(struct s3c2410_uartcfg) {
2295                 .ucon           = S5PV210_UCON_DEFAULT,
2296                 .ufcon          = S5PV210_UFCON_DEFAULT,
2297         },
2298         .fifosize = { 256, 64, 16, 16 },
2299 };
2300 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2301 #else
2302 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2303 #endif
2304
2305 #if defined(CONFIG_ARCH_EXYNOS)
2306 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2307         .info = &(struct s3c24xx_uart_info) {                   \
2308                 .name           = "Samsung Exynos UART",        \
2309                 .type           = PORT_S3C6400,                 \
2310                 .has_divslot    = 1,                            \
2311                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2312                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2313                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2314                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2315                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2316                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2317                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2318                 .num_clks       = 1,                            \
2319                 .clksel_mask    = 0,                            \
2320                 .clksel_shift   = 0,                            \
2321         },                                                      \
2322         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2323                 .ucon           = S5PV210_UCON_DEFAULT,         \
2324                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2325                 .has_fracval    = 1,                            \
2326         }                                                       \
2327
2328 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2329         EXYNOS_COMMON_SERIAL_DRV_DATA,
2330         .fifosize = { 256, 64, 16, 16 },
2331 };
2332
2333 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2334         EXYNOS_COMMON_SERIAL_DRV_DATA,
2335         .fifosize = { 64, 256, 16, 256 },
2336 };
2337
2338 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2339 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2340 #else
2341 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2342 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2343 #endif
2344
2345 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2346         {
2347                 .name           = "s3c2410-uart",
2348                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2349         }, {
2350                 .name           = "s3c2412-uart",
2351                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2352         }, {
2353                 .name           = "s3c2440-uart",
2354                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2355         }, {
2356                 .name           = "s3c6400-uart",
2357                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2358         }, {
2359                 .name           = "s5pv210-uart",
2360                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2361         }, {
2362                 .name           = "exynos4210-uart",
2363                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2364         }, {
2365                 .name           = "exynos5433-uart",
2366                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2367         },
2368         { },
2369 };
2370 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2371
2372 #ifdef CONFIG_OF
2373 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2374         { .compatible = "samsung,s3c2410-uart",
2375                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2376         { .compatible = "samsung,s3c2412-uart",
2377                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2378         { .compatible = "samsung,s3c2440-uart",
2379                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2380         { .compatible = "samsung,s3c6400-uart",
2381                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2382         { .compatible = "samsung,s5pv210-uart",
2383                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2384         { .compatible = "samsung,exynos4210-uart",
2385                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2386         { .compatible = "samsung,exynos5433-uart",
2387                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2388         {},
2389 };
2390 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2391 #endif
2392
2393 static struct platform_driver samsung_serial_driver = {
2394         .probe          = s3c24xx_serial_probe,
2395         .remove         = s3c24xx_serial_remove,
2396         .id_table       = s3c24xx_serial_driver_ids,
2397         .driver         = {
2398                 .name   = "samsung-uart",
2399                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2400                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2401         },
2402 };
2403
2404 module_platform_driver(samsung_serial_driver);
2405
2406 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2407 /*
2408  * Early console.
2409  */
2410
2411 struct samsung_early_console_data {
2412         u32 txfull_mask;
2413 };
2414
2415 static void samsung_early_busyuart(struct uart_port *port)
2416 {
2417         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2418                 ;
2419 }
2420
2421 static void samsung_early_busyuart_fifo(struct uart_port *port)
2422 {
2423         struct samsung_early_console_data *data = port->private_data;
2424
2425         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2426                 ;
2427 }
2428
2429 static void samsung_early_putc(struct uart_port *port, int c)
2430 {
2431         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2432                 samsung_early_busyuart_fifo(port);
2433         else
2434                 samsung_early_busyuart(port);
2435
2436         writeb(c, port->membase + S3C2410_UTXH);
2437 }
2438
2439 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2440 {
2441         struct earlycon_device *dev = con->data;
2442
2443         uart_console_write(&dev->port, s, n, samsung_early_putc);
2444 }
2445
2446 static int __init samsung_early_console_setup(struct earlycon_device *device,
2447                                               const char *opt)
2448 {
2449         if (!device->port.membase)
2450                 return -ENODEV;
2451
2452         device->con->write = samsung_early_write;
2453         return 0;
2454 }
2455
2456 /* S3C2410 */
2457 static struct samsung_early_console_data s3c2410_early_console_data = {
2458         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2459 };
2460
2461 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2462                                               const char *opt)
2463 {
2464         device->port.private_data = &s3c2410_early_console_data;
2465         return samsung_early_console_setup(device, opt);
2466 }
2467 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2468                         s3c2410_early_console_setup);
2469 EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup);
2470
2471 /* S3C2412, S3C2440, S3C64xx */
2472 static struct samsung_early_console_data s3c2440_early_console_data = {
2473         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2474 };
2475
2476 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2477                                               const char *opt)
2478 {
2479         device->port.private_data = &s3c2440_early_console_data;
2480         return samsung_early_console_setup(device, opt);
2481 }
2482 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2483                         s3c2440_early_console_setup);
2484 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2485                         s3c2440_early_console_setup);
2486 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2487                         s3c2440_early_console_setup);
2488 EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup);
2489 EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup);
2490 EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup);
2491
2492 /* S5PV210, EXYNOS */
2493 static struct samsung_early_console_data s5pv210_early_console_data = {
2494         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2495 };
2496
2497 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2498                                               const char *opt)
2499 {
2500         device->port.private_data = &s5pv210_early_console_data;
2501         return samsung_early_console_setup(device, opt);
2502 }
2503 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2504                         s5pv210_early_console_setup);
2505 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2506                         s5pv210_early_console_setup);
2507 EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup);
2508 EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup);
2509 #endif
2510
2511 MODULE_ALIAS("platform:samsung-uart");
2512 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2513 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2514 MODULE_LICENSE("GPL v2");