drivers/tty/serial/samsung.c

   1 /*
   2  * Driver core for Samsung SoC onboard UARTs.
   3  *
   4  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /* Hote on 2410 error handling
  13  *
  14  * The s3c2410 manual has a love/hate affair with the contents of the
  15  * UERSTAT register in the UART blocks, and keeps marking some of the
  16  * error bits as reserved. Having checked with the s3c2410x01,
  17  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  18  * feature from the latter versions of the manual.
  19  *
  20  * If it becomes aparrent that latter versions of the 2410 remove these
  21  * bits, then action will have to be taken to differentiate the versions
  22  * and change the policy on BREAK
  23  *
  24  * BJD, 04-Nov-2004
  25 */
  26
  27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  28 #define SUPPORT_SYSRQ
  29 #endif
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/ioport.h>
  36 #include <linux/io.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/init.h>
  39 #include <linux/sysrq.h>
  40 #include <linux/console.h>
  41 #include <linux/tty.h>
  42 #include <linux/tty_flip.h>
  43 #include <linux/serial_core.h>
  44 #include <linux/serial.h>
  45 #include <linux/serial_s3c.h>
  46 #include <linux/delay.h>
  47 #include <linux/clk.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/of.h>
  50
  51 #include <asm/irq.h>
  52
  53 #include "samsung.h"
  54
  55 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  56         !defined(MODULE)
  57
  58 extern void printascii(const char *);
  59
  60 __printf(1, 2)
  61 static void dbg(const char *fmt, ...)
  62 {
  63         va_list va;
  64         char buff[256];
  65
  66         va_start(va, fmt);
  67         vscnprintf(buff, sizeof(buff), fmt, va);
  68         va_end(va);
  69
  70         printascii(buff);
  71 }
  72
  73 #else
  74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  75 #endif
  76
  77 /* UART name and device definitions */
  78
  79 #define S3C24XX_SERIAL_NAME     "ttySAC"
  80 #define S3C24XX_SERIAL_MAJOR    204
  81 #define S3C24XX_SERIAL_MINOR    64
  82
  83 #define S3C24XX_TX_PIO                  1
  84 #define S3C24XX_TX_DMA                  2
  85 #define S3C24XX_RX_PIO                  1
  86 #define S3C24XX_RX_DMA                  2
  87 /* macros to change one thing to another */
  88
  89 #define tx_enabled(port) ((port)->unused[0])
  90 #define rx_enabled(port) ((port)->unused[1])
  91
  92 /* flag to ignore all characters coming in */
  93 #define RXSTAT_DUMMY_READ (0x10000000)
  94
  95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  96 {
  97         return container_of(port, struct s3c24xx_uart_port, port);
  98 }
  99
 100 /* translate a port to the device name */
 101
 102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 103 {
 104         return to_platform_device(port->dev)->name;
 105 }
 106
 107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 108 {
 109         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 110 }
 111
 112 /*
 113  * s3c64xx and later SoC's include the interrupt mask and status registers in
 114  * the controller itself, unlike the s3c24xx SoC's which have these registers
 115  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 116  */
 117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 118 {
 119         return to_ourport(port)->info->type == PORT_S3C6400;
 120 }
 121
 122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 123 {
 124         unsigned long flags;
 125         unsigned int ucon, ufcon;
 126         int count = 10000;
 127
 128         spin_lock_irqsave(&port->lock, flags);
 129
 130         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 131                 udelay(100);
 132
 133         ufcon = rd_regl(port, S3C2410_UFCON);
 134         ufcon |= S3C2410_UFCON_RESETRX;
 135         wr_regl(port, S3C2410_UFCON, ufcon);
 136
 137         ucon = rd_regl(port, S3C2410_UCON);
 138         ucon |= S3C2410_UCON_RXIRQMODE;
 139         wr_regl(port, S3C2410_UCON, ucon);
 140
 141         rx_enabled(port) = 1;
 142         spin_unlock_irqrestore(&port->lock, flags);
 143 }
 144
 145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 146 {
 147         unsigned long flags;
 148         unsigned int ucon;
 149
 150         spin_lock_irqsave(&port->lock, flags);
 151
 152         ucon = rd_regl(port, S3C2410_UCON);
 153         ucon &= ~S3C2410_UCON_RXIRQMODE;
 154         wr_regl(port, S3C2410_UCON, ucon);
 155
 156         rx_enabled(port) = 0;
 157         spin_unlock_irqrestore(&port->lock, flags);
 158 }
 159
 160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 161 {
 162         struct s3c24xx_uart_port *ourport = to_ourport(port);
 163         struct s3c24xx_uart_dma *dma = ourport->dma;
 164         struct circ_buf *xmit = &port->state->xmit;
 165         struct dma_tx_state state;
 166         int count;
 167
 168         if (!tx_enabled(port))
 169                 return;
 170
 171         if (s3c24xx_serial_has_interrupt_mask(port))
 172                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 173         else
 174                 disable_irq_nosync(ourport->tx_irq);
 175
 176         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 177                 dmaengine_pause(dma->tx_chan);
 178                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 179                 dmaengine_terminate_all(dma->tx_chan);
 180                 dma_sync_single_for_cpu(ourport->port.dev,
 181                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 182                 async_tx_ack(dma->tx_desc);
 183                 count = dma->tx_bytes_requested - state.residue;
 184                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 185                 port->icount.tx += count;
 186         }
 187
 188         tx_enabled(port) = 0;
 189         ourport->tx_in_progress = 0;
 190
 191         if (port->flags & UPF_CONS_FLOW)
 192                 s3c24xx_serial_rx_enable(port);
 193
 194         ourport->tx_mode = 0;
 195 }
 196
 197 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 198
 199 static void s3c24xx_serial_tx_dma_complete(void *args)
 200 {
 201         struct s3c24xx_uart_port *ourport = args;
 202         struct uart_port *port = &ourport->port;
 203         struct circ_buf *xmit = &port->state->xmit;
 204         struct s3c24xx_uart_dma *dma = ourport->dma;
 205         struct dma_tx_state state;
 206         unsigned long flags;
 207         int count;
 208
 209
 210         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 211         count = dma->tx_bytes_requested - state.residue;
 212         async_tx_ack(dma->tx_desc);
 213
 214         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 215                                 dma->tx_size, DMA_TO_DEVICE);
 216
 217         spin_lock_irqsave(&port->lock, flags);
 218
 219         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 220         port->icount.tx += count;
 221         ourport->tx_in_progress = 0;
 222
 223         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 224                 uart_write_wakeup(port);
 225
 226         s3c24xx_serial_start_next_tx(ourport);
 227         spin_unlock_irqrestore(&port->lock, flags);
 228 }
 229
 230 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 231 {
 232         struct uart_port *port = &ourport->port;
 233         u32 ucon;
 234
 235         /* Mask Tx interrupt */
 236         if (s3c24xx_serial_has_interrupt_mask(port))
 237                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 238         else
 239                 disable_irq_nosync(ourport->tx_irq);
 240
 241         /* Enable tx dma mode */
 242         ucon = rd_regl(port, S3C2410_UCON);
 243         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 244         ucon |= S3C64XX_UCON_TXBURST_1;
 245         ucon |= S3C64XX_UCON_TXMODE_DMA;
 246         wr_regl(port,  S3C2410_UCON, ucon);
 247
 248         ourport->tx_mode = S3C24XX_TX_DMA;
 249 }
 250
 251 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 252 {
 253         struct uart_port *port = &ourport->port;
 254         u32 ucon, ufcon;
 255
 256         /* Set ufcon txtrig */
 257         ourport->tx_in_progress = S3C24XX_TX_PIO;
 258         ufcon = rd_regl(port, S3C2410_UFCON);
 259         wr_regl(port,  S3C2410_UFCON, ufcon);
 260
 261         /* Enable tx pio mode */
 262         ucon = rd_regl(port, S3C2410_UCON);
 263         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 264         ucon |= S3C64XX_UCON_TXMODE_CPU;
 265         wr_regl(port,  S3C2410_UCON, ucon);
 266
 267         /* Unmask Tx interrupt */
 268         if (s3c24xx_serial_has_interrupt_mask(port))
 269                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 270                                   S3C64XX_UINTM);
 271         else
 272                 enable_irq(ourport->tx_irq);
 273
 274         ourport->tx_mode = S3C24XX_TX_PIO;
 275 }
 276
 277 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 278 {
 279         if (ourport->tx_mode != S3C24XX_TX_PIO)
 280                 enable_tx_pio(ourport);
 281 }
 282
 283 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 284                                       unsigned int count)
 285 {
 286         struct uart_port *port = &ourport->port;
 287         struct circ_buf *xmit = &port->state->xmit;
 288         struct s3c24xx_uart_dma *dma = ourport->dma;
 289
 290
 291         if (ourport->tx_mode != S3C24XX_TX_DMA)
 292                 enable_tx_dma(ourport);
 293
 294         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 295         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 296
 297         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 298                                 dma->tx_size, DMA_TO_DEVICE);
 299
 300         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 301                                 dma->tx_transfer_addr, dma->tx_size,
 302                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 303         if (!dma->tx_desc) {
 304                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 305                 return -EIO;
 306         }
 307
 308         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 309         dma->tx_desc->callback_param = ourport;
 310         dma->tx_bytes_requested = dma->tx_size;
 311
 312         ourport->tx_in_progress = S3C24XX_TX_DMA;
 313         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 314         dma_async_issue_pending(dma->tx_chan);
 315         return 0;
 316 }
 317
 318 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 319 {
 320         struct uart_port *port = &ourport->port;
 321         struct circ_buf *xmit = &port->state->xmit;
 322         unsigned long count;
 323
 324         /* Get data size up to the end of buffer */
 325         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 326
 327         if (!count) {
 328                 s3c24xx_serial_stop_tx(port);
 329                 return;
 330         }
 331
 332         if (!ourport->dma || !ourport->dma->tx_chan ||
 333             count < ourport->min_dma_size ||
 334             xmit->tail & (dma_get_cache_alignment() - 1))
 335                 s3c24xx_serial_start_tx_pio(ourport);
 336         else
 337                 s3c24xx_serial_start_tx_dma(ourport, count);
 338 }
 339
 340 static void s3c24xx_serial_start_tx(struct uart_port *port)
 341 {
 342         struct s3c24xx_uart_port *ourport = to_ourport(port);
 343         struct circ_buf *xmit = &port->state->xmit;
 344
 345         if (!tx_enabled(port)) {
 346                 if (port->flags & UPF_CONS_FLOW)
 347                         s3c24xx_serial_rx_disable(port);
 348
 349                 tx_enabled(port) = 1;
 350                 if (!ourport->dma || !ourport->dma->tx_chan)
 351                         s3c24xx_serial_start_tx_pio(ourport);
 352         }
 353
 354         if (ourport->dma && ourport->dma->tx_chan) {
 355                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 356                         s3c24xx_serial_start_next_tx(ourport);
 357         }
 358 }
 359
 360 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 361                 struct tty_port *tty, int count)
 362 {
 363         struct s3c24xx_uart_dma *dma = ourport->dma;
 364         int copied;
 365
 366         if (!count)
 367                 return;
 368
 369         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 370                                 dma->rx_size, DMA_FROM_DEVICE);
 371
 372         ourport->port.icount.rx += count;
 373         if (!tty) {
 374                 dev_err(ourport->port.dev, "No tty port\n");
 375                 return;
 376         }
 377         copied = tty_insert_flip_string(tty,
 378                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 379         if (copied != count) {
 380                 WARN_ON(1);
 381                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 382         }
 383 }
 384
 385 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 386 {
 387         struct s3c24xx_uart_port *ourport = to_ourport(port);
 388         struct s3c24xx_uart_dma *dma = ourport->dma;
 389         struct tty_port *t = &port->state->port;
 390         struct dma_tx_state state;
 391         enum dma_status dma_status;
 392         unsigned int received;
 393
 394         if (rx_enabled(port)) {
 395                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 396                 if (s3c24xx_serial_has_interrupt_mask(port))
 397                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 398                                         S3C64XX_UINTM);
 399                 else
 400                         disable_irq_nosync(ourport->rx_irq);
 401                 rx_enabled(port) = 0;
 402         }
 403         if (dma && dma->rx_chan) {
 404                 dmaengine_pause(dma->tx_chan);
 405                 dma_status = dmaengine_tx_status(dma->rx_chan,
 406                                 dma->rx_cookie, &state);
 407                 if (dma_status == DMA_IN_PROGRESS ||
 408                         dma_status == DMA_PAUSED) {
 409                         received = dma->rx_bytes_requested - state.residue;
 410                         dmaengine_terminate_all(dma->rx_chan);
 411                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 412                 }
 413         }
 414 }
 415
 416 static inline struct s3c24xx_uart_info
 417         *s3c24xx_port_to_info(struct uart_port *port)
 418 {
 419         return to_ourport(port)->info;
 420 }
 421
 422 static inline struct s3c2410_uartcfg
 423         *s3c24xx_port_to_cfg(struct uart_port *port)
 424 {
 425         struct s3c24xx_uart_port *ourport;
 426
 427         if (port->dev == NULL)
 428                 return NULL;
 429
 430         ourport = container_of(port, struct s3c24xx_uart_port, port);
 431         return ourport->cfg;
 432 }
 433
 434 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 435                                      unsigned long ufstat)
 436 {
 437         struct s3c24xx_uart_info *info = ourport->info;
 438
 439         if (ufstat & info->rx_fifofull)
 440                 return ourport->port.fifosize;
 441
 442         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 443 }
 444
 445 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 446 static void s3c24xx_serial_rx_dma_complete(void *args)
 447 {
 448         struct s3c24xx_uart_port *ourport = args;
 449         struct uart_port *port = &ourport->port;
 450
 451         struct s3c24xx_uart_dma *dma = ourport->dma;
 452         struct tty_port *t = &port->state->port;
 453         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 454
 455         struct dma_tx_state state;
 456         unsigned long flags;
 457         int received;
 458
 459         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 460         received  = dma->rx_bytes_requested - state.residue;
 461         async_tx_ack(dma->rx_desc);
 462
 463         spin_lock_irqsave(&port->lock, flags);
 464
 465         if (received)
 466                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 467
 468         if (tty) {
 469                 tty_flip_buffer_push(t);
 470                 tty_kref_put(tty);
 471         }
 472
 473         s3c64xx_start_rx_dma(ourport);
 474
 475         spin_unlock_irqrestore(&port->lock, flags);
 476 }
 477
 478 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 479 {
 480         struct s3c24xx_uart_dma *dma = ourport->dma;
 481
 482         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 483                                 dma->rx_size, DMA_FROM_DEVICE);
 484
 485         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 486                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 487                                 DMA_PREP_INTERRUPT);
 488         if (!dma->rx_desc) {
 489                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 490                 return;
 491         }
 492
 493         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 494         dma->rx_desc->callback_param = ourport;
 495         dma->rx_bytes_requested = dma->rx_size;
 496
 497         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 498         dma_async_issue_pending(dma->rx_chan);
 499 }
 500
 501 /* ? - where has parity gone?? */
 502 #define S3C2410_UERSTAT_PARITY (0x1000)
 503
 504 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 505 {
 506         struct uart_port *port = &ourport->port;
 507         unsigned int ucon;
 508
 509         /* set Rx mode to DMA mode */
 510         ucon = rd_regl(port, S3C2410_UCON);
 511         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 512                         S3C64XX_UCON_TIMEOUT_MASK |
 513                         S3C64XX_UCON_EMPTYINT_EN |
 514                         S3C64XX_UCON_DMASUS_EN |
 515                         S3C64XX_UCON_TIMEOUT_EN |
 516                         S3C64XX_UCON_RXMODE_MASK);
 517         ucon |= S3C64XX_UCON_RXBURST_1 |
 518                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 519                         S3C64XX_UCON_EMPTYINT_EN |
 520                         S3C64XX_UCON_TIMEOUT_EN |
 521                         S3C64XX_UCON_RXMODE_DMA;
 522         wr_regl(port, S3C2410_UCON, ucon);
 523
 524         ourport->rx_mode = S3C24XX_RX_DMA;
 525 }
 526
 527 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 528 {
 529         struct uart_port *port = &ourport->port;
 530         unsigned int ucon;
 531
 532         /* set Rx mode to DMA mode */
 533         ucon = rd_regl(port, S3C2410_UCON);
 534         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 535                         S3C64XX_UCON_EMPTYINT_EN |
 536                         S3C64XX_UCON_DMASUS_EN |
 537                         S3C64XX_UCON_TIMEOUT_EN |
 538                         S3C64XX_UCON_RXMODE_MASK);
 539         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 540                         S3C64XX_UCON_TIMEOUT_EN |
 541                         S3C64XX_UCON_RXMODE_CPU;
 542         wr_regl(port, S3C2410_UCON, ucon);
 543
 544         ourport->rx_mode = S3C24XX_RX_PIO;
 545 }
 546
 547 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 548
 549 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 550 {
 551         unsigned int utrstat, ufstat, received;
 552         struct s3c24xx_uart_port *ourport = dev_id;
 553         struct uart_port *port = &ourport->port;
 554         struct s3c24xx_uart_dma *dma = ourport->dma;
 555         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 556         struct tty_port *t = &port->state->port;
 557         unsigned long flags;
 558         struct dma_tx_state state;
 559
 560         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 561         ufstat = rd_regl(port, S3C2410_UFSTAT);
 562
 563         spin_lock_irqsave(&port->lock, flags);
 564
 565         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 566                 s3c64xx_start_rx_dma(ourport);
 567                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 568                         enable_rx_dma(ourport);
 569                 goto finish;
 570         }
 571
 572         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 573                 dmaengine_pause(dma->rx_chan);
 574                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 575                 dmaengine_terminate_all(dma->rx_chan);
 576                 received = dma->rx_bytes_requested - state.residue;
 577                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 578
 579                 enable_rx_pio(ourport);
 580         }
 581
 582         s3c24xx_serial_rx_drain_fifo(ourport);
 583
 584         if (tty) {
 585                 tty_flip_buffer_push(t);
 586                 tty_kref_put(tty);
 587         }
 588
 589         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 590
 591 finish:
 592         spin_unlock_irqrestore(&port->lock, flags);
 593
 594         return IRQ_HANDLED;
 595 }
 596
 597 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 598 {
 599         struct uart_port *port = &ourport->port;
 600         unsigned int ufcon, ch, flag, ufstat, uerstat;
 601         unsigned int fifocnt = 0;
 602         int max_count = port->fifosize;
 603
 604         while (max_count-- > 0) {
 605                 /*
 606                  * Receive all characters known to be in FIFO
 607                  * before reading FIFO level again
 608                  */
 609                 if (fifocnt == 0) {
 610                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 611                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 612                         if (fifocnt == 0)
 613                                 break;
 614                 }
 615                 fifocnt--;
 616
 617                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 618                 ch = rd_regb(port, S3C2410_URXH);
 619
 620                 if (port->flags & UPF_CONS_FLOW) {
 621                         int txe = s3c24xx_serial_txempty_nofifo(port);
 622
 623                         if (rx_enabled(port)) {
 624                                 if (!txe) {
 625                                         rx_enabled(port) = 0;
 626                                         continue;
 627                                 }
 628                         } else {
 629                                 if (txe) {
 630                                         ufcon = rd_regl(port, S3C2410_UFCON);
 631                                         ufcon |= S3C2410_UFCON_RESETRX;
 632                                         wr_regl(port, S3C2410_UFCON, ufcon);
 633                                         rx_enabled(port) = 1;
 634                                         return;
 635                                 }
 636                                 continue;
 637                         }
 638                 }
 639
 640                 /* insert the character into the buffer */
 641
 642                 flag = TTY_NORMAL;
 643                 port->icount.rx++;
 644
 645                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 646                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 647                             ch, uerstat);
 648
 649                         /* check for break */
 650                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 651                                 dbg("break!\n");
 652                                 port->icount.brk++;
 653                                 if (uart_handle_break(port))
 654                                         continue; /* Ignore character */
 655                         }
 656
 657                         if (uerstat & S3C2410_UERSTAT_FRAME)
 658                                 port->icount.frame++;
 659                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 660                                 port->icount.overrun++;
 661
 662                         uerstat &= port->read_status_mask;
 663
 664                         if (uerstat & S3C2410_UERSTAT_BREAK)
 665                                 flag = TTY_BREAK;
 666                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 667                                 flag = TTY_PARITY;
 668                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 669                                             S3C2410_UERSTAT_OVERRUN))
 670                                 flag = TTY_FRAME;
 671                 }
 672
 673                 if (uart_handle_sysrq_char(port, ch))
 674                         continue; /* Ignore character */
 675
 676                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 677                                  ch, flag);
 678         }
 679
 680         tty_flip_buffer_push(&port->state->port);
 681 }
 682
 683 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 684 {
 685         struct s3c24xx_uart_port *ourport = dev_id;
 686         struct uart_port *port = &ourport->port;
 687         unsigned long flags;
 688
 689         spin_lock_irqsave(&port->lock, flags);
 690         s3c24xx_serial_rx_drain_fifo(ourport);
 691         spin_unlock_irqrestore(&port->lock, flags);
 692
 693         return IRQ_HANDLED;
 694 }
 695
 696
 697 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 698 {
 699         struct s3c24xx_uart_port *ourport = dev_id;
 700
 701         if (ourport->dma && ourport->dma->rx_chan)
 702                 return s3c24xx_serial_rx_chars_dma(dev_id);
 703         return s3c24xx_serial_rx_chars_pio(dev_id);
 704 }
 705
 706 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 707 {
 708         struct s3c24xx_uart_port *ourport = id;
 709         struct uart_port *port = &ourport->port;
 710         struct circ_buf *xmit = &port->state->xmit;
 711         unsigned long flags;
 712         int count, dma_count = 0;
 713
 714         spin_lock_irqsave(&port->lock, flags);
 715
 716         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 717
 718         if (ourport->dma && ourport->dma->tx_chan &&
 719             count >= ourport->min_dma_size) {
 720                 int align = dma_get_cache_alignment() -
 721                         (xmit->tail & (dma_get_cache_alignment() - 1));
 722                 if (count-align >= ourport->min_dma_size) {
 723                         dma_count = count-align;
 724                         count = align;
 725                 }
 726         }
 727
 728         if (port->x_char) {
 729                 wr_regb(port, S3C2410_UTXH, port->x_char);
 730                 port->icount.tx++;
 731                 port->x_char = 0;
 732                 goto out;
 733         }
 734
 735         /* if there isn't anything more to transmit, or the uart is now
 736          * stopped, disable the uart and exit
 737         */
 738
 739         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 740                 s3c24xx_serial_stop_tx(port);
 741                 goto out;
 742         }
 743
 744         /* try and drain the buffer... */
 745
 746         if (count > port->fifosize) {
 747                 count = port->fifosize;
 748                 dma_count = 0;
 749         }
 750
 751         while (!uart_circ_empty(xmit) && count > 0) {
 752                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 753                         break;
 754
 755                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 756                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 757                 port->icount.tx++;
 758                 count--;
 759         }
 760
 761         if (!count && dma_count) {
 762                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 763                 goto out;
 764         }
 765
 766         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 767                 uart_write_wakeup(port);
 768
 769         if (uart_circ_empty(xmit))
 770                 s3c24xx_serial_stop_tx(port);
 771
 772 out:
 773         spin_unlock_irqrestore(&port->lock, flags);
 774         return IRQ_HANDLED;
 775 }
 776
 777 /* interrupt handler for s3c64xx and later SoC's.*/
 778 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 779 {
 780         struct s3c24xx_uart_port *ourport = id;
 781         struct uart_port *port = &ourport->port;
 782         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 783         irqreturn_t ret = IRQ_HANDLED;
 784
 785         if (pend & S3C64XX_UINTM_RXD_MSK) {
 786                 ret = s3c24xx_serial_rx_chars(irq, id);
 787                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 788         }
 789         if (pend & S3C64XX_UINTM_TXD_MSK) {
 790                 ret = s3c24xx_serial_tx_chars(irq, id);
 791                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 792         }
 793         return ret;
 794 }
 795
 796 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 797 {
 798         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 799         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 800         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 801
 802         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 803                 if ((ufstat & info->tx_fifomask) != 0 ||
 804                     (ufstat & info->tx_fifofull))
 805                         return 0;
 806
 807                 return 1;
 808         }
 809
 810         return s3c24xx_serial_txempty_nofifo(port);
 811 }
 812
 813 /* no modem control lines */
 814 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 815 {
 816         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 817
 818         if (umstat & S3C2410_UMSTAT_CTS)
 819                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 820         else
 821                 return TIOCM_CAR | TIOCM_DSR;
 822 }
 823
 824 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 825 {
 826         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 827
 828         if (mctrl & TIOCM_RTS)
 829                 umcon |= S3C2410_UMCOM_RTS_LOW;
 830         else
 831                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 832
 833         wr_regl(port, S3C2410_UMCON, umcon);
 834 }
 835
 836 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 837 {
 838         unsigned long flags;
 839         unsigned int ucon;
 840
 841         spin_lock_irqsave(&port->lock, flags);
 842
 843         ucon = rd_regl(port, S3C2410_UCON);
 844
 845         if (break_state)
 846                 ucon |= S3C2410_UCON_SBREAK;
 847         else
 848                 ucon &= ~S3C2410_UCON_SBREAK;
 849
 850         wr_regl(port, S3C2410_UCON, ucon);
 851
 852         spin_unlock_irqrestore(&port->lock, flags);
 853 }
 854
 855 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 856 {
 857         struct s3c24xx_uart_dma *dma = p->dma;
 858         int ret;
 859
 860         /* Default slave configuration parameters */
 861         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 862         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 863         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 864         dma->rx_conf.src_maxburst       = 1;
 865
 866         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 867         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 868         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 869         dma->tx_conf.dst_maxburst       = 1;
 870
 871         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 872
 873         if (IS_ERR(dma->rx_chan))
 874                 return PTR_ERR(dma->rx_chan);
 875
 876         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 877
 878         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
 879         if (IS_ERR(dma->tx_chan)) {
 880                 ret = PTR_ERR(dma->tx_chan);
 881                 goto err_release_rx;
 882         }
 883
 884         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 885
 886         /* RX buffer */
 887         dma->rx_size = PAGE_SIZE;
 888
 889         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 890         if (!dma->rx_buf) {
 891                 ret = -ENOMEM;
 892                 goto err_release_tx;
 893         }
 894
 895         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
 896                                 dma->rx_size, DMA_FROM_DEVICE);
 897         if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
 898                 ret = -EIO;
 899                 goto err_free_rx;
 900         }
 901
 902         /* TX buffer */
 903         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
 904                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 905         if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
 906                 ret = -EIO;
 907                 goto err_unmap_rx;
 908         }
 909
 910         return 0;
 911
 912 err_unmap_rx:
 913         dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
 914                          DMA_FROM_DEVICE);
 915 err_free_rx:
 916         kfree(dma->rx_buf);
 917 err_release_tx:
 918         dma_release_channel(dma->tx_chan);
 919 err_release_rx:
 920         dma_release_channel(dma->rx_chan);
 921         return ret;
 922 }
 923
 924 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 925 {
 926         struct s3c24xx_uart_dma *dma = p->dma;
 927
 928         if (dma->rx_chan) {
 929                 dmaengine_terminate_all(dma->rx_chan);
 930                 dma_unmap_single(p->port.dev, dma->rx_addr,
 931                                 dma->rx_size, DMA_FROM_DEVICE);
 932                 kfree(dma->rx_buf);
 933                 dma_release_channel(dma->rx_chan);
 934                 dma->rx_chan = NULL;
 935         }
 936
 937         if (dma->tx_chan) {
 938                 dmaengine_terminate_all(dma->tx_chan);
 939                 dma_unmap_single(p->port.dev, dma->tx_addr,
 940                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 941                 dma_release_channel(dma->tx_chan);
 942                 dma->tx_chan = NULL;
 943         }
 944 }
 945
 946 static void s3c24xx_serial_shutdown(struct uart_port *port)
 947 {
 948         struct s3c24xx_uart_port *ourport = to_ourport(port);
 949
 950         if (ourport->tx_claimed) {
 951                 if (!s3c24xx_serial_has_interrupt_mask(port))
 952                         free_irq(ourport->tx_irq, ourport);
 953                 tx_enabled(port) = 0;
 954                 ourport->tx_claimed = 0;
 955                 ourport->tx_mode = 0;
 956         }
 957
 958         if (ourport->rx_claimed) {
 959                 if (!s3c24xx_serial_has_interrupt_mask(port))
 960                         free_irq(ourport->rx_irq, ourport);
 961                 ourport->rx_claimed = 0;
 962                 rx_enabled(port) = 0;
 963         }
 964
 965         /* Clear pending interrupts and mask all interrupts */
 966         if (s3c24xx_serial_has_interrupt_mask(port)) {
 967                 free_irq(port->irq, ourport);
 968
 969                 wr_regl(port, S3C64XX_UINTP, 0xf);
 970                 wr_regl(port, S3C64XX_UINTM, 0xf);
 971         }
 972
 973         if (ourport->dma)
 974                 s3c24xx_serial_release_dma(ourport);
 975
 976         ourport->tx_in_progress = 0;
 977 }
 978
 979 static int s3c24xx_serial_startup(struct uart_port *port)
 980 {
 981         struct s3c24xx_uart_port *ourport = to_ourport(port);
 982         int ret;
 983
 984         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
 985             port, (unsigned long long)port->mapbase, port->membase);
 986
 987         rx_enabled(port) = 1;
 988
 989         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
 990                           s3c24xx_serial_portname(port), ourport);
 991
 992         if (ret != 0) {
 993                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
 994                 return ret;
 995         }
 996
 997         ourport->rx_claimed = 1;
 998
 999         dbg("requesting tx irq...\n");
1000
1001         tx_enabled(port) = 1;
1002
1003         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1004                           s3c24xx_serial_portname(port), ourport);
1005
1006         if (ret) {
1007                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1008                 goto err;
1009         }
1010
1011         ourport->tx_claimed = 1;
1012
1013         dbg("s3c24xx_serial_startup ok\n");
1014
1015         /* the port reset code should have done the correct
1016          * register setup for the port controls */
1017
1018         return ret;
1019
1020 err:
1021         s3c24xx_serial_shutdown(port);
1022         return ret;
1023 }
1024
1025 static int s3c64xx_serial_startup(struct uart_port *port)
1026 {
1027         struct s3c24xx_uart_port *ourport = to_ourport(port);
1028         unsigned long flags;
1029         unsigned int ufcon;
1030         int ret;
1031
1032         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1033             port, (unsigned long long)port->mapbase, port->membase);
1034
1035         wr_regl(port, S3C64XX_UINTM, 0xf);
1036         if (ourport->dma) {
1037                 ret = s3c24xx_serial_request_dma(ourport);
1038                 if (ret < 0) {
1039                         dev_warn(port->dev,
1040                                  "DMA request failed, DMA will not be used\n");
1041                         devm_kfree(port->dev, ourport->dma);
1042                         ourport->dma = NULL;
1043                 }
1044         }
1045
1046         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1047                           s3c24xx_serial_portname(port), ourport);
1048         if (ret) {
1049                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1050                 return ret;
1051         }
1052
1053         /* For compatibility with s3c24xx Soc's */
1054         rx_enabled(port) = 1;
1055         ourport->rx_claimed = 1;
1056         tx_enabled(port) = 0;
1057         ourport->tx_claimed = 1;
1058
1059         spin_lock_irqsave(&port->lock, flags);
1060
1061         ufcon = rd_regl(port, S3C2410_UFCON);
1062         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1063         if (!uart_console(port))
1064                 ufcon |= S3C2410_UFCON_RESETTX;
1065         wr_regl(port, S3C2410_UFCON, ufcon);
1066
1067         enable_rx_pio(ourport);
1068
1069         spin_unlock_irqrestore(&port->lock, flags);
1070
1071         /* Enable Rx Interrupt */
1072         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1073
1074         dbg("s3c64xx_serial_startup ok\n");
1075         return ret;
1076 }
1077
1078 /* power power management control */
1079
1080 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1081                               unsigned int old)
1082 {
1083         struct s3c24xx_uart_port *ourport = to_ourport(port);
1084         int timeout = 10000;
1085
1086         ourport->pm_level = level;
1087
1088         switch (level) {
1089         case 3:
1090                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1091                         udelay(100);
1092
1093                 if (!IS_ERR(ourport->baudclk))
1094                         clk_disable_unprepare(ourport->baudclk);
1095
1096                 clk_disable_unprepare(ourport->clk);
1097                 break;
1098
1099         case 0:
1100                 clk_prepare_enable(ourport->clk);
1101
1102                 if (!IS_ERR(ourport->baudclk))
1103                         clk_prepare_enable(ourport->baudclk);
1104
1105                 break;
1106         default:
1107                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1108         }
1109 }
1110
1111 /* baud rate calculation
1112  *
1113  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1114  * of different sources, including the peripheral clock ("pclk") and an
1115  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1116  * with a programmable extra divisor.
1117  *
1118  * The following code goes through the clock sources, and calculates the
1119  * baud clocks (and the resultant actual baud rates) and then tries to
1120  * pick the closest one and select that.
1121  *
1122 */
1123
1124 #define MAX_CLK_NAME_LENGTH 15
1125
1126 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1127 {
1128         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1129         unsigned int ucon;
1130
1131         if (info->num_clks == 1)
1132                 return 0;
1133
1134         ucon = rd_regl(port, S3C2410_UCON);
1135         ucon &= info->clksel_mask;
1136         return ucon >> info->clksel_shift;
1137 }
1138
1139 static void s3c24xx_serial_setsource(struct uart_port *port,
1140                         unsigned int clk_sel)
1141 {
1142         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1143         unsigned int ucon;
1144
1145         if (info->num_clks == 1)
1146                 return;
1147
1148         ucon = rd_regl(port, S3C2410_UCON);
1149         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1150                 return;
1151
1152         ucon &= ~info->clksel_mask;
1153         ucon |= clk_sel << info->clksel_shift;
1154         wr_regl(port, S3C2410_UCON, ucon);
1155 }
1156
1157 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1158                         unsigned int req_baud, struct clk **best_clk,
1159                         unsigned int *clk_num)
1160 {
1161         struct s3c24xx_uart_info *info = ourport->info;
1162         struct clk *clk;
1163         unsigned long rate;
1164         unsigned int cnt, baud, quot, best_quot = 0;
1165         char clkname[MAX_CLK_NAME_LENGTH];
1166         int calc_deviation, deviation = (1 << 30) - 1;
1167
1168         for (cnt = 0; cnt < info->num_clks; cnt++) {
1169                 /* Keep selected clock if provided */
1170                 if (ourport->cfg->clk_sel &&
1171                         !(ourport->cfg->clk_sel & (1 << cnt)))
1172                         continue;
1173
1174                 sprintf(clkname, "clk_uart_baud%d", cnt);
1175                 clk = clk_get(ourport->port.dev, clkname);
1176                 if (IS_ERR(clk))
1177                         continue;
1178
1179                 rate = clk_get_rate(clk);
1180                 if (!rate)
1181                         continue;
1182
1183                 if (ourport->info->has_divslot) {
1184                         unsigned long div = rate / req_baud;
1185
1186                         /* The UDIVSLOT register on the newer UARTs allows us to
1187                          * get a divisor adjustment of 1/16th on the baud clock.
1188                          *
1189                          * We don't keep the UDIVSLOT value (the 16ths we
1190                          * calculated by not multiplying the baud by 16) as it
1191                          * is easy enough to recalculate.
1192                          */
1193
1194                         quot = div / 16;
1195                         baud = rate / div;
1196                 } else {
1197                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1198                         baud = rate / (quot * 16);
1199                 }
1200                 quot--;
1201
1202                 calc_deviation = req_baud - baud;
1203                 if (calc_deviation < 0)
1204                         calc_deviation = -calc_deviation;
1205
1206                 if (calc_deviation < deviation) {
1207                         *best_clk = clk;
1208                         best_quot = quot;
1209                         *clk_num = cnt;
1210                         deviation = calc_deviation;
1211                 }
1212         }
1213
1214         return best_quot;
1215 }
1216
1217 /* udivslot_table[]
1218  *
1219  * This table takes the fractional value of the baud divisor and gives
1220  * the recommended setting for the UDIVSLOT register.
1221  */
1222 static u16 udivslot_table[16] = {
1223         [0] = 0x0000,
1224         [1] = 0x0080,
1225         [2] = 0x0808,
1226         [3] = 0x0888,
1227         [4] = 0x2222,
1228         [5] = 0x4924,
1229         [6] = 0x4A52,
1230         [7] = 0x54AA,
1231         [8] = 0x5555,
1232         [9] = 0xD555,
1233         [10] = 0xD5D5,
1234         [11] = 0xDDD5,
1235         [12] = 0xDDDD,
1236         [13] = 0xDFDD,
1237         [14] = 0xDFDF,
1238         [15] = 0xFFDF,
1239 };
1240
1241 static void s3c24xx_serial_set_termios(struct uart_port *port,
1242                                        struct ktermios *termios,
1243                                        struct ktermios *old)
1244 {
1245         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1246         struct s3c24xx_uart_port *ourport = to_ourport(port);
1247         struct clk *clk = ERR_PTR(-EINVAL);
1248         unsigned long flags;
1249         unsigned int baud, quot, clk_sel = 0;
1250         unsigned int ulcon;
1251         unsigned int umcon;
1252         unsigned int udivslot = 0;
1253
1254         /*
1255          * We don't support modem control lines.
1256          */
1257         termios->c_cflag &= ~(HUPCL | CMSPAR);
1258         termios->c_cflag |= CLOCAL;
1259
1260         /*
1261          * Ask the core to calculate the divisor for us.
1262          */
1263
1264         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1265         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1266         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1267                 quot = port->custom_divisor;
1268         if (IS_ERR(clk))
1269                 return;
1270
1271         /* check to see if we need  to change clock source */
1272
1273         if (ourport->baudclk != clk) {
1274                 clk_prepare_enable(clk);
1275
1276                 s3c24xx_serial_setsource(port, clk_sel);
1277
1278                 if (!IS_ERR(ourport->baudclk)) {
1279                         clk_disable_unprepare(ourport->baudclk);
1280                         ourport->baudclk = ERR_PTR(-EINVAL);
1281                 }
1282
1283                 ourport->baudclk = clk;
1284                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1285         }
1286
1287         if (ourport->info->has_divslot) {
1288                 unsigned int div = ourport->baudclk_rate / baud;
1289
1290                 if (cfg->has_fracval) {
1291                         udivslot = (div & 15);
1292                         dbg("fracval = %04x\n", udivslot);
1293                 } else {
1294                         udivslot = udivslot_table[div & 15];
1295                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1296                 }
1297         }
1298
1299         switch (termios->c_cflag & CSIZE) {
1300         case CS5:
1301                 dbg("config: 5bits/char\n");
1302                 ulcon = S3C2410_LCON_CS5;
1303                 break;
1304         case CS6:
1305                 dbg("config: 6bits/char\n");
1306                 ulcon = S3C2410_LCON_CS6;
1307                 break;
1308         case CS7:
1309                 dbg("config: 7bits/char\n");
1310                 ulcon = S3C2410_LCON_CS7;
1311                 break;
1312         case CS8:
1313         default:
1314                 dbg("config: 8bits/char\n");
1315                 ulcon = S3C2410_LCON_CS8;
1316                 break;
1317         }
1318
1319         /* preserve original lcon IR settings */
1320         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1321
1322         if (termios->c_cflag & CSTOPB)
1323                 ulcon |= S3C2410_LCON_STOPB;
1324
1325         if (termios->c_cflag & PARENB) {
1326                 if (termios->c_cflag & PARODD)
1327                         ulcon |= S3C2410_LCON_PODD;
1328                 else
1329                         ulcon |= S3C2410_LCON_PEVEN;
1330         } else {
1331                 ulcon |= S3C2410_LCON_PNONE;
1332         }
1333
1334         spin_lock_irqsave(&port->lock, flags);
1335
1336         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1337             ulcon, quot, udivslot);
1338
1339         wr_regl(port, S3C2410_ULCON, ulcon);
1340         wr_regl(port, S3C2410_UBRDIV, quot);
1341
1342         port->status &= ~UPSTAT_AUTOCTS;
1343
1344         umcon = rd_regl(port, S3C2410_UMCON);
1345         if (termios->c_cflag & CRTSCTS) {
1346                 umcon |= S3C2410_UMCOM_AFC;
1347                 /* Disable RTS when RX FIFO contains 63 bytes */
1348                 umcon &= ~S3C2412_UMCON_AFC_8;
1349                 port->status = UPSTAT_AUTOCTS;
1350         } else {
1351                 umcon &= ~S3C2410_UMCOM_AFC;
1352         }
1353         wr_regl(port, S3C2410_UMCON, umcon);
1354
1355         if (ourport->info->has_divslot)
1356                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1357
1358         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1359             rd_regl(port, S3C2410_ULCON),
1360             rd_regl(port, S3C2410_UCON),
1361             rd_regl(port, S3C2410_UFCON));
1362
1363         /*
1364          * Update the per-port timeout.
1365          */
1366         uart_update_timeout(port, termios->c_cflag, baud);
1367
1368         /*
1369          * Which character status flags are we interested in?
1370          */
1371         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1372         if (termios->c_iflag & INPCK)
1373                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1374                         S3C2410_UERSTAT_PARITY;
1375         /*
1376          * Which character status flags should we ignore?
1377          */
1378         port->ignore_status_mask = 0;
1379         if (termios->c_iflag & IGNPAR)
1380                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1381         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1382                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1383
1384         /*
1385          * Ignore all characters if CREAD is not set.
1386          */
1387         if ((termios->c_cflag & CREAD) == 0)
1388                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1389
1390         spin_unlock_irqrestore(&port->lock, flags);
1391 }
1392
1393 static const char *s3c24xx_serial_type(struct uart_port *port)
1394 {
1395         switch (port->type) {
1396         case PORT_S3C2410:
1397                 return "S3C2410";
1398         case PORT_S3C2440:
1399                 return "S3C2440";
1400         case PORT_S3C2412:
1401                 return "S3C2412";
1402         case PORT_S3C6400:
1403                 return "S3C6400/10";
1404         default:
1405                 return NULL;
1406         }
1407 }
1408
1409 #define MAP_SIZE (0x100)
1410
1411 static void s3c24xx_serial_release_port(struct uart_port *port)
1412 {
1413         release_mem_region(port->mapbase, MAP_SIZE);
1414 }
1415
1416 static int s3c24xx_serial_request_port(struct uart_port *port)
1417 {
1418         const char *name = s3c24xx_serial_portname(port);
1419         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1420 }
1421
1422 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1423 {
1424         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1425
1426         if (flags & UART_CONFIG_TYPE &&
1427             s3c24xx_serial_request_port(port) == 0)
1428                 port->type = info->type;
1429 }
1430
1431 /*
1432  * verify the new serial_struct (for TIOCSSERIAL).
1433  */
1434 static int
1435 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1436 {
1437         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1438
1439         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1440                 return -EINVAL;
1441
1442         return 0;
1443 }
1444
1445
1446 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1447
1448 static struct console s3c24xx_serial_console;
1449
1450 static int __init s3c24xx_serial_console_init(void)
1451 {
1452         register_console(&s3c24xx_serial_console);
1453         return 0;
1454 }
1455 console_initcall(s3c24xx_serial_console_init);
1456
1457 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1458 #else
1459 #define S3C24XX_SERIAL_CONSOLE NULL
1460 #endif
1461
1462 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1463 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1464 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1465                          unsigned char c);
1466 #endif
1467
1468 static struct uart_ops s3c24xx_serial_ops = {
1469         .pm             = s3c24xx_serial_pm,
1470         .tx_empty       = s3c24xx_serial_tx_empty,
1471         .get_mctrl      = s3c24xx_serial_get_mctrl,
1472         .set_mctrl      = s3c24xx_serial_set_mctrl,
1473         .stop_tx        = s3c24xx_serial_stop_tx,
1474         .start_tx       = s3c24xx_serial_start_tx,
1475         .stop_rx        = s3c24xx_serial_stop_rx,
1476         .break_ctl      = s3c24xx_serial_break_ctl,
1477         .startup        = s3c24xx_serial_startup,
1478         .shutdown       = s3c24xx_serial_shutdown,
1479         .set_termios    = s3c24xx_serial_set_termios,
1480         .type           = s3c24xx_serial_type,
1481         .release_port   = s3c24xx_serial_release_port,
1482         .request_port   = s3c24xx_serial_request_port,
1483         .config_port    = s3c24xx_serial_config_port,
1484         .verify_port    = s3c24xx_serial_verify_port,
1485 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1486         .poll_get_char = s3c24xx_serial_get_poll_char,
1487         .poll_put_char = s3c24xx_serial_put_poll_char,
1488 #endif
1489 };
1490
1491 static struct uart_driver s3c24xx_uart_drv = {
1492         .owner          = THIS_MODULE,
1493         .driver_name    = "s3c2410_serial",
1494         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1495         .cons           = S3C24XX_SERIAL_CONSOLE,
1496         .dev_name       = S3C24XX_SERIAL_NAME,
1497         .major          = S3C24XX_SERIAL_MAJOR,
1498         .minor          = S3C24XX_SERIAL_MINOR,
1499 };
1500
1501 #define __PORT_LOCK_UNLOCKED(i) \
1502         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1503 static struct s3c24xx_uart_port
1504 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1505         [0] = {
1506                 .port = {
1507                         .lock           = __PORT_LOCK_UNLOCKED(0),
1508                         .iotype         = UPIO_MEM,
1509                         .uartclk        = 0,
1510                         .fifosize       = 16,
1511                         .ops            = &s3c24xx_serial_ops,
1512                         .flags          = UPF_BOOT_AUTOCONF,
1513                         .line           = 0,
1514                 }
1515         },
1516         [1] = {
1517                 .port = {
1518                         .lock           = __PORT_LOCK_UNLOCKED(1),
1519                         .iotype         = UPIO_MEM,
1520                         .uartclk        = 0,
1521                         .fifosize       = 16,
1522                         .ops            = &s3c24xx_serial_ops,
1523                         .flags          = UPF_BOOT_AUTOCONF,
1524                         .line           = 1,
1525                 }
1526         },
1527 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1528
1529         [2] = {
1530                 .port = {
1531                         .lock           = __PORT_LOCK_UNLOCKED(2),
1532                         .iotype         = UPIO_MEM,
1533                         .uartclk        = 0,
1534                         .fifosize       = 16,
1535                         .ops            = &s3c24xx_serial_ops,
1536                         .flags          = UPF_BOOT_AUTOCONF,
1537                         .line           = 2,
1538                 }
1539         },
1540 #endif
1541 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1542         [3] = {
1543                 .port = {
1544                         .lock           = __PORT_LOCK_UNLOCKED(3),
1545                         .iotype         = UPIO_MEM,
1546                         .uartclk        = 0,
1547                         .fifosize       = 16,
1548                         .ops            = &s3c24xx_serial_ops,
1549                         .flags          = UPF_BOOT_AUTOCONF,
1550                         .line           = 3,
1551                 }
1552         }
1553 #endif
1554 };
1555 #undef __PORT_LOCK_UNLOCKED
1556
1557 /* s3c24xx_serial_resetport
1558  *
1559  * reset the fifos and other the settings.
1560 */
1561
1562 static void s3c24xx_serial_resetport(struct uart_port *port,
1563                                    struct s3c2410_uartcfg *cfg)
1564 {
1565         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1566         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1567         unsigned int ucon_mask;
1568
1569         ucon_mask = info->clksel_mask;
1570         if (info->type == PORT_S3C2440)
1571                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1572
1573         ucon &= ucon_mask;
1574         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1575
1576         /* reset both fifos */
1577         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1578         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1579
1580         /* some delay is required after fifo reset */
1581         udelay(1);
1582 }
1583
1584
1585 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1586
1587 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1588                                              unsigned long val, void *data)
1589 {
1590         struct s3c24xx_uart_port *port;
1591         struct uart_port *uport;
1592
1593         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1594         uport = &port->port;
1595
1596         /* check to see if port is enabled */
1597
1598         if (port->pm_level != 0)
1599                 return 0;
1600
1601         /* try and work out if the baudrate is changing, we can detect
1602          * a change in rate, but we do not have support for detecting
1603          * a disturbance in the clock-rate over the change.
1604          */
1605
1606         if (IS_ERR(port->baudclk))
1607                 goto exit;
1608
1609         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1610                 goto exit;
1611
1612         if (val == CPUFREQ_PRECHANGE) {
1613                 /* we should really shut the port down whilst the
1614                  * frequency change is in progress. */
1615
1616         } else if (val == CPUFREQ_POSTCHANGE) {
1617                 struct ktermios *termios;
1618                 struct tty_struct *tty;
1619
1620                 if (uport->state == NULL)
1621                         goto exit;
1622
1623                 tty = uport->state->port.tty;
1624
1625                 if (tty == NULL)
1626                         goto exit;
1627
1628                 termios = &tty->termios;
1629
1630                 if (termios == NULL) {
1631                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1632                         goto exit;
1633                 }
1634
1635                 s3c24xx_serial_set_termios(uport, termios, NULL);
1636         }
1637
1638 exit:
1639         return 0;
1640 }
1641
1642 static inline int
1643 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1644 {
1645         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1646
1647         return cpufreq_register_notifier(&port->freq_transition,
1648                                          CPUFREQ_TRANSITION_NOTIFIER);
1649 }
1650
1651 static inline void
1652 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1653 {
1654         cpufreq_unregister_notifier(&port->freq_transition,
1655                                     CPUFREQ_TRANSITION_NOTIFIER);
1656 }
1657
1658 #else
1659 static inline int
1660 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1661 {
1662         return 0;
1663 }
1664
1665 static inline void
1666 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1667 {
1668 }
1669 #endif
1670
1671 /* s3c24xx_serial_init_port
1672  *
1673  * initialise a single serial port from the platform device given
1674  */
1675
1676 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1677                                     struct platform_device *platdev)
1678 {
1679         struct uart_port *port = &ourport->port;
1680         struct s3c2410_uartcfg *cfg = ourport->cfg;
1681         struct resource *res;
1682         int ret;
1683
1684         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1685
1686         if (platdev == NULL)
1687                 return -ENODEV;
1688
1689         if (port->mapbase != 0)
1690                 return -EINVAL;
1691
1692         /* setup info for port */
1693         port->dev       = &platdev->dev;
1694
1695         /* Startup sequence is different for s3c64xx and higher SoC's */
1696         if (s3c24xx_serial_has_interrupt_mask(port))
1697                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1698
1699         port->uartclk = 1;
1700
1701         if (cfg->uart_flags & UPF_CONS_FLOW) {
1702                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1703                 port->flags |= UPF_CONS_FLOW;
1704         }
1705
1706         /* sort our the physical and virtual addresses for each UART */
1707
1708         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1709         if (res == NULL) {
1710                 dev_err(port->dev, "failed to find memory resource for uart\n");
1711                 return -EINVAL;
1712         }
1713
1714         dbg("resource %pR)\n", res);
1715
1716         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1717         if (!port->membase) {
1718                 dev_err(port->dev, "failed to remap controller address\n");
1719                 return -EBUSY;
1720         }
1721
1722         port->mapbase = res->start;
1723         ret = platform_get_irq(platdev, 0);
1724         if (ret < 0)
1725                 port->irq = 0;
1726         else {
1727                 port->irq = ret;
1728                 ourport->rx_irq = ret;
1729                 ourport->tx_irq = ret + 1;
1730         }
1731
1732         if (!s3c24xx_serial_has_interrupt_mask(port)) {
1733                 ret = platform_get_irq(platdev, 1);
1734                 if (ret > 0)
1735                         ourport->tx_irq = ret;
1736         }
1737         /*
1738          * DMA is currently supported only on DT platforms, if DMA properties
1739          * are specified.
1740          */
1741         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1742                                                      "dmas", NULL)) {
1743                 ourport->dma = devm_kzalloc(port->dev,
1744                                             sizeof(*ourport->dma),
1745                                             GFP_KERNEL);
1746                 if (!ourport->dma) {
1747                         ret = -ENOMEM;
1748                         goto err;
1749                 }
1750         }
1751
1752         ourport->clk    = clk_get(&platdev->dev, "uart");
1753         if (IS_ERR(ourport->clk)) {
1754                 pr_err("%s: Controller clock not found\n",
1755                                 dev_name(&platdev->dev));
1756                 ret = PTR_ERR(ourport->clk);
1757                 goto err;
1758         }
1759
1760         ret = clk_prepare_enable(ourport->clk);
1761         if (ret) {
1762                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1763                 clk_put(ourport->clk);
1764                 goto err;
1765         }
1766
1767         /* Keep all interrupts masked and cleared */
1768         if (s3c24xx_serial_has_interrupt_mask(port)) {
1769                 wr_regl(port, S3C64XX_UINTM, 0xf);
1770                 wr_regl(port, S3C64XX_UINTP, 0xf);
1771                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1772         }
1773
1774         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1775             &port->mapbase, port->membase, port->irq,
1776             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1777
1778         /* reset the fifos (and setup the uart) */
1779         s3c24xx_serial_resetport(port, cfg);
1780
1781         return 0;
1782
1783 err:
1784         port->mapbase = 0;
1785         return ret;
1786 }
1787
1788 /* Device driver serial port probe */
1789
1790 static const struct of_device_id s3c24xx_uart_dt_match[];
1791 static int probe_index;
1792
1793 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1794                         struct platform_device *pdev)
1795 {
1796 #ifdef CONFIG_OF
1797         if (pdev->dev.of_node) {
1798                 const struct of_device_id *match;
1799                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1800                 return (struct s3c24xx_serial_drv_data *)match->data;
1801         }
1802 #endif
1803         return (struct s3c24xx_serial_drv_data *)
1804                         platform_get_device_id(pdev)->driver_data;
1805 }
1806
1807 static int s3c24xx_serial_probe(struct platform_device *pdev)
1808 {
1809         struct device_node *np = pdev->dev.of_node;
1810         struct s3c24xx_uart_port *ourport;
1811         int index = probe_index;
1812         int ret;
1813
1814         if (np) {
1815                 ret = of_alias_get_id(np, "serial");
1816                 if (ret >= 0)
1817                         index = ret;
1818         }
1819
1820         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1821
1822         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1823                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1824                 return -EINVAL;
1825         }
1826         ourport = &s3c24xx_serial_ports[index];
1827
1828         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1829         if (!ourport->drv_data) {
1830                 dev_err(&pdev->dev, "could not find driver data\n");
1831                 return -ENODEV;
1832         }
1833
1834         ourport->baudclk = ERR_PTR(-EINVAL);
1835         ourport->info = ourport->drv_data->info;
1836         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1837                         dev_get_platdata(&pdev->dev) :
1838                         ourport->drv_data->def_cfg;
1839
1840         if (np)
1841                 of_property_read_u32(np,
1842                         "samsung,uart-fifosize", &ourport->port.fifosize);
1843
1844         if (ourport->drv_data->fifosize[index])
1845                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1846         else if (ourport->info->fifosize)
1847                 ourport->port.fifosize = ourport->info->fifosize;
1848
1849         /*
1850          * DMA transfers must be aligned at least to cache line size,
1851          * so find minimal transfer size suitable for DMA mode
1852          */
1853         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1854                                     dma_get_cache_alignment());
1855
1856         dbg("%s: initialising port %p...\n", __func__, ourport);
1857
1858         ret = s3c24xx_serial_init_port(ourport, pdev);
1859         if (ret < 0)
1860                 return ret;
1861
1862         if (!s3c24xx_uart_drv.state) {
1863                 ret = uart_register_driver(&s3c24xx_uart_drv);
1864                 if (ret < 0) {
1865                         pr_err("Failed to register Samsung UART driver\n");
1866                         return ret;
1867                 }
1868         }
1869
1870         dbg("%s: adding port\n", __func__);
1871         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1872         platform_set_drvdata(pdev, &ourport->port);
1873
1874         /*
1875          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1876          * so that a potential re-enablement through the pm-callback overlaps
1877          * and keeps the clock enabled in this case.
1878          */
1879         clk_disable_unprepare(ourport->clk);
1880
1881         ret = s3c24xx_serial_cpufreq_register(ourport);
1882         if (ret < 0)
1883                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1884
1885         probe_index++;
1886
1887         return 0;
1888 }
1889
1890 static int s3c24xx_serial_remove(struct platform_device *dev)
1891 {
1892         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1893
1894         if (port) {
1895                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1896                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1897         }
1898
1899         uart_unregister_driver(&s3c24xx_uart_drv);
1900
1901         return 0;
1902 }
1903
1904 /* UART power management code */
1905 #ifdef CONFIG_PM_SLEEP
1906 static int s3c24xx_serial_suspend(struct device *dev)
1907 {
1908         struct uart_port *port = s3c24xx_dev_to_port(dev);
1909
1910         if (port)
1911                 uart_suspend_port(&s3c24xx_uart_drv, port);
1912
1913         return 0;
1914 }
1915
1916 static int s3c24xx_serial_resume(struct device *dev)
1917 {
1918         struct uart_port *port = s3c24xx_dev_to_port(dev);
1919         struct s3c24xx_uart_port *ourport = to_ourport(port);
1920
1921         if (port) {
1922                 clk_prepare_enable(ourport->clk);
1923                 if (!IS_ERR(ourport->baudclk))
1924                         clk_prepare_enable(ourport->baudclk);
1925                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1926                 if (!IS_ERR(ourport->baudclk))
1927                         clk_disable_unprepare(ourport->baudclk);
1928                 clk_disable_unprepare(ourport->clk);
1929
1930                 uart_resume_port(&s3c24xx_uart_drv, port);
1931         }
1932
1933         return 0;
1934 }
1935
1936 static int s3c24xx_serial_resume_noirq(struct device *dev)
1937 {
1938         struct uart_port *port = s3c24xx_dev_to_port(dev);
1939         struct s3c24xx_uart_port *ourport = to_ourport(port);
1940
1941         if (port) {
1942                 /* restore IRQ mask */
1943                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1944                         unsigned int uintm = 0xf;
1945                         if (tx_enabled(port))
1946                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1947                         if (rx_enabled(port))
1948                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1949                         clk_prepare_enable(ourport->clk);
1950                         if (!IS_ERR(ourport->baudclk))
1951                                 clk_prepare_enable(ourport->baudclk);
1952                         wr_regl(port, S3C64XX_UINTM, uintm);
1953                         if (!IS_ERR(ourport->baudclk))
1954                                 clk_disable_unprepare(ourport->baudclk);
1955                         clk_disable_unprepare(ourport->clk);
1956                 }
1957         }
1958
1959         return 0;
1960 }
1961
1962 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1963         .suspend = s3c24xx_serial_suspend,
1964         .resume = s3c24xx_serial_resume,
1965         .resume_noirq = s3c24xx_serial_resume_noirq,
1966 };
1967 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1968
1969 #else /* !CONFIG_PM_SLEEP */
1970
1971 #define SERIAL_SAMSUNG_PM_OPS   NULL
1972 #endif /* CONFIG_PM_SLEEP */
1973
1974 /* Console code */
1975
1976 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1977
1978 static struct uart_port *cons_uart;
1979
1980 static int
1981 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1982 {
1983         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1984         unsigned long ufstat, utrstat;
1985
1986         if (ufcon & S3C2410_UFCON_FIFOMODE) {
1987                 /* fifo mode - check amount of data in fifo registers... */
1988
1989                 ufstat = rd_regl(port, S3C2410_UFSTAT);
1990                 return (ufstat & info->tx_fifofull) ? 0 : 1;
1991         }
1992
1993         /* in non-fifo mode, we go and use the tx buffer empty */
1994
1995         utrstat = rd_regl(port, S3C2410_UTRSTAT);
1996         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1997 }
1998
1999 static bool
2000 s3c24xx_port_configured(unsigned int ucon)
2001 {
2002         /* consider the serial port configured if the tx/rx mode set */
2003         return (ucon & 0xf) != 0;
2004 }
2005
2006 #ifdef CONFIG_CONSOLE_POLL
2007 /*
2008  * Console polling routines for writing and reading from the uart while
2009  * in an interrupt or debug context.
2010  */
2011
2012 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2013 {
2014         struct s3c24xx_uart_port *ourport = to_ourport(port);
2015         unsigned int ufstat;
2016
2017         ufstat = rd_regl(port, S3C2410_UFSTAT);
2018         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2019                 return NO_POLL_CHAR;
2020
2021         return rd_regb(port, S3C2410_URXH);
2022 }
2023
2024 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2025                 unsigned char c)
2026 {
2027         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2028         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2029
2030         /* not possible to xmit on unconfigured port */
2031         if (!s3c24xx_port_configured(ucon))
2032                 return;
2033
2034         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2035                 cpu_relax();
2036         wr_regb(port, S3C2410_UTXH, c);
2037 }
2038
2039 #endif /* CONFIG_CONSOLE_POLL */
2040
2041 static void
2042 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2043 {
2044         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2045
2046         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2047                 cpu_relax();
2048         wr_regb(port, S3C2410_UTXH, ch);
2049 }
2050
2051 static void
2052 s3c24xx_serial_console_write(struct console *co, const char *s,
2053                              unsigned int count)
2054 {
2055         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2056
2057         /* not possible to xmit on unconfigured port */
2058         if (!s3c24xx_port_configured(ucon))
2059                 return;
2060
2061         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2062 }
2063
2064 static void __init
2065 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2066                            int *parity, int *bits)
2067 {
2068         struct clk *clk;
2069         unsigned int ulcon;
2070         unsigned int ucon;
2071         unsigned int ubrdiv;
2072         unsigned long rate;
2073         unsigned int clk_sel;
2074         char clk_name[MAX_CLK_NAME_LENGTH];
2075
2076         ulcon  = rd_regl(port, S3C2410_ULCON);
2077         ucon   = rd_regl(port, S3C2410_UCON);
2078         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2079
2080         dbg("s3c24xx_serial_get_options: port=%p\n"
2081             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2082             port, ulcon, ucon, ubrdiv);
2083
2084         if (s3c24xx_port_configured(ucon)) {
2085                 switch (ulcon & S3C2410_LCON_CSMASK) {
2086                 case S3C2410_LCON_CS5:
2087                         *bits = 5;
2088                         break;
2089                 case S3C2410_LCON_CS6:
2090                         *bits = 6;
2091                         break;
2092                 case S3C2410_LCON_CS7:
2093                         *bits = 7;
2094                         break;
2095                 case S3C2410_LCON_CS8:
2096                 default:
2097                         *bits = 8;
2098                         break;
2099                 }
2100
2101                 switch (ulcon & S3C2410_LCON_PMASK) {
2102                 case S3C2410_LCON_PEVEN:
2103                         *parity = 'e';
2104                         break;
2105
2106                 case S3C2410_LCON_PODD:
2107                         *parity = 'o';
2108                         break;
2109
2110                 case S3C2410_LCON_PNONE:
2111                 default:
2112                         *parity = 'n';
2113                 }
2114
2115                 /* now calculate the baud rate */
2116
2117                 clk_sel = s3c24xx_serial_getsource(port);
2118                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2119
2120                 clk = clk_get(port->dev, clk_name);
2121                 if (!IS_ERR(clk))
2122                         rate = clk_get_rate(clk);
2123                 else
2124                         rate = 1;
2125
2126                 *baud = rate / (16 * (ubrdiv + 1));
2127                 dbg("calculated baud %d\n", *baud);
2128         }
2129
2130 }
2131
2132 static int __init
2133 s3c24xx_serial_console_setup(struct console *co, char *options)
2134 {
2135         struct uart_port *port;
2136         int baud = 9600;
2137         int bits = 8;
2138         int parity = 'n';
2139         int flow = 'n';
2140
2141         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2142             co, co->index, options);
2143
2144         /* is this a valid port */
2145
2146         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2147                 co->index = 0;
2148
2149         port = &s3c24xx_serial_ports[co->index].port;
2150
2151         /* is the port configured? */
2152
2153         if (port->mapbase == 0x0)
2154                 return -ENODEV;
2155
2156         cons_uart = port;
2157
2158         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2159
2160         /*
2161          * Check whether an invalid uart number has been specified, and
2162          * if so, search for the first available port that does have
2163          * console support.
2164          */
2165         if (options)
2166                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2167         else
2168                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2169
2170         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2171
2172         return uart_set_options(port, co, baud, parity, bits, flow);
2173 }
2174
2175 static struct console s3c24xx_serial_console = {
2176         .name           = S3C24XX_SERIAL_NAME,
2177         .device         = uart_console_device,
2178         .flags          = CON_PRINTBUFFER,
2179         .index          = -1,
2180         .write          = s3c24xx_serial_console_write,
2181         .setup          = s3c24xx_serial_console_setup,
2182         .data           = &s3c24xx_uart_drv,
2183 };
2184 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2185
2186 #ifdef CONFIG_CPU_S3C2410
2187 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2188         .info = &(struct s3c24xx_uart_info) {
2189                 .name           = "Samsung S3C2410 UART",
2190                 .type           = PORT_S3C2410,
2191                 .fifosize       = 16,
2192                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2193                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2194                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2195                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2196                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2197                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2198                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2199                 .num_clks       = 2,
2200                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2201                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2202         },
2203         .def_cfg = &(struct s3c2410_uartcfg) {
2204                 .ucon           = S3C2410_UCON_DEFAULT,
2205                 .ufcon          = S3C2410_UFCON_DEFAULT,
2206         },
2207 };
2208 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2209 #else
2210 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2211 #endif
2212
2213 #ifdef CONFIG_CPU_S3C2412
2214 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2215         .info = &(struct s3c24xx_uart_info) {
2216                 .name           = "Samsung S3C2412 UART",
2217                 .type           = PORT_S3C2412,
2218                 .fifosize       = 64,
2219                 .has_divslot    = 1,
2220                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2221                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2222                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2223                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2224                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2225                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2226                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2227                 .num_clks       = 4,
2228                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2229                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2230         },
2231         .def_cfg = &(struct s3c2410_uartcfg) {
2232                 .ucon           = S3C2410_UCON_DEFAULT,
2233                 .ufcon          = S3C2410_UFCON_DEFAULT,
2234         },
2235 };
2236 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2237 #else
2238 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2239 #endif
2240
2241 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2242         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2243 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2244         .info = &(struct s3c24xx_uart_info) {
2245                 .name           = "Samsung S3C2440 UART",
2246                 .type           = PORT_S3C2440,
2247                 .fifosize       = 64,
2248                 .has_divslot    = 1,
2249                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2250                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2251                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2252                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2253                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2254                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2255                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2256                 .num_clks       = 4,
2257                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2258                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2259         },
2260         .def_cfg = &(struct s3c2410_uartcfg) {
2261                 .ucon           = S3C2410_UCON_DEFAULT,
2262                 .ufcon          = S3C2410_UFCON_DEFAULT,
2263         },
2264 };
2265 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2266 #else
2267 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2268 #endif
2269
2270 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2271 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2272         .info = &(struct s3c24xx_uart_info) {
2273                 .name           = "Samsung S3C6400 UART",
2274                 .type           = PORT_S3C6400,
2275                 .fifosize       = 64,
2276                 .has_divslot    = 1,
2277                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2278                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2279                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2280                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2281                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2282                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2283                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2284                 .num_clks       = 4,
2285                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2286                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2287         },
2288         .def_cfg = &(struct s3c2410_uartcfg) {
2289                 .ucon           = S3C2410_UCON_DEFAULT,
2290                 .ufcon          = S3C2410_UFCON_DEFAULT,
2291         },
2292 };
2293 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2294 #else
2295 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2296 #endif
2297
2298 #ifdef CONFIG_CPU_S5PV210
2299 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2300         .info = &(struct s3c24xx_uart_info) {
2301                 .name           = "Samsung S5PV210 UART",
2302                 .type           = PORT_S3C6400,
2303                 .has_divslot    = 1,
2304                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2305                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2306                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2307                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2308                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2309                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2310                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2311                 .num_clks       = 2,
2312                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2313                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2314         },
2315         .def_cfg = &(struct s3c2410_uartcfg) {
2316                 .ucon           = S5PV210_UCON_DEFAULT,
2317                 .ufcon          = S5PV210_UFCON_DEFAULT,
2318         },
2319         .fifosize = { 256, 64, 16, 16 },
2320 };
2321 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2322 #else
2323 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2324 #endif
2325
2326 #if defined(CONFIG_ARCH_EXYNOS)
2327 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2328         .info = &(struct s3c24xx_uart_info) {                   \
2329                 .name           = "Samsung Exynos UART",        \
2330                 .type           = PORT_S3C6400,                 \
2331                 .has_divslot    = 1,                            \
2332                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2333                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2334                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2335                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2336                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2337                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2338                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2339                 .num_clks       = 1,                            \
2340                 .clksel_mask    = 0,                            \
2341                 .clksel_shift   = 0,                            \
2342         },                                                      \
2343         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2344                 .ucon           = S5PV210_UCON_DEFAULT,         \
2345                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2346                 .has_fracval    = 1,                            \
2347         }                                                       \
2348
2349 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2350         EXYNOS_COMMON_SERIAL_DRV_DATA,
2351         .fifosize = { 256, 64, 16, 16 },
2352 };
2353
2354 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2355         EXYNOS_COMMON_SERIAL_DRV_DATA,
2356         .fifosize = { 64, 256, 16, 256 },
2357 };
2358
2359 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2360 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2361 #else
2362 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2363 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2364 #endif
2365
2366 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2367         {
2368                 .name           = "s3c2410-uart",
2369                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2370         }, {
2371                 .name           = "s3c2412-uart",
2372                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2373         }, {
2374                 .name           = "s3c2440-uart",
2375                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2376         }, {
2377                 .name           = "s3c6400-uart",
2378                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2379         }, {
2380                 .name           = "s5pv210-uart",
2381                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2382         }, {
2383                 .name           = "exynos4210-uart",
2384                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2385         }, {
2386                 .name           = "exynos5433-uart",
2387                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2388         },
2389         { },
2390 };
2391 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2392
2393 #ifdef CONFIG_OF
2394 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2395         { .compatible = "samsung,s3c2410-uart",
2396                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2397         { .compatible = "samsung,s3c2412-uart",
2398                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2399         { .compatible = "samsung,s3c2440-uart",
2400                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2401         { .compatible = "samsung,s3c6400-uart",
2402                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2403         { .compatible = "samsung,s5pv210-uart",
2404                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2405         { .compatible = "samsung,exynos4210-uart",
2406                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2407         { .compatible = "samsung,exynos5433-uart",
2408                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2409         {},
2410 };
2411 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2412 #endif
2413
2414 static struct platform_driver samsung_serial_driver = {
2415         .probe          = s3c24xx_serial_probe,
2416         .remove         = s3c24xx_serial_remove,
2417         .id_table       = s3c24xx_serial_driver_ids,
2418         .driver         = {
2419                 .name   = "samsung-uart",
2420                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2421                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2422         },
2423 };
2424
2425 module_platform_driver(samsung_serial_driver);
2426
2427 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2428 /*
2429  * Early console.
2430  */
2431
2432 struct samsung_early_console_data {
2433         u32 txfull_mask;
2434 };
2435
2436 static void samsung_early_busyuart(struct uart_port *port)
2437 {
2438         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2439                 ;
2440 }
2441
2442 static void samsung_early_busyuart_fifo(struct uart_port *port)
2443 {
2444         struct samsung_early_console_data *data = port->private_data;
2445
2446         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2447                 ;
2448 }
2449
2450 static void samsung_early_putc(struct uart_port *port, int c)
2451 {
2452         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2453                 samsung_early_busyuart_fifo(port);
2454         else
2455                 samsung_early_busyuart(port);
2456
2457         writeb(c, port->membase + S3C2410_UTXH);
2458 }
2459
2460 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2461 {
2462         struct earlycon_device *dev = con->data;
2463
2464         uart_console_write(&dev->port, s, n, samsung_early_putc);
2465 }
2466
2467 static int __init samsung_early_console_setup(struct earlycon_device *device,
2468                                               const char *opt)
2469 {
2470         if (!device->port.membase)
2471                 return -ENODEV;
2472
2473         device->con->write = samsung_early_write;
2474         return 0;
2475 }
2476
2477 /* S3C2410 */
2478 static struct samsung_early_console_data s3c2410_early_console_data = {
2479         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2480 };
2481
2482 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2483                                               const char *opt)
2484 {
2485         device->port.private_data = &s3c2410_early_console_data;
2486         return samsung_early_console_setup(device, opt);
2487 }
2488 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2489                         s3c2410_early_console_setup);
2490
2491 /* S3C2412, S3C2440, S3C64xx */
2492 static struct samsung_early_console_data s3c2440_early_console_data = {
2493         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2494 };
2495
2496 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2497                                               const char *opt)
2498 {
2499         device->port.private_data = &s3c2440_early_console_data;
2500         return samsung_early_console_setup(device, opt);
2501 }
2502 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2503                         s3c2440_early_console_setup);
2504 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2505                         s3c2440_early_console_setup);
2506 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2507                         s3c2440_early_console_setup);
2508
2509 /* S5PV210, EXYNOS */
2510 static struct samsung_early_console_data s5pv210_early_console_data = {
2511         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2512 };
2513
2514 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2515                                               const char *opt)
2516 {
2517         device->port.private_data = &s5pv210_early_console_data;
2518         return samsung_early_console_setup(device, opt);
2519 }
2520 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2521                         s5pv210_early_console_setup);
2522 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2523                         s5pv210_early_console_setup);
2524 #endif
2525
2526 MODULE_ALIAS("platform:samsung-uart");
2527 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2528 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2529 MODULE_LICENSE("GPL v2");