1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Comtrol RocketPort EXPRESS/INFINITY cards
5 * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
7 * Inspired by, and loosely based on:
10 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
12 * rocketport_infinity_express-linux-1.20.tar.gz
13 * Copyright (C) 2004-2011 Comtrol, Inc.
16 #include <linux/bitops.h>
17 #include <linux/compiler.h>
18 #include <linux/completion.h>
19 #include <linux/console.h>
20 #include <linux/delay.h>
21 #include <linux/firmware.h>
22 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/log2.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/serial.h>
31 #include <linux/serial_core.h>
32 #include <linux/slab.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/types.h>
38 #define DRV_NAME "rp2"
40 #define RP2_FW_NAME "/*(DEBLOBBED)*/"
41 #define RP2_UCODE_BYTES 0x3f
43 #define PORTS_PER_ASIC 16
44 #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
46 #define UART_CLOCK 44236800
47 #define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16))
51 #define RP2_FPGA_CTL0 0x110
52 #define RP2_FPGA_CTL1 0x11c
53 #define RP2_IRQ_MASK 0x1ec
54 #define RP2_IRQ_MASK_EN_m BIT(0)
55 #define RP2_IRQ_STATUS 0x1f0
58 #define RP2_ASIC_SPACING 0x1000
59 #define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING))
61 #define RP2_PORT_BASE 0x000
62 #define RP2_PORT_SPACING 0x040
64 #define RP2_UCODE_BASE 0x400
65 #define RP2_UCODE_SPACING 0x80
67 #define RP2_CLK_PRESCALER 0xc00
68 #define RP2_CH_IRQ_STAT 0xc04
69 #define RP2_CH_IRQ_MASK 0xc08
70 #define RP2_ASIC_IRQ 0xd00
71 #define RP2_ASIC_IRQ_EN_m BIT(20)
72 #define RP2_GLOBAL_CMD 0xd0c
73 #define RP2_ASIC_CFG 0xd04
76 #define RP2_DATA_DWORD 0x000
78 #define RP2_DATA_BYTE 0x008
79 #define RP2_DATA_BYTE_ERR_PARITY_m BIT(8)
80 #define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
81 #define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
82 #define RP2_DATA_BYTE_BREAK_m BIT(11)
84 /* This lets uart_insert_char() drop bytes received on a !CREAD port */
85 #define RP2_DUMMY_READ BIT(16)
87 #define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \
88 RP2_DATA_BYTE_ERR_OVERRUN_m | \
89 RP2_DATA_BYTE_ERR_FRAMING_m | \
90 RP2_DATA_BYTE_BREAK_m)
92 #define RP2_RX_FIFO_COUNT 0x00c
93 #define RP2_TX_FIFO_COUNT 0x00e
95 #define RP2_CHAN_STAT 0x010
96 #define RP2_CHAN_STAT_RXDATA_m BIT(0)
97 #define RP2_CHAN_STAT_DCD_m BIT(3)
98 #define RP2_CHAN_STAT_DSR_m BIT(4)
99 #define RP2_CHAN_STAT_CTS_m BIT(5)
100 #define RP2_CHAN_STAT_RI_m BIT(6)
101 #define RP2_CHAN_STAT_OVERRUN_m BIT(13)
102 #define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
103 #define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
104 #define RP2_CHAN_STAT_CD_CHANGED_m BIT(18)
105 #define RP2_CHAN_STAT_RI_CHANGED_m BIT(22)
106 #define RP2_CHAN_STAT_TXEMPTY_m BIT(25)
108 #define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \
109 RP2_CHAN_STAT_CTS_CHANGED_m | \
110 RP2_CHAN_STAT_CD_CHANGED_m | \
111 RP2_CHAN_STAT_RI_CHANGED_m)
113 #define RP2_TXRX_CTL 0x014
114 #define RP2_TXRX_CTL_MSRIRQ_m BIT(0)
115 #define RP2_TXRX_CTL_RXIRQ_m BIT(2)
116 #define RP2_TXRX_CTL_RX_TRIG_s 3
117 #define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
118 #define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
119 #define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
120 #define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
121 #define RP2_TXRX_CTL_RX_EN_m BIT(5)
122 #define RP2_TXRX_CTL_RTSFLOW_m BIT(6)
123 #define RP2_TXRX_CTL_DTRFLOW_m BIT(7)
124 #define RP2_TXRX_CTL_TX_TRIG_s 16
125 #define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
126 #define RP2_TXRX_CTL_DSRFLOW_m BIT(18)
127 #define RP2_TXRX_CTL_TXIRQ_m BIT(19)
128 #define RP2_TXRX_CTL_CTSFLOW_m BIT(23)
129 #define RP2_TXRX_CTL_TX_EN_m BIT(24)
130 #define RP2_TXRX_CTL_RTS_m BIT(25)
131 #define RP2_TXRX_CTL_DTR_m BIT(26)
132 #define RP2_TXRX_CTL_LOOP_m BIT(27)
133 #define RP2_TXRX_CTL_BREAK_m BIT(28)
134 #define RP2_TXRX_CTL_CMSPAR_m BIT(29)
135 #define RP2_TXRX_CTL_nPARODD_m BIT(30)
136 #define RP2_TXRX_CTL_PARENB_m BIT(31)
138 #define RP2_UART_CTL 0x018
139 #define RP2_UART_CTL_MODE_s 0
140 #define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s)
141 #define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s)
142 #define RP2_UART_CTL_FLUSH_RX_m BIT(3)
143 #define RP2_UART_CTL_FLUSH_TX_m BIT(4)
144 #define RP2_UART_CTL_RESET_CH_m BIT(5)
145 #define RP2_UART_CTL_XMIT_EN_m BIT(6)
146 #define RP2_UART_CTL_DATABITS_s 8
147 #define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s)
148 #define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s)
149 #define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s)
150 #define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s)
151 #define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s)
152 #define RP2_UART_CTL_STOPBITS_m BIT(10)
154 #define RP2_BAUD 0x01c
156 /* ucode registers */
157 #define RP2_TX_SWFLOW 0x02
158 #define RP2_TX_SWFLOW_ena 0x81
159 #define RP2_TX_SWFLOW_dis 0x9d
161 #define RP2_RX_SWFLOW 0x0c
162 #define RP2_RX_SWFLOW_ena 0x81
163 #define RP2_RX_SWFLOW_dis 0x8d
165 #define RP2_RX_FIFO 0x37
166 #define RP2_RX_FIFO_ena 0x08
167 #define RP2_RX_FIFO_dis 0x81
169 static struct uart_driver rp2_uart_driver = {
170 .owner = THIS_MODULE,
171 .driver_name = DRV_NAME,
173 .nr = CONFIG_SERIAL_RP2_NR_UARTS,
178 struct rp2_uart_port {
179 struct uart_port port;
182 struct rp2_card *card;
183 void __iomem *asic_base;
189 struct pci_dev *pdev;
190 struct rp2_uart_port *ports;
192 int initialized_ports;
197 spinlock_t card_lock;
200 #define RP_ID(prod) PCI_VDEVICE(RP, (prod))
201 #define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
203 static inline void rp2_decode_cap(const struct pci_device_id *id,
204 int *ports, int *smpte)
206 *ports = id->driver_data >> 8;
207 *smpte = id->driver_data & 0xff;
210 static DEFINE_SPINLOCK(rp2_minor_lock);
211 static int rp2_minor_next;
213 static int rp2_alloc_ports(int n_ports)
217 spin_lock(&rp2_minor_lock);
218 if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) {
219 /* sorry, no support for hot unplugging individual cards */
220 ret = rp2_minor_next;
221 rp2_minor_next += n_ports;
223 spin_unlock(&rp2_minor_lock);
228 static inline struct rp2_uart_port *port_to_up(struct uart_port *port)
230 return container_of(port, struct rp2_uart_port, port);
233 static void rp2_rmw(struct rp2_uart_port *up, int reg,
234 u32 clr_bits, u32 set_bits)
236 u32 tmp = readl(up->base + reg);
239 writel(tmp, up->base + reg);
242 static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)
244 rp2_rmw(up, reg, val, 0);
247 static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)
249 rp2_rmw(up, reg, 0, val);
252 static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,
255 unsigned long flags, irq_mask;
257 spin_lock_irqsave(&up->card->card_lock, flags);
259 irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);
261 irq_mask &= ~BIT(ch_num);
263 irq_mask |= BIT(ch_num);
264 writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
266 spin_unlock_irqrestore(&up->card->card_lock, flags);
269 static unsigned int rp2_uart_tx_empty(struct uart_port *port)
271 struct rp2_uart_port *up = port_to_up(port);
272 unsigned long tx_fifo_bytes, flags;
275 * This should probably check the transmitter, not the FIFO.
276 * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is
279 spin_lock_irqsave(&up->port.lock, flags);
280 tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);
281 spin_unlock_irqrestore(&up->port.lock, flags);
283 return tx_fifo_bytes ? 0 : TIOCSER_TEMT;
286 static unsigned int rp2_uart_get_mctrl(struct uart_port *port)
288 struct rp2_uart_port *up = port_to_up(port);
291 status = readl(up->base + RP2_CHAN_STAT);
292 return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) |
293 ((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) |
294 ((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) |
295 ((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0);
298 static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
300 rp2_rmw(port_to_up(port), RP2_TXRX_CTL,
301 RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m,
302 ((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) |
303 ((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) |
304 ((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0));
307 static void rp2_uart_start_tx(struct uart_port *port)
309 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
312 static void rp2_uart_stop_tx(struct uart_port *port)
314 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
317 static void rp2_uart_stop_rx(struct uart_port *port)
319 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m);
322 static void rp2_uart_break_ctl(struct uart_port *port, int break_state)
326 spin_lock_irqsave(&port->lock, flags);
327 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m,
328 break_state ? RP2_TXRX_CTL_BREAK_m : 0);
329 spin_unlock_irqrestore(&port->lock, flags);
332 static void rp2_uart_enable_ms(struct uart_port *port)
334 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m);
337 static void __rp2_uart_set_termios(struct rp2_uart_port *up,
340 unsigned int baud_div)
342 /* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */
343 writew(baud_div - 1, up->base + RP2_BAUD);
345 /* data bits and stop bits */
346 rp2_rmw(up, RP2_UART_CTL,
347 RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m,
348 ((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) |
349 (((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) |
350 (((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) |
351 (((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) |
352 (((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0));
354 /* parity and hardware flow control */
355 rp2_rmw(up, RP2_TXRX_CTL,
356 RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m |
357 RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m |
358 RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m |
359 RP2_TXRX_CTL_CTSFLOW_m,
360 ((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) |
361 ((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) |
362 ((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) |
363 ((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m |
364 RP2_TXRX_CTL_CTSFLOW_m) : 0));
366 /* XON/XOFF software flow control */
367 writeb((ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis,
368 up->ucode + RP2_TX_SWFLOW);
369 writeb((ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis,
370 up->ucode + RP2_RX_SWFLOW);
373 static void rp2_uart_set_termios(struct uart_port *port,
374 struct ktermios *new,
375 struct ktermios *old)
377 struct rp2_uart_port *up = port_to_up(port);
379 unsigned int baud, baud_div;
381 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
382 baud_div = uart_get_divisor(port, baud);
384 if (tty_termios_baud_rate(new))
385 tty_termios_encode_baud_rate(new, baud, baud);
387 spin_lock_irqsave(&port->lock, flags);
389 /* ignore all characters if CREAD is not set */
390 port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ;
392 __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);
393 uart_update_timeout(port, new->c_cflag, baud);
395 spin_unlock_irqrestore(&port->lock, flags);
398 static void rp2_rx_chars(struct rp2_uart_port *up)
400 u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);
401 struct tty_port *port = &up->port.state->port;
403 for (; bytes != 0; bytes--) {
404 u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;
405 char ch = byte & 0xff;
407 if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) {
408 if (!uart_handle_sysrq_char(&up->port, ch))
409 uart_insert_char(&up->port, byte, 0, ch,
412 char flag = TTY_NORMAL;
414 if (byte & RP2_DATA_BYTE_BREAK_m)
416 else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m)
418 else if (byte & RP2_DATA_BYTE_ERR_PARITY_m)
420 uart_insert_char(&up->port, byte,
421 RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag);
423 up->port.icount.rx++;
426 spin_unlock(&up->port.lock);
427 tty_flip_buffer_push(port);
428 spin_lock(&up->port.lock);
431 static void rp2_tx_chars(struct rp2_uart_port *up)
433 u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT);
434 struct circ_buf *xmit = &up->port.state->xmit;
436 if (uart_tx_stopped(&up->port)) {
437 rp2_uart_stop_tx(&up->port);
441 for (; max_tx != 0; max_tx--) {
442 if (up->port.x_char) {
443 writeb(up->port.x_char, up->base + RP2_DATA_BYTE);
445 up->port.icount.tx++;
448 if (uart_circ_empty(xmit)) {
449 rp2_uart_stop_tx(&up->port);
452 writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE);
453 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
454 up->port.icount.tx++;
457 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
458 uart_write_wakeup(&up->port);
461 static void rp2_ch_interrupt(struct rp2_uart_port *up)
465 spin_lock(&up->port.lock);
468 * The IRQ status bits are clear-on-write. Other status bits in
469 * this register aren't, so it's harmless to write to them.
471 status = readl(up->base + RP2_CHAN_STAT);
472 writel(status, up->base + RP2_CHAN_STAT);
474 if (status & RP2_CHAN_STAT_RXDATA_m)
476 if (status & RP2_CHAN_STAT_TXEMPTY_m)
478 if (status & RP2_CHAN_STAT_MS_CHANGED_MASK)
479 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
481 spin_unlock(&up->port.lock);
484 static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id)
486 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
488 unsigned long status = readl(base + RP2_CH_IRQ_STAT) &
489 ~readl(base + RP2_CH_IRQ_MASK);
491 for_each_set_bit(ch, &status, PORTS_PER_ASIC) {
492 rp2_ch_interrupt(&card->ports[ch]);
498 static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id)
500 struct rp2_card *card = dev_id;
503 handled = rp2_asic_interrupt(card, 0);
504 if (card->n_ports >= PORTS_PER_ASIC)
505 handled += rp2_asic_interrupt(card, 1);
507 return handled ? IRQ_HANDLED : IRQ_NONE;
510 static inline void rp2_flush_fifos(struct rp2_uart_port *up)
512 rp2_rmw_set(up, RP2_UART_CTL,
513 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
514 readl(up->base + RP2_UART_CTL);
516 rp2_rmw_clr(up, RP2_UART_CTL,
517 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
520 static int rp2_uart_startup(struct uart_port *port)
522 struct rp2_uart_port *up = port_to_up(port);
525 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m);
526 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m,
527 RP2_TXRX_CTL_RX_TRIG_1);
528 rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
529 rp2_mask_ch_irq(up, up->idx, 1);
534 static void rp2_uart_shutdown(struct uart_port *port)
536 struct rp2_uart_port *up = port_to_up(port);
539 rp2_uart_break_ctl(port, 0);
541 spin_lock_irqsave(&port->lock, flags);
542 rp2_mask_ch_irq(up, up->idx, 0);
543 rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
544 spin_unlock_irqrestore(&port->lock, flags);
547 static const char *rp2_uart_type(struct uart_port *port)
549 return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL;
552 static void rp2_uart_release_port(struct uart_port *port)
554 /* Nothing to release ... */
557 static int rp2_uart_request_port(struct uart_port *port)
559 /* UARTs always present */
563 static void rp2_uart_config_port(struct uart_port *port, int flags)
565 if (flags & UART_CONFIG_TYPE)
566 port->type = PORT_RP2;
569 static int rp2_uart_verify_port(struct uart_port *port,
570 struct serial_struct *ser)
572 if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2)
578 static const struct uart_ops rp2_uart_ops = {
579 .tx_empty = rp2_uart_tx_empty,
580 .set_mctrl = rp2_uart_set_mctrl,
581 .get_mctrl = rp2_uart_get_mctrl,
582 .stop_tx = rp2_uart_stop_tx,
583 .start_tx = rp2_uart_start_tx,
584 .stop_rx = rp2_uart_stop_rx,
585 .enable_ms = rp2_uart_enable_ms,
586 .break_ctl = rp2_uart_break_ctl,
587 .startup = rp2_uart_startup,
588 .shutdown = rp2_uart_shutdown,
589 .set_termios = rp2_uart_set_termios,
590 .type = rp2_uart_type,
591 .release_port = rp2_uart_release_port,
592 .request_port = rp2_uart_request_port,
593 .config_port = rp2_uart_config_port,
594 .verify_port = rp2_uart_verify_port,
597 static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id)
599 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
602 writew(1, base + RP2_GLOBAL_CMD);
603 readw(base + RP2_GLOBAL_CMD);
605 writel(0, base + RP2_CLK_PRESCALER);
607 /* TDM clock configuration */
608 clk_cfg = readw(base + RP2_ASIC_CFG);
609 clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9);
610 writew(clk_cfg, base + RP2_ASIC_CFG);
613 writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
614 writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
617 static void rp2_init_card(struct rp2_card *card)
619 writel(4, card->bar0 + RP2_FPGA_CTL0);
620 writel(0, card->bar0 + RP2_FPGA_CTL1);
622 rp2_reset_asic(card, 0);
623 if (card->n_ports >= PORTS_PER_ASIC)
624 rp2_reset_asic(card, 1);
626 writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);
629 static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw)
633 writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
634 readl(up->base + RP2_UART_CTL);
637 writel(0, up->base + RP2_TXRX_CTL);
638 writel(0, up->base + RP2_UART_CTL);
639 readl(up->base + RP2_UART_CTL);
644 for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++)
645 writeb(fw->data[i], up->ucode + i);
647 __rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV);
648 rp2_uart_set_mctrl(&up->port, 0);
650 writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);
651 rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m,
652 RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232);
653 rp2_rmw_set(up, RP2_TXRX_CTL,
654 RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m);
657 static void rp2_remove_ports(struct rp2_card *card)
661 for (i = 0; i < card->initialized_ports; i++)
662 uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port);
663 card->initialized_ports = 0;
666 static int rp2_load_firmware(struct rp2_card *card, const struct firmware *fw)
668 resource_size_t phys_base;
671 phys_base = pci_resource_start(card->pdev, 1);
673 for (i = 0; i < card->n_ports; i++) {
674 struct rp2_uart_port *rp = &card->ports[i];
676 int j = (unsigned)i % PORTS_PER_ASIC;
678 rp->asic_base = card->bar1;
679 rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;
680 rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING;
685 p->line = card->minor_start + i;
686 p->dev = &card->pdev->dev;
688 p->iotype = UPIO_MEM32;
689 p->uartclk = UART_CLOCK;
691 p->fifosize = FIFO_SIZE;
692 p->ops = &rp2_uart_ops;
693 p->irq = card->pdev->irq;
694 p->membase = rp->base;
695 p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING;
697 if (i >= PORTS_PER_ASIC) {
698 rp->asic_base += RP2_ASIC_SPACING;
699 rp->base += RP2_ASIC_SPACING;
700 rp->ucode += RP2_ASIC_SPACING;
701 p->mapbase += RP2_ASIC_SPACING;
704 rp2_init_port(rp, fw);
705 rc = uart_add_one_port(&rp2_uart_driver, p);
707 dev_err(&card->pdev->dev,
708 "error registering port %d: %d\n", i, rc);
709 rp2_remove_ports(card);
712 card->initialized_ports++;
718 static int rp2_probe(struct pci_dev *pdev,
719 const struct pci_device_id *id)
721 const struct firmware *fw;
722 struct rp2_card *card;
723 struct rp2_uart_port *ports;
724 void __iomem * const *bars;
727 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
730 pci_set_drvdata(pdev, card);
731 spin_lock_init(&card->card_lock);
733 rc = pcim_enable_device(pdev);
737 rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME);
741 bars = pcim_iomap_table(pdev);
742 card->bar0 = bars[0];
743 card->bar1 = bars[1];
746 rp2_decode_cap(id, &card->n_ports, &card->smpte);
747 dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports);
749 card->minor_start = rp2_alloc_ports(card->n_ports);
750 if (card->minor_start < 0) {
752 "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n");
758 ports = devm_kcalloc(&pdev->dev, card->n_ports, sizeof(*ports),
764 rc = reject_firmware(&fw, RP2_FW_NAME, &pdev->dev);
766 dev_err(&pdev->dev, "cannot find '%s' firmware image\n",
771 rc = rp2_load_firmware(card, fw);
773 release_firmware(fw);
777 rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt,
778 IRQF_SHARED, DRV_NAME, card);
785 static void rp2_remove(struct pci_dev *pdev)
787 struct rp2_card *card = pci_get_drvdata(pdev);
789 rp2_remove_ports(card);
792 static const struct pci_device_id rp2_pci_tbl[] = {
794 /* RocketPort INFINITY cards */
796 { RP_ID(0x0040), RP_CAP(8, 0) }, /* INF Octa, RJ45, selectable */
797 { RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */
798 { RP_ID(0x0042), RP_CAP(8, 0) }, /* INF Octa, ext interface */
799 { RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */
800 { RP_ID(0x0044), RP_CAP(4, 0) }, /* INF Quad, DB, selectable */
801 { RP_ID(0x0045), RP_CAP(8, 0) }, /* INF Octa, DB, selectable */
802 { RP_ID(0x0046), RP_CAP(4, 0) }, /* INF Quad, ext interface */
803 { RP_ID(0x0047), RP_CAP(4, 0) }, /* INF Quad, RJ45 */
804 { RP_ID(0x004a), RP_CAP(4, 0) }, /* INF Plus, Quad */
805 { RP_ID(0x004b), RP_CAP(8, 0) }, /* INF Plus, Octa */
806 { RP_ID(0x004c), RP_CAP(8, 0) }, /* INF III, Octa */
807 { RP_ID(0x004d), RP_CAP(4, 0) }, /* INF III, Quad */
808 { RP_ID(0x004e), RP_CAP(2, 0) }, /* INF Plus, 2, RS232 */
809 { RP_ID(0x004f), RP_CAP(2, 1) }, /* INF Plus, 2, SMPTE */
810 { RP_ID(0x0050), RP_CAP(4, 0) }, /* INF Plus, Quad, RJ45 */
811 { RP_ID(0x0051), RP_CAP(8, 0) }, /* INF Plus, Octa, RJ45 */
812 { RP_ID(0x0052), RP_CAP(8, 1) }, /* INF Octa, SMPTE */
814 /* RocketPort EXPRESS cards */
816 { RP_ID(0x0060), RP_CAP(8, 0) }, /* EXP Octa, RJ45, selectable */
817 { RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */
818 { RP_ID(0x0062), RP_CAP(8, 0) }, /* EXP Octa, ext interface */
819 { RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */
820 { RP_ID(0x0064), RP_CAP(4, 0) }, /* EXP Quad, DB, selectable */
821 { RP_ID(0x0065), RP_CAP(8, 0) }, /* EXP Octa, DB, selectable */
822 { RP_ID(0x0066), RP_CAP(4, 0) }, /* EXP Quad, ext interface */
823 { RP_ID(0x0067), RP_CAP(4, 0) }, /* EXP Quad, RJ45 */
824 { RP_ID(0x0068), RP_CAP(8, 0) }, /* EXP Octa, RJ11 */
825 { RP_ID(0x0072), RP_CAP(8, 1) }, /* EXP Octa, SMPTE */
828 MODULE_DEVICE_TABLE(pci, rp2_pci_tbl);
830 static struct pci_driver rp2_pci_driver = {
832 .id_table = rp2_pci_tbl,
834 .remove = rp2_remove,
837 static int __init rp2_uart_init(void)
841 rc = uart_register_driver(&rp2_uart_driver);
845 rc = pci_register_driver(&rp2_pci_driver);
847 uart_unregister_driver(&rp2_uart_driver);
854 static void __exit rp2_uart_exit(void)
856 pci_unregister_driver(&rp2_pci_driver);
857 uart_unregister_driver(&rp2_uart_driver);
860 module_init(rp2_uart_init);
861 module_exit(rp2_uart_exit);
863 MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver");
864 MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>");
865 MODULE_LICENSE("GPL v2");