2 * Driver for Comtrol RocketPort EXPRESS/INFINITY cards
4 * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
6 * Inspired by, and loosely based on:
9 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
11 * rocketport_infinity_express-linux-1.20.tar.gz
12 * Copyright (C) 2004-2011 Comtrol, Inc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published
16 * by the Free Software Foundation.
19 #include <linux/bitops.h>
20 #include <linux/compiler.h>
21 #include <linux/completion.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/firmware.h>
25 #include <linux/init.h>
27 #include <linux/ioport.h>
28 #include <linux/irq.h>
29 #include <linux/kernel.h>
30 #include <linux/log2.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/serial.h>
34 #include <linux/serial_core.h>
35 #include <linux/slab.h>
36 #include <linux/sysrq.h>
37 #include <linux/tty.h>
38 #include <linux/tty_flip.h>
39 #include <linux/types.h>
41 #define DRV_NAME "rp2"
43 #define RP2_FW_NAME "/*(DEBLOBBED)*/"
44 #define RP2_UCODE_BYTES 0x3f
46 #define PORTS_PER_ASIC 16
47 #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
49 #define UART_CLOCK 44236800
50 #define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16))
54 #define RP2_FPGA_CTL0 0x110
55 #define RP2_FPGA_CTL1 0x11c
56 #define RP2_IRQ_MASK 0x1ec
57 #define RP2_IRQ_MASK_EN_m BIT(0)
58 #define RP2_IRQ_STATUS 0x1f0
61 #define RP2_ASIC_SPACING 0x1000
62 #define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING))
64 #define RP2_PORT_BASE 0x000
65 #define RP2_PORT_SPACING 0x040
67 #define RP2_UCODE_BASE 0x400
68 #define RP2_UCODE_SPACING 0x80
70 #define RP2_CLK_PRESCALER 0xc00
71 #define RP2_CH_IRQ_STAT 0xc04
72 #define RP2_CH_IRQ_MASK 0xc08
73 #define RP2_ASIC_IRQ 0xd00
74 #define RP2_ASIC_IRQ_EN_m BIT(20)
75 #define RP2_GLOBAL_CMD 0xd0c
76 #define RP2_ASIC_CFG 0xd04
79 #define RP2_DATA_DWORD 0x000
81 #define RP2_DATA_BYTE 0x008
82 #define RP2_DATA_BYTE_ERR_PARITY_m BIT(8)
83 #define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
84 #define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
85 #define RP2_DATA_BYTE_BREAK_m BIT(11)
87 /* This lets uart_insert_char() drop bytes received on a !CREAD port */
88 #define RP2_DUMMY_READ BIT(16)
90 #define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \
91 RP2_DATA_BYTE_ERR_OVERRUN_m | \
92 RP2_DATA_BYTE_ERR_FRAMING_m | \
93 RP2_DATA_BYTE_BREAK_m)
95 #define RP2_RX_FIFO_COUNT 0x00c
96 #define RP2_TX_FIFO_COUNT 0x00e
98 #define RP2_CHAN_STAT 0x010
99 #define RP2_CHAN_STAT_RXDATA_m BIT(0)
100 #define RP2_CHAN_STAT_DCD_m BIT(3)
101 #define RP2_CHAN_STAT_DSR_m BIT(4)
102 #define RP2_CHAN_STAT_CTS_m BIT(5)
103 #define RP2_CHAN_STAT_RI_m BIT(6)
104 #define RP2_CHAN_STAT_OVERRUN_m BIT(13)
105 #define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
106 #define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
107 #define RP2_CHAN_STAT_CD_CHANGED_m BIT(18)
108 #define RP2_CHAN_STAT_RI_CHANGED_m BIT(22)
109 #define RP2_CHAN_STAT_TXEMPTY_m BIT(25)
111 #define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \
112 RP2_CHAN_STAT_CTS_CHANGED_m | \
113 RP2_CHAN_STAT_CD_CHANGED_m | \
114 RP2_CHAN_STAT_RI_CHANGED_m)
116 #define RP2_TXRX_CTL 0x014
117 #define RP2_TXRX_CTL_MSRIRQ_m BIT(0)
118 #define RP2_TXRX_CTL_RXIRQ_m BIT(2)
119 #define RP2_TXRX_CTL_RX_TRIG_s 3
120 #define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
121 #define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
122 #define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
123 #define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
124 #define RP2_TXRX_CTL_RX_EN_m BIT(5)
125 #define RP2_TXRX_CTL_RTSFLOW_m BIT(6)
126 #define RP2_TXRX_CTL_DTRFLOW_m BIT(7)
127 #define RP2_TXRX_CTL_TX_TRIG_s 16
128 #define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
129 #define RP2_TXRX_CTL_DSRFLOW_m BIT(18)
130 #define RP2_TXRX_CTL_TXIRQ_m BIT(19)
131 #define RP2_TXRX_CTL_CTSFLOW_m BIT(23)
132 #define RP2_TXRX_CTL_TX_EN_m BIT(24)
133 #define RP2_TXRX_CTL_RTS_m BIT(25)
134 #define RP2_TXRX_CTL_DTR_m BIT(26)
135 #define RP2_TXRX_CTL_LOOP_m BIT(27)
136 #define RP2_TXRX_CTL_BREAK_m BIT(28)
137 #define RP2_TXRX_CTL_CMSPAR_m BIT(29)
138 #define RP2_TXRX_CTL_nPARODD_m BIT(30)
139 #define RP2_TXRX_CTL_PARENB_m BIT(31)
141 #define RP2_UART_CTL 0x018
142 #define RP2_UART_CTL_MODE_s 0
143 #define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s)
144 #define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s)
145 #define RP2_UART_CTL_FLUSH_RX_m BIT(3)
146 #define RP2_UART_CTL_FLUSH_TX_m BIT(4)
147 #define RP2_UART_CTL_RESET_CH_m BIT(5)
148 #define RP2_UART_CTL_XMIT_EN_m BIT(6)
149 #define RP2_UART_CTL_DATABITS_s 8
150 #define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s)
151 #define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s)
152 #define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s)
153 #define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s)
154 #define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s)
155 #define RP2_UART_CTL_STOPBITS_m BIT(10)
157 #define RP2_BAUD 0x01c
159 /* ucode registers */
160 #define RP2_TX_SWFLOW 0x02
161 #define RP2_TX_SWFLOW_ena 0x81
162 #define RP2_TX_SWFLOW_dis 0x9d
164 #define RP2_RX_SWFLOW 0x0c
165 #define RP2_RX_SWFLOW_ena 0x81
166 #define RP2_RX_SWFLOW_dis 0x8d
168 #define RP2_RX_FIFO 0x37
169 #define RP2_RX_FIFO_ena 0x08
170 #define RP2_RX_FIFO_dis 0x81
172 static struct uart_driver rp2_uart_driver = {
173 .owner = THIS_MODULE,
174 .driver_name = DRV_NAME,
176 .nr = CONFIG_SERIAL_RP2_NR_UARTS,
181 struct rp2_uart_port {
182 struct uart_port port;
185 struct rp2_card *card;
186 void __iomem *asic_base;
192 struct pci_dev *pdev;
193 struct rp2_uart_port *ports;
195 int initialized_ports;
200 spinlock_t card_lock;
203 #define RP_ID(prod) PCI_VDEVICE(RP, (prod))
204 #define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
206 static inline void rp2_decode_cap(const struct pci_device_id *id,
207 int *ports, int *smpte)
209 *ports = id->driver_data >> 8;
210 *smpte = id->driver_data & 0xff;
213 static DEFINE_SPINLOCK(rp2_minor_lock);
214 static int rp2_minor_next;
216 static int rp2_alloc_ports(int n_ports)
220 spin_lock(&rp2_minor_lock);
221 if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) {
222 /* sorry, no support for hot unplugging individual cards */
223 ret = rp2_minor_next;
224 rp2_minor_next += n_ports;
226 spin_unlock(&rp2_minor_lock);
231 static inline struct rp2_uart_port *port_to_up(struct uart_port *port)
233 return container_of(port, struct rp2_uart_port, port);
236 static void rp2_rmw(struct rp2_uart_port *up, int reg,
237 u32 clr_bits, u32 set_bits)
239 u32 tmp = readl(up->base + reg);
242 writel(tmp, up->base + reg);
245 static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)
247 rp2_rmw(up, reg, val, 0);
250 static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)
252 rp2_rmw(up, reg, 0, val);
255 static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,
258 unsigned long flags, irq_mask;
260 spin_lock_irqsave(&up->card->card_lock, flags);
262 irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);
264 irq_mask &= ~BIT(ch_num);
266 irq_mask |= BIT(ch_num);
267 writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
269 spin_unlock_irqrestore(&up->card->card_lock, flags);
272 static unsigned int rp2_uart_tx_empty(struct uart_port *port)
274 struct rp2_uart_port *up = port_to_up(port);
275 unsigned long tx_fifo_bytes, flags;
278 * This should probably check the transmitter, not the FIFO.
279 * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is
282 spin_lock_irqsave(&up->port.lock, flags);
283 tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);
284 spin_unlock_irqrestore(&up->port.lock, flags);
286 return tx_fifo_bytes ? 0 : TIOCSER_TEMT;
289 static unsigned int rp2_uart_get_mctrl(struct uart_port *port)
291 struct rp2_uart_port *up = port_to_up(port);
294 status = readl(up->base + RP2_CHAN_STAT);
295 return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) |
296 ((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) |
297 ((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) |
298 ((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0);
301 static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
303 rp2_rmw(port_to_up(port), RP2_TXRX_CTL,
304 RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m,
305 ((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) |
306 ((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) |
307 ((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0));
310 static void rp2_uart_start_tx(struct uart_port *port)
312 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
315 static void rp2_uart_stop_tx(struct uart_port *port)
317 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
320 static void rp2_uart_stop_rx(struct uart_port *port)
322 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m);
325 static void rp2_uart_break_ctl(struct uart_port *port, int break_state)
329 spin_lock_irqsave(&port->lock, flags);
330 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m,
331 break_state ? RP2_TXRX_CTL_BREAK_m : 0);
332 spin_unlock_irqrestore(&port->lock, flags);
335 static void rp2_uart_enable_ms(struct uart_port *port)
337 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m);
340 static void __rp2_uart_set_termios(struct rp2_uart_port *up,
343 unsigned int baud_div)
345 /* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */
346 writew(baud_div - 1, up->base + RP2_BAUD);
348 /* data bits and stop bits */
349 rp2_rmw(up, RP2_UART_CTL,
350 RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m,
351 ((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) |
352 (((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) |
353 (((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) |
354 (((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) |
355 (((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0));
357 /* parity and hardware flow control */
358 rp2_rmw(up, RP2_TXRX_CTL,
359 RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m |
360 RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m |
361 RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m |
362 RP2_TXRX_CTL_CTSFLOW_m,
363 ((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) |
364 ((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) |
365 ((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) |
366 ((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m |
367 RP2_TXRX_CTL_CTSFLOW_m) : 0));
369 /* XON/XOFF software flow control */
370 writeb((ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis,
371 up->ucode + RP2_TX_SWFLOW);
372 writeb((ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis,
373 up->ucode + RP2_RX_SWFLOW);
376 static void rp2_uart_set_termios(struct uart_port *port,
377 struct ktermios *new,
378 struct ktermios *old)
380 struct rp2_uart_port *up = port_to_up(port);
382 unsigned int baud, baud_div;
384 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
385 baud_div = uart_get_divisor(port, baud);
387 if (tty_termios_baud_rate(new))
388 tty_termios_encode_baud_rate(new, baud, baud);
390 spin_lock_irqsave(&port->lock, flags);
392 /* ignore all characters if CREAD is not set */
393 port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ;
395 __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);
396 uart_update_timeout(port, new->c_cflag, baud);
398 spin_unlock_irqrestore(&port->lock, flags);
401 static void rp2_rx_chars(struct rp2_uart_port *up)
403 u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);
404 struct tty_port *port = &up->port.state->port;
406 for (; bytes != 0; bytes--) {
407 u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;
408 char ch = byte & 0xff;
410 if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) {
411 if (!uart_handle_sysrq_char(&up->port, ch))
412 uart_insert_char(&up->port, byte, 0, ch,
415 char flag = TTY_NORMAL;
417 if (byte & RP2_DATA_BYTE_BREAK_m)
419 else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m)
421 else if (byte & RP2_DATA_BYTE_ERR_PARITY_m)
423 uart_insert_char(&up->port, byte,
424 RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag);
426 up->port.icount.rx++;
429 spin_unlock(&up->port.lock);
430 tty_flip_buffer_push(port);
431 spin_lock(&up->port.lock);
434 static void rp2_tx_chars(struct rp2_uart_port *up)
436 u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT);
437 struct circ_buf *xmit = &up->port.state->xmit;
439 if (uart_tx_stopped(&up->port)) {
440 rp2_uart_stop_tx(&up->port);
444 for (; max_tx != 0; max_tx--) {
445 if (up->port.x_char) {
446 writeb(up->port.x_char, up->base + RP2_DATA_BYTE);
448 up->port.icount.tx++;
451 if (uart_circ_empty(xmit)) {
452 rp2_uart_stop_tx(&up->port);
455 writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE);
456 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
457 up->port.icount.tx++;
460 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
461 uart_write_wakeup(&up->port);
464 static void rp2_ch_interrupt(struct rp2_uart_port *up)
468 spin_lock(&up->port.lock);
471 * The IRQ status bits are clear-on-write. Other status bits in
472 * this register aren't, so it's harmless to write to them.
474 status = readl(up->base + RP2_CHAN_STAT);
475 writel(status, up->base + RP2_CHAN_STAT);
477 if (status & RP2_CHAN_STAT_RXDATA_m)
479 if (status & RP2_CHAN_STAT_TXEMPTY_m)
481 if (status & RP2_CHAN_STAT_MS_CHANGED_MASK)
482 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
484 spin_unlock(&up->port.lock);
487 static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id)
489 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
491 unsigned long status = readl(base + RP2_CH_IRQ_STAT) &
492 ~readl(base + RP2_CH_IRQ_MASK);
494 for_each_set_bit(ch, &status, PORTS_PER_ASIC) {
495 rp2_ch_interrupt(&card->ports[ch]);
501 static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id)
503 struct rp2_card *card = dev_id;
506 handled = rp2_asic_interrupt(card, 0);
507 if (card->n_ports >= PORTS_PER_ASIC)
508 handled += rp2_asic_interrupt(card, 1);
510 return handled ? IRQ_HANDLED : IRQ_NONE;
513 static inline void rp2_flush_fifos(struct rp2_uart_port *up)
515 rp2_rmw_set(up, RP2_UART_CTL,
516 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
517 readl(up->base + RP2_UART_CTL);
519 rp2_rmw_clr(up, RP2_UART_CTL,
520 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
523 static int rp2_uart_startup(struct uart_port *port)
525 struct rp2_uart_port *up = port_to_up(port);
528 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m);
529 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m,
530 RP2_TXRX_CTL_RX_TRIG_1);
531 rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
532 rp2_mask_ch_irq(up, up->idx, 1);
537 static void rp2_uart_shutdown(struct uart_port *port)
539 struct rp2_uart_port *up = port_to_up(port);
542 rp2_uart_break_ctl(port, 0);
544 spin_lock_irqsave(&port->lock, flags);
545 rp2_mask_ch_irq(up, up->idx, 0);
546 rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
547 spin_unlock_irqrestore(&port->lock, flags);
550 static const char *rp2_uart_type(struct uart_port *port)
552 return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL;
555 static void rp2_uart_release_port(struct uart_port *port)
557 /* Nothing to release ... */
560 static int rp2_uart_request_port(struct uart_port *port)
562 /* UARTs always present */
566 static void rp2_uart_config_port(struct uart_port *port, int flags)
568 if (flags & UART_CONFIG_TYPE)
569 port->type = PORT_RP2;
572 static int rp2_uart_verify_port(struct uart_port *port,
573 struct serial_struct *ser)
575 if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2)
581 static const struct uart_ops rp2_uart_ops = {
582 .tx_empty = rp2_uart_tx_empty,
583 .set_mctrl = rp2_uart_set_mctrl,
584 .get_mctrl = rp2_uart_get_mctrl,
585 .stop_tx = rp2_uart_stop_tx,
586 .start_tx = rp2_uart_start_tx,
587 .stop_rx = rp2_uart_stop_rx,
588 .enable_ms = rp2_uart_enable_ms,
589 .break_ctl = rp2_uart_break_ctl,
590 .startup = rp2_uart_startup,
591 .shutdown = rp2_uart_shutdown,
592 .set_termios = rp2_uart_set_termios,
593 .type = rp2_uart_type,
594 .release_port = rp2_uart_release_port,
595 .request_port = rp2_uart_request_port,
596 .config_port = rp2_uart_config_port,
597 .verify_port = rp2_uart_verify_port,
600 static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id)
602 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
605 writew(1, base + RP2_GLOBAL_CMD);
606 readw(base + RP2_GLOBAL_CMD);
608 writel(0, base + RP2_CLK_PRESCALER);
610 /* TDM clock configuration */
611 clk_cfg = readw(base + RP2_ASIC_CFG);
612 clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9);
613 writew(clk_cfg, base + RP2_ASIC_CFG);
616 writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
617 writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
620 static void rp2_init_card(struct rp2_card *card)
622 writel(4, card->bar0 + RP2_FPGA_CTL0);
623 writel(0, card->bar0 + RP2_FPGA_CTL1);
625 rp2_reset_asic(card, 0);
626 if (card->n_ports >= PORTS_PER_ASIC)
627 rp2_reset_asic(card, 1);
629 writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);
632 static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw)
636 writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
637 readl(up->base + RP2_UART_CTL);
640 writel(0, up->base + RP2_TXRX_CTL);
641 writel(0, up->base + RP2_UART_CTL);
642 readl(up->base + RP2_UART_CTL);
647 for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++)
648 writeb(fw->data[i], up->ucode + i);
650 __rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV);
651 rp2_uart_set_mctrl(&up->port, 0);
653 writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);
654 rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m,
655 RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232);
656 rp2_rmw_set(up, RP2_TXRX_CTL,
657 RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m);
660 static void rp2_remove_ports(struct rp2_card *card)
664 for (i = 0; i < card->initialized_ports; i++)
665 uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port);
666 card->initialized_ports = 0;
669 static int rp2_load_firmware(struct rp2_card *card, const struct firmware *fw)
671 resource_size_t phys_base;
674 phys_base = pci_resource_start(card->pdev, 1);
676 for (i = 0; i < card->n_ports; i++) {
677 struct rp2_uart_port *rp = &card->ports[i];
679 int j = (unsigned)i % PORTS_PER_ASIC;
681 rp->asic_base = card->bar1;
682 rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;
683 rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING;
688 p->line = card->minor_start + i;
689 p->dev = &card->pdev->dev;
691 p->iotype = UPIO_MEM32;
692 p->uartclk = UART_CLOCK;
694 p->fifosize = FIFO_SIZE;
695 p->ops = &rp2_uart_ops;
696 p->irq = card->pdev->irq;
697 p->membase = rp->base;
698 p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING;
700 if (i >= PORTS_PER_ASIC) {
701 rp->asic_base += RP2_ASIC_SPACING;
702 rp->base += RP2_ASIC_SPACING;
703 rp->ucode += RP2_ASIC_SPACING;
704 p->mapbase += RP2_ASIC_SPACING;
707 rp2_init_port(rp, fw);
708 rc = uart_add_one_port(&rp2_uart_driver, p);
710 dev_err(&card->pdev->dev,
711 "error registering port %d: %d\n", i, rc);
712 rp2_remove_ports(card);
715 card->initialized_ports++;
721 static int rp2_probe(struct pci_dev *pdev,
722 const struct pci_device_id *id)
724 const struct firmware *fw;
725 struct rp2_card *card;
726 struct rp2_uart_port *ports;
727 void __iomem * const *bars;
730 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
733 pci_set_drvdata(pdev, card);
734 spin_lock_init(&card->card_lock);
736 rc = pcim_enable_device(pdev);
740 rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME);
744 bars = pcim_iomap_table(pdev);
745 card->bar0 = bars[0];
746 card->bar1 = bars[1];
749 rp2_decode_cap(id, &card->n_ports, &card->smpte);
750 dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports);
752 card->minor_start = rp2_alloc_ports(card->n_ports);
753 if (card->minor_start < 0) {
755 "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n");
761 ports = devm_kzalloc(&pdev->dev, sizeof(*ports) * card->n_ports,
767 rc = reject_firmware(&fw, RP2_FW_NAME, &pdev->dev);
769 dev_err(&pdev->dev, "cannot find '%s' firmware image\n",
774 rc = rp2_load_firmware(card, fw);
776 release_firmware(fw);
780 rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt,
781 IRQF_SHARED, DRV_NAME, card);
788 static void rp2_remove(struct pci_dev *pdev)
790 struct rp2_card *card = pci_get_drvdata(pdev);
792 rp2_remove_ports(card);
795 static const struct pci_device_id rp2_pci_tbl[] = {
797 /* RocketPort INFINITY cards */
799 { RP_ID(0x0040), RP_CAP(8, 0) }, /* INF Octa, RJ45, selectable */
800 { RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */
801 { RP_ID(0x0042), RP_CAP(8, 0) }, /* INF Octa, ext interface */
802 { RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */
803 { RP_ID(0x0044), RP_CAP(4, 0) }, /* INF Quad, DB, selectable */
804 { RP_ID(0x0045), RP_CAP(8, 0) }, /* INF Octa, DB, selectable */
805 { RP_ID(0x0046), RP_CAP(4, 0) }, /* INF Quad, ext interface */
806 { RP_ID(0x0047), RP_CAP(4, 0) }, /* INF Quad, RJ45 */
807 { RP_ID(0x004a), RP_CAP(4, 0) }, /* INF Plus, Quad */
808 { RP_ID(0x004b), RP_CAP(8, 0) }, /* INF Plus, Octa */
809 { RP_ID(0x004c), RP_CAP(8, 0) }, /* INF III, Octa */
810 { RP_ID(0x004d), RP_CAP(4, 0) }, /* INF III, Quad */
811 { RP_ID(0x004e), RP_CAP(2, 0) }, /* INF Plus, 2, RS232 */
812 { RP_ID(0x004f), RP_CAP(2, 1) }, /* INF Plus, 2, SMPTE */
813 { RP_ID(0x0050), RP_CAP(4, 0) }, /* INF Plus, Quad, RJ45 */
814 { RP_ID(0x0051), RP_CAP(8, 0) }, /* INF Plus, Octa, RJ45 */
815 { RP_ID(0x0052), RP_CAP(8, 1) }, /* INF Octa, SMPTE */
817 /* RocketPort EXPRESS cards */
819 { RP_ID(0x0060), RP_CAP(8, 0) }, /* EXP Octa, RJ45, selectable */
820 { RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */
821 { RP_ID(0x0062), RP_CAP(8, 0) }, /* EXP Octa, ext interface */
822 { RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */
823 { RP_ID(0x0064), RP_CAP(4, 0) }, /* EXP Quad, DB, selectable */
824 { RP_ID(0x0065), RP_CAP(8, 0) }, /* EXP Octa, DB, selectable */
825 { RP_ID(0x0066), RP_CAP(4, 0) }, /* EXP Quad, ext interface */
826 { RP_ID(0x0067), RP_CAP(4, 0) }, /* EXP Quad, RJ45 */
827 { RP_ID(0x0068), RP_CAP(8, 0) }, /* EXP Octa, RJ11 */
828 { RP_ID(0x0072), RP_CAP(8, 1) }, /* EXP Octa, SMPTE */
831 MODULE_DEVICE_TABLE(pci, rp2_pci_tbl);
833 static struct pci_driver rp2_pci_driver = {
835 .id_table = rp2_pci_tbl,
837 .remove = rp2_remove,
840 static int __init rp2_uart_init(void)
844 rc = uart_register_driver(&rp2_uart_driver);
848 rc = pci_register_driver(&rp2_pci_driver);
850 uart_unregister_driver(&rp2_uart_driver);
857 static void __exit rp2_uart_exit(void)
859 pci_unregister_driver(&rp2_pci_driver);
860 uart_unregister_driver(&rp2_uart_driver);
863 module_init(rp2_uart_init);
864 module_exit(rp2_uart_exit);
866 MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver");
867 MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>");
868 MODULE_LICENSE("GPL v2");