1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for PowerMac Z85c30 based ESCC cell found in the
4 * "macio" ASICs of various PowerMac models
6 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
9 * and drivers/serial/sunzilog.c by David S. Miller
11 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
12 * adapted special tweaks needed for us. I don't think it's worth
13 * merging back those though. The DMA code still has to get in
14 * and once done, I expect that driver to remain fairly stable in
15 * the long term, unless we change the driver model again...
17 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
18 * - Enable BREAK interrupt
19 * - Add support for sysreq
21 * TODO: - Add DMA support
22 * - Defer port shutdown to a few seconds after close
23 * - maybe put something right into uap->clk_divisor
28 #undef USE_CTRL_O_SYSRQ
30 #include <linux/module.h>
31 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/fcntl.h>
38 #include <linux/kernel.h>
39 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/console.h>
42 #include <linux/adb.h>
43 #include <linux/pmu.h>
44 #include <linux/bitops.h>
45 #include <linux/sysrq.h>
46 #include <linux/mutex.h>
47 #include <linux/of_address.h>
48 #include <linux/of_irq.h>
49 #include <asm/sections.h>
53 #ifdef CONFIG_PPC_PMAC
55 #include <asm/machdep.h>
56 #include <asm/pmac_feature.h>
57 #include <asm/dbdma.h>
58 #include <asm/macio.h>
60 #include <linux/platform_device.h>
61 #define of_machine_is_compatible(x) (0)
64 #include <linux/serial.h>
65 #include <linux/serial_core.h>
67 #include "pmac_zilog.h"
69 /* Not yet implemented */
72 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
73 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
74 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
75 MODULE_LICENSE("GPL");
77 #ifdef CONFIG_SERIAL_PMACZILOG_TTYS
78 #define PMACZILOG_MAJOR TTY_MAJOR
79 #define PMACZILOG_MINOR 64
80 #define PMACZILOG_NAME "ttyS"
82 #define PMACZILOG_MAJOR 204
83 #define PMACZILOG_MINOR 192
84 #define PMACZILOG_NAME "ttyPZ"
87 #define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
88 #define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
89 #define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
92 * For the sake of early serial console, we can do a pre-probe
93 * (optional) of the ports at rather early boot time.
95 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
96 static int pmz_ports_count;
98 static struct uart_driver pmz_uart_reg = {
100 .driver_name = PMACZILOG_NAME,
101 .dev_name = PMACZILOG_NAME,
102 .major = PMACZILOG_MAJOR,
103 .minor = PMACZILOG_MINOR,
108 * Load all registers to reprogram the port
109 * This function must only be called when the TX is not busy. The UART
110 * port lock must be held and local interrupts disabled.
112 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
116 /* Let pending transmits finish. */
117 for (i = 0; i < 1000; i++) {
118 unsigned char stat = read_zsreg(uap, R1);
130 /* Disable all interrupts. */
132 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
134 /* Set parity, sync config, stop bits, and clock divisor. */
135 write_zsreg(uap, R4, regs[R4]);
137 /* Set misc. TX/RX control bits. */
138 write_zsreg(uap, R10, regs[R10]);
140 /* Set TX/RX controls sans the enable bits. */
141 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
142 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
144 /* now set R7 "prime" on ESCC */
145 write_zsreg(uap, R15, regs[R15] | EN85C30);
146 write_zsreg(uap, R7, regs[R7P]);
148 /* make sure we use R7 "non-prime" on ESCC */
149 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
151 /* Synchronous mode config. */
152 write_zsreg(uap, R6, regs[R6]);
153 write_zsreg(uap, R7, regs[R7]);
155 /* Disable baud generator. */
156 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
158 /* Clock mode control. */
159 write_zsreg(uap, R11, regs[R11]);
161 /* Lower and upper byte of baud rate generator divisor. */
162 write_zsreg(uap, R12, regs[R12]);
163 write_zsreg(uap, R13, regs[R13]);
165 /* Now rewrite R14, with BRENAB (if set). */
166 write_zsreg(uap, R14, regs[R14]);
168 /* Reset external status interrupts. */
169 write_zsreg(uap, R0, RES_EXT_INT);
170 write_zsreg(uap, R0, RES_EXT_INT);
172 /* Rewrite R3/R5, this time without enables masked. */
173 write_zsreg(uap, R3, regs[R3]);
174 write_zsreg(uap, R5, regs[R5]);
176 /* Rewrite R1, this time without IRQ enabled masked. */
177 write_zsreg(uap, R1, regs[R1]);
179 /* Enable interrupts */
180 write_zsreg(uap, R9, regs[R9]);
184 * We do like sunzilog to avoid disrupting pending Tx
185 * Reprogram the Zilog channel HW registers with the copies found in the
186 * software state struct. If the transmitter is busy, we defer this update
187 * until the next TX complete interrupt. Else, we do it right now.
189 * The UART port lock must be held and local interrupts disabled.
191 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
193 if (!ZS_REGS_HELD(uap)) {
194 if (ZS_TX_ACTIVE(uap)) {
195 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
197 pmz_debug("pmz: maybe_update_regs: updating\n");
198 pmz_load_zsregs(uap, uap->curregs);
203 static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
206 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
207 if (!ZS_IS_EXTCLK(uap))
208 uap->curregs[1] |= EXT_INT_ENAB;
210 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
212 write_zsreg(uap, R1, uap->curregs[1]);
215 static bool pmz_receive_chars(struct uart_pmac_port *uap)
216 __must_hold(&uap->port.lock)
218 struct tty_port *port;
219 unsigned char ch, r1, drop, flag;
221 /* Sanity check, make sure the old bug is no longer happening */
222 if (uap->port.state == NULL) {
224 (void)read_zsdata(uap);
227 port = &uap->port.state->port;
232 r1 = read_zsreg(uap, R1);
233 ch = read_zsdata(uap);
235 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
236 write_zsreg(uap, R0, ERR_RES);
240 ch &= uap->parity_mask;
241 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
242 uap->flags &= ~PMACZILOG_FLAG_BREAK;
245 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
246 #ifdef USE_CTRL_O_SYSRQ
247 /* Handle the SysRq ^O Hack */
249 uap->port.sysrq = jiffies + HZ*5;
252 #endif /* USE_CTRL_O_SYSRQ */
253 if (uap->port.sysrq) {
255 spin_unlock(&uap->port.lock);
256 swallow = uart_handle_sysrq_char(&uap->port, ch);
257 spin_lock(&uap->port.lock);
261 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
263 /* A real serial line, record the character and status. */
268 uap->port.icount.rx++;
270 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
272 pmz_debug("pmz: got break !\n");
273 r1 &= ~(PAR_ERR | CRC_ERR);
274 uap->port.icount.brk++;
275 if (uart_handle_break(&uap->port))
278 else if (r1 & PAR_ERR)
279 uap->port.icount.parity++;
280 else if (r1 & CRC_ERR)
281 uap->port.icount.frame++;
283 uap->port.icount.overrun++;
284 r1 &= uap->port.read_status_mask;
287 else if (r1 & PAR_ERR)
289 else if (r1 & CRC_ERR)
293 if (uap->port.ignore_status_mask == 0xff ||
294 (r1 & uap->port.ignore_status_mask) == 0) {
295 tty_insert_flip_char(port, ch, flag);
298 tty_insert_flip_char(port, 0, TTY_OVERRUN);
300 ch = read_zsreg(uap, R0);
301 if (!(ch & Rx_CH_AV))
308 static void pmz_status_handle(struct uart_pmac_port *uap)
310 unsigned char status;
312 status = read_zsreg(uap, R0);
313 write_zsreg(uap, R0, RES_EXT_INT);
316 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
317 if (status & SYNC_HUNT)
318 uap->port.icount.dsr++;
320 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
321 * But it does not tell us which bit has changed, we have to keep
322 * track of this ourselves.
323 * The CTS input is inverted for some reason. -- paulus
325 if ((status ^ uap->prev_status) & DCD)
326 uart_handle_dcd_change(&uap->port,
328 if ((status ^ uap->prev_status) & CTS)
329 uart_handle_cts_change(&uap->port,
332 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
335 if (status & BRK_ABRT)
336 uap->flags |= PMACZILOG_FLAG_BREAK;
338 uap->prev_status = status;
341 static void pmz_transmit_chars(struct uart_pmac_port *uap)
343 struct circ_buf *xmit;
345 if (ZS_IS_CONS(uap)) {
346 unsigned char status = read_zsreg(uap, R0);
348 /* TX still busy? Just wait for the next TX done interrupt.
350 * It can occur because of how we do serial console writes. It would
351 * be nice to transmit console writes just like we normally would for
352 * a TTY line. (ie. buffered and TX interrupt driven). That is not
353 * easy because console writes cannot sleep. One solution might be
354 * to poll on enough port->xmit space becoming free. -DaveM
356 if (!(status & Tx_BUF_EMP))
360 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
362 if (ZS_REGS_HELD(uap)) {
363 pmz_load_zsregs(uap, uap->curregs);
364 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
367 if (ZS_TX_STOPPED(uap)) {
368 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
372 /* Under some circumstances, we see interrupts reported for
373 * a closed channel. The interrupt mask in R1 is clear, but
374 * R3 still signals the interrupts and we see them when taking
375 * an interrupt for the other channel (this could be a qemu
376 * bug but since the ESCC doc doesn't specify precsiely whether
377 * R3 interrup status bits are masked by R1 interrupt enable
378 * bits, better safe than sorry). --BenH.
380 if (!ZS_IS_OPEN(uap))
383 if (uap->port.x_char) {
384 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
385 write_zsdata(uap, uap->port.x_char);
387 uap->port.icount.tx++;
388 uap->port.x_char = 0;
392 if (uap->port.state == NULL)
394 xmit = &uap->port.state->xmit;
395 if (uart_circ_empty(xmit)) {
396 uart_write_wakeup(&uap->port);
399 if (uart_tx_stopped(&uap->port))
402 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
403 write_zsdata(uap, xmit->buf[xmit->tail]);
406 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
407 uap->port.icount.tx++;
409 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
410 uart_write_wakeup(&uap->port);
415 write_zsreg(uap, R0, RES_Tx_P);
419 /* Hrm... we register that twice, fixme later.... */
420 static irqreturn_t pmz_interrupt(int irq, void *dev_id)
422 struct uart_pmac_port *uap = dev_id;
423 struct uart_pmac_port *uap_a;
424 struct uart_pmac_port *uap_b;
429 uap_a = pmz_get_port_A(uap);
432 spin_lock(&uap_a->port.lock);
433 r3 = read_zsreg(uap_a, R3);
436 pmz_debug("irq, r3: %x\n", r3);
440 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
441 if (!ZS_IS_OPEN(uap_a)) {
442 pmz_debug("ChanA interrupt while not open !\n");
445 write_zsreg(uap_a, R0, RES_H_IUS);
448 pmz_status_handle(uap_a);
450 push = pmz_receive_chars(uap_a);
452 pmz_transmit_chars(uap_a);
456 spin_unlock(&uap_a->port.lock);
458 tty_flip_buffer_push(&uap->port.state->port);
463 spin_lock(&uap_b->port.lock);
465 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
466 if (!ZS_IS_OPEN(uap_b)) {
467 pmz_debug("ChanB interrupt while not open !\n");
470 write_zsreg(uap_b, R0, RES_H_IUS);
473 pmz_status_handle(uap_b);
475 push = pmz_receive_chars(uap_b);
477 pmz_transmit_chars(uap_b);
481 spin_unlock(&uap_b->port.lock);
483 tty_flip_buffer_push(&uap->port.state->port);
490 * Peek the status register, lock not held by caller
492 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
497 spin_lock_irqsave(&uap->port.lock, flags);
498 status = read_zsreg(uap, R0);
499 spin_unlock_irqrestore(&uap->port.lock, flags);
505 * Check if transmitter is empty
506 * The port lock is not held.
508 static unsigned int pmz_tx_empty(struct uart_port *port)
510 unsigned char status;
512 status = pmz_peek_status(to_pmz(port));
513 if (status & Tx_BUF_EMP)
519 * Set Modem Control (RTS & DTR) bits
520 * The port lock is held and interrupts are disabled.
521 * Note: Shall we really filter out RTS on external ports or
522 * should that be dealt at higher level only ?
524 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
526 struct uart_pmac_port *uap = to_pmz(port);
527 unsigned char set_bits, clear_bits;
529 /* Do nothing for irda for now... */
532 /* We get called during boot with a port not up yet */
533 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
536 set_bits = clear_bits = 0;
538 if (ZS_IS_INTMODEM(uap)) {
539 if (mctrl & TIOCM_RTS)
544 if (mctrl & TIOCM_DTR)
549 /* NOTE: Not subject to 'transmitter active' rule. */
550 uap->curregs[R5] |= set_bits;
551 uap->curregs[R5] &= ~clear_bits;
553 write_zsreg(uap, R5, uap->curregs[R5]);
554 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
555 set_bits, clear_bits, uap->curregs[R5]);
560 * Get Modem Control bits (only the input ones, the core will
561 * or that with a cached value of the control ones)
562 * The port lock is held and interrupts are disabled.
564 static unsigned int pmz_get_mctrl(struct uart_port *port)
566 struct uart_pmac_port *uap = to_pmz(port);
567 unsigned char status;
570 status = read_zsreg(uap, R0);
575 if (status & SYNC_HUNT)
584 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
585 * though for DMA, we will have to do a bit more.
586 * The port lock is held and interrupts are disabled.
588 static void pmz_stop_tx(struct uart_port *port)
590 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
595 * The port lock is held and interrupts are disabled.
597 static void pmz_start_tx(struct uart_port *port)
599 struct uart_pmac_port *uap = to_pmz(port);
600 unsigned char status;
602 pmz_debug("pmz: start_tx()\n");
604 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
605 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
607 status = read_zsreg(uap, R0);
609 /* TX busy? Just wait for the TX done interrupt. */
610 if (!(status & Tx_BUF_EMP))
613 /* Send the first character to jump-start the TX done
614 * IRQ sending engine.
617 write_zsdata(uap, port->x_char);
622 struct circ_buf *xmit = &port->state->xmit;
624 if (uart_circ_empty(xmit))
626 write_zsdata(uap, xmit->buf[xmit->tail]);
628 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
631 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
632 uart_write_wakeup(&uap->port);
635 pmz_debug("pmz: start_tx() done.\n");
639 * Stop Rx side, basically disable emitting of
640 * Rx interrupts on the port. We don't disable the rx
641 * side of the chip proper though
642 * The port lock is held.
644 static void pmz_stop_rx(struct uart_port *port)
646 struct uart_pmac_port *uap = to_pmz(port);
648 pmz_debug("pmz: stop_rx()()\n");
650 /* Disable all RX interrupts. */
651 uap->curregs[R1] &= ~RxINT_MASK;
652 pmz_maybe_update_regs(uap);
654 pmz_debug("pmz: stop_rx() done.\n");
658 * Enable modem status change interrupts
659 * The port lock is held.
661 static void pmz_enable_ms(struct uart_port *port)
663 struct uart_pmac_port *uap = to_pmz(port);
664 unsigned char new_reg;
668 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
669 if (new_reg != uap->curregs[R15]) {
670 uap->curregs[R15] = new_reg;
672 /* NOTE: Not subject to 'transmitter active' rule. */
673 write_zsreg(uap, R15, uap->curregs[R15]);
678 * Control break state emission
679 * The port lock is not held.
681 static void pmz_break_ctl(struct uart_port *port, int break_state)
683 struct uart_pmac_port *uap = to_pmz(port);
684 unsigned char set_bits, clear_bits, new_reg;
687 set_bits = clear_bits = 0;
692 clear_bits |= SND_BRK;
694 spin_lock_irqsave(&port->lock, flags);
696 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
697 if (new_reg != uap->curregs[R5]) {
698 uap->curregs[R5] = new_reg;
699 write_zsreg(uap, R5, uap->curregs[R5]);
702 spin_unlock_irqrestore(&port->lock, flags);
705 #ifdef CONFIG_PPC_PMAC
708 * Turn power on or off to the SCC and associated stuff
709 * (port drivers, modem, IR port, etc.)
710 * Returns the number of milliseconds we should wait before
711 * trying to use the port.
713 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
719 rc = pmac_call_feature(
720 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
721 pmz_debug("port power on result: %d\n", rc);
722 if (ZS_IS_INTMODEM(uap)) {
723 rc = pmac_call_feature(
724 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
725 delay = 2500; /* wait for 2.5s before using */
726 pmz_debug("modem power result: %d\n", rc);
729 /* TODO: Make that depend on a timer, don't power down
732 if (ZS_IS_INTMODEM(uap)) {
733 rc = pmac_call_feature(
734 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
735 pmz_debug("port power off result: %d\n", rc);
737 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
744 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
749 #endif /* !CONFIG_PPC_PMAC */
752 * FixZeroBug....Works around a bug in the SCC receiving channel.
753 * Inspired from Darwin code, 15 Sept. 2000 -DanM
755 * The following sequence prevents a problem that is seen with O'Hare ASICs
756 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
757 * at the input to the receiver becomes 'stuck' and locks up the receiver.
758 * This problem can occur as a result of a zero bit at the receiver input
759 * coincident with any of the following events:
761 * The SCC is initialized (hardware or software).
762 * A framing error is detected.
763 * The clocking option changes from synchronous or X1 asynchronous
764 * clocking to X16, X32, or X64 asynchronous clocking.
765 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
767 * This workaround attempts to recover from the lockup condition by placing
768 * the SCC in synchronous loopback mode with a fast clock before programming
769 * any of the asynchronous modes.
771 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
773 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
776 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
779 write_zsreg(uap, 4, X1CLK | MONSYNC);
780 write_zsreg(uap, 3, Rx8);
781 write_zsreg(uap, 5, Tx8 | RTS);
782 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
783 write_zsreg(uap, 11, RCBR | TCBR);
784 write_zsreg(uap, 12, 0);
785 write_zsreg(uap, 13, 0);
786 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
787 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
788 write_zsreg(uap, 3, Rx8 | RxENABLE);
789 write_zsreg(uap, 0, RES_EXT_INT);
790 write_zsreg(uap, 0, RES_EXT_INT);
791 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
793 /* The channel should be OK now, but it is probably receiving
795 * Switch to asynchronous mode, disable the receiver,
796 * and discard everything in the receive buffer.
798 write_zsreg(uap, 9, NV);
799 write_zsreg(uap, 4, X16CLK | SB_MASK);
800 write_zsreg(uap, 3, Rx8);
802 while (read_zsreg(uap, 0) & Rx_CH_AV) {
803 (void)read_zsreg(uap, 8);
804 write_zsreg(uap, 0, RES_EXT_INT);
805 write_zsreg(uap, 0, ERR_RES);
810 * Real startup routine, powers up the hardware and sets up
811 * the SCC. Returns a delay in ms where you need to wait before
812 * actually using the port, this is typically the internal modem
813 * powerup delay. This routine expect the lock to be taken.
815 static int __pmz_startup(struct uart_pmac_port *uap)
819 memset(&uap->curregs, 0, sizeof(uap->curregs));
821 /* Power up the SCC & underlying hardware (modem/irda) */
822 pwr_delay = pmz_set_scc_power(uap, 1);
824 /* Nice buggy HW ... */
825 pmz_fix_zero_bug_scc(uap);
827 /* Reset the channel */
828 uap->curregs[R9] = 0;
829 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
832 write_zsreg(uap, 9, 0);
835 /* Clear the interrupt registers */
836 write_zsreg(uap, R1, 0);
837 write_zsreg(uap, R0, ERR_RES);
838 write_zsreg(uap, R0, ERR_RES);
839 write_zsreg(uap, R0, RES_H_IUS);
840 write_zsreg(uap, R0, RES_H_IUS);
842 /* Setup some valid baud rate */
843 uap->curregs[R4] = X16CLK | SB1;
844 uap->curregs[R3] = Rx8;
845 uap->curregs[R5] = Tx8 | RTS;
846 if (!ZS_IS_IRDA(uap))
847 uap->curregs[R5] |= DTR;
848 uap->curregs[R12] = 0;
849 uap->curregs[R13] = 0;
850 uap->curregs[R14] = BRENAB;
852 /* Clear handshaking, enable BREAK interrupts */
853 uap->curregs[R15] = BRKIE;
855 /* Master interrupt enable */
856 uap->curregs[R9] |= NV | MIE;
858 pmz_load_zsregs(uap, uap->curregs);
860 /* Enable receiver and transmitter. */
861 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
862 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
864 /* Remember status for DCD/CTS changes */
865 uap->prev_status = read_zsreg(uap, R0);
870 static void pmz_irda_reset(struct uart_pmac_port *uap)
874 spin_lock_irqsave(&uap->port.lock, flags);
875 uap->curregs[R5] |= DTR;
876 write_zsreg(uap, R5, uap->curregs[R5]);
878 spin_unlock_irqrestore(&uap->port.lock, flags);
881 spin_lock_irqsave(&uap->port.lock, flags);
882 uap->curregs[R5] &= ~DTR;
883 write_zsreg(uap, R5, uap->curregs[R5]);
885 spin_unlock_irqrestore(&uap->port.lock, flags);
890 * This is the "normal" startup routine, using the above one
891 * wrapped with the lock and doing a schedule delay
893 static int pmz_startup(struct uart_port *port)
895 struct uart_pmac_port *uap = to_pmz(port);
899 pmz_debug("pmz: startup()\n");
901 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
903 /* A console is never powered down. Else, power up and
904 * initialize the chip
906 if (!ZS_IS_CONS(uap)) {
907 spin_lock_irqsave(&port->lock, flags);
908 pwr_delay = __pmz_startup(uap);
909 spin_unlock_irqrestore(&port->lock, flags);
911 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
912 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
913 uap->irq_name, uap)) {
914 pmz_error("Unable to register zs interrupt handler.\n");
915 pmz_set_scc_power(uap, 0);
919 /* Right now, we deal with delay by blocking here, I'll be
922 if (pwr_delay != 0) {
923 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
927 /* IrDA reset is done now */
931 /* Enable interrupt requests for the channel */
932 spin_lock_irqsave(&port->lock, flags);
933 pmz_interrupt_control(uap, 1);
934 spin_unlock_irqrestore(&port->lock, flags);
936 pmz_debug("pmz: startup() done.\n");
941 static void pmz_shutdown(struct uart_port *port)
943 struct uart_pmac_port *uap = to_pmz(port);
946 pmz_debug("pmz: shutdown()\n");
948 spin_lock_irqsave(&port->lock, flags);
950 /* Disable interrupt requests for the channel */
951 pmz_interrupt_control(uap, 0);
953 if (!ZS_IS_CONS(uap)) {
954 /* Disable receiver and transmitter */
955 uap->curregs[R3] &= ~RxENABLE;
956 uap->curregs[R5] &= ~TxENABLE;
958 /* Disable break assertion */
959 uap->curregs[R5] &= ~SND_BRK;
960 pmz_maybe_update_regs(uap);
963 spin_unlock_irqrestore(&port->lock, flags);
965 /* Release interrupt handler */
966 free_irq(uap->port.irq, uap);
968 spin_lock_irqsave(&port->lock, flags);
970 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
972 if (!ZS_IS_CONS(uap))
973 pmz_set_scc_power(uap, 0); /* Shut the chip down */
975 spin_unlock_irqrestore(&port->lock, flags);
977 pmz_debug("pmz: shutdown() done.\n");
980 /* Shared by TTY driver and serial console setup. The port lock is held
981 * and local interrupts are disabled.
983 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
984 unsigned int iflag, unsigned long baud)
988 /* Switch to external clocking for IrDA high clock rates. That
989 * code could be re-used for Midi interfaces with different
992 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
993 uap->curregs[R4] = X1CLK;
994 uap->curregs[R11] = RCTRxCP | TCTRxCP;
995 uap->curregs[R14] = 0; /* BRG off */
996 uap->curregs[R12] = 0;
997 uap->curregs[R13] = 0;
998 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1001 case ZS_CLOCK/16: /* 230400 */
1002 uap->curregs[R4] = X16CLK;
1003 uap->curregs[R11] = 0;
1004 uap->curregs[R14] = 0;
1006 case ZS_CLOCK/32: /* 115200 */
1007 uap->curregs[R4] = X32CLK;
1008 uap->curregs[R11] = 0;
1009 uap->curregs[R14] = 0;
1012 uap->curregs[R4] = X16CLK;
1013 uap->curregs[R11] = TCBR | RCBR;
1014 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1015 uap->curregs[R12] = (brg & 255);
1016 uap->curregs[R13] = ((brg >> 8) & 255);
1017 uap->curregs[R14] = BRENAB;
1019 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1022 /* Character size, stop bits, and parity. */
1023 uap->curregs[3] &= ~RxN_MASK;
1024 uap->curregs[5] &= ~TxN_MASK;
1026 switch (cflag & CSIZE) {
1028 uap->curregs[3] |= Rx5;
1029 uap->curregs[5] |= Tx5;
1030 uap->parity_mask = 0x1f;
1033 uap->curregs[3] |= Rx6;
1034 uap->curregs[5] |= Tx6;
1035 uap->parity_mask = 0x3f;
1038 uap->curregs[3] |= Rx7;
1039 uap->curregs[5] |= Tx7;
1040 uap->parity_mask = 0x7f;
1044 uap->curregs[3] |= Rx8;
1045 uap->curregs[5] |= Tx8;
1046 uap->parity_mask = 0xff;
1049 uap->curregs[4] &= ~(SB_MASK);
1051 uap->curregs[4] |= SB2;
1053 uap->curregs[4] |= SB1;
1055 uap->curregs[4] |= PAR_ENAB;
1057 uap->curregs[4] &= ~PAR_ENAB;
1058 if (!(cflag & PARODD))
1059 uap->curregs[4] |= PAR_EVEN;
1061 uap->curregs[4] &= ~PAR_EVEN;
1063 uap->port.read_status_mask = Rx_OVR;
1065 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1066 if (iflag & (IGNBRK | BRKINT | PARMRK))
1067 uap->port.read_status_mask |= BRK_ABRT;
1069 uap->port.ignore_status_mask = 0;
1071 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1072 if (iflag & IGNBRK) {
1073 uap->port.ignore_status_mask |= BRK_ABRT;
1075 uap->port.ignore_status_mask |= Rx_OVR;
1078 if ((cflag & CREAD) == 0)
1079 uap->port.ignore_status_mask = 0xff;
1084 * Set the irda codec on the imac to the specified baud rate.
1086 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1114 /* The FIR modes aren't really supported at this point, how
1115 * do we select the speed ? via the FCR on KeyLargo ?
1129 /* Wait for transmitter to drain */
1131 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1132 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1134 pmz_error("transmitter didn't drain\n");
1140 /* Drain the receiver too */
1142 (void)read_zsdata(uap);
1143 (void)read_zsdata(uap);
1144 (void)read_zsdata(uap);
1146 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1150 pmz_error("receiver didn't drain\n");
1155 /* Switch to command mode */
1156 uap->curregs[R5] |= DTR;
1157 write_zsreg(uap, R5, uap->curregs[R5]);
1161 /* Switch SCC to 19200 */
1162 pmz_convert_to_zs(uap, CS8, 0, 19200);
1163 pmz_load_zsregs(uap, uap->curregs);
1166 /* Write get_version command byte */
1167 write_zsdata(uap, 1);
1169 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1171 pmz_error("irda_setup timed out on get_version byte\n");
1176 version = read_zsdata(uap);
1179 pmz_info("IrDA: dongle version %d not supported\n", version);
1183 /* Send speed mode */
1184 write_zsdata(uap, cmdbyte);
1186 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1188 pmz_error("irda_setup timed out on speed mode byte\n");
1193 t = read_zsdata(uap);
1195 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1197 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1200 (void)read_zsdata(uap);
1201 (void)read_zsdata(uap);
1202 (void)read_zsdata(uap);
1205 /* Switch back to data mode */
1206 uap->curregs[R5] &= ~DTR;
1207 write_zsreg(uap, R5, uap->curregs[R5]);
1210 (void)read_zsdata(uap);
1211 (void)read_zsdata(uap);
1212 (void)read_zsdata(uap);
1216 static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1217 struct ktermios *old)
1219 struct uart_pmac_port *uap = to_pmz(port);
1222 pmz_debug("pmz: set_termios()\n");
1224 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1226 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1227 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1228 * about the FIR mode and high speed modes. So these are unused. For
1229 * implementing proper support for these, we should probably add some
1230 * DMA as well, at least on the Rx side, which isn't a simple thing
1233 if (ZS_IS_IRDA(uap)) {
1234 /* Calc baud rate */
1235 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1236 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1237 /* Cet the irda codec to the right rate */
1238 pmz_irda_setup(uap, &baud);
1239 /* Set final baud rate */
1240 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1241 pmz_load_zsregs(uap, uap->curregs);
1244 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1245 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1246 /* Make sure modem status interrupts are correctly configured */
1247 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1248 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1249 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1251 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1252 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1255 /* Load registers to the chip */
1256 pmz_maybe_update_regs(uap);
1258 uart_update_timeout(port, termios->c_cflag, baud);
1260 pmz_debug("pmz: set_termios() done.\n");
1263 /* The port lock is not held. */
1264 static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1265 struct ktermios *old)
1267 struct uart_pmac_port *uap = to_pmz(port);
1268 unsigned long flags;
1270 spin_lock_irqsave(&port->lock, flags);
1272 /* Disable IRQs on the port */
1273 pmz_interrupt_control(uap, 0);
1275 /* Setup new port configuration */
1276 __pmz_set_termios(port, termios, old);
1278 /* Re-enable IRQs on the port */
1279 if (ZS_IS_OPEN(uap))
1280 pmz_interrupt_control(uap, 1);
1282 spin_unlock_irqrestore(&port->lock, flags);
1285 static const char *pmz_type(struct uart_port *port)
1287 struct uart_pmac_port *uap = to_pmz(port);
1289 if (ZS_IS_IRDA(uap))
1290 return "Z85c30 ESCC - Infrared port";
1291 else if (ZS_IS_INTMODEM(uap))
1292 return "Z85c30 ESCC - Internal modem";
1293 return "Z85c30 ESCC - Serial port";
1296 /* We do not request/release mappings of the registers here, this
1297 * happens at early serial probe time.
1299 static void pmz_release_port(struct uart_port *port)
1303 static int pmz_request_port(struct uart_port *port)
1308 /* These do not need to do anything interesting either. */
1309 static void pmz_config_port(struct uart_port *port, int flags)
1313 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1314 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1319 #ifdef CONFIG_CONSOLE_POLL
1321 static int pmz_poll_get_char(struct uart_port *port)
1323 struct uart_pmac_port *uap =
1324 container_of(port, struct uart_pmac_port, port);
1328 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
1329 return read_zsdata(uap);
1334 return NO_POLL_CHAR;
1337 static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1339 struct uart_pmac_port *uap =
1340 container_of(port, struct uart_pmac_port, port);
1342 /* Wait for the transmit buffer to empty. */
1343 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1345 write_zsdata(uap, c);
1348 #endif /* CONFIG_CONSOLE_POLL */
1350 static const struct uart_ops pmz_pops = {
1351 .tx_empty = pmz_tx_empty,
1352 .set_mctrl = pmz_set_mctrl,
1353 .get_mctrl = pmz_get_mctrl,
1354 .stop_tx = pmz_stop_tx,
1355 .start_tx = pmz_start_tx,
1356 .stop_rx = pmz_stop_rx,
1357 .enable_ms = pmz_enable_ms,
1358 .break_ctl = pmz_break_ctl,
1359 .startup = pmz_startup,
1360 .shutdown = pmz_shutdown,
1361 .set_termios = pmz_set_termios,
1363 .release_port = pmz_release_port,
1364 .request_port = pmz_request_port,
1365 .config_port = pmz_config_port,
1366 .verify_port = pmz_verify_port,
1367 #ifdef CONFIG_CONSOLE_POLL
1368 .poll_get_char = pmz_poll_get_char,
1369 .poll_put_char = pmz_poll_put_char,
1373 #ifdef CONFIG_PPC_PMAC
1376 * Setup one port structure after probing, HW is down at this point,
1377 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1378 * register our console before uart_add_one_port() is called
1380 static int __init pmz_init_port(struct uart_pmac_port *uap)
1382 struct device_node *np = uap->node;
1384 const struct slot_names_prop {
1389 struct resource r_ports, r_rxdma, r_txdma;
1392 * Request & map chip registers
1394 if (of_address_to_resource(np, 0, &r_ports))
1396 uap->port.mapbase = r_ports.start;
1397 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1399 uap->control_reg = uap->port.membase;
1400 uap->data_reg = uap->control_reg + 0x10;
1403 * Request & map DBDMA registers
1406 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1407 of_address_to_resource(np, 2, &r_rxdma) == 0)
1408 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1410 memset(&r_txdma, 0, sizeof(struct resource));
1411 memset(&r_rxdma, 0, sizeof(struct resource));
1413 if (ZS_HAS_DMA(uap)) {
1414 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1415 if (uap->tx_dma_regs == NULL) {
1416 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1419 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1420 if (uap->rx_dma_regs == NULL) {
1421 iounmap(uap->tx_dma_regs);
1422 uap->tx_dma_regs = NULL;
1423 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1426 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1427 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1434 if (of_device_is_compatible(np, "cobalt"))
1435 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1436 conn = of_get_property(np, "AAPL,connector", &len);
1437 if (conn && (strcmp(conn, "infrared") == 0))
1438 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1439 uap->port_type = PMAC_SCC_ASYNC;
1440 /* 1999 Powerbook G3 has slot-names property instead */
1441 slots = of_get_property(np, "slot-names", &len);
1442 if (slots && slots->count > 0) {
1443 if (strcmp(slots->name, "IrDA") == 0)
1444 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1445 else if (strcmp(slots->name, "Modem") == 0)
1446 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1448 if (ZS_IS_IRDA(uap))
1449 uap->port_type = PMAC_SCC_IRDA;
1450 if (ZS_IS_INTMODEM(uap)) {
1451 struct device_node* i2c_modem =
1452 of_find_node_by_name(NULL, "i2c-modem");
1455 of_get_property(i2c_modem, "modem-id", NULL);
1456 if (mid) switch(*mid) {
1463 uap->port_type = PMAC_SCC_I2S1;
1465 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1467 of_node_put(i2c_modem);
1469 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1474 * Init remaining bits of "port" structure
1476 uap->port.iotype = UPIO_MEM;
1477 uap->port.irq = irq_of_parse_and_map(np, 0);
1478 uap->port.uartclk = ZS_CLOCK;
1479 uap->port.fifosize = 1;
1480 uap->port.ops = &pmz_pops;
1481 uap->port.type = PORT_PMAC_ZILOG;
1482 uap->port.flags = 0;
1485 * Fixup for the port on Gatwick for which the device-tree has
1486 * missing interrupts. Normally, the macio_dev would contain
1487 * fixed up interrupt info, but we use the device-tree directly
1488 * here due to early probing so we need the fixup too.
1490 if (uap->port.irq == 0 &&
1491 np->parent && np->parent->parent &&
1492 of_device_is_compatible(np->parent->parent, "gatwick")) {
1493 /* IRQs on gatwick are offset by 64 */
1494 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1495 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1496 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1499 /* Setup some valid baud rate information in the register
1500 * shadows so we don't write crap there before baud rate is
1501 * first initialized.
1503 pmz_convert_to_zs(uap, CS8, 0, 9600);
1509 * Get rid of a port on module removal
1511 static void pmz_dispose_port(struct uart_pmac_port *uap)
1513 struct device_node *np;
1516 iounmap(uap->rx_dma_regs);
1517 iounmap(uap->tx_dma_regs);
1518 iounmap(uap->control_reg);
1521 memset(uap, 0, sizeof(struct uart_pmac_port));
1525 * Called upon match with an escc node in the device-tree.
1527 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1529 struct uart_pmac_port *uap;
1532 /* Iterate the pmz_ports array to find a matching entry
1534 for (i = 0; i < MAX_ZS_PORTS; i++)
1535 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
1537 if (i >= MAX_ZS_PORTS)
1541 uap = &pmz_ports[i];
1543 uap->port.dev = &mdev->ofdev.dev;
1544 dev_set_drvdata(&mdev->ofdev.dev, uap);
1546 /* We still activate the port even when failing to request resources
1547 * to work around bugs in ancient Apple device-trees
1549 if (macio_request_resources(uap->dev, "pmac_zilog"))
1550 printk(KERN_WARNING "%pOFn: Failed to request resource"
1551 ", port still active\n",
1554 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1556 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1560 * That one should not be called, macio isn't really a hotswap device,
1561 * we don't expect one of those serial ports to go away...
1563 static int pmz_detach(struct macio_dev *mdev)
1565 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1570 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1572 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1573 macio_release_resources(uap->dev);
1574 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1576 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1578 uap->port.dev = NULL;
1584 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1586 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1589 printk("HRM... pmz_suspend with NULL uap\n");
1593 uart_suspend_port(&pmz_uart_reg, &uap->port);
1599 static int pmz_resume(struct macio_dev *mdev)
1601 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1606 uart_resume_port(&pmz_uart_reg, &uap->port);
1612 * Probe all ports in the system and build the ports array, we register
1613 * with the serial layer later, so we get a proper struct device which
1614 * allows the tty to attach properly. This is later than it used to be
1615 * but the tty layer really wants it that way.
1617 static int __init pmz_probe(void)
1619 struct device_node *node_p, *node_a, *node_b, *np;
1624 * Find all escc chips in the system
1626 for_each_node_by_name(node_p, "escc") {
1628 * First get channel A/B node pointers
1630 * TODO: Add routines with proper locking to do that...
1632 node_a = node_b = NULL;
1633 for_each_child_of_node(node_p, np) {
1634 if (of_node_name_prefix(np, "ch-a"))
1635 node_a = of_node_get(np);
1636 else if (of_node_name_prefix(np, "ch-b"))
1637 node_b = of_node_get(np);
1639 if (!node_a && !node_b) {
1640 of_node_put(node_a);
1641 of_node_put(node_b);
1642 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n",
1643 (!node_a) ? 'a' : 'b', node_p);
1648 * Fill basic fields in the port structures
1650 if (node_b != NULL) {
1651 pmz_ports[count].mate = &pmz_ports[count+1];
1652 pmz_ports[count+1].mate = &pmz_ports[count];
1654 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1655 pmz_ports[count].node = node_a;
1656 pmz_ports[count+1].node = node_b;
1657 pmz_ports[count].port.line = count;
1658 pmz_ports[count+1].port.line = count+1;
1661 * Setup the ports for real
1663 rc = pmz_init_port(&pmz_ports[count]);
1664 if (rc == 0 && node_b != NULL)
1665 rc = pmz_init_port(&pmz_ports[count+1]);
1667 of_node_put(node_a);
1668 of_node_put(node_b);
1669 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1670 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1675 pmz_ports_count = count;
1682 /* On PCI PowerMacs, pmz_probe() does an explicit search of the OpenFirmware
1683 * tree to obtain the device_nodes needed to start the console before the
1684 * macio driver. On Macs without OpenFirmware, global platform_devices take
1685 * the place of those device_nodes.
1687 extern struct platform_device scc_a_pdev, scc_b_pdev;
1689 static int __init pmz_init_port(struct uart_pmac_port *uap)
1691 struct resource *r_ports, *r_irq;
1693 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
1694 r_irq = platform_get_resource(uap->pdev, IORESOURCE_IRQ, 0);
1695 if (!r_ports || !r_irq)
1698 uap->port.mapbase = r_ports->start;
1699 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1700 uap->port.iotype = UPIO_MEM;
1701 uap->port.irq = r_irq->start;
1702 uap->port.uartclk = ZS_CLOCK;
1703 uap->port.fifosize = 1;
1704 uap->port.ops = &pmz_pops;
1705 uap->port.type = PORT_PMAC_ZILOG;
1706 uap->port.flags = 0;
1708 uap->control_reg = uap->port.membase;
1709 uap->data_reg = uap->control_reg + 4;
1711 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE);
1713 pmz_convert_to_zs(uap, CS8, 0, 9600);
1718 static int __init pmz_probe(void)
1722 pmz_ports_count = 0;
1724 pmz_ports[0].port.line = 0;
1725 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1726 pmz_ports[0].pdev = &scc_a_pdev;
1727 err = pmz_init_port(&pmz_ports[0]);
1732 pmz_ports[0].mate = &pmz_ports[1];
1733 pmz_ports[1].mate = &pmz_ports[0];
1734 pmz_ports[1].port.line = 1;
1735 pmz_ports[1].flags = 0;
1736 pmz_ports[1].pdev = &scc_b_pdev;
1737 err = pmz_init_port(&pmz_ports[1]);
1745 static void pmz_dispose_port(struct uart_pmac_port *uap)
1747 memset(uap, 0, sizeof(struct uart_pmac_port));
1750 static int __init pmz_attach(struct platform_device *pdev)
1752 struct uart_pmac_port *uap;
1755 /* Iterate the pmz_ports array to find a matching entry */
1756 for (i = 0; i < pmz_ports_count; i++)
1757 if (pmz_ports[i].pdev == pdev)
1759 if (i >= pmz_ports_count)
1762 uap = &pmz_ports[i];
1763 uap->port.dev = &pdev->dev;
1764 platform_set_drvdata(pdev, uap);
1766 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1769 static int __exit pmz_detach(struct platform_device *pdev)
1771 struct uart_pmac_port *uap = platform_get_drvdata(pdev);
1776 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1778 uap->port.dev = NULL;
1783 #endif /* !CONFIG_PPC_PMAC */
1785 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1787 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1788 static int __init pmz_console_setup(struct console *co, char *options);
1790 static struct console pmz_console = {
1791 .name = PMACZILOG_NAME,
1792 .write = pmz_console_write,
1793 .device = uart_console_device,
1794 .setup = pmz_console_setup,
1795 .flags = CON_PRINTBUFFER,
1797 .data = &pmz_uart_reg,
1800 #define PMACZILOG_CONSOLE &pmz_console
1801 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1802 #define PMACZILOG_CONSOLE (NULL)
1803 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1806 * Register the driver, console driver and ports with the serial
1809 static int __init pmz_register(void)
1811 pmz_uart_reg.nr = pmz_ports_count;
1812 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1815 * Register this driver with the serial core
1817 return uart_register_driver(&pmz_uart_reg);
1820 #ifdef CONFIG_PPC_PMAC
1822 static const struct of_device_id pmz_match[] =
1832 MODULE_DEVICE_TABLE (of, pmz_match);
1834 static struct macio_driver pmz_driver = {
1836 .name = "pmac_zilog",
1837 .owner = THIS_MODULE,
1838 .of_match_table = pmz_match,
1840 .probe = pmz_attach,
1841 .remove = pmz_detach,
1842 .suspend = pmz_suspend,
1843 .resume = pmz_resume,
1848 static struct platform_driver pmz_driver = {
1849 .remove = __exit_p(pmz_detach),
1855 #endif /* !CONFIG_PPC_PMAC */
1857 static int __init init_pmz(void)
1860 printk(KERN_INFO "%s\n", version);
1863 * First, we need to do a direct OF-based probe pass. We
1864 * do that because we want serial console up before the
1865 * macio stuffs calls us back, and since that makes it
1866 * easier to pass the proper number of channels to
1867 * uart_register_driver()
1869 if (pmz_ports_count == 0)
1873 * Bail early if no port found
1875 if (pmz_ports_count == 0)
1879 * Now we register with the serial layer
1881 rc = pmz_register();
1884 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1885 "pmac_zilog: Did another serial driver already claim the minors?\n");
1886 /* effectively "pmz_unprobe()" */
1887 for (i=0; i < pmz_ports_count; i++)
1888 pmz_dispose_port(&pmz_ports[i]);
1893 * Then we register the macio driver itself
1895 #ifdef CONFIG_PPC_PMAC
1896 return macio_register_driver(&pmz_driver);
1898 return platform_driver_probe(&pmz_driver, pmz_attach);
1902 static void __exit exit_pmz(void)
1906 #ifdef CONFIG_PPC_PMAC
1907 /* Get rid of macio-driver (detach from macio) */
1908 macio_unregister_driver(&pmz_driver);
1910 platform_driver_unregister(&pmz_driver);
1913 for (i = 0; i < pmz_ports_count; i++) {
1914 struct uart_pmac_port *uport = &pmz_ports[i];
1915 #ifdef CONFIG_PPC_PMAC
1916 if (uport->node != NULL)
1917 pmz_dispose_port(uport);
1919 if (uport->pdev != NULL)
1920 pmz_dispose_port(uport);
1923 /* Unregister UART driver */
1924 uart_unregister_driver(&pmz_uart_reg);
1927 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1929 static void pmz_console_putchar(struct uart_port *port, int ch)
1931 struct uart_pmac_port *uap =
1932 container_of(port, struct uart_pmac_port, port);
1934 /* Wait for the transmit buffer to empty. */
1935 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1937 write_zsdata(uap, ch);
1941 * Print a string to the serial port trying not to disturb
1942 * any possible real use of the port...
1944 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1946 struct uart_pmac_port *uap = &pmz_ports[con->index];
1947 unsigned long flags;
1949 spin_lock_irqsave(&uap->port.lock, flags);
1951 /* Turn of interrupts and enable the transmitter. */
1952 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1953 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1955 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1957 /* Restore the values in the registers. */
1958 write_zsreg(uap, R1, uap->curregs[1]);
1959 /* Don't disable the transmitter. */
1961 spin_unlock_irqrestore(&uap->port.lock, flags);
1965 * Setup the serial console
1967 static int __init pmz_console_setup(struct console *co, char *options)
1969 struct uart_pmac_port *uap;
1970 struct uart_port *port;
1975 unsigned long pwr_delay;
1978 * XServe's default to 57600 bps
1980 if (of_machine_is_compatible("RackMac1,1")
1981 || of_machine_is_compatible("RackMac1,2")
1982 || of_machine_is_compatible("MacRISC4"))
1986 * Check whether an invalid uart number has been specified, and
1987 * if so, search for the first available port that does have
1990 if (co->index >= pmz_ports_count)
1992 uap = &pmz_ports[co->index];
1993 #ifdef CONFIG_PPC_PMAC
1994 if (uap->node == NULL)
1997 if (uap->pdev == NULL)
2003 * Mark port as beeing a console
2005 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2008 * Temporary fix for uart layer who didn't setup the spinlock yet
2010 spin_lock_init(&port->lock);
2013 * Enable the hardware
2015 pwr_delay = __pmz_startup(uap);
2020 uart_parse_options(options, &baud, &parity, &bits, &flow);
2022 return uart_set_options(port, co, baud, parity, bits, flow);
2025 static int __init pmz_console_init(void)
2030 if (pmz_ports_count == 0)
2033 /* TODO: Autoprobe console based on OF */
2034 /* pmz_console.index = i; */
2035 register_console(&pmz_console);
2040 console_initcall(pmz_console_init);
2041 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2043 module_init(init_pmz);
2044 module_exit(exit_pmz);