1 // SPDX-License-Identifier: GPL-2.0+
3 * PIC32 Integrated Serial Driver.
5 * Copyright (C) 2015 Microchip Technology, Inc.
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
11 #include <linux/kernel.h>
12 #include <linux/platform_device.h>
14 #include <linux/of_device.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_gpio.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/console.h>
21 #include <linux/clk.h>
22 #include <linux/tty.h>
23 #include <linux/tty_flip.h>
24 #include <linux/serial_core.h>
25 #include <linux/delay.h>
27 #include <asm/mach-pic32/pic32.h>
29 /* UART name and device definitions */
30 #define PIC32_DEV_NAME "pic32-uart"
31 #define PIC32_MAX_UARTS 6
32 #define PIC32_SDEV_NAME "ttyPIC"
34 #define PIC32_UART_DFLT_BRATE 9600
35 #define PIC32_UART_TX_FIFO_DEPTH 8
36 #define PIC32_UART_RX_FIFO_DEPTH 8
38 #define PIC32_UART_MODE 0x00
39 #define PIC32_UART_STA 0x10
40 #define PIC32_UART_TX 0x20
41 #define PIC32_UART_RX 0x30
42 #define PIC32_UART_BRG 0x40
44 /* struct pic32_sport - pic32 serial port descriptor
45 * @port: uart port descriptor
47 * @irq_fault: virtual fault interrupt number
48 * @irq_fault_name: irq fault name
49 * @irq_rx: virtual rx interrupt number
50 * @irq_rx_name: irq rx name
51 * @irq_tx: virtual tx interrupt number
52 * @irq_tx_name: irq tx name
53 * @cts_gpio: clear to send gpio
54 * @dev: device descriptor
57 struct uart_port port;
61 const char *irq_fault_name;
63 const char *irq_rx_name;
65 const char *irq_tx_name;
76 static inline struct pic32_sport *to_pic32_sport(struct uart_port *port)
78 return container_of(port, struct pic32_sport, port);
81 static inline void pic32_uart_writel(struct pic32_sport *sport,
84 __raw_writel(val, sport->port.membase + reg);
87 static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
89 return __raw_readl(sport->port.membase + reg);
92 /* pic32 uart mode register bits */
93 #define PIC32_UART_MODE_ON BIT(15)
94 #define PIC32_UART_MODE_FRZ BIT(14)
95 #define PIC32_UART_MODE_SIDL BIT(13)
96 #define PIC32_UART_MODE_IREN BIT(12)
97 #define PIC32_UART_MODE_RTSMD BIT(11)
98 #define PIC32_UART_MODE_RESV1 BIT(10)
99 #define PIC32_UART_MODE_UEN1 BIT(9)
100 #define PIC32_UART_MODE_UEN0 BIT(8)
101 #define PIC32_UART_MODE_WAKE BIT(7)
102 #define PIC32_UART_MODE_LPBK BIT(6)
103 #define PIC32_UART_MODE_ABAUD BIT(5)
104 #define PIC32_UART_MODE_RXINV BIT(4)
105 #define PIC32_UART_MODE_BRGH BIT(3)
106 #define PIC32_UART_MODE_PDSEL1 BIT(2)
107 #define PIC32_UART_MODE_PDSEL0 BIT(1)
108 #define PIC32_UART_MODE_STSEL BIT(0)
110 /* pic32 uart status register bits */
111 #define PIC32_UART_STA_UTXISEL1 BIT(15)
112 #define PIC32_UART_STA_UTXISEL0 BIT(14)
113 #define PIC32_UART_STA_UTXINV BIT(13)
114 #define PIC32_UART_STA_URXEN BIT(12)
115 #define PIC32_UART_STA_UTXBRK BIT(11)
116 #define PIC32_UART_STA_UTXEN BIT(10)
117 #define PIC32_UART_STA_UTXBF BIT(9)
118 #define PIC32_UART_STA_TRMT BIT(8)
119 #define PIC32_UART_STA_URXISEL1 BIT(7)
120 #define PIC32_UART_STA_URXISEL0 BIT(6)
121 #define PIC32_UART_STA_ADDEN BIT(5)
122 #define PIC32_UART_STA_RIDLE BIT(4)
123 #define PIC32_UART_STA_PERR BIT(3)
124 #define PIC32_UART_STA_FERR BIT(2)
125 #define PIC32_UART_STA_OERR BIT(1)
126 #define PIC32_UART_STA_URXDA BIT(0)
128 /* pic32_sport pointer for console use */
129 static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
131 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
133 /* wait for tx empty, otherwise chars will be lost or corrupted */
134 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
138 /* serial core request to check if uart tx buffer is empty */
139 static unsigned int pic32_uart_tx_empty(struct uart_port *port)
141 struct pic32_sport *sport = to_pic32_sport(port);
142 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
144 return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
147 /* serial core request to set UART outputs */
148 static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
150 struct pic32_sport *sport = to_pic32_sport(port);
152 /* set loopback mode */
153 if (mctrl & TIOCM_LOOP)
154 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
155 PIC32_UART_MODE_LPBK);
157 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
158 PIC32_UART_MODE_LPBK);
161 /* get the state of CTS input pin for this port */
162 static unsigned int get_cts_state(struct pic32_sport *sport)
164 /* read and invert UxCTS */
165 if (gpio_is_valid(sport->cts_gpio))
166 return !gpio_get_value(sport->cts_gpio);
171 /* serial core request to return the state of misc UART input pins */
172 static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
174 struct pic32_sport *sport = to_pic32_sport(port);
175 unsigned int mctrl = 0;
177 if (!sport->hw_flow_ctrl)
179 else if (get_cts_state(sport))
182 /* DSR and CD are not supported in PIC32, so return 1
183 * RI is not supported in PIC32, so return 0
191 /* stop tx and start tx are not called in pairs, therefore a flag indicates
192 * the status of irq to control the irq-depth.
194 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
196 if (en && !sport->enable_tx_irq) {
197 enable_irq(sport->irq_tx);
198 sport->enable_tx_irq = true;
199 } else if (!en && sport->enable_tx_irq) {
200 /* use disable_irq_nosync() and not disable_irq() to avoid self
201 * imposed deadlock by not waiting for irq handler to end,
202 * since this callback is called from interrupt context.
204 disable_irq_nosync(sport->irq_tx);
205 sport->enable_tx_irq = false;
209 /* serial core request to disable tx ASAP (used for flow control) */
210 static void pic32_uart_stop_tx(struct uart_port *port)
212 struct pic32_sport *sport = to_pic32_sport(port);
214 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
217 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
220 /* wait for tx empty */
221 pic32_wait_deplete_txbuf(sport);
223 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
224 PIC32_UART_STA_UTXEN);
225 pic32_uart_irqtxen(sport, 0);
228 /* serial core request to (re)enable tx */
229 static void pic32_uart_start_tx(struct uart_port *port)
231 struct pic32_sport *sport = to_pic32_sport(port);
233 pic32_uart_irqtxen(sport, 1);
234 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
235 PIC32_UART_STA_UTXEN);
238 /* serial core request to stop rx, called before port shutdown */
239 static void pic32_uart_stop_rx(struct uart_port *port)
241 struct pic32_sport *sport = to_pic32_sport(port);
243 /* disable rx interrupts */
244 disable_irq(sport->irq_rx);
246 /* receiver Enable bit OFF */
247 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
248 PIC32_UART_STA_URXEN);
251 /* serial core request to start/stop emitting break char */
252 static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
254 struct pic32_sport *sport = to_pic32_sport(port);
257 spin_lock_irqsave(&port->lock, flags);
260 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
261 PIC32_UART_STA_UTXBRK);
263 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
264 PIC32_UART_STA_UTXBRK);
266 spin_unlock_irqrestore(&port->lock, flags);
269 /* get port type in string format */
270 static const char *pic32_uart_type(struct uart_port *port)
272 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
275 /* read all chars in rx fifo and send them to core */
276 static void pic32_uart_do_rx(struct uart_port *port)
278 struct pic32_sport *sport = to_pic32_sport(port);
279 struct tty_port *tty;
280 unsigned int max_count;
282 /* limit number of char read in interrupt, should not be
283 * higher than fifo size anyway since we're much faster than
286 max_count = PIC32_UART_RX_FIFO_DEPTH;
288 spin_lock(&port->lock);
290 tty = &port->state->port;
296 /* get overrun/fifo empty information from status register */
297 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
298 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
300 /* fifo reset is required to clear interrupt */
301 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
302 PIC32_UART_STA_OERR);
304 port->icount.overrun++;
305 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
308 /* Can at least one more character can be read? */
309 if (!(sta_reg & PIC32_UART_STA_URXDA))
312 /* read the character and increment the rx counter */
313 c = pic32_uart_readl(sport, PIC32_UART_RX);
319 if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
320 (sta_reg & PIC32_UART_STA_FERR))) {
323 if (sta_reg & PIC32_UART_STA_PERR)
324 port->icount.parity++;
325 if (sta_reg & PIC32_UART_STA_FERR)
326 port->icount.frame++;
328 /* update flag wrt read_status_mask */
329 sta_reg &= port->read_status_mask;
331 if (sta_reg & PIC32_UART_STA_FERR)
333 if (sta_reg & PIC32_UART_STA_PERR)
337 if (uart_handle_sysrq_char(port, c))
340 if ((sta_reg & port->ignore_status_mask) == 0)
341 tty_insert_flip_char(tty, c, flag);
343 } while (--max_count);
345 spin_unlock(&port->lock);
347 tty_flip_buffer_push(tty);
350 /* fill tx fifo with chars to send, stop when fifo is about to be full
351 * or when all chars have been sent.
353 static void pic32_uart_do_tx(struct uart_port *port)
355 struct pic32_sport *sport = to_pic32_sport(port);
356 struct circ_buf *xmit = &port->state->xmit;
357 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
360 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
366 if (uart_tx_stopped(port)) {
367 pic32_uart_stop_tx(port);
371 if (uart_circ_empty(xmit))
374 /* keep stuffing chars into uart tx buffer
375 * 1) until uart fifo is full
377 * 2) until the circ buffer is empty
378 * (all chars have been sent)
380 * 3) until the max count is reached
381 * (prevents lingering here for too long in certain cases)
383 while (!(PIC32_UART_STA_UTXBF &
384 pic32_uart_readl(sport, PIC32_UART_STA))) {
385 unsigned int c = xmit->buf[xmit->tail];
387 pic32_uart_writel(sport, PIC32_UART_TX, c);
389 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
391 if (uart_circ_empty(xmit))
393 if (--max_count == 0)
397 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
398 uart_write_wakeup(port);
400 if (uart_circ_empty(xmit))
406 pic32_uart_irqtxen(sport, 0);
409 /* RX interrupt handler */
410 static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
412 struct uart_port *port = dev_id;
414 pic32_uart_do_rx(port);
419 /* TX interrupt handler */
420 static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
422 struct uart_port *port = dev_id;
425 spin_lock_irqsave(&port->lock, flags);
426 pic32_uart_do_tx(port);
427 spin_unlock_irqrestore(&port->lock, flags);
432 /* FAULT interrupt handler */
433 static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
435 /* do nothing: pic32_uart_do_rx() handles faults. */
439 /* enable rx & tx operation on uart */
440 static void pic32_uart_en_and_unmask(struct uart_port *port)
442 struct pic32_sport *sport = to_pic32_sport(port);
444 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
445 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
446 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
450 /* disable rx & tx operation on uart */
451 static void pic32_uart_dsbl_and_mask(struct uart_port *port)
453 struct pic32_sport *sport = to_pic32_sport(port);
455 /* wait for tx empty, otherwise chars will be lost or corrupted */
456 pic32_wait_deplete_txbuf(sport);
458 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
459 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
460 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
464 /* serial core request to initialize uart and start rx operation */
465 static int pic32_uart_startup(struct uart_port *port)
467 struct pic32_sport *sport = to_pic32_sport(port);
468 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
472 local_irq_save(flags);
474 ret = clk_prepare_enable(sport->clk);
476 local_irq_restore(flags);
480 /* clear status and mode registers */
481 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
482 pic32_uart_writel(sport, PIC32_UART_STA, 0);
484 /* disable uart and mask all interrupts */
485 pic32_uart_dsbl_and_mask(port);
487 /* set default baud */
488 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
490 local_irq_restore(flags);
492 /* Each UART of a PIC32 has three interrupts therefore,
493 * we setup driver to register the 3 irqs for the device.
495 * For each irq request_irq() is called with interrupt disabled.
496 * And the irq is enabled as soon as we are ready to handle them.
498 sport->enable_tx_irq = false;
500 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
501 pic32_uart_type(port),
503 if (!sport->irq_fault_name) {
504 dev_err(port->dev, "%s: kasprintf err!", __func__);
508 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
509 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
510 IRQF_NO_THREAD, sport->irq_fault_name, port);
512 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
513 __func__, sport->irq_fault, ret,
514 pic32_uart_type(port));
518 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
519 pic32_uart_type(port),
521 if (!sport->irq_rx_name) {
522 dev_err(port->dev, "%s: kasprintf err!", __func__);
526 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
527 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
528 IRQF_NO_THREAD, sport->irq_rx_name, port);
530 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
531 __func__, sport->irq_rx, ret,
532 pic32_uart_type(port));
536 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
537 pic32_uart_type(port),
539 if (!sport->irq_tx_name) {
540 dev_err(port->dev, "%s: kasprintf err!", __func__);
544 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
545 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
546 IRQF_NO_THREAD, sport->irq_tx_name, port);
548 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
549 __func__, sport->irq_tx, ret,
550 pic32_uart_type(port));
554 local_irq_save(flags);
556 /* set rx interrupt on first receive */
557 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
558 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
560 /* set interrupt on empty */
561 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
562 PIC32_UART_STA_UTXISEL1);
564 /* enable all interrupts and eanable uart */
565 pic32_uart_en_and_unmask(port);
567 local_irq_restore(flags);
569 enable_irq(sport->irq_rx);
574 free_irq(sport->irq_tx, port);
575 kfree(sport->irq_tx_name);
577 free_irq(sport->irq_rx, port);
578 kfree(sport->irq_rx_name);
580 free_irq(sport->irq_fault, port);
581 kfree(sport->irq_fault_name);
586 /* serial core request to flush & disable uart */
587 static void pic32_uart_shutdown(struct uart_port *port)
589 struct pic32_sport *sport = to_pic32_sport(port);
593 spin_lock_irqsave(&port->lock, flags);
594 pic32_uart_dsbl_and_mask(port);
595 spin_unlock_irqrestore(&port->lock, flags);
596 clk_disable_unprepare(sport->clk);
598 /* free all 3 interrupts for this UART */
599 free_irq(sport->irq_fault, port);
600 kfree(sport->irq_fault_name);
601 free_irq(sport->irq_tx, port);
602 kfree(sport->irq_tx_name);
603 free_irq(sport->irq_rx, port);
604 kfree(sport->irq_rx_name);
607 /* serial core request to change current uart setting */
608 static void pic32_uart_set_termios(struct uart_port *port,
609 struct ktermios *new,
610 struct ktermios *old)
612 struct pic32_sport *sport = to_pic32_sport(port);
617 spin_lock_irqsave(&port->lock, flags);
619 /* disable uart and mask all interrupts while changing speed */
620 pic32_uart_dsbl_and_mask(port);
622 /* stop bit options */
623 if (new->c_cflag & CSTOPB)
624 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
625 PIC32_UART_MODE_STSEL);
627 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
628 PIC32_UART_MODE_STSEL);
631 if (new->c_cflag & PARENB) {
632 if (new->c_cflag & PARODD) {
633 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
634 PIC32_UART_MODE_PDSEL1);
635 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
636 PIC32_UART_MODE_PDSEL0);
638 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
639 PIC32_UART_MODE_PDSEL0);
640 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
641 PIC32_UART_MODE_PDSEL1);
644 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
645 PIC32_UART_MODE_PDSEL1 |
646 PIC32_UART_MODE_PDSEL0);
648 /* if hw flow ctrl, then the pins must be specified in device tree */
649 if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) {
650 /* enable hardware flow control */
651 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
652 PIC32_UART_MODE_UEN1);
653 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
654 PIC32_UART_MODE_UEN0);
655 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
656 PIC32_UART_MODE_RTSMD);
658 /* disable hardware flow control */
659 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
660 PIC32_UART_MODE_UEN1);
661 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
662 PIC32_UART_MODE_UEN0);
663 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
664 PIC32_UART_MODE_RTSMD);
670 /* Mark/Space parity is not supported */
671 new->c_cflag &= ~CMSPAR;
674 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
675 quot = uart_get_divisor(port, baud) - 1;
676 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
677 uart_update_timeout(port, new->c_cflag, baud);
679 if (tty_termios_baud_rate(new))
680 tty_termios_encode_baud_rate(new, baud, baud);
683 pic32_uart_en_and_unmask(port);
685 spin_unlock_irqrestore(&port->lock, flags);
688 /* serial core request to claim uart iomem */
689 static int pic32_uart_request_port(struct uart_port *port)
691 struct platform_device *pdev = to_platform_device(port->dev);
692 struct resource *res_mem;
694 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
695 if (unlikely(!res_mem))
698 if (!request_mem_region(port->mapbase, resource_size(res_mem),
702 port->membase = devm_ioremap(port->dev, port->mapbase,
703 resource_size(res_mem));
704 if (!port->membase) {
705 dev_err(port->dev, "Unable to map registers\n");
706 release_mem_region(port->mapbase, resource_size(res_mem));
713 /* serial core request to release uart iomem */
714 static void pic32_uart_release_port(struct uart_port *port)
716 struct platform_device *pdev = to_platform_device(port->dev);
717 struct resource *res_mem;
718 unsigned int res_size;
720 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
721 if (unlikely(!res_mem))
723 res_size = resource_size(res_mem);
725 release_mem_region(port->mapbase, res_size);
728 /* serial core request to do any port required auto-configuration */
729 static void pic32_uart_config_port(struct uart_port *port, int flags)
731 if (flags & UART_CONFIG_TYPE) {
732 if (pic32_uart_request_port(port))
734 port->type = PORT_PIC32;
738 /* serial core request to check that port information in serinfo are suitable */
739 static int pic32_uart_verify_port(struct uart_port *port,
740 struct serial_struct *serinfo)
742 if (port->type != PORT_PIC32)
744 if (port->irq != serinfo->irq)
746 if (port->iotype != serinfo->io_type)
748 if (port->mapbase != (unsigned long)serinfo->iomem_base)
754 /* serial core callbacks */
755 static const struct uart_ops pic32_uart_ops = {
756 .tx_empty = pic32_uart_tx_empty,
757 .get_mctrl = pic32_uart_get_mctrl,
758 .set_mctrl = pic32_uart_set_mctrl,
759 .start_tx = pic32_uart_start_tx,
760 .stop_tx = pic32_uart_stop_tx,
761 .stop_rx = pic32_uart_stop_rx,
762 .break_ctl = pic32_uart_break_ctl,
763 .startup = pic32_uart_startup,
764 .shutdown = pic32_uart_shutdown,
765 .set_termios = pic32_uart_set_termios,
766 .type = pic32_uart_type,
767 .release_port = pic32_uart_release_port,
768 .request_port = pic32_uart_request_port,
769 .config_port = pic32_uart_config_port,
770 .verify_port = pic32_uart_verify_port,
773 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
774 /* output given char */
775 static void pic32_console_putchar(struct uart_port *port, unsigned char ch)
777 struct pic32_sport *sport = to_pic32_sport(port);
779 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
782 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
785 /* wait for tx empty */
786 pic32_wait_deplete_txbuf(sport);
788 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
791 /* console core request to output given string */
792 static void pic32_console_write(struct console *co, const char *s,
795 struct pic32_sport *sport = pic32_sports[co->index];
797 /* call uart helper to deal with \r\n */
798 uart_console_write(&sport->port, s, count, pic32_console_putchar);
801 /* console core request to setup given console, find matching uart
804 static int pic32_console_setup(struct console *co, char *options)
806 struct pic32_sport *sport;
813 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
816 sport = pic32_sports[co->index];
820 ret = clk_prepare_enable(sport->clk);
825 uart_parse_options(options, &baud, &parity, &bits, &flow);
827 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
830 static struct uart_driver pic32_uart_driver;
831 static struct console pic32_console = {
832 .name = PIC32_SDEV_NAME,
833 .write = pic32_console_write,
834 .device = uart_console_device,
835 .setup = pic32_console_setup,
836 .flags = CON_PRINTBUFFER,
838 .data = &pic32_uart_driver,
840 #define PIC32_SCONSOLE (&pic32_console)
842 static int __init pic32_console_init(void)
844 register_console(&pic32_console);
847 console_initcall(pic32_console_init);
850 * Late console initialization.
852 static int __init pic32_late_console_init(void)
854 if (!(pic32_console.flags & CON_ENABLED))
855 register_console(&pic32_console);
860 core_initcall(pic32_late_console_init);
863 #define PIC32_SCONSOLE NULL
866 static struct uart_driver pic32_uart_driver = {
867 .owner = THIS_MODULE,
868 .driver_name = PIC32_DEV_NAME,
869 .dev_name = PIC32_SDEV_NAME,
870 .nr = PIC32_MAX_UARTS,
871 .cons = PIC32_SCONSOLE,
874 static int pic32_uart_probe(struct platform_device *pdev)
876 struct device_node *np = pdev->dev.of_node;
877 struct pic32_sport *sport;
879 struct resource *res_mem;
880 struct uart_port *port;
883 uart_idx = of_alias_get_id(np, "serial");
884 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
887 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
891 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
895 sport->idx = uart_idx;
896 sport->irq_fault = irq_of_parse_and_map(np, 0);
897 sport->irq_rx = irq_of_parse_and_map(np, 1);
898 sport->irq_tx = irq_of_parse_and_map(np, 2);
899 sport->clk = devm_clk_get(&pdev->dev, NULL);
900 sport->dev = &pdev->dev;
902 /* Hardware flow control: gpios
903 * !Note: Basically, CTS is needed for reading the status.
905 sport->hw_flow_ctrl = false;
906 sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0);
907 if (gpio_is_valid(sport->cts_gpio)) {
908 sport->hw_flow_ctrl = true;
910 ret = devm_gpio_request(sport->dev,
911 sport->cts_gpio, "CTS");
914 "error requesting CTS GPIO\n");
918 ret = gpio_direction_input(sport->cts_gpio);
920 dev_err(&pdev->dev, "error setting CTS GPIO\n");
925 pic32_sports[uart_idx] = sport;
927 port->iotype = UPIO_MEM;
928 port->mapbase = res_mem->start;
929 port->ops = &pic32_uart_ops;
930 port->flags = UPF_BOOT_AUTOCONF;
931 port->dev = &pdev->dev;
932 port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
933 port->uartclk = clk_get_rate(sport->clk);
934 port->line = uart_idx;
936 ret = uart_add_one_port(&pic32_uart_driver, port);
938 port->membase = NULL;
939 dev_err(port->dev, "%s: uart add port error!\n", __func__);
943 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
944 if (uart_console(port) && (pic32_console.flags & CON_ENABLED)) {
945 /* The peripheral clock has been enabled by console_setup,
946 * so disable it till the port is used.
948 clk_disable_unprepare(sport->clk);
952 platform_set_drvdata(pdev, port);
954 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
959 /* automatic unroll of sport and gpios */
963 static int pic32_uart_remove(struct platform_device *pdev)
965 struct uart_port *port = platform_get_drvdata(pdev);
966 struct pic32_sport *sport = to_pic32_sport(port);
968 uart_remove_one_port(&pic32_uart_driver, port);
969 clk_disable_unprepare(sport->clk);
970 platform_set_drvdata(pdev, NULL);
971 pic32_sports[sport->idx] = NULL;
973 /* automatic unroll of sport and gpios */
977 static const struct of_device_id pic32_serial_dt_ids[] = {
978 { .compatible = "microchip,pic32mzda-uart" },
981 MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
983 static struct platform_driver pic32_uart_platform_driver = {
984 .probe = pic32_uart_probe,
985 .remove = pic32_uart_remove,
987 .name = PIC32_DEV_NAME,
988 .of_match_table = of_match_ptr(pic32_serial_dt_ids),
989 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32),
993 static int __init pic32_uart_init(void)
997 ret = uart_register_driver(&pic32_uart_driver);
999 pr_err("failed to register %s:%d\n",
1000 pic32_uart_driver.driver_name, ret);
1004 ret = platform_driver_register(&pic32_uart_platform_driver);
1006 pr_err("fail to register pic32 uart\n");
1007 uart_unregister_driver(&pic32_uart_driver);
1012 arch_initcall(pic32_uart_init);
1014 static void __exit pic32_uart_exit(void)
1016 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
1017 unregister_console(&pic32_console);
1019 platform_driver_unregister(&pic32_uart_platform_driver);
1020 uart_unregister_driver(&pic32_uart_driver);
1022 module_exit(pic32_uart_exit);
1024 MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
1025 MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
1026 MODULE_LICENSE("GPL v2");