drivers/tty/serial/pch_uart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   4  */
   5 #include <linux/kernel.h>
   6 #include <linux/serial_reg.h>
   7 #include <linux/slab.h>
   8 #include <linux/module.h>
   9 #include <linux/pci.h>
  10 #include <linux/console.h>
  11 #include <linux/serial_core.h>
  12 #include <linux/tty.h>
  13 #include <linux/tty_flip.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/dmi.h>
  17 #include <linux/nmi.h>
  18 #include <linux/delay.h>
  19 #include <linux/of.h>
  20
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/pch_dma.h>
  24
  25 enum {
  26         PCH_UART_HANDLED_RX_INT_SHIFT,
  27         PCH_UART_HANDLED_TX_INT_SHIFT,
  28         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  29         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  30         PCH_UART_HANDLED_MS_INT_SHIFT,
  31         PCH_UART_HANDLED_LS_INT_SHIFT,
  32 };
  33
  34 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  35
  36 /* Set the max number of UART port
  37  * Intel EG20T PCH: 4 port
  38  * LAPIS Semiconductor ML7213 IOH: 3 port
  39  * LAPIS Semiconductor ML7223 IOH: 2 port
  40 */
  41 #define PCH_UART_NR     4
  42
  43 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  44 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  45 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  46                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  47 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  48                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  49 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  50
  51 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  52
  53 #define PCH_UART_RBR            0x00
  54 #define PCH_UART_THR            0x00
  55
  56 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  57                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  58 #define PCH_UART_IER_ERBFI      0x00000001
  59 #define PCH_UART_IER_ETBEI      0x00000002
  60 #define PCH_UART_IER_ELSI       0x00000004
  61 #define PCH_UART_IER_EDSSI      0x00000008
  62
  63 #define PCH_UART_IIR_IP                 0x00000001
  64 #define PCH_UART_IIR_IID                0x00000006
  65 #define PCH_UART_IIR_MSI                0x00000000
  66 #define PCH_UART_IIR_TRI                0x00000002
  67 #define PCH_UART_IIR_RRI                0x00000004
  68 #define PCH_UART_IIR_REI                0x00000006
  69 #define PCH_UART_IIR_TOI                0x00000008
  70 #define PCH_UART_IIR_FIFO256            0x00000020
  71 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  72 #define PCH_UART_IIR_FE                 0x000000C0
  73
  74 #define PCH_UART_FCR_FIFOE              0x00000001
  75 #define PCH_UART_FCR_RFR                0x00000002
  76 #define PCH_UART_FCR_TFR                0x00000004
  77 #define PCH_UART_FCR_DMS                0x00000008
  78 #define PCH_UART_FCR_FIFO256            0x00000020
  79 #define PCH_UART_FCR_RFTL               0x000000C0
  80
  81 #define PCH_UART_FCR_RFTL1              0x00000000
  82 #define PCH_UART_FCR_RFTL64             0x00000040
  83 #define PCH_UART_FCR_RFTL128            0x00000080
  84 #define PCH_UART_FCR_RFTL224            0x000000C0
  85 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  86 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  87 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  88 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  89 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  90 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
  91 #define PCH_UART_FCR_RFTL_SHIFT         6
  92
  93 #define PCH_UART_LCR_WLS        0x00000003
  94 #define PCH_UART_LCR_STB        0x00000004
  95 #define PCH_UART_LCR_PEN        0x00000008
  96 #define PCH_UART_LCR_EPS        0x00000010
  97 #define PCH_UART_LCR_SP         0x00000020
  98 #define PCH_UART_LCR_SB         0x00000040
  99 #define PCH_UART_LCR_DLAB       0x00000080
 100 #define PCH_UART_LCR_NP         0x00000000
 101 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 102 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 103 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 104 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 105                                 PCH_UART_LCR_SP)
 106
 107 #define PCH_UART_LCR_5BIT       0x00000000
 108 #define PCH_UART_LCR_6BIT       0x00000001
 109 #define PCH_UART_LCR_7BIT       0x00000002
 110 #define PCH_UART_LCR_8BIT       0x00000003
 111
 112 #define PCH_UART_MCR_DTR        0x00000001
 113 #define PCH_UART_MCR_RTS        0x00000002
 114 #define PCH_UART_MCR_OUT        0x0000000C
 115 #define PCH_UART_MCR_LOOP       0x00000010
 116 #define PCH_UART_MCR_AFE        0x00000020
 117
 118 #define PCH_UART_LSR_DR         0x00000001
 119 #define PCH_UART_LSR_ERR        (1<<7)
 120
 121 #define PCH_UART_MSR_DCTS       0x00000001
 122 #define PCH_UART_MSR_DDSR       0x00000002
 123 #define PCH_UART_MSR_TERI       0x00000004
 124 #define PCH_UART_MSR_DDCD       0x00000008
 125 #define PCH_UART_MSR_CTS        0x00000010
 126 #define PCH_UART_MSR_DSR        0x00000020
 127 #define PCH_UART_MSR_RI         0x00000040
 128 #define PCH_UART_MSR_DCD        0x00000080
 129 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 130                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 131
 132 #define PCH_UART_DLL            0x00
 133 #define PCH_UART_DLM            0x01
 134
 135 #define PCH_UART_BRCSR          0x0E
 136
 137 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 138 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 139 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 140 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 141 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 142
 143 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 144 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 145 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 146 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 147 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 148 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 149 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 150 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 151 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 152 #define PCH_UART_HAL_STB1               0
 153 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 154
 155 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 156 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 157 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 158                                         PCH_UART_HAL_CLR_RX_FIFO)
 159
 160 #define PCH_UART_HAL_DMA_MODE0          0
 161 #define PCH_UART_HAL_FIFO_DIS           0
 162 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 163 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 164                                         PCH_UART_FCR_FIFO256)
 165 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 166 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 167 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 168 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 169 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 170 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 171 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 172 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 173 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 174 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 175 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 176 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 177 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 178 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 179
 180 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 181 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 182 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 183 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 184 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 185
 186 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 187 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 188 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 189 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 190 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 191
 192 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 193
 194 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 195 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 196 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 197 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 198 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 199 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
 200
 201 struct pch_uart_buffer {
 202         unsigned char *buf;
 203         int size;
 204 };
 205
 206 struct eg20t_port {
 207         struct uart_port port;
 208         int port_type;
 209         void __iomem *membase;
 210         resource_size_t mapbase;
 211         unsigned int iobase;
 212         struct pci_dev *pdev;
 213         int fifo_size;
 214         unsigned int uartclk;
 215         int start_tx;
 216         int start_rx;
 217         int tx_empty;
 218         int trigger;
 219         int trigger_level;
 220         struct pch_uart_buffer rxbuf;
 221         unsigned int dmsr;
 222         unsigned int fcr;
 223         unsigned int mcr;
 224         unsigned int use_dma;
 225         struct dma_async_tx_descriptor  *desc_tx;
 226         struct dma_async_tx_descriptor  *desc_rx;
 227         struct pch_dma_slave            param_tx;
 228         struct pch_dma_slave            param_rx;
 229         struct dma_chan                 *chan_tx;
 230         struct dma_chan                 *chan_rx;
 231         struct scatterlist              *sg_tx_p;
 232         int                             nent;
 233         int                             orig_nent;
 234         struct scatterlist              sg_rx;
 235         int                             tx_dma_use;
 236         void                            *rx_buf_virt;
 237         dma_addr_t                      rx_buf_dma;
 238
 239 #define IRQ_NAME_SIZE 17
 240         char                            irq_name[IRQ_NAME_SIZE];
 241
 242         /* protect the eg20t_port private structure and io access to membase */
 243         spinlock_t lock;
 244 };
 245
 246 /**
 247  * struct pch_uart_driver_data - private data structure for UART-DMA
 248  * @port_type:                  The type of UART port
 249  * @line_no:                    UART port line number (0, 1, 2...)
 250  */
 251 struct pch_uart_driver_data {
 252         int port_type;
 253         int line_no;
 254 };
 255
 256 enum pch_uart_num_t {
 257         pch_et20t_uart0 = 0,
 258         pch_et20t_uart1,
 259         pch_et20t_uart2,
 260         pch_et20t_uart3,
 261         pch_ml7213_uart0,
 262         pch_ml7213_uart1,
 263         pch_ml7213_uart2,
 264         pch_ml7223_uart0,
 265         pch_ml7223_uart1,
 266         pch_ml7831_uart0,
 267         pch_ml7831_uart1,
 268 };
 269
 270 static struct pch_uart_driver_data drv_dat[] = {
 271         [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
 272         [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
 273         [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
 274         [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
 275         [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
 276         [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
 277         [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
 278         [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
 279         [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
 280         [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
 281         [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
 282 };
 283
 284 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 285 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 286 #endif
 287 static unsigned int default_baud = 9600;
 288 static unsigned int user_uartclk = 0;
 289 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 290 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 291 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 292 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 293
 294 #define PCH_REGS_BUFSIZE        1024
 295
 296
 297 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 298                                 size_t count, loff_t *ppos)
 299 {
 300         struct eg20t_port *priv = file->private_data;
 301         char *buf;
 302         u32 len = 0;
 303         ssize_t ret;
 304         unsigned char lcr;
 305
 306         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 307         if (!buf)
 308                 return 0;
 309
 310         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 311                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 312
 313         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 314                         "=================================\n");
 315         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 316                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 317         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 318                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 319         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 320                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 321         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 322                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 323         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 324                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 325         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 326                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 327         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 328                         "BRCSR: \t0x%02x\n",
 329                         ioread8(priv->membase + PCH_UART_BRCSR));
 330
 331         lcr = ioread8(priv->membase + UART_LCR);
 332         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 333         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 334                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 335         len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
 336                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 337         iowrite8(lcr, priv->membase + UART_LCR);
 338
 339         if (len > PCH_REGS_BUFSIZE)
 340                 len = PCH_REGS_BUFSIZE;
 341
 342         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 343         kfree(buf);
 344         return ret;
 345 }
 346
 347 static const struct file_operations port_regs_ops = {
 348         .owner          = THIS_MODULE,
 349         .open           = simple_open,
 350         .read           = port_show_regs,
 351         .llseek         = default_llseek,
 352 };
 353
 354 static const struct dmi_system_id pch_uart_dmi_table[] = {
 355         {
 356                 .ident = "CM-iTC",
 357                 {
 358                         DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
 359                 },
 360                 (void *)CMITC_UARTCLK,
 361         },
 362         {
 363                 .ident = "FRI2",
 364                 {
 365                         DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
 366                 },
 367                 (void *)FRI2_64_UARTCLK,
 368         },
 369         {
 370                 .ident = "Fish River Island II",
 371                 {
 372                         DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
 373                 },
 374                 (void *)FRI2_48_UARTCLK,
 375         },
 376         {
 377                 .ident = "COMe-mTT",
 378                 {
 379                         DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
 380                 },
 381                 (void *)NTC1_UARTCLK,
 382         },
 383         {
 384                 .ident = "nanoETXexpress-TT",
 385                 {
 386                         DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
 387                 },
 388                 (void *)NTC1_UARTCLK,
 389         },
 390         {
 391                 .ident = "MinnowBoard",
 392                 {
 393                         DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
 394                 },
 395                 (void *)MINNOW_UARTCLK,
 396         },
 397         { }
 398 };
 399
 400 /* Return UART clock, checking for board specific clocks. */
 401 static unsigned int pch_uart_get_uartclk(void)
 402 {
 403         const struct dmi_system_id *d;
 404
 405         if (user_uartclk)
 406                 return user_uartclk;
 407
 408         d = dmi_first_match(pch_uart_dmi_table);
 409         if (d)
 410                 return (unsigned long)d->driver_data;
 411
 412         return DEFAULT_UARTCLK;
 413 }
 414
 415 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 416                                           unsigned int flag)
 417 {
 418         u8 ier = ioread8(priv->membase + UART_IER);
 419         ier |= flag & PCH_UART_IER_MASK;
 420         iowrite8(ier, priv->membase + UART_IER);
 421 }
 422
 423 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 424                                            unsigned int flag)
 425 {
 426         u8 ier = ioread8(priv->membase + UART_IER);
 427         ier &= ~(flag & PCH_UART_IER_MASK);
 428         iowrite8(ier, priv->membase + UART_IER);
 429 }
 430
 431 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
 432                                  unsigned int parity, unsigned int bits,
 433                                  unsigned int stb)
 434 {
 435         unsigned int dll, dlm, lcr;
 436         int div;
 437
 438         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 439         if (div < 0 || USHRT_MAX <= div) {
 440                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 441                 return -EINVAL;
 442         }
 443
 444         dll = (unsigned int)div & 0x00FFU;
 445         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 446
 447         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 448                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 449                 return -EINVAL;
 450         }
 451
 452         if (bits & ~PCH_UART_LCR_WLS) {
 453                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 454                 return -EINVAL;
 455         }
 456
 457         if (stb & ~PCH_UART_LCR_STB) {
 458                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 459                 return -EINVAL;
 460         }
 461
 462         lcr = parity;
 463         lcr |= bits;
 464         lcr |= stb;
 465
 466         dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
 467                  __func__, baud, div, lcr, jiffies);
 468         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 469         iowrite8(dll, priv->membase + PCH_UART_DLL);
 470         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 471         iowrite8(lcr, priv->membase + UART_LCR);
 472
 473         return 0;
 474 }
 475
 476 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 477                                     unsigned int flag)
 478 {
 479         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 480                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 481                         __func__, flag);
 482                 return -EINVAL;
 483         }
 484
 485         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 486         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 487                  priv->membase + UART_FCR);
 488         iowrite8(priv->fcr, priv->membase + UART_FCR);
 489
 490         return 0;
 491 }
 492
 493 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 494                                  unsigned int dmamode,
 495                                  unsigned int fifo_size, unsigned int trigger)
 496 {
 497         u8 fcr;
 498
 499         if (dmamode & ~PCH_UART_FCR_DMS) {
 500                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 501                         __func__, dmamode);
 502                 return -EINVAL;
 503         }
 504
 505         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 506                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 507                         __func__, fifo_size);
 508                 return -EINVAL;
 509         }
 510
 511         if (trigger & ~PCH_UART_FCR_RFTL) {
 512                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 513                         __func__, trigger);
 514                 return -EINVAL;
 515         }
 516
 517         switch (priv->fifo_size) {
 518         case 256:
 519                 priv->trigger_level =
 520                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 521                 break;
 522         case 64:
 523                 priv->trigger_level =
 524                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 525                 break;
 526         case 16:
 527                 priv->trigger_level =
 528                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 529                 break;
 530         default:
 531                 priv->trigger_level =
 532                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 533                 break;
 534         }
 535         fcr =
 536             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 537         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 538         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 539                  priv->membase + UART_FCR);
 540         iowrite8(fcr, priv->membase + UART_FCR);
 541         priv->fcr = fcr;
 542
 543         return 0;
 544 }
 545
 546 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 547 {
 548         unsigned int msr = ioread8(priv->membase + UART_MSR);
 549         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 550         return (u8)msr;
 551 }
 552
 553 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 554                              int rx_size)
 555 {
 556         int i;
 557         u8 rbr, lsr;
 558         struct uart_port *port = &priv->port;
 559
 560         lsr = ioread8(priv->membase + UART_LSR);
 561         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 562              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 563              lsr = ioread8(priv->membase + UART_LSR)) {
 564                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 565
 566                 if (lsr & UART_LSR_BI) {
 567                         port->icount.brk++;
 568                         if (uart_handle_break(port))
 569                                 continue;
 570                 }
 571                 if (uart_handle_sysrq_char(port, rbr))
 572                         continue;
 573
 574                 buf[i++] = rbr;
 575         }
 576         return i;
 577 }
 578
 579 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 580 {
 581         return ioread8(priv->membase + UART_IIR) &\
 582                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 583 }
 584
 585 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 586 {
 587         return ioread8(priv->membase + UART_LSR);
 588 }
 589
 590 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 591 {
 592         unsigned int lcr;
 593
 594         lcr = ioread8(priv->membase + UART_LCR);
 595         if (on)
 596                 lcr |= PCH_UART_LCR_SB;
 597         else
 598                 lcr &= ~PCH_UART_LCR_SB;
 599
 600         iowrite8(lcr, priv->membase + UART_LCR);
 601 }
 602
 603 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 604                    int size)
 605 {
 606         struct uart_port *port = &priv->port;
 607         struct tty_port *tport = &port->state->port;
 608
 609         tty_insert_flip_string(tport, buf, size);
 610         tty_flip_buffer_push(tport);
 611
 612         return 0;
 613 }
 614
 615 static int dma_push_rx(struct eg20t_port *priv, int size)
 616 {
 617         int room;
 618         struct uart_port *port = &priv->port;
 619         struct tty_port *tport = &port->state->port;
 620
 621         room = tty_buffer_request_room(tport, size);
 622
 623         if (room < size)
 624                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 625                          size - room);
 626         if (!room)
 627                 return 0;
 628
 629         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 630
 631         port->icount.rx += room;
 632
 633         return room;
 634 }
 635
 636 static void pch_free_dma(struct uart_port *port)
 637 {
 638         struct eg20t_port *priv;
 639         priv = container_of(port, struct eg20t_port, port);
 640
 641         if (priv->chan_tx) {
 642                 dma_release_channel(priv->chan_tx);
 643                 priv->chan_tx = NULL;
 644         }
 645         if (priv->chan_rx) {
 646                 dma_release_channel(priv->chan_rx);
 647                 priv->chan_rx = NULL;
 648         }
 649
 650         if (priv->rx_buf_dma) {
 651                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 652                                   priv->rx_buf_dma);
 653                 priv->rx_buf_virt = NULL;
 654                 priv->rx_buf_dma = 0;
 655         }
 656
 657         return;
 658 }
 659
 660 static bool filter(struct dma_chan *chan, void *slave)
 661 {
 662         struct pch_dma_slave *param = slave;
 663
 664         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 665                                                   chan->device->dev)) {
 666                 chan->private = param;
 667                 return true;
 668         } else {
 669                 return false;
 670         }
 671 }
 672
 673 static void pch_request_dma(struct uart_port *port)
 674 {
 675         dma_cap_mask_t mask;
 676         struct dma_chan *chan;
 677         struct pci_dev *dma_dev;
 678         struct pch_dma_slave *param;
 679         struct eg20t_port *priv =
 680                                 container_of(port, struct eg20t_port, port);
 681         dma_cap_zero(mask);
 682         dma_cap_set(DMA_SLAVE, mask);
 683
 684         /* Get DMA's dev information */
 685         dma_dev = pci_get_slot(priv->pdev->bus,
 686                         PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
 687
 688         /* Set Tx DMA */
 689         param = &priv->param_tx;
 690         param->dma_dev = &dma_dev->dev;
 691         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 692
 693         param->tx_reg = port->mapbase + UART_TX;
 694         chan = dma_request_channel(mask, filter, param);
 695         if (!chan) {
 696                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 697                         __func__);
 698                 return;
 699         }
 700         priv->chan_tx = chan;
 701
 702         /* Set Rx DMA */
 703         param = &priv->param_rx;
 704         param->dma_dev = &dma_dev->dev;
 705         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 706
 707         param->rx_reg = port->mapbase + UART_RX;
 708         chan = dma_request_channel(mask, filter, param);
 709         if (!chan) {
 710                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 711                         __func__);
 712                 dma_release_channel(priv->chan_tx);
 713                 priv->chan_tx = NULL;
 714                 return;
 715         }
 716
 717         /* Get Consistent memory for DMA */
 718         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 719                                     &priv->rx_buf_dma, GFP_KERNEL);
 720         priv->chan_rx = chan;
 721 }
 722
 723 static void pch_dma_rx_complete(void *arg)
 724 {
 725         struct eg20t_port *priv = arg;
 726         struct uart_port *port = &priv->port;
 727         int count;
 728
 729         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 730         count = dma_push_rx(priv, priv->trigger_level);
 731         if (count)
 732                 tty_flip_buffer_push(&port->state->port);
 733         async_tx_ack(priv->desc_rx);
 734         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 735                                             PCH_UART_HAL_RX_ERR_INT);
 736 }
 737
 738 static void pch_dma_tx_complete(void *arg)
 739 {
 740         struct eg20t_port *priv = arg;
 741         struct uart_port *port = &priv->port;
 742         struct circ_buf *xmit = &port->state->xmit;
 743         struct scatterlist *sg = priv->sg_tx_p;
 744         int i;
 745
 746         for (i = 0; i < priv->nent; i++, sg++) {
 747                 xmit->tail += sg_dma_len(sg);
 748                 port->icount.tx += sg_dma_len(sg);
 749         }
 750         xmit->tail &= UART_XMIT_SIZE - 1;
 751         async_tx_ack(priv->desc_tx);
 752         dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
 753         priv->tx_dma_use = 0;
 754         priv->nent = 0;
 755         priv->orig_nent = 0;
 756         kfree(priv->sg_tx_p);
 757         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 758 }
 759
 760 static int handle_rx_to(struct eg20t_port *priv)
 761 {
 762         struct pch_uart_buffer *buf;
 763         int rx_size;
 764         int ret;
 765         if (!priv->start_rx) {
 766                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 767                                                      PCH_UART_HAL_RX_ERR_INT);
 768                 return 0;
 769         }
 770         buf = &priv->rxbuf;
 771         do {
 772                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 773                 ret = push_rx(priv, buf->buf, rx_size);
 774                 if (ret)
 775                         return 0;
 776         } while (rx_size == buf->size);
 777
 778         return PCH_UART_HANDLED_RX_INT;
 779 }
 780
 781 static int handle_rx(struct eg20t_port *priv)
 782 {
 783         return handle_rx_to(priv);
 784 }
 785
 786 static int dma_handle_rx(struct eg20t_port *priv)
 787 {
 788         struct uart_port *port = &priv->port;
 789         struct dma_async_tx_descriptor *desc;
 790         struct scatterlist *sg;
 791
 792         priv = container_of(port, struct eg20t_port, port);
 793         sg = &priv->sg_rx;
 794
 795         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 796
 797         sg_dma_len(sg) = priv->trigger_level;
 798
 799         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 800                      sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
 801
 802         sg_dma_address(sg) = priv->rx_buf_dma;
 803
 804         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 805                         sg, 1, DMA_DEV_TO_MEM,
 806                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 807
 808         if (!desc)
 809                 return 0;
 810
 811         priv->desc_rx = desc;
 812         desc->callback = pch_dma_rx_complete;
 813         desc->callback_param = priv;
 814         desc->tx_submit(desc);
 815         dma_async_issue_pending(priv->chan_rx);
 816
 817         return PCH_UART_HANDLED_RX_INT;
 818 }
 819
 820 static unsigned int handle_tx(struct eg20t_port *priv)
 821 {
 822         struct uart_port *port = &priv->port;
 823         struct circ_buf *xmit = &port->state->xmit;
 824         int fifo_size;
 825         int tx_empty;
 826
 827         if (!priv->start_tx) {
 828                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 829                         __func__, jiffies);
 830                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 831                 priv->tx_empty = 1;
 832                 return 0;
 833         }
 834
 835         fifo_size = max(priv->fifo_size, 1);
 836         tx_empty = 1;
 837         if (port->x_char) {
 838                 iowrite8(port->x_char, priv->membase + PCH_UART_THR);
 839                 port->icount.tx++;
 840                 port->x_char = 0;
 841                 tx_empty = 0;
 842                 fifo_size--;
 843         }
 844
 845         while (!uart_tx_stopped(port) && !uart_circ_empty(xmit) && fifo_size) {
 846                 iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR);
 847                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 848                 port->icount.tx++;
 849                 fifo_size--;
 850                 tx_empty = 0;
 851         }
 852
 853         priv->tx_empty = tx_empty;
 854
 855         if (tx_empty) {
 856                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 857                 uart_write_wakeup(port);
 858         }
 859
 860         return PCH_UART_HANDLED_TX_INT;
 861 }
 862
 863 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 864 {
 865         struct uart_port *port = &priv->port;
 866         struct circ_buf *xmit = &port->state->xmit;
 867         struct scatterlist *sg;
 868         int nent;
 869         int fifo_size;
 870         struct dma_async_tx_descriptor *desc;
 871         int num;
 872         int i;
 873         int bytes;
 874         int size;
 875         int rem;
 876
 877         if (!priv->start_tx) {
 878                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 879                         __func__, jiffies);
 880                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 881                 priv->tx_empty = 1;
 882                 return 0;
 883         }
 884
 885         if (priv->tx_dma_use) {
 886                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 887                         __func__, jiffies);
 888                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 889                 priv->tx_empty = 1;
 890                 return 0;
 891         }
 892
 893         fifo_size = max(priv->fifo_size, 1);
 894
 895         if (port->x_char) {
 896                 iowrite8(port->x_char, priv->membase + PCH_UART_THR);
 897                 port->icount.tx++;
 898                 port->x_char = 0;
 899                 fifo_size--;
 900         }
 901
 902         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 903                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 904                              xmit->tail, UART_XMIT_SIZE));
 905         if (!bytes) {
 906                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 907                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 908                 uart_write_wakeup(port);
 909                 return 0;
 910         }
 911
 912         if (bytes > fifo_size) {
 913                 num = bytes / fifo_size + 1;
 914                 size = fifo_size;
 915                 rem = bytes % fifo_size;
 916         } else {
 917                 num = 1;
 918                 size = bytes;
 919                 rem = bytes;
 920         }
 921
 922         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 923                 __func__, num, size, rem);
 924
 925         priv->tx_dma_use = 1;
 926
 927         priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC);
 928         if (!priv->sg_tx_p) {
 929                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
 930                 return 0;
 931         }
 932
 933         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 934         sg = priv->sg_tx_p;
 935
 936         for (i = 0; i < num; i++, sg++) {
 937                 if (i == (num - 1))
 938                         sg_set_page(sg, virt_to_page(xmit->buf),
 939                                     rem, fifo_size * i);
 940                 else
 941                         sg_set_page(sg, virt_to_page(xmit->buf),
 942                                     size, fifo_size * i);
 943         }
 944
 945         sg = priv->sg_tx_p;
 946         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 947         if (!nent) {
 948                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
 949                 return 0;
 950         }
 951         priv->orig_nent = num;
 952         priv->nent = nent;
 953
 954         for (i = 0; i < nent; i++, sg++) {
 955                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
 956                               fifo_size * i;
 957                 sg_dma_address(sg) = (sg_dma_address(sg) &
 958                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
 959                 if (i == (nent - 1))
 960                         sg_dma_len(sg) = rem;
 961                 else
 962                         sg_dma_len(sg) = size;
 963         }
 964
 965         desc = dmaengine_prep_slave_sg(priv->chan_tx,
 966                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
 967                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 968         if (!desc) {
 969                 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
 970                         __func__);
 971                 return 0;
 972         }
 973         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
 974         priv->desc_tx = desc;
 975         desc->callback = pch_dma_tx_complete;
 976         desc->callback_param = priv;
 977
 978         desc->tx_submit(desc);
 979
 980         dma_async_issue_pending(priv->chan_tx);
 981
 982         return PCH_UART_HANDLED_TX_INT;
 983 }
 984
 985 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
 986 {
 987         struct uart_port *port = &priv->port;
 988         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 989         char   *error_msg[5] = {};
 990         int    i = 0;
 991
 992         if (lsr & PCH_UART_LSR_ERR)
 993                 error_msg[i++] = "Error data in FIFO\n";
 994
 995         if (lsr & UART_LSR_FE) {
 996                 port->icount.frame++;
 997                 error_msg[i++] = "  Framing Error\n";
 998         }
 999
1000         if (lsr & UART_LSR_PE) {
1001                 port->icount.parity++;
1002                 error_msg[i++] = "  Parity Error\n";
1003         }
1004
1005         if (lsr & UART_LSR_OE) {
1006                 port->icount.overrun++;
1007                 error_msg[i++] = "  Overrun Error\n";
1008         }
1009
1010         if (tty == NULL) {
1011                 for (i = 0; error_msg[i] != NULL; i++)
1012                         dev_err(&priv->pdev->dev, error_msg[i]);
1013         } else {
1014                 tty_kref_put(tty);
1015         }
1016 }
1017
1018 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1019 {
1020         struct eg20t_port *priv = dev_id;
1021         unsigned int handled;
1022         u8 lsr;
1023         int ret = 0;
1024         unsigned char iid;
1025         unsigned long flags;
1026         int next = 1;
1027         u8 msr;
1028
1029         spin_lock_irqsave(&priv->lock, flags);
1030         handled = 0;
1031         while (next) {
1032                 iid = pch_uart_hal_get_iid(priv);
1033                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1034                         break;
1035                 switch (iid) {
1036                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1037                         lsr = pch_uart_hal_get_line_status(priv);
1038                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1039                                                 UART_LSR_PE | UART_LSR_OE)) {
1040                                 pch_uart_err_ir(priv, lsr);
1041                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1042                         } else {
1043                                 ret = PCH_UART_HANDLED_LS_INT;
1044                         }
1045                         break;
1046                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1047                         if (priv->use_dma) {
1048                                 pch_uart_hal_disable_interrupt(priv,
1049                                                 PCH_UART_HAL_RX_INT |
1050                                                 PCH_UART_HAL_RX_ERR_INT);
1051                                 ret = dma_handle_rx(priv);
1052                                 if (!ret)
1053                                         pch_uart_hal_enable_interrupt(priv,
1054                                                 PCH_UART_HAL_RX_INT |
1055                                                 PCH_UART_HAL_RX_ERR_INT);
1056                         } else {
1057                                 ret = handle_rx(priv);
1058                         }
1059                         break;
1060                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1061                                                    (FIFO Timeout) */
1062                         ret = handle_rx_to(priv);
1063                         break;
1064                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1065                                                    Empty */
1066                         if (priv->use_dma)
1067                                 ret = dma_handle_tx(priv);
1068                         else
1069                                 ret = handle_tx(priv);
1070                         break;
1071                 case PCH_UART_IID_MS:   /* Modem Status */
1072                         msr = pch_uart_hal_get_modem(priv);
1073                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1074                                      means final interrupt */
1075                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1076                                 break;
1077                         ret |= PCH_UART_HANDLED_MS_INT;
1078                         break;
1079                 default:        /* Never junp to this label */
1080                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1081                                 iid, jiffies);
1082                         ret = -1;
1083                         next = 0;
1084                         break;
1085                 }
1086                 handled |= (unsigned int)ret;
1087         }
1088
1089         spin_unlock_irqrestore(&priv->lock, flags);
1090         return IRQ_RETVAL(handled);
1091 }
1092
1093 /* This function tests whether the transmitter fifo and shifter for the port
1094                                                 described by 'port' is empty. */
1095 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1096 {
1097         struct eg20t_port *priv;
1098
1099         priv = container_of(port, struct eg20t_port, port);
1100         if (priv->tx_empty)
1101                 return TIOCSER_TEMT;
1102         else
1103                 return 0;
1104 }
1105
1106 /* Returns the current state of modem control inputs. */
1107 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1108 {
1109         struct eg20t_port *priv;
1110         u8 modem;
1111         unsigned int ret = 0;
1112
1113         priv = container_of(port, struct eg20t_port, port);
1114         modem = pch_uart_hal_get_modem(priv);
1115
1116         if (modem & UART_MSR_DCD)
1117                 ret |= TIOCM_CAR;
1118
1119         if (modem & UART_MSR_RI)
1120                 ret |= TIOCM_RNG;
1121
1122         if (modem & UART_MSR_DSR)
1123                 ret |= TIOCM_DSR;
1124
1125         if (modem & UART_MSR_CTS)
1126                 ret |= TIOCM_CTS;
1127
1128         return ret;
1129 }
1130
1131 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1132 {
1133         u32 mcr = 0;
1134         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1135
1136         if (mctrl & TIOCM_DTR)
1137                 mcr |= UART_MCR_DTR;
1138         if (mctrl & TIOCM_RTS)
1139                 mcr |= UART_MCR_RTS;
1140         if (mctrl & TIOCM_LOOP)
1141                 mcr |= UART_MCR_LOOP;
1142
1143         if (priv->mcr & UART_MCR_AFE)
1144                 mcr |= UART_MCR_AFE;
1145
1146         if (mctrl)
1147                 iowrite8(mcr, priv->membase + UART_MCR);
1148 }
1149
1150 static void pch_uart_stop_tx(struct uart_port *port)
1151 {
1152         struct eg20t_port *priv;
1153         priv = container_of(port, struct eg20t_port, port);
1154         priv->start_tx = 0;
1155         priv->tx_dma_use = 0;
1156 }
1157
1158 static void pch_uart_start_tx(struct uart_port *port)
1159 {
1160         struct eg20t_port *priv;
1161
1162         priv = container_of(port, struct eg20t_port, port);
1163
1164         if (priv->use_dma) {
1165                 if (priv->tx_dma_use) {
1166                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1167                                 __func__);
1168                         return;
1169                 }
1170         }
1171
1172         priv->start_tx = 1;
1173         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1174 }
1175
1176 static void pch_uart_stop_rx(struct uart_port *port)
1177 {
1178         struct eg20t_port *priv;
1179         priv = container_of(port, struct eg20t_port, port);
1180         priv->start_rx = 0;
1181         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1182                                              PCH_UART_HAL_RX_ERR_INT);
1183 }
1184
1185 /* Enable the modem status interrupts. */
1186 static void pch_uart_enable_ms(struct uart_port *port)
1187 {
1188         struct eg20t_port *priv;
1189         priv = container_of(port, struct eg20t_port, port);
1190         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1191 }
1192
1193 /* Control the transmission of a break signal. */
1194 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1195 {
1196         struct eg20t_port *priv;
1197         unsigned long flags;
1198
1199         priv = container_of(port, struct eg20t_port, port);
1200         spin_lock_irqsave(&priv->lock, flags);
1201         pch_uart_hal_set_break(priv, ctl);
1202         spin_unlock_irqrestore(&priv->lock, flags);
1203 }
1204
1205 /* Grab any interrupt resources and initialise any low level driver state. */
1206 static int pch_uart_startup(struct uart_port *port)
1207 {
1208         struct eg20t_port *priv;
1209         int ret;
1210         int fifo_size;
1211         int trigger_level;
1212
1213         priv = container_of(port, struct eg20t_port, port);
1214         priv->tx_empty = 1;
1215
1216         if (port->uartclk)
1217                 priv->uartclk = port->uartclk;
1218         else
1219                 port->uartclk = priv->uartclk;
1220
1221         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1222         ret = pch_uart_hal_set_line(priv, default_baud,
1223                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1224                               PCH_UART_HAL_STB1);
1225         if (ret)
1226                 return ret;
1227
1228         switch (priv->fifo_size) {
1229         case 256:
1230                 fifo_size = PCH_UART_HAL_FIFO256;
1231                 break;
1232         case 64:
1233                 fifo_size = PCH_UART_HAL_FIFO64;
1234                 break;
1235         case 16:
1236                 fifo_size = PCH_UART_HAL_FIFO16;
1237                 break;
1238         case 1:
1239         default:
1240                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1241                 break;
1242         }
1243
1244         switch (priv->trigger) {
1245         case PCH_UART_HAL_TRIGGER1:
1246                 trigger_level = 1;
1247                 break;
1248         case PCH_UART_HAL_TRIGGER_L:
1249                 trigger_level = priv->fifo_size / 4;
1250                 break;
1251         case PCH_UART_HAL_TRIGGER_M:
1252                 trigger_level = priv->fifo_size / 2;
1253                 break;
1254         case PCH_UART_HAL_TRIGGER_H:
1255         default:
1256                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1257                 break;
1258         }
1259
1260         priv->trigger_level = trigger_level;
1261         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1262                                     fifo_size, priv->trigger);
1263         if (ret < 0)
1264                 return ret;
1265
1266         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1267                         priv->irq_name, priv);
1268         if (ret < 0)
1269                 return ret;
1270
1271         if (priv->use_dma)
1272                 pch_request_dma(port);
1273
1274         priv->start_rx = 1;
1275         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1276                                             PCH_UART_HAL_RX_ERR_INT);
1277         uart_update_timeout(port, CS8, default_baud);
1278
1279         return 0;
1280 }
1281
1282 static void pch_uart_shutdown(struct uart_port *port)
1283 {
1284         struct eg20t_port *priv;
1285         int ret;
1286
1287         priv = container_of(port, struct eg20t_port, port);
1288         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1289         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1290         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1291                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1292         if (ret)
1293                 dev_err(priv->port.dev,
1294                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1295
1296         pch_free_dma(port);
1297
1298         free_irq(priv->port.irq, priv);
1299 }
1300
1301 /* Change the port parameters, including word length, parity, stop
1302  *bits.  Update read_status_mask and ignore_status_mask to indicate
1303  *the types of events we are interested in receiving.  */
1304 static void pch_uart_set_termios(struct uart_port *port,
1305                                  struct ktermios *termios, struct ktermios *old)
1306 {
1307         int rtn;
1308         unsigned int baud, parity, bits, stb;
1309         struct eg20t_port *priv;
1310         unsigned long flags;
1311
1312         priv = container_of(port, struct eg20t_port, port);
1313         switch (termios->c_cflag & CSIZE) {
1314         case CS5:
1315                 bits = PCH_UART_HAL_5BIT;
1316                 break;
1317         case CS6:
1318                 bits = PCH_UART_HAL_6BIT;
1319                 break;
1320         case CS7:
1321                 bits = PCH_UART_HAL_7BIT;
1322                 break;
1323         default:                /* CS8 */
1324                 bits = PCH_UART_HAL_8BIT;
1325                 break;
1326         }
1327         if (termios->c_cflag & CSTOPB)
1328                 stb = PCH_UART_HAL_STB2;
1329         else
1330                 stb = PCH_UART_HAL_STB1;
1331
1332         if (termios->c_cflag & PARENB) {
1333                 if (termios->c_cflag & PARODD)
1334                         parity = PCH_UART_HAL_PARITY_ODD;
1335                 else
1336                         parity = PCH_UART_HAL_PARITY_EVEN;
1337
1338         } else
1339                 parity = PCH_UART_HAL_PARITY_NONE;
1340
1341         /* Only UART0 has auto hardware flow function */
1342         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1343                 priv->mcr |= UART_MCR_AFE;
1344         else
1345                 priv->mcr &= ~UART_MCR_AFE;
1346
1347         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1348
1349         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1350
1351         spin_lock_irqsave(&priv->lock, flags);
1352         spin_lock(&port->lock);
1353
1354         uart_update_timeout(port, termios->c_cflag, baud);
1355         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1356         if (rtn)
1357                 goto out;
1358
1359         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1360         /* Don't rewrite B0 */
1361         if (tty_termios_baud_rate(termios))
1362                 tty_termios_encode_baud_rate(termios, baud, baud);
1363
1364 out:
1365         spin_unlock(&port->lock);
1366         spin_unlock_irqrestore(&priv->lock, flags);
1367 }
1368
1369 static const char *pch_uart_type(struct uart_port *port)
1370 {
1371         return KBUILD_MODNAME;
1372 }
1373
1374 static void pch_uart_release_port(struct uart_port *port)
1375 {
1376         struct eg20t_port *priv;
1377
1378         priv = container_of(port, struct eg20t_port, port);
1379         pci_iounmap(priv->pdev, priv->membase);
1380         pci_release_regions(priv->pdev);
1381 }
1382
1383 static int pch_uart_request_port(struct uart_port *port)
1384 {
1385         struct eg20t_port *priv;
1386         int ret;
1387         void __iomem *membase;
1388
1389         priv = container_of(port, struct eg20t_port, port);
1390         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1391         if (ret < 0)
1392                 return -EBUSY;
1393
1394         membase = pci_iomap(priv->pdev, 1, 0);
1395         if (!membase) {
1396                 pci_release_regions(priv->pdev);
1397                 return -EBUSY;
1398         }
1399         priv->membase = port->membase = membase;
1400
1401         return 0;
1402 }
1403
1404 static void pch_uart_config_port(struct uart_port *port, int type)
1405 {
1406         struct eg20t_port *priv;
1407
1408         priv = container_of(port, struct eg20t_port, port);
1409         if (type & UART_CONFIG_TYPE) {
1410                 port->type = priv->port_type;
1411                 pch_uart_request_port(port);
1412         }
1413 }
1414
1415 static int pch_uart_verify_port(struct uart_port *port,
1416                                 struct serial_struct *serinfo)
1417 {
1418         struct eg20t_port *priv;
1419
1420         priv = container_of(port, struct eg20t_port, port);
1421         if (serinfo->flags & UPF_LOW_LATENCY) {
1422                 dev_info(priv->port.dev,
1423                         "PCH UART : Use PIO Mode (without DMA)\n");
1424                 priv->use_dma = 0;
1425                 serinfo->flags &= ~UPF_LOW_LATENCY;
1426         } else {
1427 #ifndef CONFIG_PCH_DMA
1428                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1429                         __func__);
1430                 return -EOPNOTSUPP;
1431 #endif
1432                 if (!priv->use_dma) {
1433                         pch_request_dma(port);
1434                         if (priv->chan_rx)
1435                                 priv->use_dma = 1;
1436                 }
1437                 dev_info(priv->port.dev, "PCH UART: %s\n",
1438                                 priv->use_dma ?
1439                                 "Use DMA Mode" : "No DMA");
1440         }
1441
1442         return 0;
1443 }
1444
1445 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1446 /*
1447  *      Wait for transmitter & holding register to empty
1448  */
1449 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1450 {
1451         unsigned int status, tmout = 10000;
1452
1453         /* Wait up to 10ms for the character(s) to be sent. */
1454         for (;;) {
1455                 status = ioread8(up->membase + UART_LSR);
1456
1457                 if ((status & bits) == bits)
1458                         break;
1459                 if (--tmout == 0)
1460                         break;
1461                 udelay(1);
1462         }
1463
1464         /* Wait up to 1s for flow control if necessary */
1465         if (up->port.flags & UPF_CONS_FLOW) {
1466                 unsigned int tmout;
1467                 for (tmout = 1000000; tmout; tmout--) {
1468                         unsigned int msr = ioread8(up->membase + UART_MSR);
1469                         if (msr & UART_MSR_CTS)
1470                                 break;
1471                         udelay(1);
1472                         touch_nmi_watchdog();
1473                 }
1474         }
1475 }
1476 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1477
1478 #ifdef CONFIG_CONSOLE_POLL
1479 /*
1480  * Console polling routines for communicate via uart while
1481  * in an interrupt or debug context.
1482  */
1483 static int pch_uart_get_poll_char(struct uart_port *port)
1484 {
1485         struct eg20t_port *priv =
1486                 container_of(port, struct eg20t_port, port);
1487         u8 lsr = ioread8(priv->membase + UART_LSR);
1488
1489         if (!(lsr & UART_LSR_DR))
1490                 return NO_POLL_CHAR;
1491
1492         return ioread8(priv->membase + PCH_UART_RBR);
1493 }
1494
1495
1496 static void pch_uart_put_poll_char(struct uart_port *port,
1497                          unsigned char c)
1498 {
1499         unsigned int ier;
1500         struct eg20t_port *priv =
1501                 container_of(port, struct eg20t_port, port);
1502
1503         /*
1504          * First save the IER then disable the interrupts
1505          */
1506         ier = ioread8(priv->membase + UART_IER);
1507         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1508
1509         wait_for_xmitr(priv, UART_LSR_THRE);
1510         /*
1511          * Send the character out.
1512          */
1513         iowrite8(c, priv->membase + PCH_UART_THR);
1514
1515         /*
1516          * Finally, wait for transmitter to become empty
1517          * and restore the IER
1518          */
1519         wait_for_xmitr(priv, BOTH_EMPTY);
1520         iowrite8(ier, priv->membase + UART_IER);
1521 }
1522 #endif /* CONFIG_CONSOLE_POLL */
1523
1524 static const struct uart_ops pch_uart_ops = {
1525         .tx_empty = pch_uart_tx_empty,
1526         .set_mctrl = pch_uart_set_mctrl,
1527         .get_mctrl = pch_uart_get_mctrl,
1528         .stop_tx = pch_uart_stop_tx,
1529         .start_tx = pch_uart_start_tx,
1530         .stop_rx = pch_uart_stop_rx,
1531         .enable_ms = pch_uart_enable_ms,
1532         .break_ctl = pch_uart_break_ctl,
1533         .startup = pch_uart_startup,
1534         .shutdown = pch_uart_shutdown,
1535         .set_termios = pch_uart_set_termios,
1536 /*      .pm             = pch_uart_pm,          Not supported yet */
1537         .type = pch_uart_type,
1538         .release_port = pch_uart_release_port,
1539         .request_port = pch_uart_request_port,
1540         .config_port = pch_uart_config_port,
1541         .verify_port = pch_uart_verify_port,
1542 #ifdef CONFIG_CONSOLE_POLL
1543         .poll_get_char = pch_uart_get_poll_char,
1544         .poll_put_char = pch_uart_put_poll_char,
1545 #endif
1546 };
1547
1548 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1549
1550 static void pch_console_putchar(struct uart_port *port, unsigned char ch)
1551 {
1552         struct eg20t_port *priv =
1553                 container_of(port, struct eg20t_port, port);
1554
1555         wait_for_xmitr(priv, UART_LSR_THRE);
1556         iowrite8(ch, priv->membase + PCH_UART_THR);
1557 }
1558
1559 /*
1560  *      Print a string to the serial port trying not to disturb
1561  *      any possible real use of the port...
1562  *
1563  *      The console_lock must be held when we get here.
1564  */
1565 static void
1566 pch_console_write(struct console *co, const char *s, unsigned int count)
1567 {
1568         struct eg20t_port *priv;
1569         unsigned long flags;
1570         int priv_locked = 1;
1571         int port_locked = 1;
1572         u8 ier;
1573
1574         priv = pch_uart_ports[co->index];
1575
1576         touch_nmi_watchdog();
1577
1578         local_irq_save(flags);
1579         if (priv->port.sysrq) {
1580                 /* call to uart_handle_sysrq_char already took the priv lock */
1581                 priv_locked = 0;
1582                 /* serial8250_handle_port() already took the port lock */
1583                 port_locked = 0;
1584         } else if (oops_in_progress) {
1585                 priv_locked = spin_trylock(&priv->lock);
1586                 port_locked = spin_trylock(&priv->port.lock);
1587         } else {
1588                 spin_lock(&priv->lock);
1589                 spin_lock(&priv->port.lock);
1590         }
1591
1592         /*
1593          *      First save the IER then disable the interrupts
1594          */
1595         ier = ioread8(priv->membase + UART_IER);
1596
1597         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1598
1599         uart_console_write(&priv->port, s, count, pch_console_putchar);
1600
1601         /*
1602          *      Finally, wait for transmitter to become empty
1603          *      and restore the IER
1604          */
1605         wait_for_xmitr(priv, BOTH_EMPTY);
1606         iowrite8(ier, priv->membase + UART_IER);
1607
1608         if (port_locked)
1609                 spin_unlock(&priv->port.lock);
1610         if (priv_locked)
1611                 spin_unlock(&priv->lock);
1612         local_irq_restore(flags);
1613 }
1614
1615 static int __init pch_console_setup(struct console *co, char *options)
1616 {
1617         struct uart_port *port;
1618         int baud = default_baud;
1619         int bits = 8;
1620         int parity = 'n';
1621         int flow = 'n';
1622
1623         /*
1624          * Check whether an invalid uart number has been specified, and
1625          * if so, search for the first available port that does have
1626          * console support.
1627          */
1628         if (co->index >= PCH_UART_NR)
1629                 co->index = 0;
1630         port = &pch_uart_ports[co->index]->port;
1631
1632         if (!port || (!port->iobase && !port->membase))
1633                 return -ENODEV;
1634
1635         port->uartclk = pch_uart_get_uartclk();
1636
1637         if (options)
1638                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1639
1640         return uart_set_options(port, co, baud, parity, bits, flow);
1641 }
1642
1643 static struct uart_driver pch_uart_driver;
1644
1645 static struct console pch_console = {
1646         .name           = PCH_UART_DRIVER_DEVICE,
1647         .write          = pch_console_write,
1648         .device         = uart_console_device,
1649         .setup          = pch_console_setup,
1650         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1651         .index          = -1,
1652         .data           = &pch_uart_driver,
1653 };
1654
1655 #define PCH_CONSOLE     (&pch_console)
1656 #else
1657 #define PCH_CONSOLE     NULL
1658 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1659
1660 static struct uart_driver pch_uart_driver = {
1661         .owner = THIS_MODULE,
1662         .driver_name = KBUILD_MODNAME,
1663         .dev_name = PCH_UART_DRIVER_DEVICE,
1664         .major = 0,
1665         .minor = 0,
1666         .nr = PCH_UART_NR,
1667         .cons = PCH_CONSOLE,
1668 };
1669
1670 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1671                                              const struct pci_device_id *id)
1672 {
1673         struct eg20t_port *priv;
1674         int ret;
1675         unsigned int iobase;
1676         unsigned int mapbase;
1677         unsigned char *rxbuf;
1678         int fifosize;
1679         int port_type;
1680         struct pch_uart_driver_data *board;
1681         char name[32];
1682
1683         board = &drv_dat[id->driver_data];
1684         port_type = board->port_type;
1685
1686         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1687         if (priv == NULL)
1688                 goto init_port_alloc_err;
1689
1690         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1691         if (!rxbuf)
1692                 goto init_port_free_txbuf;
1693
1694         switch (port_type) {
1695         case PORT_PCH_8LINE:
1696                 fifosize = 256; /* EG20T/ML7213: UART0 */
1697                 break;
1698         case PORT_PCH_2LINE:
1699                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1700                 break;
1701         default:
1702                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1703                 goto init_port_hal_free;
1704         }
1705
1706         pci_enable_msi(pdev);
1707         pci_set_master(pdev);
1708
1709         spin_lock_init(&priv->lock);
1710
1711         iobase = pci_resource_start(pdev, 0);
1712         mapbase = pci_resource_start(pdev, 1);
1713         priv->mapbase = mapbase;
1714         priv->iobase = iobase;
1715         priv->pdev = pdev;
1716         priv->tx_empty = 1;
1717         priv->rxbuf.buf = rxbuf;
1718         priv->rxbuf.size = PAGE_SIZE;
1719
1720         priv->fifo_size = fifosize;
1721         priv->uartclk = pch_uart_get_uartclk();
1722         priv->port_type = port_type;
1723         priv->port.dev = &pdev->dev;
1724         priv->port.iobase = iobase;
1725         priv->port.membase = NULL;
1726         priv->port.mapbase = mapbase;
1727         priv->port.irq = pdev->irq;
1728         priv->port.iotype = UPIO_PORT;
1729         priv->port.ops = &pch_uart_ops;
1730         priv->port.flags = UPF_BOOT_AUTOCONF;
1731         priv->port.fifosize = fifosize;
1732         priv->port.line = board->line_no;
1733         priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE);
1734         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1735
1736         snprintf(priv->irq_name, IRQ_NAME_SIZE,
1737                  KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1738                  priv->port.line);
1739
1740         spin_lock_init(&priv->port.lock);
1741
1742         pci_set_drvdata(pdev, priv);
1743         priv->trigger_level = 1;
1744         priv->fcr = 0;
1745
1746         if (pdev->dev.of_node)
1747                 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1748                                          , &user_uartclk);
1749
1750 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1751         pch_uart_ports[board->line_no] = priv;
1752 #endif
1753         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1754         if (ret < 0)
1755                 goto init_port_hal_free;
1756
1757         snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);
1758         debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv,
1759                             &port_regs_ops);
1760
1761         return priv;
1762
1763 init_port_hal_free:
1764 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1765         pch_uart_ports[board->line_no] = NULL;
1766 #endif
1767         free_page((unsigned long)rxbuf);
1768 init_port_free_txbuf:
1769         kfree(priv);
1770 init_port_alloc_err:
1771
1772         return NULL;
1773 }
1774
1775 static void pch_uart_exit_port(struct eg20t_port *priv)
1776 {
1777         char name[32];
1778
1779         snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);
1780         debugfs_remove(debugfs_lookup(name, NULL));
1781         uart_remove_one_port(&pch_uart_driver, &priv->port);
1782         free_page((unsigned long)priv->rxbuf.buf);
1783 }
1784
1785 static void pch_uart_pci_remove(struct pci_dev *pdev)
1786 {
1787         struct eg20t_port *priv = pci_get_drvdata(pdev);
1788
1789         pci_disable_msi(pdev);
1790
1791 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1792         pch_uart_ports[priv->port.line] = NULL;
1793 #endif
1794         pch_uart_exit_port(priv);
1795         pci_disable_device(pdev);
1796         kfree(priv);
1797         return;
1798 }
1799
1800 static int __maybe_unused pch_uart_pci_suspend(struct device *dev)
1801 {
1802         struct eg20t_port *priv = dev_get_drvdata(dev);
1803
1804         uart_suspend_port(&pch_uart_driver, &priv->port);
1805
1806         return 0;
1807 }
1808
1809 static int __maybe_unused pch_uart_pci_resume(struct device *dev)
1810 {
1811         struct eg20t_port *priv = dev_get_drvdata(dev);
1812
1813         uart_resume_port(&pch_uart_driver, &priv->port);
1814
1815         return 0;
1816 }
1817
1818 static const struct pci_device_id pch_uart_pci_id[] = {
1819         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1820          .driver_data = pch_et20t_uart0},
1821         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1822          .driver_data = pch_et20t_uart1},
1823         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1824          .driver_data = pch_et20t_uart2},
1825         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1826          .driver_data = pch_et20t_uart3},
1827         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1828          .driver_data = pch_ml7213_uart0},
1829         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1830          .driver_data = pch_ml7213_uart1},
1831         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1832          .driver_data = pch_ml7213_uart2},
1833         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1834          .driver_data = pch_ml7223_uart0},
1835         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1836          .driver_data = pch_ml7223_uart1},
1837         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1838          .driver_data = pch_ml7831_uart0},
1839         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1840          .driver_data = pch_ml7831_uart1},
1841         {0,},
1842 };
1843
1844 static int pch_uart_pci_probe(struct pci_dev *pdev,
1845                                         const struct pci_device_id *id)
1846 {
1847         int ret;
1848         struct eg20t_port *priv;
1849
1850         ret = pci_enable_device(pdev);
1851         if (ret < 0)
1852                 goto probe_error;
1853
1854         priv = pch_uart_init_port(pdev, id);
1855         if (!priv) {
1856                 ret = -EBUSY;
1857                 goto probe_disable_device;
1858         }
1859         pci_set_drvdata(pdev, priv);
1860
1861         return ret;
1862
1863 probe_disable_device:
1864         pci_disable_msi(pdev);
1865         pci_disable_device(pdev);
1866 probe_error:
1867         return ret;
1868 }
1869
1870 static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops,
1871                          pch_uart_pci_suspend,
1872                          pch_uart_pci_resume);
1873
1874 static struct pci_driver pch_uart_pci_driver = {
1875         .name = "pch_uart",
1876         .id_table = pch_uart_pci_id,
1877         .probe = pch_uart_pci_probe,
1878         .remove = pch_uart_pci_remove,
1879         .driver.pm = &pch_uart_pci_pm_ops,
1880 };
1881
1882 static int __init pch_uart_module_init(void)
1883 {
1884         int ret;
1885
1886         /* register as UART driver */
1887         ret = uart_register_driver(&pch_uart_driver);
1888         if (ret < 0)
1889                 return ret;
1890
1891         /* register as PCI driver */
1892         ret = pci_register_driver(&pch_uart_pci_driver);
1893         if (ret < 0)
1894                 uart_unregister_driver(&pch_uart_driver);
1895
1896         return ret;
1897 }
1898 module_init(pch_uart_module_init);
1899
1900 static void __exit pch_uart_module_exit(void)
1901 {
1902         pci_unregister_driver(&pch_uart_pci_driver);
1903         uart_unregister_driver(&pch_uart_driver);
1904 }
1905 module_exit(pch_uart_module_exit);
1906
1907 MODULE_LICENSE("GPL v2");
1908 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1909 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1910
1911 module_param(default_baud, uint, S_IRUGO);
1912 MODULE_PARM_DESC(default_baud,
1913                  "Default BAUD for initial driver state and console (default 9600)");
1914 module_param(user_uartclk, uint, S_IRUGO);
1915 MODULE_PARM_DESC(user_uartclk,
1916                  "Override UART default or board specific UART clock");