2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #include <linux/kernel.h>
21 #include <linux/serial_reg.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/console.h>
26 #include <linux/serial_core.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/interrupt.h>
31 #include <linux/dmi.h>
32 #include <linux/nmi.h>
33 #include <linux/delay.h>
36 #include <linux/debugfs.h>
37 #include <linux/dmaengine.h>
38 #include <linux/pch_dma.h>
41 PCH_UART_HANDLED_RX_INT_SHIFT,
42 PCH_UART_HANDLED_TX_INT_SHIFT,
43 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
44 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
45 PCH_UART_HANDLED_MS_INT_SHIFT,
46 PCH_UART_HANDLED_LS_INT_SHIFT,
49 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
51 /* Set the max number of UART port
52 * Intel EG20T PCH: 4 port
53 * LAPIS Semiconductor ML7213 IOH: 3 port
54 * LAPIS Semiconductor ML7223 IOH: 2 port
58 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
59 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
60 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
61 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
62 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
63 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
64 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
66 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
68 #define PCH_UART_RBR 0x00
69 #define PCH_UART_THR 0x00
71 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
72 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
73 #define PCH_UART_IER_ERBFI 0x00000001
74 #define PCH_UART_IER_ETBEI 0x00000002
75 #define PCH_UART_IER_ELSI 0x00000004
76 #define PCH_UART_IER_EDSSI 0x00000008
78 #define PCH_UART_IIR_IP 0x00000001
79 #define PCH_UART_IIR_IID 0x00000006
80 #define PCH_UART_IIR_MSI 0x00000000
81 #define PCH_UART_IIR_TRI 0x00000002
82 #define PCH_UART_IIR_RRI 0x00000004
83 #define PCH_UART_IIR_REI 0x00000006
84 #define PCH_UART_IIR_TOI 0x00000008
85 #define PCH_UART_IIR_FIFO256 0x00000020
86 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
87 #define PCH_UART_IIR_FE 0x000000C0
89 #define PCH_UART_FCR_FIFOE 0x00000001
90 #define PCH_UART_FCR_RFR 0x00000002
91 #define PCH_UART_FCR_TFR 0x00000004
92 #define PCH_UART_FCR_DMS 0x00000008
93 #define PCH_UART_FCR_FIFO256 0x00000020
94 #define PCH_UART_FCR_RFTL 0x000000C0
96 #define PCH_UART_FCR_RFTL1 0x00000000
97 #define PCH_UART_FCR_RFTL64 0x00000040
98 #define PCH_UART_FCR_RFTL128 0x00000080
99 #define PCH_UART_FCR_RFTL224 0x000000C0
100 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
101 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
102 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
103 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
104 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
105 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
106 #define PCH_UART_FCR_RFTL_SHIFT 6
108 #define PCH_UART_LCR_WLS 0x00000003
109 #define PCH_UART_LCR_STB 0x00000004
110 #define PCH_UART_LCR_PEN 0x00000008
111 #define PCH_UART_LCR_EPS 0x00000010
112 #define PCH_UART_LCR_SP 0x00000020
113 #define PCH_UART_LCR_SB 0x00000040
114 #define PCH_UART_LCR_DLAB 0x00000080
115 #define PCH_UART_LCR_NP 0x00000000
116 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
117 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
118 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
119 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
122 #define PCH_UART_LCR_5BIT 0x00000000
123 #define PCH_UART_LCR_6BIT 0x00000001
124 #define PCH_UART_LCR_7BIT 0x00000002
125 #define PCH_UART_LCR_8BIT 0x00000003
127 #define PCH_UART_MCR_DTR 0x00000001
128 #define PCH_UART_MCR_RTS 0x00000002
129 #define PCH_UART_MCR_OUT 0x0000000C
130 #define PCH_UART_MCR_LOOP 0x00000010
131 #define PCH_UART_MCR_AFE 0x00000020
133 #define PCH_UART_LSR_DR 0x00000001
134 #define PCH_UART_LSR_ERR (1<<7)
136 #define PCH_UART_MSR_DCTS 0x00000001
137 #define PCH_UART_MSR_DDSR 0x00000002
138 #define PCH_UART_MSR_TERI 0x00000004
139 #define PCH_UART_MSR_DDCD 0x00000008
140 #define PCH_UART_MSR_CTS 0x00000010
141 #define PCH_UART_MSR_DSR 0x00000020
142 #define PCH_UART_MSR_RI 0x00000040
143 #define PCH_UART_MSR_DCD 0x00000080
144 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
145 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
147 #define PCH_UART_DLL 0x00
148 #define PCH_UART_DLM 0x01
150 #define PCH_UART_BRCSR 0x0E
152 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
153 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
154 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
155 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
156 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
158 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
159 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
160 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
161 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
162 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
163 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
164 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
165 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
166 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
167 #define PCH_UART_HAL_STB1 0
168 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
170 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
171 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
172 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
173 PCH_UART_HAL_CLR_RX_FIFO)
175 #define PCH_UART_HAL_DMA_MODE0 0
176 #define PCH_UART_HAL_FIFO_DIS 0
177 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
178 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
179 PCH_UART_FCR_FIFO256)
180 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
181 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
182 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
183 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
184 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
185 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
186 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
187 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
188 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
189 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
190 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
191 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
192 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
193 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
195 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
196 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
197 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
198 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
199 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
201 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
202 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
203 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
204 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
205 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
207 #define PCI_VENDOR_ID_ROHM 0x10DB
209 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
211 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
212 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
213 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
214 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
215 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
216 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
218 struct pch_uart_buffer {
224 struct uart_port port;
226 void __iomem *membase;
227 resource_size_t mapbase;
229 struct pci_dev *pdev;
231 unsigned int uartclk;
237 struct pch_uart_buffer rxbuf;
241 unsigned int use_dma;
242 struct dma_async_tx_descriptor *desc_tx;
243 struct dma_async_tx_descriptor *desc_rx;
244 struct pch_dma_slave param_tx;
245 struct pch_dma_slave param_rx;
246 struct dma_chan *chan_tx;
247 struct dma_chan *chan_rx;
248 struct scatterlist *sg_tx_p;
251 struct scatterlist sg_rx;
254 dma_addr_t rx_buf_dma;
256 struct dentry *debugfs;
257 #define IRQ_NAME_SIZE 17
258 char irq_name[IRQ_NAME_SIZE];
260 /* protect the eg20t_port private structure and io access to membase */
265 * struct pch_uart_driver_data - private data structure for UART-DMA
266 * @port_type: The type of UART port
267 * @line_no: UART port line number (0, 1, 2...)
269 struct pch_uart_driver_data {
274 enum pch_uart_num_t {
288 static struct pch_uart_driver_data drv_dat[] = {
289 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
290 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
291 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
292 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
293 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
294 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
295 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
296 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
297 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
298 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
299 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
302 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
303 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
305 static unsigned int default_baud = 9600;
306 static unsigned int user_uartclk = 0;
307 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
308 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
309 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
310 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
312 #ifdef CONFIG_DEBUG_FS
314 #define PCH_REGS_BUFSIZE 1024
317 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
318 size_t count, loff_t *ppos)
320 struct eg20t_port *priv = file->private_data;
326 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
330 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
331 "PCH EG20T port[%d] regs:\n", priv->port.line);
333 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
334 "=================================\n");
335 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
336 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
337 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
338 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
339 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
340 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
341 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
342 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
343 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
344 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
345 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
346 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
347 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
349 ioread8(priv->membase + PCH_UART_BRCSR));
351 lcr = ioread8(priv->membase + UART_LCR);
352 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
353 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
354 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
355 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
356 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
357 iowrite8(lcr, priv->membase + UART_LCR);
359 if (len > PCH_REGS_BUFSIZE)
360 len = PCH_REGS_BUFSIZE;
362 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
367 static const struct file_operations port_regs_ops = {
368 .owner = THIS_MODULE,
370 .read = port_show_regs,
371 .llseek = default_llseek,
373 #endif /* CONFIG_DEBUG_FS */
375 static const struct dmi_system_id pch_uart_dmi_table[] = {
379 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
381 (void *)CMITC_UARTCLK,
386 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
388 (void *)FRI2_64_UARTCLK,
391 .ident = "Fish River Island II",
393 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
395 (void *)FRI2_48_UARTCLK,
400 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
402 (void *)NTC1_UARTCLK,
405 .ident = "nanoETXexpress-TT",
407 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
409 (void *)NTC1_UARTCLK,
412 .ident = "MinnowBoard",
414 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
416 (void *)MINNOW_UARTCLK,
421 /* Return UART clock, checking for board specific clocks. */
422 static unsigned int pch_uart_get_uartclk(void)
424 const struct dmi_system_id *d;
429 d = dmi_first_match(pch_uart_dmi_table);
431 return (unsigned long)d->driver_data;
433 return DEFAULT_UARTCLK;
436 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
439 u8 ier = ioread8(priv->membase + UART_IER);
440 ier |= flag & PCH_UART_IER_MASK;
441 iowrite8(ier, priv->membase + UART_IER);
444 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
447 u8 ier = ioread8(priv->membase + UART_IER);
448 ier &= ~(flag & PCH_UART_IER_MASK);
449 iowrite8(ier, priv->membase + UART_IER);
452 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
453 unsigned int parity, unsigned int bits,
456 unsigned int dll, dlm, lcr;
459 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
460 if (div < 0 || USHRT_MAX <= div) {
461 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
465 dll = (unsigned int)div & 0x00FFU;
466 dlm = ((unsigned int)div >> 8) & 0x00FFU;
468 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
469 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
473 if (bits & ~PCH_UART_LCR_WLS) {
474 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
478 if (stb & ~PCH_UART_LCR_STB) {
479 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
487 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
488 __func__, baud, div, lcr, jiffies);
489 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
490 iowrite8(dll, priv->membase + PCH_UART_DLL);
491 iowrite8(dlm, priv->membase + PCH_UART_DLM);
492 iowrite8(lcr, priv->membase + UART_LCR);
497 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
500 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
501 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
506 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
507 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
508 priv->membase + UART_FCR);
509 iowrite8(priv->fcr, priv->membase + UART_FCR);
514 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
515 unsigned int dmamode,
516 unsigned int fifo_size, unsigned int trigger)
520 if (dmamode & ~PCH_UART_FCR_DMS) {
521 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
526 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
527 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
528 __func__, fifo_size);
532 if (trigger & ~PCH_UART_FCR_RFTL) {
533 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
538 switch (priv->fifo_size) {
540 priv->trigger_level =
541 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
544 priv->trigger_level =
545 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
548 priv->trigger_level =
549 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
552 priv->trigger_level =
553 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
557 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
558 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
559 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
560 priv->membase + UART_FCR);
561 iowrite8(fcr, priv->membase + UART_FCR);
567 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
569 unsigned int msr = ioread8(priv->membase + UART_MSR);
570 priv->dmsr = msr & PCH_UART_MSR_DELTA;
574 static void pch_uart_hal_write(struct eg20t_port *priv,
575 const unsigned char *buf, int tx_size)
580 for (i = 0; i < tx_size;) {
582 iowrite8(thr, priv->membase + PCH_UART_THR);
586 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
591 struct uart_port *port = &priv->port;
593 lsr = ioread8(priv->membase + UART_LSR);
594 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
595 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
596 lsr = ioread8(priv->membase + UART_LSR)) {
597 rbr = ioread8(priv->membase + PCH_UART_RBR);
599 if (lsr & UART_LSR_BI) {
601 if (uart_handle_break(port))
606 if (uart_handle_sysrq_char(port, rbr))
616 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
618 return ioread8(priv->membase + UART_IIR) &\
619 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
622 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
624 return ioread8(priv->membase + UART_LSR);
627 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
631 lcr = ioread8(priv->membase + UART_LCR);
633 lcr |= PCH_UART_LCR_SB;
635 lcr &= ~PCH_UART_LCR_SB;
637 iowrite8(lcr, priv->membase + UART_LCR);
640 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
643 struct uart_port *port = &priv->port;
644 struct tty_port *tport = &port->state->port;
646 tty_insert_flip_string(tport, buf, size);
647 tty_flip_buffer_push(tport);
652 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
655 struct uart_port *port = &priv->port;
658 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
659 __func__, port->x_char, jiffies);
660 buf[0] = port->x_char;
668 static int dma_push_rx(struct eg20t_port *priv, int size)
671 struct uart_port *port = &priv->port;
672 struct tty_port *tport = &port->state->port;
674 room = tty_buffer_request_room(tport, size);
677 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
682 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
684 port->icount.rx += room;
689 static void pch_free_dma(struct uart_port *port)
691 struct eg20t_port *priv;
692 priv = container_of(port, struct eg20t_port, port);
695 dma_release_channel(priv->chan_tx);
696 priv->chan_tx = NULL;
699 dma_release_channel(priv->chan_rx);
700 priv->chan_rx = NULL;
703 if (priv->rx_buf_dma) {
704 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
706 priv->rx_buf_virt = NULL;
707 priv->rx_buf_dma = 0;
713 static bool filter(struct dma_chan *chan, void *slave)
715 struct pch_dma_slave *param = slave;
717 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
718 chan->device->dev)) {
719 chan->private = param;
726 static void pch_request_dma(struct uart_port *port)
729 struct dma_chan *chan;
730 struct pci_dev *dma_dev;
731 struct pch_dma_slave *param;
732 struct eg20t_port *priv =
733 container_of(port, struct eg20t_port, port);
735 dma_cap_set(DMA_SLAVE, mask);
737 /* Get DMA's dev information */
738 dma_dev = pci_get_slot(priv->pdev->bus,
739 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
742 param = &priv->param_tx;
743 param->dma_dev = &dma_dev->dev;
744 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
746 param->tx_reg = port->mapbase + UART_TX;
747 chan = dma_request_channel(mask, filter, param);
749 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
751 pci_dev_put(dma_dev);
754 priv->chan_tx = chan;
757 param = &priv->param_rx;
758 param->dma_dev = &dma_dev->dev;
759 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
761 param->rx_reg = port->mapbase + UART_RX;
762 chan = dma_request_channel(mask, filter, param);
764 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
766 dma_release_channel(priv->chan_tx);
767 priv->chan_tx = NULL;
768 pci_dev_put(dma_dev);
772 /* Get Consistent memory for DMA */
773 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
774 &priv->rx_buf_dma, GFP_KERNEL);
775 priv->chan_rx = chan;
777 pci_dev_put(dma_dev);
780 static void pch_dma_rx_complete(void *arg)
782 struct eg20t_port *priv = arg;
783 struct uart_port *port = &priv->port;
786 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
787 count = dma_push_rx(priv, priv->trigger_level);
789 tty_flip_buffer_push(&port->state->port);
790 async_tx_ack(priv->desc_rx);
791 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
792 PCH_UART_HAL_RX_ERR_INT);
795 static void pch_dma_tx_complete(void *arg)
797 struct eg20t_port *priv = arg;
798 struct uart_port *port = &priv->port;
799 struct circ_buf *xmit = &port->state->xmit;
800 struct scatterlist *sg = priv->sg_tx_p;
803 for (i = 0; i < priv->nent; i++, sg++) {
804 xmit->tail += sg_dma_len(sg);
805 port->icount.tx += sg_dma_len(sg);
807 xmit->tail &= UART_XMIT_SIZE - 1;
808 async_tx_ack(priv->desc_tx);
809 dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE);
810 priv->tx_dma_use = 0;
813 kfree(priv->sg_tx_p);
814 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
817 static int pop_tx(struct eg20t_port *priv, int size)
820 struct uart_port *port = &priv->port;
821 struct circ_buf *xmit = &port->state->xmit;
823 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
828 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
829 int sz = min(size - count, cnt_to_end);
830 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
831 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
833 } while (!uart_circ_empty(xmit) && count < size);
836 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
837 count, size - count, jiffies);
842 static int handle_rx_to(struct eg20t_port *priv)
844 struct pch_uart_buffer *buf;
847 if (!priv->start_rx) {
848 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
849 PCH_UART_HAL_RX_ERR_INT);
854 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
855 ret = push_rx(priv, buf->buf, rx_size);
858 } while (rx_size == buf->size);
860 return PCH_UART_HANDLED_RX_INT;
863 static int handle_rx(struct eg20t_port *priv)
865 return handle_rx_to(priv);
868 static int dma_handle_rx(struct eg20t_port *priv)
870 struct uart_port *port = &priv->port;
871 struct dma_async_tx_descriptor *desc;
872 struct scatterlist *sg;
874 priv = container_of(port, struct eg20t_port, port);
877 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
879 sg_dma_len(sg) = priv->trigger_level;
881 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
882 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
884 sg_dma_address(sg) = priv->rx_buf_dma;
886 desc = dmaengine_prep_slave_sg(priv->chan_rx,
887 sg, 1, DMA_DEV_TO_MEM,
888 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
893 priv->desc_rx = desc;
894 desc->callback = pch_dma_rx_complete;
895 desc->callback_param = priv;
896 desc->tx_submit(desc);
897 dma_async_issue_pending(priv->chan_rx);
899 return PCH_UART_HANDLED_RX_INT;
902 static unsigned int handle_tx(struct eg20t_port *priv)
904 struct uart_port *port = &priv->port;
905 struct circ_buf *xmit = &port->state->xmit;
911 if (!priv->start_tx) {
912 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
914 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
919 fifo_size = max(priv->fifo_size, 1);
921 if (pop_tx_x(priv, xmit->buf)) {
922 pch_uart_hal_write(priv, xmit->buf, 1);
927 size = min(xmit->head - xmit->tail, fifo_size);
931 tx_size = pop_tx(priv, size);
933 port->icount.tx += tx_size;
937 priv->tx_empty = tx_empty;
940 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
941 uart_write_wakeup(port);
944 return PCH_UART_HANDLED_TX_INT;
947 static unsigned int dma_handle_tx(struct eg20t_port *priv)
949 struct uart_port *port = &priv->port;
950 struct circ_buf *xmit = &port->state->xmit;
951 struct scatterlist *sg;
955 struct dma_async_tx_descriptor *desc;
962 if (!priv->start_tx) {
963 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
965 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
970 if (priv->tx_dma_use) {
971 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
973 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
978 fifo_size = max(priv->fifo_size, 1);
980 if (pop_tx_x(priv, xmit->buf)) {
981 pch_uart_hal_write(priv, xmit->buf, 1);
987 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
988 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
989 xmit->tail, UART_XMIT_SIZE));
991 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
992 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
993 uart_write_wakeup(port);
997 if (bytes > fifo_size) {
998 num = bytes / fifo_size + 1;
1000 rem = bytes % fifo_size;
1007 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1008 __func__, num, size, rem);
1010 priv->tx_dma_use = 1;
1012 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1013 if (!priv->sg_tx_p) {
1014 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1018 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1021 for (i = 0; i < num; i++, sg++) {
1023 sg_set_page(sg, virt_to_page(xmit->buf),
1024 rem, fifo_size * i);
1026 sg_set_page(sg, virt_to_page(xmit->buf),
1027 size, fifo_size * i);
1031 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1033 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1036 priv->orig_nent = num;
1039 for (i = 0; i < nent; i++, sg++) {
1040 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1042 sg_dma_address(sg) = (sg_dma_address(sg) &
1043 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1044 if (i == (nent - 1))
1045 sg_dma_len(sg) = rem;
1047 sg_dma_len(sg) = size;
1050 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1051 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1052 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1054 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1058 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1059 priv->desc_tx = desc;
1060 desc->callback = pch_dma_tx_complete;
1061 desc->callback_param = priv;
1063 desc->tx_submit(desc);
1065 dma_async_issue_pending(priv->chan_tx);
1067 return PCH_UART_HANDLED_TX_INT;
1070 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1072 struct uart_port *port = &priv->port;
1073 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1074 char *error_msg[5] = {};
1077 if (lsr & PCH_UART_LSR_ERR)
1078 error_msg[i++] = "Error data in FIFO\n";
1080 if (lsr & UART_LSR_FE) {
1081 port->icount.frame++;
1082 error_msg[i++] = " Framing Error\n";
1085 if (lsr & UART_LSR_PE) {
1086 port->icount.parity++;
1087 error_msg[i++] = " Parity Error\n";
1090 if (lsr & UART_LSR_OE) {
1091 port->icount.overrun++;
1092 error_msg[i++] = " Overrun Error\n";
1096 for (i = 0; error_msg[i] != NULL; i++)
1097 dev_err(&priv->pdev->dev, error_msg[i]);
1103 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1105 struct eg20t_port *priv = dev_id;
1106 unsigned int handled;
1110 unsigned long flags;
1114 spin_lock_irqsave(&priv->lock, flags);
1117 iid = pch_uart_hal_get_iid(priv);
1118 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1121 case PCH_UART_IID_RLS: /* Receiver Line Status */
1122 lsr = pch_uart_hal_get_line_status(priv);
1123 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1124 UART_LSR_PE | UART_LSR_OE)) {
1125 pch_uart_err_ir(priv, lsr);
1126 ret = PCH_UART_HANDLED_RX_ERR_INT;
1128 ret = PCH_UART_HANDLED_LS_INT;
1131 case PCH_UART_IID_RDR: /* Received Data Ready */
1132 if (priv->use_dma) {
1133 pch_uart_hal_disable_interrupt(priv,
1134 PCH_UART_HAL_RX_INT |
1135 PCH_UART_HAL_RX_ERR_INT);
1136 ret = dma_handle_rx(priv);
1138 pch_uart_hal_enable_interrupt(priv,
1139 PCH_UART_HAL_RX_INT |
1140 PCH_UART_HAL_RX_ERR_INT);
1142 ret = handle_rx(priv);
1145 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1147 ret = handle_rx_to(priv);
1149 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1152 ret = dma_handle_tx(priv);
1154 ret = handle_tx(priv);
1156 case PCH_UART_IID_MS: /* Modem Status */
1157 msr = pch_uart_hal_get_modem(priv);
1158 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1159 means final interrupt */
1160 if ((msr & UART_MSR_ANY_DELTA) == 0)
1162 ret |= PCH_UART_HANDLED_MS_INT;
1164 default: /* Never junp to this label */
1165 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1171 handled |= (unsigned int)ret;
1174 spin_unlock_irqrestore(&priv->lock, flags);
1175 return IRQ_RETVAL(handled);
1178 /* This function tests whether the transmitter fifo and shifter for the port
1179 described by 'port' is empty. */
1180 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1182 struct eg20t_port *priv;
1184 priv = container_of(port, struct eg20t_port, port);
1186 return TIOCSER_TEMT;
1191 /* Returns the current state of modem control inputs. */
1192 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1194 struct eg20t_port *priv;
1196 unsigned int ret = 0;
1198 priv = container_of(port, struct eg20t_port, port);
1199 modem = pch_uart_hal_get_modem(priv);
1201 if (modem & UART_MSR_DCD)
1204 if (modem & UART_MSR_RI)
1207 if (modem & UART_MSR_DSR)
1210 if (modem & UART_MSR_CTS)
1216 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1219 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1221 if (mctrl & TIOCM_DTR)
1222 mcr |= UART_MCR_DTR;
1223 if (mctrl & TIOCM_RTS)
1224 mcr |= UART_MCR_RTS;
1225 if (mctrl & TIOCM_LOOP)
1226 mcr |= UART_MCR_LOOP;
1228 if (priv->mcr & UART_MCR_AFE)
1229 mcr |= UART_MCR_AFE;
1232 iowrite8(mcr, priv->membase + UART_MCR);
1235 static void pch_uart_stop_tx(struct uart_port *port)
1237 struct eg20t_port *priv;
1238 priv = container_of(port, struct eg20t_port, port);
1240 priv->tx_dma_use = 0;
1243 static void pch_uart_start_tx(struct uart_port *port)
1245 struct eg20t_port *priv;
1247 priv = container_of(port, struct eg20t_port, port);
1249 if (priv->use_dma) {
1250 if (priv->tx_dma_use) {
1251 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1258 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1261 static void pch_uart_stop_rx(struct uart_port *port)
1263 struct eg20t_port *priv;
1264 priv = container_of(port, struct eg20t_port, port);
1266 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1267 PCH_UART_HAL_RX_ERR_INT);
1270 /* Enable the modem status interrupts. */
1271 static void pch_uart_enable_ms(struct uart_port *port)
1273 struct eg20t_port *priv;
1274 priv = container_of(port, struct eg20t_port, port);
1275 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1278 /* Control the transmission of a break signal. */
1279 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1281 struct eg20t_port *priv;
1282 unsigned long flags;
1284 priv = container_of(port, struct eg20t_port, port);
1285 spin_lock_irqsave(&priv->lock, flags);
1286 pch_uart_hal_set_break(priv, ctl);
1287 spin_unlock_irqrestore(&priv->lock, flags);
1290 /* Grab any interrupt resources and initialise any low level driver state. */
1291 static int pch_uart_startup(struct uart_port *port)
1293 struct eg20t_port *priv;
1298 priv = container_of(port, struct eg20t_port, port);
1302 priv->uartclk = port->uartclk;
1304 port->uartclk = priv->uartclk;
1306 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1307 ret = pch_uart_hal_set_line(priv, default_baud,
1308 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1313 switch (priv->fifo_size) {
1315 fifo_size = PCH_UART_HAL_FIFO256;
1318 fifo_size = PCH_UART_HAL_FIFO64;
1321 fifo_size = PCH_UART_HAL_FIFO16;
1325 fifo_size = PCH_UART_HAL_FIFO_DIS;
1329 switch (priv->trigger) {
1330 case PCH_UART_HAL_TRIGGER1:
1333 case PCH_UART_HAL_TRIGGER_L:
1334 trigger_level = priv->fifo_size / 4;
1336 case PCH_UART_HAL_TRIGGER_M:
1337 trigger_level = priv->fifo_size / 2;
1339 case PCH_UART_HAL_TRIGGER_H:
1341 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1345 priv->trigger_level = trigger_level;
1346 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1347 fifo_size, priv->trigger);
1351 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1352 priv->irq_name, priv);
1357 pch_request_dma(port);
1360 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1361 PCH_UART_HAL_RX_ERR_INT);
1362 uart_update_timeout(port, CS8, default_baud);
1367 static void pch_uart_shutdown(struct uart_port *port)
1369 struct eg20t_port *priv;
1372 priv = container_of(port, struct eg20t_port, port);
1373 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1374 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1375 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1376 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1378 dev_err(priv->port.dev,
1379 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1383 free_irq(priv->port.irq, priv);
1386 /* Change the port parameters, including word length, parity, stop
1387 *bits. Update read_status_mask and ignore_status_mask to indicate
1388 *the types of events we are interested in receiving. */
1389 static void pch_uart_set_termios(struct uart_port *port,
1390 struct ktermios *termios, struct ktermios *old)
1393 unsigned int baud, parity, bits, stb;
1394 struct eg20t_port *priv;
1395 unsigned long flags;
1397 priv = container_of(port, struct eg20t_port, port);
1398 switch (termios->c_cflag & CSIZE) {
1400 bits = PCH_UART_HAL_5BIT;
1403 bits = PCH_UART_HAL_6BIT;
1406 bits = PCH_UART_HAL_7BIT;
1409 bits = PCH_UART_HAL_8BIT;
1412 if (termios->c_cflag & CSTOPB)
1413 stb = PCH_UART_HAL_STB2;
1415 stb = PCH_UART_HAL_STB1;
1417 if (termios->c_cflag & PARENB) {
1418 if (termios->c_cflag & PARODD)
1419 parity = PCH_UART_HAL_PARITY_ODD;
1421 parity = PCH_UART_HAL_PARITY_EVEN;
1424 parity = PCH_UART_HAL_PARITY_NONE;
1426 /* Only UART0 has auto hardware flow function */
1427 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1428 priv->mcr |= UART_MCR_AFE;
1430 priv->mcr &= ~UART_MCR_AFE;
1432 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1434 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1436 spin_lock_irqsave(&priv->lock, flags);
1437 spin_lock(&port->lock);
1439 uart_update_timeout(port, termios->c_cflag, baud);
1440 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1444 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1445 /* Don't rewrite B0 */
1446 if (tty_termios_baud_rate(termios))
1447 tty_termios_encode_baud_rate(termios, baud, baud);
1450 spin_unlock(&port->lock);
1451 spin_unlock_irqrestore(&priv->lock, flags);
1454 static const char *pch_uart_type(struct uart_port *port)
1456 return KBUILD_MODNAME;
1459 static void pch_uart_release_port(struct uart_port *port)
1461 struct eg20t_port *priv;
1463 priv = container_of(port, struct eg20t_port, port);
1464 pci_iounmap(priv->pdev, priv->membase);
1465 pci_release_regions(priv->pdev);
1468 static int pch_uart_request_port(struct uart_port *port)
1470 struct eg20t_port *priv;
1472 void __iomem *membase;
1474 priv = container_of(port, struct eg20t_port, port);
1475 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1479 membase = pci_iomap(priv->pdev, 1, 0);
1481 pci_release_regions(priv->pdev);
1484 priv->membase = port->membase = membase;
1489 static void pch_uart_config_port(struct uart_port *port, int type)
1491 struct eg20t_port *priv;
1493 priv = container_of(port, struct eg20t_port, port);
1494 if (type & UART_CONFIG_TYPE) {
1495 port->type = priv->port_type;
1496 pch_uart_request_port(port);
1500 static int pch_uart_verify_port(struct uart_port *port,
1501 struct serial_struct *serinfo)
1503 struct eg20t_port *priv;
1505 priv = container_of(port, struct eg20t_port, port);
1506 if (serinfo->flags & UPF_LOW_LATENCY) {
1507 dev_info(priv->port.dev,
1508 "PCH UART : Use PIO Mode (without DMA)\n");
1510 serinfo->flags &= ~UPF_LOW_LATENCY;
1512 #ifndef CONFIG_PCH_DMA
1513 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1517 if (!priv->use_dma) {
1518 pch_request_dma(port);
1522 dev_info(priv->port.dev, "PCH UART: %s\n",
1524 "Use DMA Mode" : "No DMA");
1530 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1532 * Wait for transmitter & holding register to empty
1534 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1536 unsigned int status, tmout = 10000;
1538 /* Wait up to 10ms for the character(s) to be sent. */
1540 status = ioread8(up->membase + UART_LSR);
1542 if ((status & bits) == bits)
1549 /* Wait up to 1s for flow control if necessary */
1550 if (up->port.flags & UPF_CONS_FLOW) {
1552 for (tmout = 1000000; tmout; tmout--) {
1553 unsigned int msr = ioread8(up->membase + UART_MSR);
1554 if (msr & UART_MSR_CTS)
1557 touch_nmi_watchdog();
1561 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1563 #ifdef CONFIG_CONSOLE_POLL
1565 * Console polling routines for communicate via uart while
1566 * in an interrupt or debug context.
1568 static int pch_uart_get_poll_char(struct uart_port *port)
1570 struct eg20t_port *priv =
1571 container_of(port, struct eg20t_port, port);
1572 u8 lsr = ioread8(priv->membase + UART_LSR);
1574 if (!(lsr & UART_LSR_DR))
1575 return NO_POLL_CHAR;
1577 return ioread8(priv->membase + PCH_UART_RBR);
1581 static void pch_uart_put_poll_char(struct uart_port *port,
1585 struct eg20t_port *priv =
1586 container_of(port, struct eg20t_port, port);
1589 * First save the IER then disable the interrupts
1591 ier = ioread8(priv->membase + UART_IER);
1592 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1594 wait_for_xmitr(priv, UART_LSR_THRE);
1596 * Send the character out.
1598 iowrite8(c, priv->membase + PCH_UART_THR);
1601 * Finally, wait for transmitter to become empty
1602 * and restore the IER
1604 wait_for_xmitr(priv, BOTH_EMPTY);
1605 iowrite8(ier, priv->membase + UART_IER);
1607 #endif /* CONFIG_CONSOLE_POLL */
1609 static const struct uart_ops pch_uart_ops = {
1610 .tx_empty = pch_uart_tx_empty,
1611 .set_mctrl = pch_uart_set_mctrl,
1612 .get_mctrl = pch_uart_get_mctrl,
1613 .stop_tx = pch_uart_stop_tx,
1614 .start_tx = pch_uart_start_tx,
1615 .stop_rx = pch_uart_stop_rx,
1616 .enable_ms = pch_uart_enable_ms,
1617 .break_ctl = pch_uart_break_ctl,
1618 .startup = pch_uart_startup,
1619 .shutdown = pch_uart_shutdown,
1620 .set_termios = pch_uart_set_termios,
1621 /* .pm = pch_uart_pm, Not supported yet */
1622 .type = pch_uart_type,
1623 .release_port = pch_uart_release_port,
1624 .request_port = pch_uart_request_port,
1625 .config_port = pch_uart_config_port,
1626 .verify_port = pch_uart_verify_port,
1627 #ifdef CONFIG_CONSOLE_POLL
1628 .poll_get_char = pch_uart_get_poll_char,
1629 .poll_put_char = pch_uart_put_poll_char,
1633 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1635 static void pch_console_putchar(struct uart_port *port, int ch)
1637 struct eg20t_port *priv =
1638 container_of(port, struct eg20t_port, port);
1640 wait_for_xmitr(priv, UART_LSR_THRE);
1641 iowrite8(ch, priv->membase + PCH_UART_THR);
1645 * Print a string to the serial port trying not to disturb
1646 * any possible real use of the port...
1648 * The console_lock must be held when we get here.
1651 pch_console_write(struct console *co, const char *s, unsigned int count)
1653 struct eg20t_port *priv;
1654 unsigned long flags;
1655 int priv_locked = 1;
1656 int port_locked = 1;
1659 priv = pch_uart_ports[co->index];
1661 touch_nmi_watchdog();
1663 local_irq_save(flags);
1664 if (priv->port.sysrq) {
1665 /* call to uart_handle_sysrq_char already took the priv lock */
1667 /* serial8250_handle_port() already took the port lock */
1669 } else if (oops_in_progress) {
1670 priv_locked = spin_trylock(&priv->lock);
1671 port_locked = spin_trylock(&priv->port.lock);
1673 spin_lock(&priv->lock);
1674 spin_lock(&priv->port.lock);
1678 * First save the IER then disable the interrupts
1680 ier = ioread8(priv->membase + UART_IER);
1682 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1684 uart_console_write(&priv->port, s, count, pch_console_putchar);
1687 * Finally, wait for transmitter to become empty
1688 * and restore the IER
1690 wait_for_xmitr(priv, BOTH_EMPTY);
1691 iowrite8(ier, priv->membase + UART_IER);
1694 spin_unlock(&priv->port.lock);
1696 spin_unlock(&priv->lock);
1697 local_irq_restore(flags);
1700 static int __init pch_console_setup(struct console *co, char *options)
1702 struct uart_port *port;
1703 int baud = default_baud;
1709 * Check whether an invalid uart number has been specified, and
1710 * if so, search for the first available port that does have
1713 if (co->index >= PCH_UART_NR)
1715 port = &pch_uart_ports[co->index]->port;
1717 if (!port || (!port->iobase && !port->membase))
1720 port->uartclk = pch_uart_get_uartclk();
1723 uart_parse_options(options, &baud, &parity, &bits, &flow);
1725 return uart_set_options(port, co, baud, parity, bits, flow);
1728 static struct uart_driver pch_uart_driver;
1730 static struct console pch_console = {
1731 .name = PCH_UART_DRIVER_DEVICE,
1732 .write = pch_console_write,
1733 .device = uart_console_device,
1734 .setup = pch_console_setup,
1735 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1737 .data = &pch_uart_driver,
1740 #define PCH_CONSOLE (&pch_console)
1742 #define PCH_CONSOLE NULL
1743 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1745 static struct uart_driver pch_uart_driver = {
1746 .owner = THIS_MODULE,
1747 .driver_name = KBUILD_MODNAME,
1748 .dev_name = PCH_UART_DRIVER_DEVICE,
1752 .cons = PCH_CONSOLE,
1755 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1756 const struct pci_device_id *id)
1758 struct eg20t_port *priv;
1760 unsigned int iobase;
1761 unsigned int mapbase;
1762 unsigned char *rxbuf;
1765 struct pch_uart_driver_data *board;
1766 #ifdef CONFIG_DEBUG_FS
1767 char name[32]; /* for debugfs file name */
1770 board = &drv_dat[id->driver_data];
1771 port_type = board->port_type;
1773 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1775 goto init_port_alloc_err;
1777 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1779 goto init_port_free_txbuf;
1781 switch (port_type) {
1782 case PORT_PCH_8LINE:
1783 fifosize = 256; /* EG20T/ML7213: UART0 */
1785 case PORT_PCH_2LINE:
1786 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1789 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1790 goto init_port_hal_free;
1793 pci_enable_msi(pdev);
1794 pci_set_master(pdev);
1796 spin_lock_init(&priv->lock);
1798 iobase = pci_resource_start(pdev, 0);
1799 mapbase = pci_resource_start(pdev, 1);
1800 priv->mapbase = mapbase;
1801 priv->iobase = iobase;
1804 priv->rxbuf.buf = rxbuf;
1805 priv->rxbuf.size = PAGE_SIZE;
1807 priv->fifo_size = fifosize;
1808 priv->uartclk = pch_uart_get_uartclk();
1809 priv->port_type = port_type;
1810 priv->port.dev = &pdev->dev;
1811 priv->port.iobase = iobase;
1812 priv->port.membase = NULL;
1813 priv->port.mapbase = mapbase;
1814 priv->port.irq = pdev->irq;
1815 priv->port.iotype = UPIO_PORT;
1816 priv->port.ops = &pch_uart_ops;
1817 priv->port.flags = UPF_BOOT_AUTOCONF;
1818 priv->port.fifosize = fifosize;
1819 priv->port.line = board->line_no;
1820 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1822 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1823 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1826 spin_lock_init(&priv->port.lock);
1828 pci_set_drvdata(pdev, priv);
1829 priv->trigger_level = 1;
1832 if (pdev->dev.of_node)
1833 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1836 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1837 pch_uart_ports[board->line_no] = priv;
1839 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1841 goto init_port_hal_free;
1843 #ifdef CONFIG_DEBUG_FS
1844 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1845 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1846 NULL, priv, &port_regs_ops);
1852 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1853 pch_uart_ports[board->line_no] = NULL;
1855 free_page((unsigned long)rxbuf);
1856 init_port_free_txbuf:
1858 init_port_alloc_err:
1863 static void pch_uart_exit_port(struct eg20t_port *priv)
1866 #ifdef CONFIG_DEBUG_FS
1867 debugfs_remove(priv->debugfs);
1869 uart_remove_one_port(&pch_uart_driver, &priv->port);
1870 free_page((unsigned long)priv->rxbuf.buf);
1873 static void pch_uart_pci_remove(struct pci_dev *pdev)
1875 struct eg20t_port *priv = pci_get_drvdata(pdev);
1877 pci_disable_msi(pdev);
1879 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1880 pch_uart_ports[priv->port.line] = NULL;
1882 pch_uart_exit_port(priv);
1883 pci_disable_device(pdev);
1888 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1890 struct eg20t_port *priv = pci_get_drvdata(pdev);
1892 uart_suspend_port(&pch_uart_driver, &priv->port);
1894 pci_save_state(pdev);
1895 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1899 static int pch_uart_pci_resume(struct pci_dev *pdev)
1901 struct eg20t_port *priv = pci_get_drvdata(pdev);
1904 pci_set_power_state(pdev, PCI_D0);
1905 pci_restore_state(pdev);
1907 ret = pci_enable_device(pdev);
1910 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1914 uart_resume_port(&pch_uart_driver, &priv->port);
1919 #define pch_uart_pci_suspend NULL
1920 #define pch_uart_pci_resume NULL
1923 static const struct pci_device_id pch_uart_pci_id[] = {
1924 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1925 .driver_data = pch_et20t_uart0},
1926 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1927 .driver_data = pch_et20t_uart1},
1928 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1929 .driver_data = pch_et20t_uart2},
1930 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1931 .driver_data = pch_et20t_uart3},
1932 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1933 .driver_data = pch_ml7213_uart0},
1934 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1935 .driver_data = pch_ml7213_uart1},
1936 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1937 .driver_data = pch_ml7213_uart2},
1938 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1939 .driver_data = pch_ml7223_uart0},
1940 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1941 .driver_data = pch_ml7223_uart1},
1942 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1943 .driver_data = pch_ml7831_uart0},
1944 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1945 .driver_data = pch_ml7831_uart1},
1949 static int pch_uart_pci_probe(struct pci_dev *pdev,
1950 const struct pci_device_id *id)
1953 struct eg20t_port *priv;
1955 ret = pci_enable_device(pdev);
1959 priv = pch_uart_init_port(pdev, id);
1962 goto probe_disable_device;
1964 pci_set_drvdata(pdev, priv);
1968 probe_disable_device:
1969 pci_disable_msi(pdev);
1970 pci_disable_device(pdev);
1975 static struct pci_driver pch_uart_pci_driver = {
1977 .id_table = pch_uart_pci_id,
1978 .probe = pch_uart_pci_probe,
1979 .remove = pch_uart_pci_remove,
1980 .suspend = pch_uart_pci_suspend,
1981 .resume = pch_uart_pci_resume,
1984 static int __init pch_uart_module_init(void)
1988 /* register as UART driver */
1989 ret = uart_register_driver(&pch_uart_driver);
1993 /* register as PCI driver */
1994 ret = pci_register_driver(&pch_uart_pci_driver);
1996 uart_unregister_driver(&pch_uart_driver);
2000 module_init(pch_uart_module_init);
2002 static void __exit pch_uart_module_exit(void)
2004 pci_unregister_driver(&pch_uart_pci_driver);
2005 uart_unregister_driver(&pch_uart_driver);
2007 module_exit(pch_uart_module_exit);
2009 MODULE_LICENSE("GPL v2");
2010 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2011 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2013 module_param(default_baud, uint, S_IRUGO);
2014 MODULE_PARM_DESC(default_baud,
2015 "Default BAUD for initial driver state and console (default 9600)");
2016 module_param(user_uartclk, uint, S_IRUGO);
2017 MODULE_PARM_DESC(user_uartclk,
2018 "Override UART default or board specific UART clock");