2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #include <linux/kernel.h>
21 #include <linux/serial_reg.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/console.h>
26 #include <linux/serial_core.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/interrupt.h>
31 #include <linux/dmi.h>
32 #include <linux/nmi.h>
33 #include <linux/delay.h>
36 #include <linux/debugfs.h>
37 #include <linux/dmaengine.h>
38 #include <linux/pch_dma.h>
41 PCH_UART_HANDLED_RX_INT_SHIFT,
42 PCH_UART_HANDLED_TX_INT_SHIFT,
43 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
44 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
45 PCH_UART_HANDLED_MS_INT_SHIFT,
46 PCH_UART_HANDLED_LS_INT_SHIFT,
54 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
56 /* Set the max number of UART port
57 * Intel EG20T PCH: 4 port
58 * LAPIS Semiconductor ML7213 IOH: 3 port
59 * LAPIS Semiconductor ML7223 IOH: 2 port
63 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
64 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
65 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
66 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
67 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
68 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
69 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
71 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
73 #define PCH_UART_RBR 0x00
74 #define PCH_UART_THR 0x00
76 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
77 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
78 #define PCH_UART_IER_ERBFI 0x00000001
79 #define PCH_UART_IER_ETBEI 0x00000002
80 #define PCH_UART_IER_ELSI 0x00000004
81 #define PCH_UART_IER_EDSSI 0x00000008
83 #define PCH_UART_IIR_IP 0x00000001
84 #define PCH_UART_IIR_IID 0x00000006
85 #define PCH_UART_IIR_MSI 0x00000000
86 #define PCH_UART_IIR_TRI 0x00000002
87 #define PCH_UART_IIR_RRI 0x00000004
88 #define PCH_UART_IIR_REI 0x00000006
89 #define PCH_UART_IIR_TOI 0x00000008
90 #define PCH_UART_IIR_FIFO256 0x00000020
91 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
92 #define PCH_UART_IIR_FE 0x000000C0
94 #define PCH_UART_FCR_FIFOE 0x00000001
95 #define PCH_UART_FCR_RFR 0x00000002
96 #define PCH_UART_FCR_TFR 0x00000004
97 #define PCH_UART_FCR_DMS 0x00000008
98 #define PCH_UART_FCR_FIFO256 0x00000020
99 #define PCH_UART_FCR_RFTL 0x000000C0
101 #define PCH_UART_FCR_RFTL1 0x00000000
102 #define PCH_UART_FCR_RFTL64 0x00000040
103 #define PCH_UART_FCR_RFTL128 0x00000080
104 #define PCH_UART_FCR_RFTL224 0x000000C0
105 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
106 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
107 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
108 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
109 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
110 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
111 #define PCH_UART_FCR_RFTL_SHIFT 6
113 #define PCH_UART_LCR_WLS 0x00000003
114 #define PCH_UART_LCR_STB 0x00000004
115 #define PCH_UART_LCR_PEN 0x00000008
116 #define PCH_UART_LCR_EPS 0x00000010
117 #define PCH_UART_LCR_SP 0x00000020
118 #define PCH_UART_LCR_SB 0x00000040
119 #define PCH_UART_LCR_DLAB 0x00000080
120 #define PCH_UART_LCR_NP 0x00000000
121 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
122 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
123 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
124 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
127 #define PCH_UART_LCR_5BIT 0x00000000
128 #define PCH_UART_LCR_6BIT 0x00000001
129 #define PCH_UART_LCR_7BIT 0x00000002
130 #define PCH_UART_LCR_8BIT 0x00000003
132 #define PCH_UART_MCR_DTR 0x00000001
133 #define PCH_UART_MCR_RTS 0x00000002
134 #define PCH_UART_MCR_OUT 0x0000000C
135 #define PCH_UART_MCR_LOOP 0x00000010
136 #define PCH_UART_MCR_AFE 0x00000020
138 #define PCH_UART_LSR_DR 0x00000001
139 #define PCH_UART_LSR_ERR (1<<7)
141 #define PCH_UART_MSR_DCTS 0x00000001
142 #define PCH_UART_MSR_DDSR 0x00000002
143 #define PCH_UART_MSR_TERI 0x00000004
144 #define PCH_UART_MSR_DDCD 0x00000008
145 #define PCH_UART_MSR_CTS 0x00000010
146 #define PCH_UART_MSR_DSR 0x00000020
147 #define PCH_UART_MSR_RI 0x00000040
148 #define PCH_UART_MSR_DCD 0x00000080
149 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
150 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
152 #define PCH_UART_DLL 0x00
153 #define PCH_UART_DLM 0x01
155 #define PCH_UART_BRCSR 0x0E
157 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
158 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
159 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
160 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
161 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
163 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
164 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
165 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
166 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
167 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
168 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
169 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
170 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
171 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
172 #define PCH_UART_HAL_STB1 0
173 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
175 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
176 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
177 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
178 PCH_UART_HAL_CLR_RX_FIFO)
180 #define PCH_UART_HAL_DMA_MODE0 0
181 #define PCH_UART_HAL_FIFO_DIS 0
182 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
183 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
184 PCH_UART_FCR_FIFO256)
185 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
186 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
187 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
188 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
189 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
190 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
191 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
192 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
193 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
194 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
195 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
196 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
197 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
198 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
200 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
201 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
202 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
203 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
204 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
206 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
207 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
208 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
209 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
210 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
212 #define PCI_VENDOR_ID_ROHM 0x10DB
214 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
216 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
217 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
218 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
219 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
220 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
221 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
223 struct pch_uart_buffer {
229 struct uart_port port;
231 void __iomem *membase;
232 resource_size_t mapbase;
234 struct pci_dev *pdev;
236 unsigned int uartclk;
242 struct pch_uart_buffer rxbuf;
246 unsigned int use_dma;
247 struct dma_async_tx_descriptor *desc_tx;
248 struct dma_async_tx_descriptor *desc_rx;
249 struct pch_dma_slave param_tx;
250 struct pch_dma_slave param_rx;
251 struct dma_chan *chan_tx;
252 struct dma_chan *chan_rx;
253 struct scatterlist *sg_tx_p;
256 struct scatterlist sg_rx;
259 dma_addr_t rx_buf_dma;
261 struct dentry *debugfs;
262 #define IRQ_NAME_SIZE 17
263 char irq_name[IRQ_NAME_SIZE];
265 /* protect the eg20t_port private structure and io access to membase */
270 * struct pch_uart_driver_data - private data structure for UART-DMA
271 * @port_type: The number of DMA channel
272 * @line_no: UART port line number (0, 1, 2...)
274 struct pch_uart_driver_data {
279 enum pch_uart_num_t {
293 static struct pch_uart_driver_data drv_dat[] = {
294 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
295 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
296 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
297 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
298 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
299 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
300 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
301 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
302 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
303 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
304 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
307 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
308 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
310 static unsigned int default_baud = 9600;
311 static unsigned int user_uartclk = 0;
312 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
313 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
314 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
315 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
317 #ifdef CONFIG_DEBUG_FS
319 #define PCH_REGS_BUFSIZE 1024
322 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
323 size_t count, loff_t *ppos)
325 struct eg20t_port *priv = file->private_data;
331 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
335 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
336 "PCH EG20T port[%d] regs:\n", priv->port.line);
338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
339 "=================================\n");
340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
341 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
343 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
345 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
346 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
347 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
348 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
349 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
350 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
351 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
352 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
354 ioread8(priv->membase + PCH_UART_BRCSR));
356 lcr = ioread8(priv->membase + UART_LCR);
357 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
358 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
359 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
360 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
361 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
362 iowrite8(lcr, priv->membase + UART_LCR);
364 if (len > PCH_REGS_BUFSIZE)
365 len = PCH_REGS_BUFSIZE;
367 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
372 static const struct file_operations port_regs_ops = {
373 .owner = THIS_MODULE,
375 .read = port_show_regs,
376 .llseek = default_llseek,
378 #endif /* CONFIG_DEBUG_FS */
380 static struct dmi_system_id pch_uart_dmi_table[] = {
384 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
386 (void *)CMITC_UARTCLK,
391 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
393 (void *)FRI2_64_UARTCLK,
396 .ident = "Fish River Island II",
398 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
400 (void *)FRI2_48_UARTCLK,
405 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
407 (void *)NTC1_UARTCLK,
410 .ident = "nanoETXexpress-TT",
412 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
414 (void *)NTC1_UARTCLK,
417 .ident = "MinnowBoard",
419 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
421 (void *)MINNOW_UARTCLK,
426 /* Return UART clock, checking for board specific clocks. */
427 static unsigned int pch_uart_get_uartclk(void)
429 const struct dmi_system_id *d;
434 d = dmi_first_match(pch_uart_dmi_table);
436 return (unsigned long)d->driver_data;
438 return DEFAULT_UARTCLK;
441 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
444 u8 ier = ioread8(priv->membase + UART_IER);
445 ier |= flag & PCH_UART_IER_MASK;
446 iowrite8(ier, priv->membase + UART_IER);
449 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
452 u8 ier = ioread8(priv->membase + UART_IER);
453 ier &= ~(flag & PCH_UART_IER_MASK);
454 iowrite8(ier, priv->membase + UART_IER);
457 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
458 unsigned int parity, unsigned int bits,
461 unsigned int dll, dlm, lcr;
464 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
465 if (div < 0 || USHRT_MAX <= div) {
466 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
470 dll = (unsigned int)div & 0x00FFU;
471 dlm = ((unsigned int)div >> 8) & 0x00FFU;
473 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
474 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
478 if (bits & ~PCH_UART_LCR_WLS) {
479 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
483 if (stb & ~PCH_UART_LCR_STB) {
484 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
492 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
493 __func__, baud, div, lcr, jiffies);
494 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
495 iowrite8(dll, priv->membase + PCH_UART_DLL);
496 iowrite8(dlm, priv->membase + PCH_UART_DLM);
497 iowrite8(lcr, priv->membase + UART_LCR);
502 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
505 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
506 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
511 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
512 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
513 priv->membase + UART_FCR);
514 iowrite8(priv->fcr, priv->membase + UART_FCR);
519 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
520 unsigned int dmamode,
521 unsigned int fifo_size, unsigned int trigger)
525 if (dmamode & ~PCH_UART_FCR_DMS) {
526 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
531 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
532 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
533 __func__, fifo_size);
537 if (trigger & ~PCH_UART_FCR_RFTL) {
538 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
543 switch (priv->fifo_size) {
545 priv->trigger_level =
546 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
549 priv->trigger_level =
550 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
553 priv->trigger_level =
554 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
557 priv->trigger_level =
558 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
562 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
563 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
564 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
565 priv->membase + UART_FCR);
566 iowrite8(fcr, priv->membase + UART_FCR);
572 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
574 unsigned int msr = ioread8(priv->membase + UART_MSR);
575 priv->dmsr = msr & PCH_UART_MSR_DELTA;
579 static void pch_uart_hal_write(struct eg20t_port *priv,
580 const unsigned char *buf, int tx_size)
585 for (i = 0; i < tx_size;) {
587 iowrite8(thr, priv->membase + PCH_UART_THR);
591 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
596 struct uart_port *port = &priv->port;
598 lsr = ioread8(priv->membase + UART_LSR);
599 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
600 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
601 lsr = ioread8(priv->membase + UART_LSR)) {
602 rbr = ioread8(priv->membase + PCH_UART_RBR);
604 if (lsr & UART_LSR_BI) {
606 if (uart_handle_break(port))
611 if (uart_handle_sysrq_char(port, rbr))
621 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
623 return ioread8(priv->membase + UART_IIR) &\
624 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
627 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
629 return ioread8(priv->membase + UART_LSR);
632 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
636 lcr = ioread8(priv->membase + UART_LCR);
638 lcr |= PCH_UART_LCR_SB;
640 lcr &= ~PCH_UART_LCR_SB;
642 iowrite8(lcr, priv->membase + UART_LCR);
645 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
648 struct uart_port *port = &priv->port;
649 struct tty_port *tport = &port->state->port;
651 tty_insert_flip_string(tport, buf, size);
652 tty_flip_buffer_push(tport);
657 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
660 struct uart_port *port = &priv->port;
663 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
664 __func__, port->x_char, jiffies);
665 buf[0] = port->x_char;
673 static int dma_push_rx(struct eg20t_port *priv, int size)
676 struct uart_port *port = &priv->port;
677 struct tty_port *tport = &port->state->port;
679 room = tty_buffer_request_room(tport, size);
682 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
687 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
689 port->icount.rx += room;
694 static void pch_free_dma(struct uart_port *port)
696 struct eg20t_port *priv;
697 priv = container_of(port, struct eg20t_port, port);
700 dma_release_channel(priv->chan_tx);
701 priv->chan_tx = NULL;
704 dma_release_channel(priv->chan_rx);
705 priv->chan_rx = NULL;
708 if (priv->rx_buf_dma) {
709 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
711 priv->rx_buf_virt = NULL;
712 priv->rx_buf_dma = 0;
718 static bool filter(struct dma_chan *chan, void *slave)
720 struct pch_dma_slave *param = slave;
722 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
723 chan->device->dev)) {
724 chan->private = param;
731 static void pch_request_dma(struct uart_port *port)
734 struct dma_chan *chan;
735 struct pci_dev *dma_dev;
736 struct pch_dma_slave *param;
737 struct eg20t_port *priv =
738 container_of(port, struct eg20t_port, port);
740 dma_cap_set(DMA_SLAVE, mask);
742 /* Get DMA's dev information */
743 dma_dev = pci_get_slot(priv->pdev->bus,
744 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
747 param = &priv->param_tx;
748 param->dma_dev = &dma_dev->dev;
749 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
751 param->tx_reg = port->mapbase + UART_TX;
752 chan = dma_request_channel(mask, filter, param);
754 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
758 priv->chan_tx = chan;
761 param = &priv->param_rx;
762 param->dma_dev = &dma_dev->dev;
763 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
765 param->rx_reg = port->mapbase + UART_RX;
766 chan = dma_request_channel(mask, filter, param);
768 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
770 dma_release_channel(priv->chan_tx);
771 priv->chan_tx = NULL;
775 /* Get Consistent memory for DMA */
776 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
777 &priv->rx_buf_dma, GFP_KERNEL);
778 priv->chan_rx = chan;
781 static void pch_dma_rx_complete(void *arg)
783 struct eg20t_port *priv = arg;
784 struct uart_port *port = &priv->port;
787 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
788 count = dma_push_rx(priv, priv->trigger_level);
790 tty_flip_buffer_push(&port->state->port);
791 async_tx_ack(priv->desc_rx);
792 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
793 PCH_UART_HAL_RX_ERR_INT);
796 static void pch_dma_tx_complete(void *arg)
798 struct eg20t_port *priv = arg;
799 struct uart_port *port = &priv->port;
800 struct circ_buf *xmit = &port->state->xmit;
801 struct scatterlist *sg = priv->sg_tx_p;
804 for (i = 0; i < priv->nent; i++, sg++) {
805 xmit->tail += sg_dma_len(sg);
806 port->icount.tx += sg_dma_len(sg);
808 xmit->tail &= UART_XMIT_SIZE - 1;
809 async_tx_ack(priv->desc_tx);
810 dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
811 priv->tx_dma_use = 0;
814 kfree(priv->sg_tx_p);
815 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
818 static int pop_tx(struct eg20t_port *priv, int size)
821 struct uart_port *port = &priv->port;
822 struct circ_buf *xmit = &port->state->xmit;
824 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
829 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
830 int sz = min(size - count, cnt_to_end);
831 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
832 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
834 } while (!uart_circ_empty(xmit) && count < size);
837 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
838 count, size - count, jiffies);
843 static int handle_rx_to(struct eg20t_port *priv)
845 struct pch_uart_buffer *buf;
848 if (!priv->start_rx) {
849 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
850 PCH_UART_HAL_RX_ERR_INT);
855 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
856 ret = push_rx(priv, buf->buf, rx_size);
859 } while (rx_size == buf->size);
861 return PCH_UART_HANDLED_RX_INT;
864 static int handle_rx(struct eg20t_port *priv)
866 return handle_rx_to(priv);
869 static int dma_handle_rx(struct eg20t_port *priv)
871 struct uart_port *port = &priv->port;
872 struct dma_async_tx_descriptor *desc;
873 struct scatterlist *sg;
875 priv = container_of(port, struct eg20t_port, port);
878 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
880 sg_dma_len(sg) = priv->trigger_level;
882 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
883 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
886 sg_dma_address(sg) = priv->rx_buf_dma;
888 desc = dmaengine_prep_slave_sg(priv->chan_rx,
889 sg, 1, DMA_DEV_TO_MEM,
890 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
895 priv->desc_rx = desc;
896 desc->callback = pch_dma_rx_complete;
897 desc->callback_param = priv;
898 desc->tx_submit(desc);
899 dma_async_issue_pending(priv->chan_rx);
901 return PCH_UART_HANDLED_RX_INT;
904 static unsigned int handle_tx(struct eg20t_port *priv)
906 struct uart_port *port = &priv->port;
907 struct circ_buf *xmit = &port->state->xmit;
913 if (!priv->start_tx) {
914 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
916 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
921 fifo_size = max(priv->fifo_size, 1);
923 if (pop_tx_x(priv, xmit->buf)) {
924 pch_uart_hal_write(priv, xmit->buf, 1);
929 size = min(xmit->head - xmit->tail, fifo_size);
933 tx_size = pop_tx(priv, size);
935 port->icount.tx += tx_size;
939 priv->tx_empty = tx_empty;
942 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
943 uart_write_wakeup(port);
946 return PCH_UART_HANDLED_TX_INT;
949 static unsigned int dma_handle_tx(struct eg20t_port *priv)
951 struct uart_port *port = &priv->port;
952 struct circ_buf *xmit = &port->state->xmit;
953 struct scatterlist *sg;
957 struct dma_async_tx_descriptor *desc;
964 if (!priv->start_tx) {
965 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
967 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
972 if (priv->tx_dma_use) {
973 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
975 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
980 fifo_size = max(priv->fifo_size, 1);
982 if (pop_tx_x(priv, xmit->buf)) {
983 pch_uart_hal_write(priv, xmit->buf, 1);
989 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
990 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
991 xmit->tail, UART_XMIT_SIZE));
993 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
994 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
995 uart_write_wakeup(port);
999 if (bytes > fifo_size) {
1000 num = bytes / fifo_size + 1;
1002 rem = bytes % fifo_size;
1009 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1010 __func__, num, size, rem);
1012 priv->tx_dma_use = 1;
1014 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1015 if (!priv->sg_tx_p) {
1016 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1020 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1023 for (i = 0; i < num; i++, sg++) {
1025 sg_set_page(sg, virt_to_page(xmit->buf),
1026 rem, fifo_size * i);
1028 sg_set_page(sg, virt_to_page(xmit->buf),
1029 size, fifo_size * i);
1033 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1035 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1038 priv->orig_nent = num;
1041 for (i = 0; i < nent; i++, sg++) {
1042 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1044 sg_dma_address(sg) = (sg_dma_address(sg) &
1045 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1046 if (i == (nent - 1))
1047 sg_dma_len(sg) = rem;
1049 sg_dma_len(sg) = size;
1052 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1053 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1054 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1056 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1060 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1061 priv->desc_tx = desc;
1062 desc->callback = pch_dma_tx_complete;
1063 desc->callback_param = priv;
1065 desc->tx_submit(desc);
1067 dma_async_issue_pending(priv->chan_tx);
1069 return PCH_UART_HANDLED_TX_INT;
1072 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1074 struct uart_port *port = &priv->port;
1075 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1076 char *error_msg[5] = {};
1079 if (lsr & PCH_UART_LSR_ERR)
1080 error_msg[i++] = "Error data in FIFO\n";
1082 if (lsr & UART_LSR_FE) {
1083 port->icount.frame++;
1084 error_msg[i++] = " Framing Error\n";
1087 if (lsr & UART_LSR_PE) {
1088 port->icount.parity++;
1089 error_msg[i++] = " Parity Error\n";
1092 if (lsr & UART_LSR_OE) {
1093 port->icount.overrun++;
1094 error_msg[i++] = " Overrun Error\n";
1098 for (i = 0; error_msg[i] != NULL; i++)
1099 dev_err(&priv->pdev->dev, error_msg[i]);
1105 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1107 struct eg20t_port *priv = dev_id;
1108 unsigned int handled;
1112 unsigned long flags;
1116 spin_lock_irqsave(&priv->lock, flags);
1119 iid = pch_uart_hal_get_iid(priv);
1120 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1123 case PCH_UART_IID_RLS: /* Receiver Line Status */
1124 lsr = pch_uart_hal_get_line_status(priv);
1125 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1126 UART_LSR_PE | UART_LSR_OE)) {
1127 pch_uart_err_ir(priv, lsr);
1128 ret = PCH_UART_HANDLED_RX_ERR_INT;
1130 ret = PCH_UART_HANDLED_LS_INT;
1133 case PCH_UART_IID_RDR: /* Received Data Ready */
1134 if (priv->use_dma) {
1135 pch_uart_hal_disable_interrupt(priv,
1136 PCH_UART_HAL_RX_INT |
1137 PCH_UART_HAL_RX_ERR_INT);
1138 ret = dma_handle_rx(priv);
1140 pch_uart_hal_enable_interrupt(priv,
1141 PCH_UART_HAL_RX_INT |
1142 PCH_UART_HAL_RX_ERR_INT);
1144 ret = handle_rx(priv);
1147 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1149 ret = handle_rx_to(priv);
1151 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1154 ret = dma_handle_tx(priv);
1156 ret = handle_tx(priv);
1158 case PCH_UART_IID_MS: /* Modem Status */
1159 msr = pch_uart_hal_get_modem(priv);
1160 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1161 means final interrupt */
1162 if ((msr & UART_MSR_ANY_DELTA) == 0)
1164 ret |= PCH_UART_HANDLED_MS_INT;
1166 default: /* Never junp to this label */
1167 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1173 handled |= (unsigned int)ret;
1176 spin_unlock_irqrestore(&priv->lock, flags);
1177 return IRQ_RETVAL(handled);
1180 /* This function tests whether the transmitter fifo and shifter for the port
1181 described by 'port' is empty. */
1182 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1184 struct eg20t_port *priv;
1186 priv = container_of(port, struct eg20t_port, port);
1188 return TIOCSER_TEMT;
1193 /* Returns the current state of modem control inputs. */
1194 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1196 struct eg20t_port *priv;
1198 unsigned int ret = 0;
1200 priv = container_of(port, struct eg20t_port, port);
1201 modem = pch_uart_hal_get_modem(priv);
1203 if (modem & UART_MSR_DCD)
1206 if (modem & UART_MSR_RI)
1209 if (modem & UART_MSR_DSR)
1212 if (modem & UART_MSR_CTS)
1218 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1221 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1223 if (mctrl & TIOCM_DTR)
1224 mcr |= UART_MCR_DTR;
1225 if (mctrl & TIOCM_RTS)
1226 mcr |= UART_MCR_RTS;
1227 if (mctrl & TIOCM_LOOP)
1228 mcr |= UART_MCR_LOOP;
1230 if (priv->mcr & UART_MCR_AFE)
1231 mcr |= UART_MCR_AFE;
1234 iowrite8(mcr, priv->membase + UART_MCR);
1237 static void pch_uart_stop_tx(struct uart_port *port)
1239 struct eg20t_port *priv;
1240 priv = container_of(port, struct eg20t_port, port);
1242 priv->tx_dma_use = 0;
1245 static void pch_uart_start_tx(struct uart_port *port)
1247 struct eg20t_port *priv;
1249 priv = container_of(port, struct eg20t_port, port);
1251 if (priv->use_dma) {
1252 if (priv->tx_dma_use) {
1253 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1260 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1263 static void pch_uart_stop_rx(struct uart_port *port)
1265 struct eg20t_port *priv;
1266 priv = container_of(port, struct eg20t_port, port);
1268 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1269 PCH_UART_HAL_RX_ERR_INT);
1272 /* Enable the modem status interrupts. */
1273 static void pch_uart_enable_ms(struct uart_port *port)
1275 struct eg20t_port *priv;
1276 priv = container_of(port, struct eg20t_port, port);
1277 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1280 /* Control the transmission of a break signal. */
1281 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1283 struct eg20t_port *priv;
1284 unsigned long flags;
1286 priv = container_of(port, struct eg20t_port, port);
1287 spin_lock_irqsave(&priv->lock, flags);
1288 pch_uart_hal_set_break(priv, ctl);
1289 spin_unlock_irqrestore(&priv->lock, flags);
1292 /* Grab any interrupt resources and initialise any low level driver state. */
1293 static int pch_uart_startup(struct uart_port *port)
1295 struct eg20t_port *priv;
1300 priv = container_of(port, struct eg20t_port, port);
1304 priv->uartclk = port->uartclk;
1306 port->uartclk = priv->uartclk;
1308 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1309 ret = pch_uart_hal_set_line(priv, default_baud,
1310 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1315 switch (priv->fifo_size) {
1317 fifo_size = PCH_UART_HAL_FIFO256;
1320 fifo_size = PCH_UART_HAL_FIFO64;
1323 fifo_size = PCH_UART_HAL_FIFO16;
1327 fifo_size = PCH_UART_HAL_FIFO_DIS;
1331 switch (priv->trigger) {
1332 case PCH_UART_HAL_TRIGGER1:
1335 case PCH_UART_HAL_TRIGGER_L:
1336 trigger_level = priv->fifo_size / 4;
1338 case PCH_UART_HAL_TRIGGER_M:
1339 trigger_level = priv->fifo_size / 2;
1341 case PCH_UART_HAL_TRIGGER_H:
1343 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1347 priv->trigger_level = trigger_level;
1348 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1349 fifo_size, priv->trigger);
1353 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1354 priv->irq_name, priv);
1359 pch_request_dma(port);
1362 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1363 PCH_UART_HAL_RX_ERR_INT);
1364 uart_update_timeout(port, CS8, default_baud);
1369 static void pch_uart_shutdown(struct uart_port *port)
1371 struct eg20t_port *priv;
1374 priv = container_of(port, struct eg20t_port, port);
1375 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1376 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1377 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1378 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1380 dev_err(priv->port.dev,
1381 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1385 free_irq(priv->port.irq, priv);
1388 /* Change the port parameters, including word length, parity, stop
1389 *bits. Update read_status_mask and ignore_status_mask to indicate
1390 *the types of events we are interested in receiving. */
1391 static void pch_uart_set_termios(struct uart_port *port,
1392 struct ktermios *termios, struct ktermios *old)
1395 unsigned int baud, parity, bits, stb;
1396 struct eg20t_port *priv;
1397 unsigned long flags;
1399 priv = container_of(port, struct eg20t_port, port);
1400 switch (termios->c_cflag & CSIZE) {
1402 bits = PCH_UART_HAL_5BIT;
1405 bits = PCH_UART_HAL_6BIT;
1408 bits = PCH_UART_HAL_7BIT;
1411 bits = PCH_UART_HAL_8BIT;
1414 if (termios->c_cflag & CSTOPB)
1415 stb = PCH_UART_HAL_STB2;
1417 stb = PCH_UART_HAL_STB1;
1419 if (termios->c_cflag & PARENB) {
1420 if (termios->c_cflag & PARODD)
1421 parity = PCH_UART_HAL_PARITY_ODD;
1423 parity = PCH_UART_HAL_PARITY_EVEN;
1426 parity = PCH_UART_HAL_PARITY_NONE;
1428 /* Only UART0 has auto hardware flow function */
1429 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1430 priv->mcr |= UART_MCR_AFE;
1432 priv->mcr &= ~UART_MCR_AFE;
1434 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1436 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1438 spin_lock_irqsave(&priv->lock, flags);
1439 spin_lock(&port->lock);
1441 uart_update_timeout(port, termios->c_cflag, baud);
1442 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1446 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1447 /* Don't rewrite B0 */
1448 if (tty_termios_baud_rate(termios))
1449 tty_termios_encode_baud_rate(termios, baud, baud);
1452 spin_unlock(&port->lock);
1453 spin_unlock_irqrestore(&priv->lock, flags);
1456 static const char *pch_uart_type(struct uart_port *port)
1458 return KBUILD_MODNAME;
1461 static void pch_uart_release_port(struct uart_port *port)
1463 struct eg20t_port *priv;
1465 priv = container_of(port, struct eg20t_port, port);
1466 pci_iounmap(priv->pdev, priv->membase);
1467 pci_release_regions(priv->pdev);
1470 static int pch_uart_request_port(struct uart_port *port)
1472 struct eg20t_port *priv;
1474 void __iomem *membase;
1476 priv = container_of(port, struct eg20t_port, port);
1477 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1481 membase = pci_iomap(priv->pdev, 1, 0);
1483 pci_release_regions(priv->pdev);
1486 priv->membase = port->membase = membase;
1491 static void pch_uart_config_port(struct uart_port *port, int type)
1493 struct eg20t_port *priv;
1495 priv = container_of(port, struct eg20t_port, port);
1496 if (type & UART_CONFIG_TYPE) {
1497 port->type = priv->port_type;
1498 pch_uart_request_port(port);
1502 static int pch_uart_verify_port(struct uart_port *port,
1503 struct serial_struct *serinfo)
1505 struct eg20t_port *priv;
1507 priv = container_of(port, struct eg20t_port, port);
1508 if (serinfo->flags & UPF_LOW_LATENCY) {
1509 dev_info(priv->port.dev,
1510 "PCH UART : Use PIO Mode (without DMA)\n");
1512 serinfo->flags &= ~UPF_LOW_LATENCY;
1514 #ifndef CONFIG_PCH_DMA
1515 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1519 if (!priv->use_dma) {
1520 pch_request_dma(port);
1524 dev_info(priv->port.dev, "PCH UART: %s\n",
1526 "Use DMA Mode" : "No DMA");
1532 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1534 * Wait for transmitter & holding register to empty
1536 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1538 unsigned int status, tmout = 10000;
1540 /* Wait up to 10ms for the character(s) to be sent. */
1542 status = ioread8(up->membase + UART_LSR);
1544 if ((status & bits) == bits)
1551 /* Wait up to 1s for flow control if necessary */
1552 if (up->port.flags & UPF_CONS_FLOW) {
1554 for (tmout = 1000000; tmout; tmout--) {
1555 unsigned int msr = ioread8(up->membase + UART_MSR);
1556 if (msr & UART_MSR_CTS)
1559 touch_nmi_watchdog();
1563 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1565 #ifdef CONFIG_CONSOLE_POLL
1567 * Console polling routines for communicate via uart while
1568 * in an interrupt or debug context.
1570 static int pch_uart_get_poll_char(struct uart_port *port)
1572 struct eg20t_port *priv =
1573 container_of(port, struct eg20t_port, port);
1574 u8 lsr = ioread8(priv->membase + UART_LSR);
1576 if (!(lsr & UART_LSR_DR))
1577 return NO_POLL_CHAR;
1579 return ioread8(priv->membase + PCH_UART_RBR);
1583 static void pch_uart_put_poll_char(struct uart_port *port,
1587 struct eg20t_port *priv =
1588 container_of(port, struct eg20t_port, port);
1591 * First save the IER then disable the interrupts
1593 ier = ioread8(priv->membase + UART_IER);
1594 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1596 wait_for_xmitr(priv, UART_LSR_THRE);
1598 * Send the character out.
1600 iowrite8(c, priv->membase + PCH_UART_THR);
1603 * Finally, wait for transmitter to become empty
1604 * and restore the IER
1606 wait_for_xmitr(priv, BOTH_EMPTY);
1607 iowrite8(ier, priv->membase + UART_IER);
1609 #endif /* CONFIG_CONSOLE_POLL */
1611 static const struct uart_ops pch_uart_ops = {
1612 .tx_empty = pch_uart_tx_empty,
1613 .set_mctrl = pch_uart_set_mctrl,
1614 .get_mctrl = pch_uart_get_mctrl,
1615 .stop_tx = pch_uart_stop_tx,
1616 .start_tx = pch_uart_start_tx,
1617 .stop_rx = pch_uart_stop_rx,
1618 .enable_ms = pch_uart_enable_ms,
1619 .break_ctl = pch_uart_break_ctl,
1620 .startup = pch_uart_startup,
1621 .shutdown = pch_uart_shutdown,
1622 .set_termios = pch_uart_set_termios,
1623 /* .pm = pch_uart_pm, Not supported yet */
1624 .type = pch_uart_type,
1625 .release_port = pch_uart_release_port,
1626 .request_port = pch_uart_request_port,
1627 .config_port = pch_uart_config_port,
1628 .verify_port = pch_uart_verify_port,
1629 #ifdef CONFIG_CONSOLE_POLL
1630 .poll_get_char = pch_uart_get_poll_char,
1631 .poll_put_char = pch_uart_put_poll_char,
1635 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1637 static void pch_console_putchar(struct uart_port *port, int ch)
1639 struct eg20t_port *priv =
1640 container_of(port, struct eg20t_port, port);
1642 wait_for_xmitr(priv, UART_LSR_THRE);
1643 iowrite8(ch, priv->membase + PCH_UART_THR);
1647 * Print a string to the serial port trying not to disturb
1648 * any possible real use of the port...
1650 * The console_lock must be held when we get here.
1653 pch_console_write(struct console *co, const char *s, unsigned int count)
1655 struct eg20t_port *priv;
1656 unsigned long flags;
1657 int priv_locked = 1;
1658 int port_locked = 1;
1661 priv = pch_uart_ports[co->index];
1663 touch_nmi_watchdog();
1665 local_irq_save(flags);
1666 if (priv->port.sysrq) {
1667 /* call to uart_handle_sysrq_char already took the priv lock */
1669 /* serial8250_handle_port() already took the port lock */
1671 } else if (oops_in_progress) {
1672 priv_locked = spin_trylock(&priv->lock);
1673 port_locked = spin_trylock(&priv->port.lock);
1675 spin_lock(&priv->lock);
1676 spin_lock(&priv->port.lock);
1680 * First save the IER then disable the interrupts
1682 ier = ioread8(priv->membase + UART_IER);
1684 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1686 uart_console_write(&priv->port, s, count, pch_console_putchar);
1689 * Finally, wait for transmitter to become empty
1690 * and restore the IER
1692 wait_for_xmitr(priv, BOTH_EMPTY);
1693 iowrite8(ier, priv->membase + UART_IER);
1696 spin_unlock(&priv->port.lock);
1698 spin_unlock(&priv->lock);
1699 local_irq_restore(flags);
1702 static int __init pch_console_setup(struct console *co, char *options)
1704 struct uart_port *port;
1705 int baud = default_baud;
1711 * Check whether an invalid uart number has been specified, and
1712 * if so, search for the first available port that does have
1715 if (co->index >= PCH_UART_NR)
1717 port = &pch_uart_ports[co->index]->port;
1719 if (!port || (!port->iobase && !port->membase))
1722 port->uartclk = pch_uart_get_uartclk();
1725 uart_parse_options(options, &baud, &parity, &bits, &flow);
1727 return uart_set_options(port, co, baud, parity, bits, flow);
1730 static struct uart_driver pch_uart_driver;
1732 static struct console pch_console = {
1733 .name = PCH_UART_DRIVER_DEVICE,
1734 .write = pch_console_write,
1735 .device = uart_console_device,
1736 .setup = pch_console_setup,
1737 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1739 .data = &pch_uart_driver,
1742 #define PCH_CONSOLE (&pch_console)
1744 #define PCH_CONSOLE NULL
1745 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1747 static struct uart_driver pch_uart_driver = {
1748 .owner = THIS_MODULE,
1749 .driver_name = KBUILD_MODNAME,
1750 .dev_name = PCH_UART_DRIVER_DEVICE,
1754 .cons = PCH_CONSOLE,
1757 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1758 const struct pci_device_id *id)
1760 struct eg20t_port *priv;
1762 unsigned int iobase;
1763 unsigned int mapbase;
1764 unsigned char *rxbuf;
1767 struct pch_uart_driver_data *board;
1768 #ifdef CONFIG_DEBUG_FS
1769 char name[32]; /* for debugfs file name */
1772 board = &drv_dat[id->driver_data];
1773 port_type = board->port_type;
1775 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1777 goto init_port_alloc_err;
1779 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1781 goto init_port_free_txbuf;
1783 switch (port_type) {
1785 fifosize = 256; /* EG20T/ML7213: UART0 */
1788 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1791 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1792 goto init_port_hal_free;
1795 pci_enable_msi(pdev);
1796 pci_set_master(pdev);
1798 spin_lock_init(&priv->lock);
1800 iobase = pci_resource_start(pdev, 0);
1801 mapbase = pci_resource_start(pdev, 1);
1802 priv->mapbase = mapbase;
1803 priv->iobase = iobase;
1806 priv->rxbuf.buf = rxbuf;
1807 priv->rxbuf.size = PAGE_SIZE;
1809 priv->fifo_size = fifosize;
1810 priv->uartclk = pch_uart_get_uartclk();
1811 priv->port_type = PORT_MAX_8250 + port_type + 1;
1812 priv->port.dev = &pdev->dev;
1813 priv->port.iobase = iobase;
1814 priv->port.membase = NULL;
1815 priv->port.mapbase = mapbase;
1816 priv->port.irq = pdev->irq;
1817 priv->port.iotype = UPIO_PORT;
1818 priv->port.ops = &pch_uart_ops;
1819 priv->port.flags = UPF_BOOT_AUTOCONF;
1820 priv->port.fifosize = fifosize;
1821 priv->port.line = board->line_no;
1822 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1824 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1825 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1828 spin_lock_init(&priv->port.lock);
1830 pci_set_drvdata(pdev, priv);
1831 priv->trigger_level = 1;
1834 if (pdev->dev.of_node)
1835 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1838 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1839 pch_uart_ports[board->line_no] = priv;
1841 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1843 goto init_port_hal_free;
1845 #ifdef CONFIG_DEBUG_FS
1846 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1847 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1848 NULL, priv, &port_regs_ops);
1854 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1855 pch_uart_ports[board->line_no] = NULL;
1857 free_page((unsigned long)rxbuf);
1858 init_port_free_txbuf:
1860 init_port_alloc_err:
1865 static void pch_uart_exit_port(struct eg20t_port *priv)
1868 #ifdef CONFIG_DEBUG_FS
1870 debugfs_remove(priv->debugfs);
1872 uart_remove_one_port(&pch_uart_driver, &priv->port);
1873 free_page((unsigned long)priv->rxbuf.buf);
1876 static void pch_uart_pci_remove(struct pci_dev *pdev)
1878 struct eg20t_port *priv = pci_get_drvdata(pdev);
1880 pci_disable_msi(pdev);
1882 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1883 pch_uart_ports[priv->port.line] = NULL;
1885 pch_uart_exit_port(priv);
1886 pci_disable_device(pdev);
1891 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1893 struct eg20t_port *priv = pci_get_drvdata(pdev);
1895 uart_suspend_port(&pch_uart_driver, &priv->port);
1897 pci_save_state(pdev);
1898 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1902 static int pch_uart_pci_resume(struct pci_dev *pdev)
1904 struct eg20t_port *priv = pci_get_drvdata(pdev);
1907 pci_set_power_state(pdev, PCI_D0);
1908 pci_restore_state(pdev);
1910 ret = pci_enable_device(pdev);
1913 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1917 uart_resume_port(&pch_uart_driver, &priv->port);
1922 #define pch_uart_pci_suspend NULL
1923 #define pch_uart_pci_resume NULL
1926 static const struct pci_device_id pch_uart_pci_id[] = {
1927 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1928 .driver_data = pch_et20t_uart0},
1929 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1930 .driver_data = pch_et20t_uart1},
1931 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1932 .driver_data = pch_et20t_uart2},
1933 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1934 .driver_data = pch_et20t_uart3},
1935 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1936 .driver_data = pch_ml7213_uart0},
1937 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1938 .driver_data = pch_ml7213_uart1},
1939 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1940 .driver_data = pch_ml7213_uart2},
1941 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1942 .driver_data = pch_ml7223_uart0},
1943 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1944 .driver_data = pch_ml7223_uart1},
1945 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1946 .driver_data = pch_ml7831_uart0},
1947 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1948 .driver_data = pch_ml7831_uart1},
1952 static int pch_uart_pci_probe(struct pci_dev *pdev,
1953 const struct pci_device_id *id)
1956 struct eg20t_port *priv;
1958 ret = pci_enable_device(pdev);
1962 priv = pch_uart_init_port(pdev, id);
1965 goto probe_disable_device;
1967 pci_set_drvdata(pdev, priv);
1971 probe_disable_device:
1972 pci_disable_msi(pdev);
1973 pci_disable_device(pdev);
1978 static struct pci_driver pch_uart_pci_driver = {
1980 .id_table = pch_uart_pci_id,
1981 .probe = pch_uart_pci_probe,
1982 .remove = pch_uart_pci_remove,
1983 .suspend = pch_uart_pci_suspend,
1984 .resume = pch_uart_pci_resume,
1987 static int __init pch_uart_module_init(void)
1991 /* register as UART driver */
1992 ret = uart_register_driver(&pch_uart_driver);
1996 /* register as PCI driver */
1997 ret = pci_register_driver(&pch_uart_pci_driver);
1999 uart_unregister_driver(&pch_uart_driver);
2003 module_init(pch_uart_module_init);
2005 static void __exit pch_uart_module_exit(void)
2007 pci_unregister_driver(&pch_uart_pci_driver);
2008 uart_unregister_driver(&pch_uart_driver);
2010 module_exit(pch_uart_module_exit);
2012 MODULE_LICENSE("GPL v2");
2013 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2014 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2016 module_param(default_baud, uint, S_IRUGO);
2017 MODULE_PARM_DESC(default_baud,
2018 "Default BAUD for initial driver state and console (default 9600)");
2019 module_param(user_uartclk, uint, S_IRUGO);
2020 MODULE_PARM_DESC(user_uartclk,
2021 "Override UART default or board specific UART clock");