1 // SPDX-License-Identifier: GPL-2.0+
3 * Application UART driver for:
4 * Freescale STMP37XX/STMP378X
7 * Author: dmitry pervushin <dimka@embeddedalley.com>
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
10 * Provide Alphascale ASM9260 support.
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
12 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/slab.h>
22 #include <linux/wait.h>
23 #include <linux/tty.h>
24 #include <linux/tty_driver.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_core.h>
28 #include <linux/platform_device.h>
29 #include <linux/device.h>
30 #include <linux/clk.h>
31 #include <linux/delay.h>
33 #include <linux/of_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/dmaengine.h>
37 #include <asm/cacheflush.h>
39 #include <linux/gpio/consumer.h>
40 #include <linux/err.h>
41 #include <linux/irq.h>
42 #include "serial_mctrl_gpio.h"
44 #define MXS_AUART_PORTS 5
45 #define MXS_AUART_FIFO_SIZE 16
51 #define AUART_CTRL0 0x00000000
52 #define AUART_CTRL1 0x00000010
53 #define AUART_CTRL2 0x00000020
54 #define AUART_LINECTRL 0x00000030
55 #define AUART_LINECTRL2 0x00000040
56 #define AUART_INTR 0x00000050
57 #define AUART_DATA 0x00000060
58 #define AUART_STAT 0x00000070
59 #define AUART_DEBUG 0x00000080
60 #define AUART_VERSION 0x00000090
61 #define AUART_AUTOBAUD 0x000000a0
63 #define AUART_CTRL0_SFTRST (1 << 31)
64 #define AUART_CTRL0_CLKGATE (1 << 30)
65 #define AUART_CTRL0_RXTO_ENABLE (1 << 27)
66 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
67 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
69 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
71 #define AUART_CTRL2_DMAONERR (1 << 26)
72 #define AUART_CTRL2_TXDMAE (1 << 25)
73 #define AUART_CTRL2_RXDMAE (1 << 24)
75 #define AUART_CTRL2_CTSEN (1 << 15)
76 #define AUART_CTRL2_RTSEN (1 << 14)
77 #define AUART_CTRL2_RTS (1 << 11)
78 #define AUART_CTRL2_RXE (1 << 9)
79 #define AUART_CTRL2_TXE (1 << 8)
80 #define AUART_CTRL2_UARTEN (1 << 0)
82 #define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
83 #define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
84 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
85 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
86 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
87 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
88 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
89 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
90 #define AUART_LINECTRL_SPS (1 << 7)
91 #define AUART_LINECTRL_WLEN_MASK 0x00000060
92 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
93 #define AUART_LINECTRL_FEN (1 << 4)
94 #define AUART_LINECTRL_STP2 (1 << 3)
95 #define AUART_LINECTRL_EPS (1 << 2)
96 #define AUART_LINECTRL_PEN (1 << 1)
97 #define AUART_LINECTRL_BRK (1 << 0)
99 #define AUART_INTR_RTIEN (1 << 22)
100 #define AUART_INTR_TXIEN (1 << 21)
101 #define AUART_INTR_RXIEN (1 << 20)
102 #define AUART_INTR_CTSMIEN (1 << 17)
103 #define AUART_INTR_RTIS (1 << 6)
104 #define AUART_INTR_TXIS (1 << 5)
105 #define AUART_INTR_RXIS (1 << 4)
106 #define AUART_INTR_CTSMIS (1 << 1)
108 #define AUART_STAT_BUSY (1 << 29)
109 #define AUART_STAT_CTS (1 << 28)
110 #define AUART_STAT_TXFE (1 << 27)
111 #define AUART_STAT_TXFF (1 << 25)
112 #define AUART_STAT_RXFE (1 << 24)
113 #define AUART_STAT_OERR (1 << 19)
114 #define AUART_STAT_BERR (1 << 18)
115 #define AUART_STAT_PERR (1 << 17)
116 #define AUART_STAT_FERR (1 << 16)
117 #define AUART_STAT_RXCOUNT_MASK 0xffff
120 * Start of Alphascale asm9260 defines
121 * This list contains only differences of existing bits
122 * between imx2x and asm9260
124 #define ASM9260_HW_CTRL0 0x0000
126 * RW. Tell the UART to execute the RX DMA Command. The
127 * UART will clear this bit at the end of receive execution.
129 #define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
130 /* RW. 0 use FIFO for status register; 1 use DMA */
131 #define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
133 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
134 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
135 * operation. If this bit is set to 1, a receive timeout will cause the receive
136 * DMA logic to terminate by filling the remaining DMA bytes with garbage data.
138 #define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
140 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
141 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX
142 * input is idle, then the watchdog counter will decrement each bit-time. Note
143 * 7-bit-time is added to the programmed value, so a value of zero will set
144 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
145 * note that the counter is reloaded at the end of each frame, so if the frame
146 * is 10 bits long and the timeout counter value is zero, then timeout will
147 * occur (when FIFO is not empty) even if the RX input is not idle. The default
148 * value is 0x3 (31 bit-time).
150 #define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
151 /* TIMEOUT = (100*7+1)*(1/BAUD) */
152 #define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
154 /* TX ctrl register */
155 #define ASM9260_HW_CTRL1 0x0010
157 * RW. Tell the UART to execute the TX DMA Command. The
158 * UART will clear this bit at the end of transmit execution.
160 #define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
162 #define ASM9260_HW_CTRL2 0x0020
164 * RW. Receive Interrupt FIFO Level Select.
165 * The trigger points for the receive interrupt are as follows:
166 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
167 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
168 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
169 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
170 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
172 #define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
173 #define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
174 /* RW. Same as RXIFLSEL */
175 #define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
176 #define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
177 /* RW. Set DTR. When this bit is 1, the output is 0. */
178 #define ASM9260_BM_CTRL2_DTR BIT(10)
179 /* RW. Loop Back Enable */
180 #define ASM9260_BM_CTRL2_LBE BIT(7)
181 #define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
183 #define ASM9260_HW_LINECTRL 0x0030
185 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
186 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
187 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
188 * bit is cleared stick parity is disabled.
190 #define ASM9260_BM_LCTRL_SPS BIT(7)
191 /* RW. Word length */
192 #define ASM9260_BM_LCTRL_WLEN (3 << 5)
193 #define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
194 #define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
195 #define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
196 #define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
199 * Interrupt register.
200 * contains the interrupt enables and the interrupt status bits
202 #define ASM9260_HW_INTR 0x0040
203 /* Tx FIFO EMPTY Raw Interrupt enable */
204 #define ASM9260_BM_INTR_TFEIEN BIT(27)
205 /* Overrun Error Interrupt Enable. */
206 #define ASM9260_BM_INTR_OEIEN BIT(26)
207 /* Break Error Interrupt Enable. */
208 #define ASM9260_BM_INTR_BEIEN BIT(25)
209 /* Parity Error Interrupt Enable. */
210 #define ASM9260_BM_INTR_PEIEN BIT(24)
211 /* Framing Error Interrupt Enable. */
212 #define ASM9260_BM_INTR_FEIEN BIT(23)
214 /* nUARTDSR Modem Interrupt Enable. */
215 #define ASM9260_BM_INTR_DSRMIEN BIT(19)
216 /* nUARTDCD Modem Interrupt Enable. */
217 #define ASM9260_BM_INTR_DCDMIEN BIT(18)
218 /* nUARTRI Modem Interrupt Enable. */
219 #define ASM9260_BM_INTR_RIMIEN BIT(16)
220 /* Auto-Boud Timeout */
221 #define ASM9260_BM_INTR_ABTO BIT(13)
222 #define ASM9260_BM_INTR_ABEO BIT(12)
223 /* Tx FIFO EMPTY Raw Interrupt state */
224 #define ASM9260_BM_INTR_TFEIS BIT(11)
226 #define ASM9260_BM_INTR_OEIS BIT(10)
228 #define ASM9260_BM_INTR_BEIS BIT(9)
230 #define ASM9260_BM_INTR_PEIS BIT(8)
232 #define ASM9260_BM_INTR_FEIS BIT(7)
233 #define ASM9260_BM_INTR_DSRMIS BIT(3)
234 #define ASM9260_BM_INTR_DCDMIS BIT(2)
235 #define ASM9260_BM_INTR_RIMIS BIT(0)
238 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
239 * time. In PIO mode, only one character can be accessed at a time. The status
240 * register contains the receive data flags and valid bits.
242 #define ASM9260_HW_DATA 0x0050
244 #define ASM9260_HW_STAT 0x0060
245 /* RO. If 1, UARTAPP is present in this product. */
246 #define ASM9260_BM_STAT_PRESENT BIT(31)
247 /* RO. If 1, HISPEED is present in this product. */
248 #define ASM9260_BM_STAT_HISPEED BIT(30)
249 /* RO. Receive FIFO Full. */
250 #define ASM9260_BM_STAT_RXFULL BIT(26)
252 /* RO. The UART Debug Register contains the state of the DMA signals. */
253 #define ASM9260_HW_DEBUG 0x0070
254 /* DMA Command Run Status */
255 #define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
256 #define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
257 /* DMA Command End Status */
258 #define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
259 #define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
260 /* DMA Request Status */
261 #define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
262 #define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
264 #define ASM9260_HW_ILPR 0x0080
266 #define ASM9260_HW_RS485CTRL 0x0090
268 * RW. This bit reverses the polarity of the direction control signal on the RTS
270 * If 0, The direction control pin will be driven to logic ‘0’ when the
271 * transmitter has data to be sent. It will be driven to logic ‘1’ after the
272 * last bit of data has been transmitted.
274 #define ASM9260_BM_RS485CTRL_ONIV BIT(5)
275 /* RW. Enable Auto Direction Control. */
276 #define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
278 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
279 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
281 #define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
282 /* RW. Enable Auto Address Detect (AAD). */
283 #define ASM9260_BM_RS485CTRL_AADEN BIT(2)
284 /* RW. Disable receiver. */
285 #define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
286 /* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
287 #define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
289 #define ASM9260_HW_RS485ADRMATCH 0x00a0
290 /* Contains the address match value. */
291 #define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
293 #define ASM9260_HW_RS485DLY 0x00b0
295 * RW. Contains the direction control (RTS or DTR) delay value. This delay time
296 * is in periods of the baud clock.
298 #define ASM9260_BM_RS485DLY_MASK (0xff << 0)
300 #define ASM9260_HW_AUTOBAUD 0x00c0
301 /* WO. Auto-baud time-out interrupt clear bit. */
302 #define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
303 /* WO. End of auto-baud interrupt clear bit. */
304 #define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
305 /* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
306 #define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
307 /* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
308 #define ASM9260_BM_AUTOBAUD_MODE BIT(1)
310 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
311 * automatically cleared after auto-baud completion.
313 #define ASM9260_BM_AUTOBAUD_START BIT(0)
315 #define ASM9260_HW_CTRL3 0x00d0
316 #define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
318 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
321 #define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
322 /* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
323 #define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
324 /* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
325 #define ASM9260_BM_CTRL3_MSBF BIT(2)
326 /* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
327 #define ASM9260_BM_CTRL3_BAUD8 BIT(1)
328 /* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
329 #define ASM9260_BM_CTRL3_9BIT BIT(0)
331 #define ASM9260_HW_ISO7816_CTRL 0x00e0
332 /* RW. Enable High Speed mode. */
333 #define ASM9260_BM_ISO7816CTRL_HS BIT(12)
334 /* Disable Successive Receive NACK */
335 #define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
336 #define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
337 /* Receive NACK Inhibit */
338 #define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
339 #define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
340 /* RW. 1 - ISO7816 mode; 0 - USART mode */
341 #define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
343 #define ASM9260_HW_ISO7816_ERRCNT 0x00f0
344 /* Parity error counter. Will be cleared after reading */
345 #define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
347 #define ASM9260_HW_ISO7816_STATUS 0x0100
348 /* Max number of Repetitions Reached */
349 #define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
351 /* End of Alphascale asm9260 defines */
353 static struct uart_driver auart_driver;
355 enum mxs_auart_type {
362 const u16 *reg_offset;
378 /* The size of the array - must be last */
382 static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
383 [REG_CTRL0] = ASM9260_HW_CTRL0,
384 [REG_CTRL1] = ASM9260_HW_CTRL1,
385 [REG_CTRL2] = ASM9260_HW_CTRL2,
386 [REG_LINECTRL] = ASM9260_HW_LINECTRL,
387 [REG_INTR] = ASM9260_HW_INTR,
388 [REG_DATA] = ASM9260_HW_DATA,
389 [REG_STAT] = ASM9260_HW_STAT,
390 [REG_DEBUG] = ASM9260_HW_DEBUG,
391 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
394 static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
395 [REG_CTRL0] = AUART_CTRL0,
396 [REG_CTRL1] = AUART_CTRL1,
397 [REG_CTRL2] = AUART_CTRL2,
398 [REG_LINECTRL] = AUART_LINECTRL,
399 [REG_LINECTRL2] = AUART_LINECTRL2,
400 [REG_INTR] = AUART_INTR,
401 [REG_DATA] = AUART_DATA,
402 [REG_STAT] = AUART_STAT,
403 [REG_DEBUG] = AUART_DEBUG,
404 [REG_VERSION] = AUART_VERSION,
405 [REG_AUTOBAUD] = AUART_AUTOBAUD,
408 static const struct vendor_data vendor_alphascale_asm9260 = {
409 .reg_offset = mxs_asm9260_offsets,
412 static const struct vendor_data vendor_freescale_stmp37xx = {
413 .reg_offset = mxs_stmp37xx_offsets,
416 struct mxs_auart_port {
417 struct uart_port port;
419 #define MXS_AUART_DMA_ENABLED 0x2
420 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
421 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
422 #define MXS_AUART_RTSCTS 4 /* bit 4 */
424 unsigned int mctrl_prev;
425 enum mxs_auart_type devtype;
426 const struct vendor_data *vendor;
433 struct scatterlist tx_sgl;
434 struct dma_chan *tx_dma_chan;
437 struct scatterlist rx_sgl;
438 struct dma_chan *rx_dma_chan;
441 struct mctrl_gpios *gpios;
442 int gpio_irq[UART_GPIO_MAX];
446 static const struct platform_device_id mxs_auart_devtype[] = {
447 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
448 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
449 { .name = "as-auart-asm9260", .driver_data = ASM9260_AUART },
452 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
454 static const struct of_device_id mxs_auart_dt_ids[] = {
456 .compatible = "fsl,imx28-auart",
457 .data = &mxs_auart_devtype[IMX28_AUART]
459 .compatible = "fsl,imx23-auart",
460 .data = &mxs_auart_devtype[IMX23_AUART]
462 .compatible = "alphascale,asm9260-auart",
463 .data = &mxs_auart_devtype[ASM9260_AUART]
464 }, { /* sentinel */ }
466 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
468 static inline int is_imx28_auart(struct mxs_auart_port *s)
470 return s->devtype == IMX28_AUART;
473 static inline int is_asm9260_auart(struct mxs_auart_port *s)
475 return s->devtype == ASM9260_AUART;
478 static inline bool auart_dma_enabled(struct mxs_auart_port *s)
480 return s->flags & MXS_AUART_DMA_ENABLED;
483 static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
486 return uap->vendor->reg_offset[reg];
489 static unsigned int mxs_read(const struct mxs_auart_port *uap,
492 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
494 return readl_relaxed(addr);
497 static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
500 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
502 writel_relaxed(val, addr);
505 static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
508 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
510 writel_relaxed(val, addr + SET_REG);
513 static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
516 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
518 writel_relaxed(val, addr + CLR_REG);
521 static void mxs_auart_stop_tx(struct uart_port *u);
523 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
525 static void mxs_auart_tx_chars(struct mxs_auart_port *s);
527 static void dma_tx_callback(void *param)
529 struct mxs_auart_port *s = param;
530 struct circ_buf *xmit = &s->port.state->xmit;
532 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
534 /* clear the bit used to serialize the DMA tx. */
535 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
536 smp_mb__after_atomic();
538 /* wake up the possible processes. */
539 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
540 uart_write_wakeup(&s->port);
542 mxs_auart_tx_chars(s);
545 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
547 struct dma_async_tx_descriptor *desc;
548 struct scatterlist *sgl = &s->tx_sgl;
549 struct dma_chan *channel = s->tx_dma_chan;
552 /* [1] : send PIO. Note, the first pio word is CTRL1. */
553 pio = AUART_CTRL1_XFER_COUNT(size);
554 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
555 1, DMA_TRANS_NONE, 0);
557 dev_err(s->dev, "step 1 error\n");
561 /* [2] : set DMA buffer. */
562 sg_init_one(sgl, s->tx_dma_buf, size);
563 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
564 desc = dmaengine_prep_slave_sg(channel, sgl,
565 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
567 dev_err(s->dev, "step 2 error\n");
571 /* [3] : submit the DMA */
572 desc->callback = dma_tx_callback;
573 desc->callback_param = s;
574 dmaengine_submit(desc);
575 dma_async_issue_pending(channel);
579 static void mxs_auart_tx_chars(struct mxs_auart_port *s)
581 struct circ_buf *xmit = &s->port.state->xmit;
583 if (auart_dma_enabled(s)) {
586 void *buffer = s->tx_dma_buf;
588 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
591 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
592 size = min_t(u32, UART_XMIT_SIZE - i,
593 CIRC_CNT_TO_END(xmit->head,
596 memcpy(buffer + i, xmit->buf + xmit->tail, size);
597 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
600 if (i >= UART_XMIT_SIZE)
604 if (uart_tx_stopped(&s->port))
605 mxs_auart_stop_tx(&s->port);
608 mxs_auart_dma_tx(s, i);
610 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
611 smp_mb__after_atomic();
617 while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) {
618 if (s->port.x_char) {
620 mxs_write(s->port.x_char, s, REG_DATA);
624 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
626 mxs_write(xmit->buf[xmit->tail], s, REG_DATA);
627 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
631 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
632 uart_write_wakeup(&s->port);
634 if (uart_circ_empty(&(s->port.state->xmit)))
635 mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);
637 mxs_set(AUART_INTR_TXIEN, s, REG_INTR);
639 if (uart_tx_stopped(&s->port))
640 mxs_auart_stop_tx(&s->port);
643 static void mxs_auart_rx_char(struct mxs_auart_port *s)
649 c = mxs_read(s, REG_DATA);
650 stat = mxs_read(s, REG_STAT);
655 if (stat & AUART_STAT_BERR) {
656 s->port.icount.brk++;
657 if (uart_handle_break(&s->port))
659 } else if (stat & AUART_STAT_PERR) {
660 s->port.icount.parity++;
661 } else if (stat & AUART_STAT_FERR) {
662 s->port.icount.frame++;
666 * Mask off conditions which should be ingored.
668 stat &= s->port.read_status_mask;
670 if (stat & AUART_STAT_BERR) {
672 } else if (stat & AUART_STAT_PERR)
674 else if (stat & AUART_STAT_FERR)
677 if (stat & AUART_STAT_OERR)
678 s->port.icount.overrun++;
680 if (uart_handle_sysrq_char(&s->port, c))
683 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
685 mxs_write(stat, s, REG_STAT);
688 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
693 stat = mxs_read(s, REG_STAT);
694 if (stat & AUART_STAT_RXFE)
696 mxs_auart_rx_char(s);
699 mxs_write(stat, s, REG_STAT);
700 tty_flip_buffer_push(&s->port.state->port);
703 static int mxs_auart_request_port(struct uart_port *u)
708 static int mxs_auart_verify_port(struct uart_port *u,
709 struct serial_struct *ser)
711 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
716 static void mxs_auart_config_port(struct uart_port *u, int flags)
720 static const char *mxs_auart_type(struct uart_port *u)
722 struct mxs_auart_port *s = to_auart_port(u);
724 return dev_name(s->dev);
727 static void mxs_auart_release_port(struct uart_port *u)
731 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
733 struct mxs_auart_port *s = to_auart_port(u);
735 u32 ctrl = mxs_read(s, REG_CTRL2);
737 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
738 if (mctrl & TIOCM_RTS) {
739 if (uart_cts_enabled(u))
740 ctrl |= AUART_CTRL2_RTSEN;
742 ctrl |= AUART_CTRL2_RTS;
745 mxs_write(ctrl, s, REG_CTRL2);
747 mctrl_gpio_set(s->gpios, mctrl);
750 #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
751 static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
755 mctrl_diff = mctrl ^ s->mctrl_prev;
756 s->mctrl_prev = mctrl;
757 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
758 s->port.state != NULL) {
759 if (mctrl_diff & TIOCM_RI)
760 s->port.icount.rng++;
761 if (mctrl_diff & TIOCM_DSR)
762 s->port.icount.dsr++;
763 if (mctrl_diff & TIOCM_CD)
764 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
765 if (mctrl_diff & TIOCM_CTS)
766 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
768 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
773 static u32 mxs_auart_get_mctrl(struct uart_port *u)
775 struct mxs_auart_port *s = to_auart_port(u);
776 u32 stat = mxs_read(s, REG_STAT);
779 if (stat & AUART_STAT_CTS)
782 return mctrl_gpio_get(s->gpios, &mctrl);
786 * Enable modem status interrupts
788 static void mxs_auart_enable_ms(struct uart_port *port)
790 struct mxs_auart_port *s = to_auart_port(port);
793 * Interrupt should not be enabled twice
795 if (s->ms_irq_enabled)
798 s->ms_irq_enabled = true;
800 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
801 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
802 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
804 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
805 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
807 if (s->gpio_irq[UART_GPIO_RI] >= 0)
808 enable_irq(s->gpio_irq[UART_GPIO_RI]);
810 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
811 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
815 * Disable modem status interrupts
817 static void mxs_auart_disable_ms(struct uart_port *port)
819 struct mxs_auart_port *s = to_auart_port(port);
822 * Interrupt should not be disabled twice
824 if (!s->ms_irq_enabled)
827 s->ms_irq_enabled = false;
829 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
830 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
831 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
833 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
834 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
836 if (s->gpio_irq[UART_GPIO_RI] >= 0)
837 disable_irq(s->gpio_irq[UART_GPIO_RI]);
839 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
840 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
843 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
844 static void dma_rx_callback(void *arg)
846 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
847 struct tty_port *port = &s->port.state->port;
851 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
853 stat = mxs_read(s, REG_STAT);
854 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
855 AUART_STAT_PERR | AUART_STAT_FERR);
857 count = stat & AUART_STAT_RXCOUNT_MASK;
858 tty_insert_flip_string(port, s->rx_dma_buf, count);
860 mxs_write(stat, s, REG_STAT);
861 tty_flip_buffer_push(port);
863 /* start the next DMA for RX. */
864 mxs_auart_dma_prep_rx(s);
867 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
869 struct dma_async_tx_descriptor *desc;
870 struct scatterlist *sgl = &s->rx_sgl;
871 struct dma_chan *channel = s->rx_dma_chan;
875 pio[0] = AUART_CTRL0_RXTO_ENABLE
876 | AUART_CTRL0_RXTIMEOUT(0x80)
877 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
878 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
879 1, DMA_TRANS_NONE, 0);
881 dev_err(s->dev, "step 1 error\n");
885 /* [2] : send DMA request */
886 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
887 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
888 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
889 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
891 dev_err(s->dev, "step 2 error\n");
895 /* [3] : submit the DMA, but do not issue it. */
896 desc->callback = dma_rx_callback;
897 desc->callback_param = s;
898 dmaengine_submit(desc);
899 dma_async_issue_pending(channel);
903 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
905 if (s->tx_dma_chan) {
906 dma_release_channel(s->tx_dma_chan);
907 s->tx_dma_chan = NULL;
909 if (s->rx_dma_chan) {
910 dma_release_channel(s->rx_dma_chan);
911 s->rx_dma_chan = NULL;
914 kfree(s->tx_dma_buf);
915 kfree(s->rx_dma_buf);
916 s->tx_dma_buf = NULL;
917 s->rx_dma_buf = NULL;
920 static void mxs_auart_dma_exit(struct mxs_auart_port *s)
923 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
926 mxs_auart_dma_exit_channel(s);
927 s->flags &= ~MXS_AUART_DMA_ENABLED;
928 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
929 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
932 static int mxs_auart_dma_init(struct mxs_auart_port *s)
934 if (auart_dma_enabled(s))
938 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
941 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
946 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
949 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
954 s->flags |= MXS_AUART_DMA_ENABLED;
955 dev_dbg(s->dev, "enabled the DMA support.");
957 /* The DMA buffer is now the FIFO the TTY subsystem can use */
958 s->port.fifosize = UART_XMIT_SIZE;
963 mxs_auart_dma_exit_channel(s);
968 #define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS)
969 #define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS)
970 static void mxs_auart_settermios(struct uart_port *u,
971 struct ktermios *termios,
972 struct ktermios *old)
974 struct mxs_auart_port *s = to_auart_port(u);
975 u32 bm, ctrl, ctrl2, div;
976 unsigned int cflag, baud, baud_min, baud_max;
978 cflag = termios->c_cflag;
980 ctrl = AUART_LINECTRL_FEN;
981 ctrl2 = mxs_read(s, REG_CTRL2);
984 switch (cflag & CSIZE) {
1001 ctrl |= AUART_LINECTRL_WLEN(bm);
1004 if (cflag & PARENB) {
1005 ctrl |= AUART_LINECTRL_PEN;
1006 if ((cflag & PARODD) == 0)
1007 ctrl |= AUART_LINECTRL_EPS;
1009 ctrl |= AUART_LINECTRL_SPS;
1012 u->read_status_mask = AUART_STAT_OERR;
1014 if (termios->c_iflag & INPCK)
1015 u->read_status_mask |= AUART_STAT_PERR;
1016 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1017 u->read_status_mask |= AUART_STAT_BERR;
1020 * Characters to ignore
1022 u->ignore_status_mask = 0;
1023 if (termios->c_iflag & IGNPAR)
1024 u->ignore_status_mask |= AUART_STAT_PERR;
1025 if (termios->c_iflag & IGNBRK) {
1026 u->ignore_status_mask |= AUART_STAT_BERR;
1028 * If we're ignoring parity and break indicators,
1029 * ignore overruns too (for real raw support).
1031 if (termios->c_iflag & IGNPAR)
1032 u->ignore_status_mask |= AUART_STAT_OERR;
1036 * ignore all characters if CREAD is not set
1039 ctrl2 |= AUART_CTRL2_RXE;
1041 ctrl2 &= ~AUART_CTRL2_RXE;
1043 /* figure out the stop bits requested */
1045 ctrl |= AUART_LINECTRL_STP2;
1047 /* figure out the hardware flow control settings */
1048 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
1049 if (cflag & CRTSCTS) {
1051 * The DMA has a bug(see errata:2836) in mx23.
1052 * So we can not implement the DMA for auart in mx23,
1053 * we can only implement the DMA support for auart
1056 if (is_imx28_auart(s)
1057 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
1058 if (!mxs_auart_dma_init(s))
1059 /* enable DMA tranfer */
1060 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
1061 | AUART_CTRL2_DMAONERR;
1063 /* Even if RTS is GPIO line RTSEN can be enabled because
1064 * the pinctrl configuration decides about RTS pin function */
1065 ctrl2 |= AUART_CTRL2_RTSEN;
1067 ctrl2 |= AUART_CTRL2_CTSEN;
1071 if (is_asm9260_auart(s)) {
1072 baud = uart_get_baud_rate(u, termios, old,
1073 u->uartclk * 4 / 0x3FFFFF,
1075 div = u->uartclk * 4 / baud;
1077 baud_min = DIV_ROUND_UP(u->uartclk * 32,
1078 AUART_LINECTRL_BAUD_DIV_MAX);
1079 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
1080 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
1081 div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);
1084 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
1085 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
1086 mxs_write(ctrl, s, REG_LINECTRL);
1088 mxs_write(ctrl2, s, REG_CTRL2);
1090 uart_update_timeout(u, termios->c_cflag, baud);
1092 /* prepare for the DMA RX. */
1093 if (auart_dma_enabled(s) &&
1094 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
1095 if (!mxs_auart_dma_prep_rx(s)) {
1096 /* Disable the normal RX interrupt. */
1097 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
1100 mxs_auart_dma_exit(s);
1101 dev_err(s->dev, "We can not start up the DMA.\n");
1105 /* CTS flow-control and modem-status interrupts */
1106 if (UART_ENABLE_MS(u, termios->c_cflag))
1107 mxs_auart_enable_ms(u);
1109 mxs_auart_disable_ms(u);
1112 static void mxs_auart_set_ldisc(struct uart_port *port,
1113 struct ktermios *termios)
1115 if (termios->c_line == N_PPS) {
1116 port->flags |= UPF_HARDPPS_CD;
1117 mxs_auart_enable_ms(port);
1119 port->flags &= ~UPF_HARDPPS_CD;
1123 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
1126 struct mxs_auart_port *s = context;
1127 u32 mctrl_temp = s->mctrl_prev;
1128 u32 stat = mxs_read(s, REG_STAT);
1130 istat = mxs_read(s, REG_INTR);
1133 mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
1134 | AUART_INTR_CTSMIS), s, REG_INTR);
1137 * Dealing with GPIO interrupt
1139 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
1140 irq == s->gpio_irq[UART_GPIO_DCD] ||
1141 irq == s->gpio_irq[UART_GPIO_DSR] ||
1142 irq == s->gpio_irq[UART_GPIO_RI])
1143 mxs_auart_modem_status(s,
1144 mctrl_gpio_get(s->gpios, &mctrl_temp));
1146 if (istat & AUART_INTR_CTSMIS) {
1147 if (CTS_AT_AUART() && s->ms_irq_enabled)
1148 uart_handle_cts_change(&s->port,
1149 stat & AUART_STAT_CTS);
1150 mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);
1151 istat &= ~AUART_INTR_CTSMIS;
1154 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
1155 if (!auart_dma_enabled(s))
1156 mxs_auart_rx_chars(s);
1157 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
1160 if (istat & AUART_INTR_TXIS) {
1161 mxs_auart_tx_chars(s);
1162 istat &= ~AUART_INTR_TXIS;
1168 static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
1173 mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1175 for (i = 0; i < 10000; i++) {
1176 reg = mxs_read(s, REG_CTRL0);
1177 if (!(reg & AUART_CTRL0_SFTRST))
1181 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1184 static void mxs_auart_reset_assert(struct mxs_auart_port *s)
1189 reg = mxs_read(s, REG_CTRL0);
1190 /* if already in reset state, keep it untouched */
1191 if (reg & AUART_CTRL0_SFTRST)
1194 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1195 mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1197 for (i = 0; i < 1000; i++) {
1198 reg = mxs_read(s, REG_CTRL0);
1199 /* reset is finished when the clock is gated */
1200 if (reg & AUART_CTRL0_CLKGATE)
1205 dev_err(s->dev, "Failed to reset the unit.");
1208 static int mxs_auart_startup(struct uart_port *u)
1211 struct mxs_auart_port *s = to_auart_port(u);
1213 ret = clk_prepare_enable(s->clk);
1217 if (uart_console(u)) {
1218 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1220 /* reset the unit to a well known state */
1221 mxs_auart_reset_assert(s);
1222 mxs_auart_reset_deassert(s);
1225 mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1227 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
1230 /* Reset FIFO size (it could have changed if DMA was enabled) */
1231 u->fifosize = MXS_AUART_FIFO_SIZE;
1234 * Enable fifo so all four bytes of a DMA word are written to
1235 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
1237 mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);
1239 /* get initial status of modem lines */
1240 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
1242 s->ms_irq_enabled = false;
1246 static void mxs_auart_shutdown(struct uart_port *u)
1248 struct mxs_auart_port *s = to_auart_port(u);
1250 mxs_auart_disable_ms(u);
1252 if (auart_dma_enabled(s))
1253 mxs_auart_dma_exit(s);
1255 if (uart_console(u)) {
1256 mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1258 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
1259 AUART_INTR_CTSMIEN, s, REG_INTR);
1260 mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1262 mxs_auart_reset_assert(s);
1265 clk_disable_unprepare(s->clk);
1268 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
1270 struct mxs_auart_port *s = to_auart_port(u);
1272 if ((mxs_read(s, REG_STAT) &
1273 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
1274 return TIOCSER_TEMT;
1279 static void mxs_auart_start_tx(struct uart_port *u)
1281 struct mxs_auart_port *s = to_auart_port(u);
1283 /* enable transmitter */
1284 mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);
1286 mxs_auart_tx_chars(s);
1289 static void mxs_auart_stop_tx(struct uart_port *u)
1291 struct mxs_auart_port *s = to_auart_port(u);
1293 mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);
1296 static void mxs_auart_stop_rx(struct uart_port *u)
1298 struct mxs_auart_port *s = to_auart_port(u);
1300 mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);
1303 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
1305 struct mxs_auart_port *s = to_auart_port(u);
1308 mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1310 mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1313 static const struct uart_ops mxs_auart_ops = {
1314 .tx_empty = mxs_auart_tx_empty,
1315 .start_tx = mxs_auart_start_tx,
1316 .stop_tx = mxs_auart_stop_tx,
1317 .stop_rx = mxs_auart_stop_rx,
1318 .enable_ms = mxs_auart_enable_ms,
1319 .break_ctl = mxs_auart_break_ctl,
1320 .set_mctrl = mxs_auart_set_mctrl,
1321 .get_mctrl = mxs_auart_get_mctrl,
1322 .startup = mxs_auart_startup,
1323 .shutdown = mxs_auart_shutdown,
1324 .set_termios = mxs_auart_settermios,
1325 .set_ldisc = mxs_auart_set_ldisc,
1326 .type = mxs_auart_type,
1327 .release_port = mxs_auart_release_port,
1328 .request_port = mxs_auart_request_port,
1329 .config_port = mxs_auart_config_port,
1330 .verify_port = mxs_auart_verify_port,
1333 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
1335 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1336 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
1338 struct mxs_auart_port *s = to_auart_port(port);
1339 unsigned int to = 1000;
1341 while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {
1347 mxs_write(ch, s, REG_DATA);
1351 auart_console_write(struct console *co, const char *str, unsigned int count)
1353 struct mxs_auart_port *s;
1354 struct uart_port *port;
1355 unsigned int old_ctrl0, old_ctrl2;
1356 unsigned int to = 20000;
1358 if (co->index >= MXS_AUART_PORTS || co->index < 0)
1361 s = auart_port[co->index];
1366 /* First save the CR then disable the interrupts */
1367 old_ctrl2 = mxs_read(s, REG_CTRL2);
1368 old_ctrl0 = mxs_read(s, REG_CTRL0);
1370 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1371 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);
1373 uart_console_write(port, str, count, mxs_auart_console_putchar);
1375 /* Finally, wait for transmitter to become empty ... */
1376 while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {
1383 * ... and restore the TCR if we waited long enough for the transmitter
1384 * to be idle. This might keep the transmitter enabled although it is
1385 * unused, but that is better than to disable it while it is still
1388 if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {
1389 mxs_write(old_ctrl0, s, REG_CTRL0);
1390 mxs_write(old_ctrl2, s, REG_CTRL2);
1393 clk_disable(s->clk);
1397 auart_console_get_options(struct mxs_auart_port *s, int *baud,
1398 int *parity, int *bits)
1400 struct uart_port *port = &s->port;
1401 unsigned int lcr_h, quot;
1403 if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))
1406 lcr_h = mxs_read(s, REG_LINECTRL);
1409 if (lcr_h & AUART_LINECTRL_PEN) {
1410 if (lcr_h & AUART_LINECTRL_EPS)
1416 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
1421 quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
1422 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1423 quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1424 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1428 *baud = (port->uartclk << 2) / quot;
1432 auart_console_setup(struct console *co, char *options)
1434 struct mxs_auart_port *s;
1442 * Check whether an invalid uart number has been specified, and
1443 * if so, search for the first available port that does have
1446 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1448 s = auart_port[co->index];
1452 ret = clk_prepare_enable(s->clk);
1457 uart_parse_options(options, &baud, &parity, &bits, &flow);
1459 auart_console_get_options(s, &baud, &parity, &bits);
1461 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1463 clk_disable_unprepare(s->clk);
1468 static struct console auart_console = {
1470 .write = auart_console_write,
1471 .device = uart_console_device,
1472 .setup = auart_console_setup,
1473 .flags = CON_PRINTBUFFER,
1475 .data = &auart_driver,
1479 static struct uart_driver auart_driver = {
1480 .owner = THIS_MODULE,
1481 .driver_name = "ttyAPP",
1482 .dev_name = "ttyAPP",
1485 .nr = MXS_AUART_PORTS,
1486 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1487 .cons = &auart_console,
1491 static void mxs_init_regs(struct mxs_auart_port *s)
1493 if (is_asm9260_auart(s))
1494 s->vendor = &vendor_alphascale_asm9260;
1496 s->vendor = &vendor_freescale_stmp37xx;
1499 static int mxs_get_clks(struct mxs_auart_port *s,
1500 struct platform_device *pdev)
1504 if (!is_asm9260_auart(s)) {
1505 s->clk = devm_clk_get(&pdev->dev, NULL);
1506 return PTR_ERR_OR_ZERO(s->clk);
1509 s->clk = devm_clk_get(s->dev, "mod");
1510 if (IS_ERR(s->clk)) {
1511 dev_err(s->dev, "Failed to get \"mod\" clk\n");
1512 return PTR_ERR(s->clk);
1515 s->clk_ahb = devm_clk_get(s->dev, "ahb");
1516 if (IS_ERR(s->clk_ahb)) {
1517 dev_err(s->dev, "Failed to get \"ahb\" clk\n");
1518 return PTR_ERR(s->clk_ahb);
1521 err = clk_prepare_enable(s->clk_ahb);
1523 dev_err(s->dev, "Failed to enable ahb_clk!\n");
1527 err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
1529 dev_err(s->dev, "Failed to set rate!\n");
1530 goto disable_clk_ahb;
1533 err = clk_prepare_enable(s->clk);
1535 dev_err(s->dev, "Failed to enable clk!\n");
1536 goto disable_clk_ahb;
1542 clk_disable_unprepare(s->clk_ahb);
1547 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1548 * could successfully get all information from dt or a negative errno.
1550 static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1551 struct platform_device *pdev)
1553 struct device_node *np = pdev->dev.of_node;
1557 /* no device tree device */
1560 ret = of_alias_get_id(np, "serial");
1562 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1567 if (of_get_property(np, "uart-has-rtscts", NULL) ||
1568 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
1569 set_bit(MXS_AUART_RTSCTS, &s->flags);
1574 static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1576 enum mctrl_gpio_idx i;
1577 struct gpio_desc *gpiod;
1579 s->gpios = mctrl_gpio_init_noauto(dev, 0);
1580 if (IS_ERR(s->gpios))
1581 return PTR_ERR(s->gpios);
1583 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1584 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1585 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1587 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1588 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1591 for (i = 0; i < UART_GPIO_MAX; i++) {
1592 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1593 if (gpiod && (gpiod_get_direction(gpiod) == 1))
1594 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1596 s->gpio_irq[i] = -EINVAL;
1602 static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1604 enum mctrl_gpio_idx i;
1606 for (i = 0; i < UART_GPIO_MAX; i++)
1607 if (s->gpio_irq[i] >= 0)
1608 free_irq(s->gpio_irq[i], s);
1611 static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1613 int *irq = s->gpio_irq;
1614 enum mctrl_gpio_idx i;
1617 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1621 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1622 err = request_irq(irq[i], mxs_auart_irq_handle,
1623 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1625 dev_err(s->dev, "%s - Can't get %d irq\n",
1630 * If something went wrong, rollback.
1631 * Be careful: i may be unsigned.
1633 while (err && (i-- > 0))
1635 free_irq(irq[i], s);
1640 static int mxs_auart_probe(struct platform_device *pdev)
1642 const struct of_device_id *of_id =
1643 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1644 struct mxs_auart_port *s;
1649 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
1653 s->port.dev = &pdev->dev;
1654 s->dev = &pdev->dev;
1656 ret = serial_mxs_probe_dt(s, pdev);
1658 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1661 if (s->port.line >= ARRAY_SIZE(auart_port)) {
1662 dev_err(&pdev->dev, "serial%d out of range\n", s->port.line);
1667 pdev->id_entry = of_id->data;
1668 s->devtype = pdev->id_entry->driver_data;
1671 ret = mxs_get_clks(s, pdev);
1675 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1678 goto out_disable_clks;
1681 s->port.mapbase = r->start;
1682 s->port.membase = ioremap(r->start, resource_size(r));
1683 if (!s->port.membase) {
1685 goto out_disable_clks;
1687 s->port.ops = &mxs_auart_ops;
1688 s->port.iotype = UPIO_MEM;
1689 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1690 s->port.uartclk = clk_get_rate(s->clk);
1691 s->port.type = PORT_IMX;
1692 s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_MXS_AUART_CONSOLE);
1698 irq = platform_get_irq(pdev, 0);
1705 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
1706 dev_name(&pdev->dev), s);
1710 platform_set_drvdata(pdev, s);
1712 ret = mxs_auart_init_gpios(s, &pdev->dev);
1714 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1719 * Get the GPIO lines IRQ
1721 ret = mxs_auart_request_gpio_irq(s);
1725 auart_port[s->port.line] = s;
1727 mxs_auart_reset_deassert(s);
1729 ret = uart_add_one_port(&auart_driver, &s->port);
1731 goto out_free_qpio_irq;
1733 /* ASM9260 don't have version reg */
1734 if (is_asm9260_auart(s)) {
1735 dev_info(&pdev->dev, "Found APPUART ASM9260\n");
1737 version = mxs_read(s, REG_VERSION);
1738 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1739 (version >> 24) & 0xff,
1740 (version >> 16) & 0xff, version & 0xffff);
1746 mxs_auart_free_gpio_irq(s);
1747 auart_port[pdev->id] = NULL;
1750 iounmap(s->port.membase);
1753 if (is_asm9260_auart(s)) {
1754 clk_disable_unprepare(s->clk);
1755 clk_disable_unprepare(s->clk_ahb);
1760 static int mxs_auart_remove(struct platform_device *pdev)
1762 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1764 uart_remove_one_port(&auart_driver, &s->port);
1765 auart_port[pdev->id] = NULL;
1766 mxs_auart_free_gpio_irq(s);
1767 iounmap(s->port.membase);
1768 if (is_asm9260_auart(s)) {
1769 clk_disable_unprepare(s->clk);
1770 clk_disable_unprepare(s->clk_ahb);
1776 static struct platform_driver mxs_auart_driver = {
1777 .probe = mxs_auart_probe,
1778 .remove = mxs_auart_remove,
1780 .name = "mxs-auart",
1781 .of_match_table = mxs_auart_dt_ids,
1785 static int __init mxs_auart_init(void)
1789 r = uart_register_driver(&auart_driver);
1793 r = platform_driver_register(&mxs_auart_driver);
1799 uart_unregister_driver(&auart_driver);
1804 static void __exit mxs_auart_exit(void)
1806 platform_driver_unregister(&mxs_auart_driver);
1807 uart_unregister_driver(&auart_driver);
1810 module_init(mxs_auart_init);
1811 module_exit(mxs_auart_exit);
1812 MODULE_LICENSE("GPL");
1813 MODULE_DESCRIPTION("Freescale MXS application uart driver");
1814 MODULE_ALIAS("platform:mxs-auart");