drivers/tty/serial/msm_serial.c

   1 /*
   2  * Driver for msm7k serial device and console
   3  *
   4  * Copyright (C) 2007 Google, Inc.
   5  * Author: Robert Love <rlove@google.com>
   6  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  19 # define SUPPORT_SYSRQ
  20 #endif
  21
  22 #include <linux/kernel.h>
  23 #include <linux/atomic.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/module.h>
  27 #include <linux/io.h>
  28 #include <linux/ioport.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/init.h>
  31 #include <linux/console.h>
  32 #include <linux/tty.h>
  33 #include <linux/tty_flip.h>
  34 #include <linux/serial_core.h>
  35 #include <linux/slab.h>
  36 #include <linux/clk.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/delay.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41 #include <linux/wait.h>
  42
  43 #define UART_MR1                        0x0000
  44
  45 #define UART_MR1_AUTO_RFR_LEVEL0        0x3F
  46 #define UART_MR1_AUTO_RFR_LEVEL1        0x3FF00
  47 #define UART_DM_MR1_AUTO_RFR_LEVEL1     0xFFFFFF00
  48 #define UART_MR1_RX_RDY_CTL             BIT(7)
  49 #define UART_MR1_CTS_CTL                BIT(6)
  50
  51 #define UART_MR2                        0x0004
  52 #define UART_MR2_ERROR_MODE             BIT(6)
  53 #define UART_MR2_BITS_PER_CHAR          0x30
  54 #define UART_MR2_BITS_PER_CHAR_5        (0x0 << 4)
  55 #define UART_MR2_BITS_PER_CHAR_6        (0x1 << 4)
  56 #define UART_MR2_BITS_PER_CHAR_7        (0x2 << 4)
  57 #define UART_MR2_BITS_PER_CHAR_8        (0x3 << 4)
  58 #define UART_MR2_STOP_BIT_LEN_ONE       (0x1 << 2)
  59 #define UART_MR2_STOP_BIT_LEN_TWO       (0x3 << 2)
  60 #define UART_MR2_PARITY_MODE_NONE       0x0
  61 #define UART_MR2_PARITY_MODE_ODD        0x1
  62 #define UART_MR2_PARITY_MODE_EVEN       0x2
  63 #define UART_MR2_PARITY_MODE_SPACE      0x3
  64 #define UART_MR2_PARITY_MODE            0x3
  65
  66 #define UART_CSR                        0x0008
  67
  68 #define UART_TF                         0x000C
  69 #define UARTDM_TF                       0x0070
  70
  71 #define UART_CR                         0x0010
  72 #define UART_CR_CMD_NULL                (0 << 4)
  73 #define UART_CR_CMD_RESET_RX            (1 << 4)
  74 #define UART_CR_CMD_RESET_TX            (2 << 4)
  75 #define UART_CR_CMD_RESET_ERR           (3 << 4)
  76 #define UART_CR_CMD_RESET_BREAK_INT     (4 << 4)
  77 #define UART_CR_CMD_START_BREAK         (5 << 4)
  78 #define UART_CR_CMD_STOP_BREAK          (6 << 4)
  79 #define UART_CR_CMD_RESET_CTS           (7 << 4)
  80 #define UART_CR_CMD_RESET_STALE_INT     (8 << 4)
  81 #define UART_CR_CMD_PACKET_MODE         (9 << 4)
  82 #define UART_CR_CMD_MODE_RESET          (12 << 4)
  83 #define UART_CR_CMD_SET_RFR             (13 << 4)
  84 #define UART_CR_CMD_RESET_RFR           (14 << 4)
  85 #define UART_CR_CMD_PROTECTION_EN       (16 << 4)
  86 #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
  87 #define UART_CR_CMD_STALE_EVENT_ENABLE  (80 << 4)
  88 #define UART_CR_CMD_FORCE_STALE         (4 << 8)
  89 #define UART_CR_CMD_RESET_TX_READY      (3 << 8)
  90 #define UART_CR_TX_DISABLE              BIT(3)
  91 #define UART_CR_TX_ENABLE               BIT(2)
  92 #define UART_CR_RX_DISABLE              BIT(1)
  93 #define UART_CR_RX_ENABLE               BIT(0)
  94 #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
  95
  96 #define UART_IMR                        0x0014
  97 #define UART_IMR_TXLEV                  BIT(0)
  98 #define UART_IMR_RXSTALE                BIT(3)
  99 #define UART_IMR_RXLEV                  BIT(4)
 100 #define UART_IMR_DELTA_CTS              BIT(5)
 101 #define UART_IMR_CURRENT_CTS            BIT(6)
 102 #define UART_IMR_RXBREAK_START          BIT(10)
 103
 104 #define UART_IPR_RXSTALE_LAST           0x20
 105 #define UART_IPR_STALE_LSB              0x1F
 106 #define UART_IPR_STALE_TIMEOUT_MSB      0x3FF80
 107 #define UART_DM_IPR_STALE_TIMEOUT_MSB   0xFFFFFF80
 108
 109 #define UART_IPR                        0x0018
 110 #define UART_TFWR                       0x001C
 111 #define UART_RFWR                       0x0020
 112 #define UART_HCR                        0x0024
 113
 114 #define UART_MREG                       0x0028
 115 #define UART_NREG                       0x002C
 116 #define UART_DREG                       0x0030
 117 #define UART_MNDREG                     0x0034
 118 #define UART_IRDA                       0x0038
 119 #define UART_MISR_MODE                  0x0040
 120 #define UART_MISR_RESET                 0x0044
 121 #define UART_MISR_EXPORT                0x0048
 122 #define UART_MISR_VAL                   0x004C
 123 #define UART_TEST_CTRL                  0x0050
 124
 125 #define UART_SR                         0x0008
 126 #define UART_SR_HUNT_CHAR               BIT(7)
 127 #define UART_SR_RX_BREAK                BIT(6)
 128 #define UART_SR_PAR_FRAME_ERR           BIT(5)
 129 #define UART_SR_OVERRUN                 BIT(4)
 130 #define UART_SR_TX_EMPTY                BIT(3)
 131 #define UART_SR_TX_READY                BIT(2)
 132 #define UART_SR_RX_FULL                 BIT(1)
 133 #define UART_SR_RX_READY                BIT(0)
 134
 135 #define UART_RF                         0x000C
 136 #define UARTDM_RF                       0x0070
 137 #define UART_MISR                       0x0010
 138 #define UART_ISR                        0x0014
 139 #define UART_ISR_TX_READY               BIT(7)
 140
 141 #define UARTDM_RXFS                     0x50
 142 #define UARTDM_RXFS_BUF_SHIFT           0x7
 143 #define UARTDM_RXFS_BUF_MASK            0x7
 144
 145 #define UARTDM_DMEN                     0x3C
 146 #define UARTDM_DMEN_RX_SC_ENABLE        BIT(5)
 147 #define UARTDM_DMEN_TX_SC_ENABLE        BIT(4)
 148
 149 #define UARTDM_DMEN_TX_BAM_ENABLE       BIT(2)  /* UARTDM_1P4 */
 150 #define UARTDM_DMEN_TX_DM_ENABLE        BIT(0)  /* < UARTDM_1P4 */
 151
 152 #define UARTDM_DMEN_RX_BAM_ENABLE       BIT(3)  /* UARTDM_1P4 */
 153 #define UARTDM_DMEN_RX_DM_ENABLE        BIT(1)  /* < UARTDM_1P4 */
 154
 155 #define UARTDM_DMRX                     0x34
 156 #define UARTDM_NCF_TX                   0x40
 157 #define UARTDM_RX_TOTAL_SNAP            0x38
 158
 159 #define UARTDM_BURST_SIZE               16   /* in bytes */
 160 #define UARTDM_TX_AIGN(x)               ((x) & ~0x3) /* valid for > 1p3 */
 161 #define UARTDM_TX_MAX                   256   /* in bytes, valid for <= 1p3 */
 162 #define UARTDM_RX_SIZE                  (UART_XMIT_SIZE / 4)
 163
 164 enum {
 165         UARTDM_1P1 = 1,
 166         UARTDM_1P2,
 167         UARTDM_1P3,
 168         UARTDM_1P4,
 169 };
 170
 171 struct msm_dma {
 172         struct dma_chan         *chan;
 173         enum dma_data_direction dir;
 174         dma_addr_t              phys;
 175         unsigned char           *virt;
 176         dma_cookie_t            cookie;
 177         u32                     enable_bit;
 178         unsigned int            count;
 179         struct dma_async_tx_descriptor  *desc;
 180 };
 181
 182 struct msm_port {
 183         struct uart_port        uart;
 184         char                    name[16];
 185         struct clk              *clk;
 186         struct clk              *pclk;
 187         unsigned int            imr;
 188         int                     is_uartdm;
 189         unsigned int            old_snap_state;
 190         bool                    break_detected;
 191         struct msm_dma          tx_dma;
 192         struct msm_dma          rx_dma;
 193 };
 194
 195 #define UART_TO_MSM(uart_port)  container_of(uart_port, struct msm_port, uart)
 196
 197 static
 198 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
 199 {
 200         writel_relaxed(val, port->membase + off);
 201 }
 202
 203 static
 204 unsigned int msm_read(struct uart_port *port, unsigned int off)
 205 {
 206         return readl_relaxed(port->membase + off);
 207 }
 208
 209 /*
 210  * Setup the MND registers to use the TCXO clock.
 211  */
 212 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
 213 {
 214         msm_write(port, 0x06, UART_MREG);
 215         msm_write(port, 0xF1, UART_NREG);
 216         msm_write(port, 0x0F, UART_DREG);
 217         msm_write(port, 0x1A, UART_MNDREG);
 218         port->uartclk = 1843200;
 219 }
 220
 221 /*
 222  * Setup the MND registers to use the TCXO clock divided by 4.
 223  */
 224 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
 225 {
 226         msm_write(port, 0x18, UART_MREG);
 227         msm_write(port, 0xF6, UART_NREG);
 228         msm_write(port, 0x0F, UART_DREG);
 229         msm_write(port, 0x0A, UART_MNDREG);
 230         port->uartclk = 1843200;
 231 }
 232
 233 static void msm_serial_set_mnd_regs(struct uart_port *port)
 234 {
 235         struct msm_port *msm_port = UART_TO_MSM(port);
 236
 237         /*
 238          * These registers don't exist so we change the clk input rate
 239          * on uartdm hardware instead
 240          */
 241         if (msm_port->is_uartdm)
 242                 return;
 243
 244         if (port->uartclk == 19200000)
 245                 msm_serial_set_mnd_regs_tcxo(port);
 246         else if (port->uartclk == 4800000)
 247                 msm_serial_set_mnd_regs_tcxoby4(port);
 248 }
 249
 250 static void msm_handle_tx(struct uart_port *port);
 251 static void msm_start_rx_dma(struct msm_port *msm_port);
 252
 253 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
 254 {
 255         struct device *dev = port->dev;
 256         unsigned int mapped;
 257         u32 val;
 258
 259         mapped = dma->count;
 260         dma->count = 0;
 261
 262         dmaengine_terminate_all(dma->chan);
 263
 264         /*
 265          * DMA Stall happens if enqueue and flush command happens concurrently.
 266          * For example before changing the baud rate/protocol configuration and
 267          * sending flush command to ADM, disable the channel of UARTDM.
 268          * Note: should not reset the receiver here immediately as it is not
 269          * suggested to do disable/reset or reset/disable at the same time.
 270          */
 271         val = msm_read(port, UARTDM_DMEN);
 272         val &= ~dma->enable_bit;
 273         msm_write(port, val, UARTDM_DMEN);
 274
 275         if (mapped)
 276                 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
 277 }
 278
 279 static void msm_release_dma(struct msm_port *msm_port)
 280 {
 281         struct msm_dma *dma;
 282
 283         dma = &msm_port->tx_dma;
 284         if (dma->chan) {
 285                 msm_stop_dma(&msm_port->uart, dma);
 286                 dma_release_channel(dma->chan);
 287         }
 288
 289         memset(dma, 0, sizeof(*dma));
 290
 291         dma = &msm_port->rx_dma;
 292         if (dma->chan) {
 293                 msm_stop_dma(&msm_port->uart, dma);
 294                 dma_release_channel(dma->chan);
 295                 kfree(dma->virt);
 296         }
 297
 298         memset(dma, 0, sizeof(*dma));
 299 }
 300
 301 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
 302 {
 303         struct device *dev = msm_port->uart.dev;
 304         struct dma_slave_config conf;
 305         struct msm_dma *dma;
 306         u32 crci = 0;
 307         int ret;
 308
 309         dma = &msm_port->tx_dma;
 310
 311         /* allocate DMA resources, if available */
 312         dma->chan = dma_request_slave_channel_reason(dev, "tx");
 313         if (IS_ERR(dma->chan))
 314                 goto no_tx;
 315
 316         of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
 317
 318         memset(&conf, 0, sizeof(conf));
 319         conf.direction = DMA_MEM_TO_DEV;
 320         conf.device_fc = true;
 321         conf.dst_addr = base + UARTDM_TF;
 322         conf.dst_maxburst = UARTDM_BURST_SIZE;
 323         conf.slave_id = crci;
 324
 325         ret = dmaengine_slave_config(dma->chan, &conf);
 326         if (ret)
 327                 goto rel_tx;
 328
 329         dma->dir = DMA_TO_DEVICE;
 330
 331         if (msm_port->is_uartdm < UARTDM_1P4)
 332                 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
 333         else
 334                 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
 335
 336         return;
 337
 338 rel_tx:
 339         dma_release_channel(dma->chan);
 340 no_tx:
 341         memset(dma, 0, sizeof(*dma));
 342 }
 343
 344 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
 345 {
 346         struct device *dev = msm_port->uart.dev;
 347         struct dma_slave_config conf;
 348         struct msm_dma *dma;
 349         u32 crci = 0;
 350         int ret;
 351
 352         dma = &msm_port->rx_dma;
 353
 354         /* allocate DMA resources, if available */
 355         dma->chan = dma_request_slave_channel_reason(dev, "rx");
 356         if (IS_ERR(dma->chan))
 357                 goto no_rx;
 358
 359         of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
 360
 361         dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
 362         if (!dma->virt)
 363                 goto rel_rx;
 364
 365         memset(&conf, 0, sizeof(conf));
 366         conf.direction = DMA_DEV_TO_MEM;
 367         conf.device_fc = true;
 368         conf.src_addr = base + UARTDM_RF;
 369         conf.src_maxburst = UARTDM_BURST_SIZE;
 370         conf.slave_id = crci;
 371
 372         ret = dmaengine_slave_config(dma->chan, &conf);
 373         if (ret)
 374                 goto err;
 375
 376         dma->dir = DMA_FROM_DEVICE;
 377
 378         if (msm_port->is_uartdm < UARTDM_1P4)
 379                 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
 380         else
 381                 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
 382
 383         return;
 384 err:
 385         kfree(dma->virt);
 386 rel_rx:
 387         dma_release_channel(dma->chan);
 388 no_rx:
 389         memset(dma, 0, sizeof(*dma));
 390 }
 391
 392 static inline void msm_wait_for_xmitr(struct uart_port *port)
 393 {
 394         unsigned int timeout = 500000;
 395
 396         while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
 397                 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
 398                         break;
 399                 udelay(1);
 400                 if (!timeout--)
 401                         break;
 402         }
 403         msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
 404 }
 405
 406 static void msm_stop_tx(struct uart_port *port)
 407 {
 408         struct msm_port *msm_port = UART_TO_MSM(port);
 409
 410         msm_port->imr &= ~UART_IMR_TXLEV;
 411         msm_write(port, msm_port->imr, UART_IMR);
 412 }
 413
 414 static void msm_start_tx(struct uart_port *port)
 415 {
 416         struct msm_port *msm_port = UART_TO_MSM(port);
 417         struct msm_dma *dma = &msm_port->tx_dma;
 418
 419         /* Already started in DMA mode */
 420         if (dma->count)
 421                 return;
 422
 423         msm_port->imr |= UART_IMR_TXLEV;
 424         msm_write(port, msm_port->imr, UART_IMR);
 425 }
 426
 427 static void msm_reset_dm_count(struct uart_port *port, int count)
 428 {
 429         msm_wait_for_xmitr(port);
 430         msm_write(port, count, UARTDM_NCF_TX);
 431         msm_read(port, UARTDM_NCF_TX);
 432 }
 433
 434 static void msm_complete_tx_dma(void *args)
 435 {
 436         struct msm_port *msm_port = args;
 437         struct uart_port *port = &msm_port->uart;
 438         struct circ_buf *xmit = &port->state->xmit;
 439         struct msm_dma *dma = &msm_port->tx_dma;
 440         struct dma_tx_state state;
 441         enum dma_status status;
 442         unsigned long flags;
 443         unsigned int count;
 444         u32 val;
 445
 446         spin_lock_irqsave(&port->lock, flags);
 447
 448         /* Already stopped */
 449         if (!dma->count)
 450                 goto done;
 451
 452         status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
 453
 454         dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
 455
 456         val = msm_read(port, UARTDM_DMEN);
 457         val &= ~dma->enable_bit;
 458         msm_write(port, val, UARTDM_DMEN);
 459
 460         if (msm_port->is_uartdm > UARTDM_1P3) {
 461                 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
 462                 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
 463         }
 464
 465         count = dma->count - state.residue;
 466         port->icount.tx += count;
 467         dma->count = 0;
 468
 469         xmit->tail += count;
 470         xmit->tail &= UART_XMIT_SIZE - 1;
 471
 472         /* Restore "Tx FIFO below watermark" interrupt */
 473         msm_port->imr |= UART_IMR_TXLEV;
 474         msm_write(port, msm_port->imr, UART_IMR);
 475
 476         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 477                 uart_write_wakeup(port);
 478
 479         msm_handle_tx(port);
 480 done:
 481         spin_unlock_irqrestore(&port->lock, flags);
 482 }
 483
 484 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
 485 {
 486         struct circ_buf *xmit = &msm_port->uart.state->xmit;
 487         struct uart_port *port = &msm_port->uart;
 488         struct msm_dma *dma = &msm_port->tx_dma;
 489         void *cpu_addr;
 490         int ret;
 491         u32 val;
 492
 493         cpu_addr = &xmit->buf[xmit->tail];
 494
 495         dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
 496         ret = dma_mapping_error(port->dev, dma->phys);
 497         if (ret)
 498                 return ret;
 499
 500         dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
 501                                                 count, DMA_MEM_TO_DEV,
 502                                                 DMA_PREP_INTERRUPT |
 503                                                 DMA_PREP_FENCE);
 504         if (!dma->desc) {
 505                 ret = -EIO;
 506                 goto unmap;
 507         }
 508
 509         dma->desc->callback = msm_complete_tx_dma;
 510         dma->desc->callback_param = msm_port;
 511
 512         dma->cookie = dmaengine_submit(dma->desc);
 513         ret = dma_submit_error(dma->cookie);
 514         if (ret)
 515                 goto unmap;
 516
 517         /*
 518          * Using DMA complete for Tx FIFO reload, no need for
 519          * "Tx FIFO below watermark" one, disable it
 520          */
 521         msm_port->imr &= ~UART_IMR_TXLEV;
 522         msm_write(port, msm_port->imr, UART_IMR);
 523
 524         dma->count = count;
 525
 526         val = msm_read(port, UARTDM_DMEN);
 527         val |= dma->enable_bit;
 528
 529         if (msm_port->is_uartdm < UARTDM_1P4)
 530                 msm_write(port, val, UARTDM_DMEN);
 531
 532         msm_reset_dm_count(port, count);
 533
 534         if (msm_port->is_uartdm > UARTDM_1P3)
 535                 msm_write(port, val, UARTDM_DMEN);
 536
 537         dma_async_issue_pending(dma->chan);
 538         return 0;
 539 unmap:
 540         dma_unmap_single(port->dev, dma->phys, count, dma->dir);
 541         return ret;
 542 }
 543
 544 static void msm_complete_rx_dma(void *args)
 545 {
 546         struct msm_port *msm_port = args;
 547         struct uart_port *port = &msm_port->uart;
 548         struct tty_port *tport = &port->state->port;
 549         struct msm_dma *dma = &msm_port->rx_dma;
 550         int count = 0, i, sysrq;
 551         unsigned long flags;
 552         u32 val;
 553
 554         spin_lock_irqsave(&port->lock, flags);
 555
 556         /* Already stopped */
 557         if (!dma->count)
 558                 goto done;
 559
 560         val = msm_read(port, UARTDM_DMEN);
 561         val &= ~dma->enable_bit;
 562         msm_write(port, val, UARTDM_DMEN);
 563
 564         if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
 565                 port->icount.overrun++;
 566                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 567                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 568         }
 569
 570         count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
 571
 572         port->icount.rx += count;
 573
 574         dma->count = 0;
 575
 576         dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
 577
 578         for (i = 0; i < count; i++) {
 579                 char flag = TTY_NORMAL;
 580
 581                 if (msm_port->break_detected && dma->virt[i] == 0) {
 582                         port->icount.brk++;
 583                         flag = TTY_BREAK;
 584                         msm_port->break_detected = false;
 585                         if (uart_handle_break(port))
 586                                 continue;
 587                 }
 588
 589                 if (!(port->read_status_mask & UART_SR_RX_BREAK))
 590                         flag = TTY_NORMAL;
 591
 592                 spin_unlock_irqrestore(&port->lock, flags);
 593                 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
 594                 spin_lock_irqsave(&port->lock, flags);
 595                 if (!sysrq)
 596                         tty_insert_flip_char(tport, dma->virt[i], flag);
 597         }
 598
 599         msm_start_rx_dma(msm_port);
 600 done:
 601         spin_unlock_irqrestore(&port->lock, flags);
 602
 603         if (count)
 604                 tty_flip_buffer_push(tport);
 605 }
 606
 607 static void msm_start_rx_dma(struct msm_port *msm_port)
 608 {
 609         struct msm_dma *dma = &msm_port->rx_dma;
 610         struct uart_port *uart = &msm_port->uart;
 611         u32 val;
 612         int ret;
 613
 614         if (!dma->chan)
 615                 return;
 616
 617         dma->phys = dma_map_single(uart->dev, dma->virt,
 618                                    UARTDM_RX_SIZE, dma->dir);
 619         ret = dma_mapping_error(uart->dev, dma->phys);
 620         if (ret)
 621                 return;
 622
 623         dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
 624                                                 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
 625                                                 DMA_PREP_INTERRUPT);
 626         if (!dma->desc)
 627                 goto unmap;
 628
 629         dma->desc->callback = msm_complete_rx_dma;
 630         dma->desc->callback_param = msm_port;
 631
 632         dma->cookie = dmaengine_submit(dma->desc);
 633         ret = dma_submit_error(dma->cookie);
 634         if (ret)
 635                 goto unmap;
 636         /*
 637          * Using DMA for FIFO off-load, no need for "Rx FIFO over
 638          * watermark" or "stale" interrupts, disable them
 639          */
 640         msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
 641
 642         /*
 643          * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
 644          * we need RXSTALE to flush input DMA fifo to memory
 645          */
 646         if (msm_port->is_uartdm < UARTDM_1P4)
 647                 msm_port->imr |= UART_IMR_RXSTALE;
 648
 649         msm_write(uart, msm_port->imr, UART_IMR);
 650
 651         dma->count = UARTDM_RX_SIZE;
 652
 653         dma_async_issue_pending(dma->chan);
 654
 655         msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
 656         msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
 657
 658         val = msm_read(uart, UARTDM_DMEN);
 659         val |= dma->enable_bit;
 660
 661         if (msm_port->is_uartdm < UARTDM_1P4)
 662                 msm_write(uart, val, UARTDM_DMEN);
 663
 664         msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
 665
 666         if (msm_port->is_uartdm > UARTDM_1P3)
 667                 msm_write(uart, val, UARTDM_DMEN);
 668
 669         return;
 670 unmap:
 671         dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
 672 }
 673
 674 static void msm_stop_rx(struct uart_port *port)
 675 {
 676         struct msm_port *msm_port = UART_TO_MSM(port);
 677         struct msm_dma *dma = &msm_port->rx_dma;
 678
 679         msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
 680         msm_write(port, msm_port->imr, UART_IMR);
 681
 682         if (dma->chan)
 683                 msm_stop_dma(port, dma);
 684 }
 685
 686 static void msm_enable_ms(struct uart_port *port)
 687 {
 688         struct msm_port *msm_port = UART_TO_MSM(port);
 689
 690         msm_port->imr |= UART_IMR_DELTA_CTS;
 691         msm_write(port, msm_port->imr, UART_IMR);
 692 }
 693
 694 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
 695 {
 696         struct tty_port *tport = &port->state->port;
 697         unsigned int sr;
 698         int count = 0;
 699         struct msm_port *msm_port = UART_TO_MSM(port);
 700
 701         if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
 702                 port->icount.overrun++;
 703                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 704                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 705         }
 706
 707         if (misr & UART_IMR_RXSTALE) {
 708                 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
 709                         msm_port->old_snap_state;
 710                 msm_port->old_snap_state = 0;
 711         } else {
 712                 count = 4 * (msm_read(port, UART_RFWR));
 713                 msm_port->old_snap_state += count;
 714         }
 715
 716         /* TODO: Precise error reporting */
 717
 718         port->icount.rx += count;
 719
 720         while (count > 0) {
 721                 unsigned char buf[4];
 722                 int sysrq, r_count, i;
 723
 724                 sr = msm_read(port, UART_SR);
 725                 if ((sr & UART_SR_RX_READY) == 0) {
 726                         msm_port->old_snap_state -= count;
 727                         break;
 728                 }
 729
 730                 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
 731                 r_count = min_t(int, count, sizeof(buf));
 732
 733                 for (i = 0; i < r_count; i++) {
 734                         char flag = TTY_NORMAL;
 735
 736                         if (msm_port->break_detected && buf[i] == 0) {
 737                                 port->icount.brk++;
 738                                 flag = TTY_BREAK;
 739                                 msm_port->break_detected = false;
 740                                 if (uart_handle_break(port))
 741                                         continue;
 742                         }
 743
 744                         if (!(port->read_status_mask & UART_SR_RX_BREAK))
 745                                 flag = TTY_NORMAL;
 746
 747                         spin_unlock(&port->lock);
 748                         sysrq = uart_handle_sysrq_char(port, buf[i]);
 749                         spin_lock(&port->lock);
 750                         if (!sysrq)
 751                                 tty_insert_flip_char(tport, buf[i], flag);
 752                 }
 753                 count -= r_count;
 754         }
 755
 756         spin_unlock(&port->lock);
 757         tty_flip_buffer_push(tport);
 758         spin_lock(&port->lock);
 759
 760         if (misr & (UART_IMR_RXSTALE))
 761                 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
 762         msm_write(port, 0xFFFFFF, UARTDM_DMRX);
 763         msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
 764
 765         /* Try to use DMA */
 766         msm_start_rx_dma(msm_port);
 767 }
 768
 769 static void msm_handle_rx(struct uart_port *port)
 770 {
 771         struct tty_port *tport = &port->state->port;
 772         unsigned int sr;
 773
 774         /*
 775          * Handle overrun. My understanding of the hardware is that overrun
 776          * is not tied to the RX buffer, so we handle the case out of band.
 777          */
 778         if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
 779                 port->icount.overrun++;
 780                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 781                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 782         }
 783
 784         /* and now the main RX loop */
 785         while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
 786                 unsigned int c;
 787                 char flag = TTY_NORMAL;
 788                 int sysrq;
 789
 790                 c = msm_read(port, UART_RF);
 791
 792                 if (sr & UART_SR_RX_BREAK) {
 793                         port->icount.brk++;
 794                         if (uart_handle_break(port))
 795                                 continue;
 796                 } else if (sr & UART_SR_PAR_FRAME_ERR) {
 797                         port->icount.frame++;
 798                 } else {
 799                         port->icount.rx++;
 800                 }
 801
 802                 /* Mask conditions we're ignorning. */
 803                 sr &= port->read_status_mask;
 804
 805                 if (sr & UART_SR_RX_BREAK)
 806                         flag = TTY_BREAK;
 807                 else if (sr & UART_SR_PAR_FRAME_ERR)
 808                         flag = TTY_FRAME;
 809
 810                 spin_unlock(&port->lock);
 811                 sysrq = uart_handle_sysrq_char(port, c);
 812                 spin_lock(&port->lock);
 813                 if (!sysrq)
 814                         tty_insert_flip_char(tport, c, flag);
 815         }
 816
 817         spin_unlock(&port->lock);
 818         tty_flip_buffer_push(tport);
 819         spin_lock(&port->lock);
 820 }
 821
 822 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
 823 {
 824         struct circ_buf *xmit = &port->state->xmit;
 825         struct msm_port *msm_port = UART_TO_MSM(port);
 826         unsigned int num_chars;
 827         unsigned int tf_pointer = 0;
 828         void __iomem *tf;
 829
 830         if (msm_port->is_uartdm)
 831                 tf = port->membase + UARTDM_TF;
 832         else
 833                 tf = port->membase + UART_TF;
 834
 835         if (tx_count && msm_port->is_uartdm)
 836                 msm_reset_dm_count(port, tx_count);
 837
 838         while (tf_pointer < tx_count) {
 839                 int i;
 840                 char buf[4] = { 0 };
 841
 842                 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
 843                         break;
 844
 845                 if (msm_port->is_uartdm)
 846                         num_chars = min(tx_count - tf_pointer,
 847                                         (unsigned int)sizeof(buf));
 848                 else
 849                         num_chars = 1;
 850
 851                 for (i = 0; i < num_chars; i++) {
 852                         buf[i] = xmit->buf[xmit->tail + i];
 853                         port->icount.tx++;
 854                 }
 855
 856                 iowrite32_rep(tf, buf, 1);
 857                 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
 858                 tf_pointer += num_chars;
 859         }
 860
 861         /* disable tx interrupts if nothing more to send */
 862         if (uart_circ_empty(xmit))
 863                 msm_stop_tx(port);
 864
 865         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 866                 uart_write_wakeup(port);
 867 }
 868
 869 static void msm_handle_tx(struct uart_port *port)
 870 {
 871         struct msm_port *msm_port = UART_TO_MSM(port);
 872         struct circ_buf *xmit = &msm_port->uart.state->xmit;
 873         struct msm_dma *dma = &msm_port->tx_dma;
 874         unsigned int pio_count, dma_count, dma_min;
 875         char buf[4] = { 0 };
 876         void __iomem *tf;
 877         int err = 0;
 878
 879         if (port->x_char) {
 880                 if (msm_port->is_uartdm)
 881                         tf = port->membase + UARTDM_TF;
 882                 else
 883                         tf = port->membase + UART_TF;
 884
 885                 buf[0] = port->x_char;
 886
 887                 if (msm_port->is_uartdm)
 888                         msm_reset_dm_count(port, 1);
 889
 890                 iowrite32_rep(tf, buf, 1);
 891                 port->icount.tx++;
 892                 port->x_char = 0;
 893                 return;
 894         }
 895
 896         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 897                 msm_stop_tx(port);
 898                 return;
 899         }
 900
 901         pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 902         dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 903
 904         dma_min = 1;    /* Always DMA */
 905         if (msm_port->is_uartdm > UARTDM_1P3) {
 906                 dma_count = UARTDM_TX_AIGN(dma_count);
 907                 dma_min = UARTDM_BURST_SIZE;
 908         } else {
 909                 if (dma_count > UARTDM_TX_MAX)
 910                         dma_count = UARTDM_TX_MAX;
 911         }
 912
 913         if (pio_count > port->fifosize)
 914                 pio_count = port->fifosize;
 915
 916         if (!dma->chan || dma_count < dma_min)
 917                 msm_handle_tx_pio(port, pio_count);
 918         else
 919                 err = msm_handle_tx_dma(msm_port, dma_count);
 920
 921         if (err)        /* fall back to PIO mode */
 922                 msm_handle_tx_pio(port, pio_count);
 923 }
 924
 925 static void msm_handle_delta_cts(struct uart_port *port)
 926 {
 927         msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
 928         port->icount.cts++;
 929         wake_up_interruptible(&port->state->port.delta_msr_wait);
 930 }
 931
 932 static irqreturn_t msm_uart_irq(int irq, void *dev_id)
 933 {
 934         struct uart_port *port = dev_id;
 935         struct msm_port *msm_port = UART_TO_MSM(port);
 936         struct msm_dma *dma = &msm_port->rx_dma;
 937         unsigned long flags;
 938         unsigned int misr;
 939         u32 val;
 940
 941         spin_lock_irqsave(&port->lock, flags);
 942         misr = msm_read(port, UART_MISR);
 943         msm_write(port, 0, UART_IMR); /* disable interrupt */
 944
 945         if (misr & UART_IMR_RXBREAK_START) {
 946                 msm_port->break_detected = true;
 947                 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
 948         }
 949
 950         if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
 951                 if (dma->count) {
 952                         val = UART_CR_CMD_STALE_EVENT_DISABLE;
 953                         msm_write(port, val, UART_CR);
 954                         val = UART_CR_CMD_RESET_STALE_INT;
 955                         msm_write(port, val, UART_CR);
 956                         /*
 957                          * Flush DMA input fifo to memory, this will also
 958                          * trigger DMA RX completion
 959                          */
 960                         dmaengine_terminate_all(dma->chan);
 961                 } else if (msm_port->is_uartdm) {
 962                         msm_handle_rx_dm(port, misr);
 963                 } else {
 964                         msm_handle_rx(port);
 965                 }
 966         }
 967         if (misr & UART_IMR_TXLEV)
 968                 msm_handle_tx(port);
 969         if (misr & UART_IMR_DELTA_CTS)
 970                 msm_handle_delta_cts(port);
 971
 972         msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
 973         spin_unlock_irqrestore(&port->lock, flags);
 974
 975         return IRQ_HANDLED;
 976 }
 977
 978 static unsigned int msm_tx_empty(struct uart_port *port)
 979 {
 980         return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
 981 }
 982
 983 static unsigned int msm_get_mctrl(struct uart_port *port)
 984 {
 985         return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
 986 }
 987
 988 static void msm_reset(struct uart_port *port)
 989 {
 990         struct msm_port *msm_port = UART_TO_MSM(port);
 991         unsigned int mr;
 992
 993         /* reset everything */
 994         msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
 995         msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
 996         msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 997         msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
 998         msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
 999         msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1000         mr = msm_read(port, UART_MR1);
1001         mr &= ~UART_MR1_RX_RDY_CTL;
1002         msm_write(port, mr, UART_MR1);
1003
1004         /* Disable DM modes */
1005         if (msm_port->is_uartdm)
1006                 msm_write(port, 0, UARTDM_DMEN);
1007 }
1008
1009 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
1010 {
1011         unsigned int mr;
1012
1013         mr = msm_read(port, UART_MR1);
1014
1015         if (!(mctrl & TIOCM_RTS)) {
1016                 mr &= ~UART_MR1_RX_RDY_CTL;
1017                 msm_write(port, mr, UART_MR1);
1018                 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1019         } else {
1020                 mr |= UART_MR1_RX_RDY_CTL;
1021                 msm_write(port, mr, UART_MR1);
1022         }
1023 }
1024
1025 static void msm_break_ctl(struct uart_port *port, int break_ctl)
1026 {
1027         if (break_ctl)
1028                 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1029         else
1030                 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1031 }
1032
1033 struct msm_baud_map {
1034         u16     divisor;
1035         u8      code;
1036         u8      rxstale;
1037 };
1038
1039 static const struct msm_baud_map *
1040 msm_find_best_baud(struct uart_port *port, unsigned int baud,
1041                    unsigned long *rate)
1042 {
1043         struct msm_port *msm_port = UART_TO_MSM(port);
1044         unsigned int divisor, result;
1045         unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1046         const struct msm_baud_map *entry, *end, *best;
1047         static const struct msm_baud_map table[] = {
1048                 {    1, 0xff, 31 },
1049                 {    2, 0xee, 16 },
1050                 {    3, 0xdd,  8 },
1051                 {    4, 0xcc,  6 },
1052                 {    6, 0xbb,  6 },
1053                 {    8, 0xaa,  6 },
1054                 {   12, 0x99,  6 },
1055                 {   16, 0x88,  1 },
1056                 {   24, 0x77,  1 },
1057                 {   32, 0x66,  1 },
1058                 {   48, 0x55,  1 },
1059                 {   96, 0x44,  1 },
1060                 {  192, 0x33,  1 },
1061                 {  384, 0x22,  1 },
1062                 {  768, 0x11,  1 },
1063                 { 1536, 0x00,  1 },
1064         };
1065
1066         best = table; /* Default to smallest divider */
1067         target = clk_round_rate(msm_port->clk, 16 * baud);
1068         divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1069
1070         end = table + ARRAY_SIZE(table);
1071         entry = table;
1072         while (entry < end) {
1073                 if (entry->divisor <= divisor) {
1074                         result = target / entry->divisor / 16;
1075                         diff = abs(result - baud);
1076
1077                         /* Keep track of best entry */
1078                         if (diff < best_diff) {
1079                                 best_diff = diff;
1080                                 best = entry;
1081                                 best_rate = target;
1082                         }
1083
1084                         if (result == baud)
1085                                 break;
1086                 } else if (entry->divisor > divisor) {
1087                         old = target;
1088                         target = clk_round_rate(msm_port->clk, old + 1);
1089                         /*
1090                          * The rate didn't get any faster so we can't do
1091                          * better at dividing it down
1092                          */
1093                         if (target == old)
1094                                 break;
1095
1096                         /* Start the divisor search over at this new rate */
1097                         entry = table;
1098                         divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1099                         continue;
1100                 }
1101                 entry++;
1102         }
1103
1104         *rate = best_rate;
1105         return best;
1106 }
1107
1108 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1109                              unsigned long *saved_flags)
1110 {
1111         unsigned int rxstale, watermark, mask;
1112         struct msm_port *msm_port = UART_TO_MSM(port);
1113         const struct msm_baud_map *entry;
1114         unsigned long flags, rate;
1115
1116         flags = *saved_flags;
1117         spin_unlock_irqrestore(&port->lock, flags);
1118
1119         entry = msm_find_best_baud(port, baud, &rate);
1120         clk_set_rate(msm_port->clk, rate);
1121         baud = rate / 16 / entry->divisor;
1122
1123         spin_lock_irqsave(&port->lock, flags);
1124         *saved_flags = flags;
1125         port->uartclk = rate;
1126
1127         msm_write(port, entry->code, UART_CSR);
1128
1129         /* RX stale watermark */
1130         rxstale = entry->rxstale;
1131         watermark = UART_IPR_STALE_LSB & rxstale;
1132         if (msm_port->is_uartdm) {
1133                 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1134         } else {
1135                 watermark |= UART_IPR_RXSTALE_LAST;
1136                 mask = UART_IPR_STALE_TIMEOUT_MSB;
1137         }
1138
1139         watermark |= mask & (rxstale << 2);
1140
1141         msm_write(port, watermark, UART_IPR);
1142
1143         /* set RX watermark */
1144         watermark = (port->fifosize * 3) / 4;
1145         msm_write(port, watermark, UART_RFWR);
1146
1147         /* set TX watermark */
1148         msm_write(port, 10, UART_TFWR);
1149
1150         msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1151         msm_reset(port);
1152
1153         /* Enable RX and TX */
1154         msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1155
1156         /* turn on RX and CTS interrupts */
1157         msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1158                         UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1159
1160         msm_write(port, msm_port->imr, UART_IMR);
1161
1162         if (msm_port->is_uartdm) {
1163                 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1164                 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1165                 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1166         }
1167
1168         return baud;
1169 }
1170
1171 static void msm_init_clock(struct uart_port *port)
1172 {
1173         struct msm_port *msm_port = UART_TO_MSM(port);
1174
1175         clk_prepare_enable(msm_port->clk);
1176         clk_prepare_enable(msm_port->pclk);
1177         msm_serial_set_mnd_regs(port);
1178 }
1179
1180 static int msm_startup(struct uart_port *port)
1181 {
1182         struct msm_port *msm_port = UART_TO_MSM(port);
1183         unsigned int data, rfr_level, mask;
1184         int ret;
1185
1186         snprintf(msm_port->name, sizeof(msm_port->name),
1187                  "msm_serial%d", port->line);
1188
1189         msm_init_clock(port);
1190
1191         if (likely(port->fifosize > 12))
1192                 rfr_level = port->fifosize - 12;
1193         else
1194                 rfr_level = port->fifosize;
1195
1196         /* set automatic RFR level */
1197         data = msm_read(port, UART_MR1);
1198
1199         if (msm_port->is_uartdm)
1200                 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1201         else
1202                 mask = UART_MR1_AUTO_RFR_LEVEL1;
1203
1204         data &= ~mask;
1205         data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1206         data |= mask & (rfr_level << 2);
1207         data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1208         msm_write(port, data, UART_MR1);
1209
1210         if (msm_port->is_uartdm) {
1211                 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1212                 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1213         }
1214
1215         ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1216                           msm_port->name, port);
1217         if (unlikely(ret))
1218                 goto err_irq;
1219
1220         return 0;
1221
1222 err_irq:
1223         if (msm_port->is_uartdm)
1224                 msm_release_dma(msm_port);
1225
1226         clk_disable_unprepare(msm_port->pclk);
1227         clk_disable_unprepare(msm_port->clk);
1228
1229         return ret;
1230 }
1231
1232 static void msm_shutdown(struct uart_port *port)
1233 {
1234         struct msm_port *msm_port = UART_TO_MSM(port);
1235
1236         msm_port->imr = 0;
1237         msm_write(port, 0, UART_IMR); /* disable interrupts */
1238
1239         if (msm_port->is_uartdm)
1240                 msm_release_dma(msm_port);
1241
1242         clk_disable_unprepare(msm_port->clk);
1243
1244         free_irq(port->irq, port);
1245 }
1246
1247 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1248                             struct ktermios *old)
1249 {
1250         struct msm_port *msm_port = UART_TO_MSM(port);
1251         struct msm_dma *dma = &msm_port->rx_dma;
1252         unsigned long flags;
1253         unsigned int baud, mr;
1254
1255         spin_lock_irqsave(&port->lock, flags);
1256
1257         if (dma->chan) /* Terminate if any */
1258                 msm_stop_dma(port, dma);
1259
1260         /* calculate and set baud rate */
1261         baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1262         baud = msm_set_baud_rate(port, baud, &flags);
1263         if (tty_termios_baud_rate(termios))
1264                 tty_termios_encode_baud_rate(termios, baud, baud);
1265
1266         /* calculate parity */
1267         mr = msm_read(port, UART_MR2);
1268         mr &= ~UART_MR2_PARITY_MODE;
1269         if (termios->c_cflag & PARENB) {
1270                 if (termios->c_cflag & PARODD)
1271                         mr |= UART_MR2_PARITY_MODE_ODD;
1272                 else if (termios->c_cflag & CMSPAR)
1273                         mr |= UART_MR2_PARITY_MODE_SPACE;
1274                 else
1275                         mr |= UART_MR2_PARITY_MODE_EVEN;
1276         }
1277
1278         /* calculate bits per char */
1279         mr &= ~UART_MR2_BITS_PER_CHAR;
1280         switch (termios->c_cflag & CSIZE) {
1281         case CS5:
1282                 mr |= UART_MR2_BITS_PER_CHAR_5;
1283                 break;
1284         case CS6:
1285                 mr |= UART_MR2_BITS_PER_CHAR_6;
1286                 break;
1287         case CS7:
1288                 mr |= UART_MR2_BITS_PER_CHAR_7;
1289                 break;
1290         case CS8:
1291         default:
1292                 mr |= UART_MR2_BITS_PER_CHAR_8;
1293                 break;
1294         }
1295
1296         /* calculate stop bits */
1297         mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1298         if (termios->c_cflag & CSTOPB)
1299                 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1300         else
1301                 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1302
1303         /* set parity, bits per char, and stop bit */
1304         msm_write(port, mr, UART_MR2);
1305
1306         /* calculate and set hardware flow control */
1307         mr = msm_read(port, UART_MR1);
1308         mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1309         if (termios->c_cflag & CRTSCTS) {
1310                 mr |= UART_MR1_CTS_CTL;
1311                 mr |= UART_MR1_RX_RDY_CTL;
1312         }
1313         msm_write(port, mr, UART_MR1);
1314
1315         /* Configure status bits to ignore based on termio flags. */
1316         port->read_status_mask = 0;
1317         if (termios->c_iflag & INPCK)
1318                 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1319         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1320                 port->read_status_mask |= UART_SR_RX_BREAK;
1321
1322         uart_update_timeout(port, termios->c_cflag, baud);
1323
1324         /* Try to use DMA */
1325         msm_start_rx_dma(msm_port);
1326
1327         spin_unlock_irqrestore(&port->lock, flags);
1328 }
1329
1330 static const char *msm_type(struct uart_port *port)
1331 {
1332         return "MSM";
1333 }
1334
1335 static void msm_release_port(struct uart_port *port)
1336 {
1337         struct platform_device *pdev = to_platform_device(port->dev);
1338         struct resource *uart_resource;
1339         resource_size_t size;
1340
1341         uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1342         if (unlikely(!uart_resource))
1343                 return;
1344         size = resource_size(uart_resource);
1345
1346         release_mem_region(port->mapbase, size);
1347         iounmap(port->membase);
1348         port->membase = NULL;
1349 }
1350
1351 static int msm_request_port(struct uart_port *port)
1352 {
1353         struct platform_device *pdev = to_platform_device(port->dev);
1354         struct resource *uart_resource;
1355         resource_size_t size;
1356         int ret;
1357
1358         uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1359         if (unlikely(!uart_resource))
1360                 return -ENXIO;
1361
1362         size = resource_size(uart_resource);
1363
1364         if (!request_mem_region(port->mapbase, size, "msm_serial"))
1365                 return -EBUSY;
1366
1367         port->membase = ioremap(port->mapbase, size);
1368         if (!port->membase) {
1369                 ret = -EBUSY;
1370                 goto fail_release_port;
1371         }
1372
1373         return 0;
1374
1375 fail_release_port:
1376         release_mem_region(port->mapbase, size);
1377         return ret;
1378 }
1379
1380 static void msm_config_port(struct uart_port *port, int flags)
1381 {
1382         int ret;
1383
1384         if (flags & UART_CONFIG_TYPE) {
1385                 port->type = PORT_MSM;
1386                 ret = msm_request_port(port);
1387                 if (ret)
1388                         return;
1389         }
1390 }
1391
1392 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1393 {
1394         if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1395                 return -EINVAL;
1396         if (unlikely(port->irq != ser->irq))
1397                 return -EINVAL;
1398         return 0;
1399 }
1400
1401 static void msm_power(struct uart_port *port, unsigned int state,
1402                       unsigned int oldstate)
1403 {
1404         struct msm_port *msm_port = UART_TO_MSM(port);
1405
1406         switch (state) {
1407         case 0:
1408                 clk_prepare_enable(msm_port->clk);
1409                 clk_prepare_enable(msm_port->pclk);
1410                 break;
1411         case 3:
1412                 clk_disable_unprepare(msm_port->clk);
1413                 clk_disable_unprepare(msm_port->pclk);
1414                 break;
1415         default:
1416                 pr_err("msm_serial: Unknown PM state %d\n", state);
1417         }
1418 }
1419
1420 #ifdef CONFIG_CONSOLE_POLL
1421 static int msm_poll_get_char_single(struct uart_port *port)
1422 {
1423         struct msm_port *msm_port = UART_TO_MSM(port);
1424         unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1425
1426         if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1427                 return NO_POLL_CHAR;
1428
1429         return msm_read(port, rf_reg) & 0xff;
1430 }
1431
1432 static int msm_poll_get_char_dm(struct uart_port *port)
1433 {
1434         int c;
1435         static u32 slop;
1436         static int count;
1437         unsigned char *sp = (unsigned char *)&slop;
1438
1439         /* Check if a previous read had more than one char */
1440         if (count) {
1441                 c = sp[sizeof(slop) - count];
1442                 count--;
1443         /* Or if FIFO is empty */
1444         } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1445                 /*
1446                  * If RX packing buffer has less than a word, force stale to
1447                  * push contents into RX FIFO
1448                  */
1449                 count = msm_read(port, UARTDM_RXFS);
1450                 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1451                 if (count) {
1452                         msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1453                         slop = msm_read(port, UARTDM_RF);
1454                         c = sp[0];
1455                         count--;
1456                         msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1457                         msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1458                         msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1459                                   UART_CR);
1460                 } else {
1461                         c = NO_POLL_CHAR;
1462                 }
1463         /* FIFO has a word */
1464         } else {
1465                 slop = msm_read(port, UARTDM_RF);
1466                 c = sp[0];
1467                 count = sizeof(slop) - 1;
1468         }
1469
1470         return c;
1471 }
1472
1473 static int msm_poll_get_char(struct uart_port *port)
1474 {
1475         u32 imr;
1476         int c;
1477         struct msm_port *msm_port = UART_TO_MSM(port);
1478
1479         /* Disable all interrupts */
1480         imr = msm_read(port, UART_IMR);
1481         msm_write(port, 0, UART_IMR);
1482
1483         if (msm_port->is_uartdm)
1484                 c = msm_poll_get_char_dm(port);
1485         else
1486                 c = msm_poll_get_char_single(port);
1487
1488         /* Enable interrupts */
1489         msm_write(port, imr, UART_IMR);
1490
1491         return c;
1492 }
1493
1494 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1495 {
1496         u32 imr;
1497         struct msm_port *msm_port = UART_TO_MSM(port);
1498
1499         /* Disable all interrupts */
1500         imr = msm_read(port, UART_IMR);
1501         msm_write(port, 0, UART_IMR);
1502
1503         if (msm_port->is_uartdm)
1504                 msm_reset_dm_count(port, 1);
1505
1506         /* Wait until FIFO is empty */
1507         while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1508                 cpu_relax();
1509
1510         /* Write a character */
1511         msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1512
1513         /* Wait until FIFO is empty */
1514         while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1515                 cpu_relax();
1516
1517         /* Enable interrupts */
1518         msm_write(port, imr, UART_IMR);
1519 }
1520 #endif
1521
1522 static struct uart_ops msm_uart_pops = {
1523         .tx_empty = msm_tx_empty,
1524         .set_mctrl = msm_set_mctrl,
1525         .get_mctrl = msm_get_mctrl,
1526         .stop_tx = msm_stop_tx,
1527         .start_tx = msm_start_tx,
1528         .stop_rx = msm_stop_rx,
1529         .enable_ms = msm_enable_ms,
1530         .break_ctl = msm_break_ctl,
1531         .startup = msm_startup,
1532         .shutdown = msm_shutdown,
1533         .set_termios = msm_set_termios,
1534         .type = msm_type,
1535         .release_port = msm_release_port,
1536         .request_port = msm_request_port,
1537         .config_port = msm_config_port,
1538         .verify_port = msm_verify_port,
1539         .pm = msm_power,
1540 #ifdef CONFIG_CONSOLE_POLL
1541         .poll_get_char  = msm_poll_get_char,
1542         .poll_put_char  = msm_poll_put_char,
1543 #endif
1544 };
1545
1546 static struct msm_port msm_uart_ports[] = {
1547         {
1548                 .uart = {
1549                         .iotype = UPIO_MEM,
1550                         .ops = &msm_uart_pops,
1551                         .flags = UPF_BOOT_AUTOCONF,
1552                         .fifosize = 64,
1553                         .line = 0,
1554                 },
1555         },
1556         {
1557                 .uart = {
1558                         .iotype = UPIO_MEM,
1559                         .ops = &msm_uart_pops,
1560                         .flags = UPF_BOOT_AUTOCONF,
1561                         .fifosize = 64,
1562                         .line = 1,
1563                 },
1564         },
1565         {
1566                 .uart = {
1567                         .iotype = UPIO_MEM,
1568                         .ops = &msm_uart_pops,
1569                         .flags = UPF_BOOT_AUTOCONF,
1570                         .fifosize = 64,
1571                         .line = 2,
1572                 },
1573         },
1574 };
1575
1576 #define UART_NR ARRAY_SIZE(msm_uart_ports)
1577
1578 static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1579 {
1580         return &msm_uart_ports[line].uart;
1581 }
1582
1583 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1584 static void __msm_console_write(struct uart_port *port, const char *s,
1585                                 unsigned int count, bool is_uartdm)
1586 {
1587         int i;
1588         int num_newlines = 0;
1589         bool replaced = false;
1590         void __iomem *tf;
1591         int locked = 1;
1592
1593         if (is_uartdm)
1594                 tf = port->membase + UARTDM_TF;
1595         else
1596                 tf = port->membase + UART_TF;
1597
1598         /* Account for newlines that will get a carriage return added */
1599         for (i = 0; i < count; i++)
1600                 if (s[i] == '\n')
1601                         num_newlines++;
1602         count += num_newlines;
1603
1604         if (port->sysrq)
1605                 locked = 0;
1606         else if (oops_in_progress)
1607                 locked = spin_trylock(&port->lock);
1608         else
1609                 spin_lock(&port->lock);
1610
1611         if (is_uartdm)
1612                 msm_reset_dm_count(port, count);
1613
1614         i = 0;
1615         while (i < count) {
1616                 int j;
1617                 unsigned int num_chars;
1618                 char buf[4] = { 0 };
1619
1620                 if (is_uartdm)
1621                         num_chars = min(count - i, (unsigned int)sizeof(buf));
1622                 else
1623                         num_chars = 1;
1624
1625                 for (j = 0; j < num_chars; j++) {
1626                         char c = *s;
1627
1628                         if (c == '\n' && !replaced) {
1629                                 buf[j] = '\r';
1630                                 j++;
1631                                 replaced = true;
1632                         }
1633                         if (j < num_chars) {
1634                                 buf[j] = c;
1635                                 s++;
1636                                 replaced = false;
1637                         }
1638                 }
1639
1640                 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1641                         cpu_relax();
1642
1643                 iowrite32_rep(tf, buf, 1);
1644                 i += num_chars;
1645         }
1646
1647         if (locked)
1648                 spin_unlock(&port->lock);
1649 }
1650
1651 static void msm_console_write(struct console *co, const char *s,
1652                               unsigned int count)
1653 {
1654         struct uart_port *port;
1655         struct msm_port *msm_port;
1656
1657         BUG_ON(co->index < 0 || co->index >= UART_NR);
1658
1659         port = msm_get_port_from_line(co->index);
1660         msm_port = UART_TO_MSM(port);
1661
1662         __msm_console_write(port, s, count, msm_port->is_uartdm);
1663 }
1664
1665 static int __init msm_console_setup(struct console *co, char *options)
1666 {
1667         struct uart_port *port;
1668         int baud = 115200;
1669         int bits = 8;
1670         int parity = 'n';
1671         int flow = 'n';
1672
1673         if (unlikely(co->index >= UART_NR || co->index < 0))
1674                 return -ENXIO;
1675
1676         port = msm_get_port_from_line(co->index);
1677
1678         if (unlikely(!port->membase))
1679                 return -ENXIO;
1680
1681         msm_init_clock(port);
1682
1683         if (options)
1684                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1685
1686         pr_info("msm_serial: console setup on port #%d\n", port->line);
1687
1688         return uart_set_options(port, co, baud, parity, bits, flow);
1689 }
1690
1691 static void
1692 msm_serial_early_write(struct console *con, const char *s, unsigned n)
1693 {
1694         struct earlycon_device *dev = con->data;
1695
1696         __msm_console_write(&dev->port, s, n, false);
1697 }
1698
1699 static int __init
1700 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1701 {
1702         if (!device->port.membase)
1703                 return -ENODEV;
1704
1705         device->con->write = msm_serial_early_write;
1706         return 0;
1707 }
1708 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1709                     msm_serial_early_console_setup);
1710
1711 static void
1712 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1713 {
1714         struct earlycon_device *dev = con->data;
1715
1716         __msm_console_write(&dev->port, s, n, true);
1717 }
1718
1719 static int __init
1720 msm_serial_early_console_setup_dm(struct earlycon_device *device,
1721                                   const char *opt)
1722 {
1723         if (!device->port.membase)
1724                 return -ENODEV;
1725
1726         device->con->write = msm_serial_early_write_dm;
1727         return 0;
1728 }
1729 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1730                     msm_serial_early_console_setup_dm);
1731
1732 static struct uart_driver msm_uart_driver;
1733
1734 static struct console msm_console = {
1735         .name = "ttyMSM",
1736         .write = msm_console_write,
1737         .device = uart_console_device,
1738         .setup = msm_console_setup,
1739         .flags = CON_PRINTBUFFER,
1740         .index = -1,
1741         .data = &msm_uart_driver,
1742 };
1743
1744 #define MSM_CONSOLE     (&msm_console)
1745
1746 #else
1747 #define MSM_CONSOLE     NULL
1748 #endif
1749
1750 static struct uart_driver msm_uart_driver = {
1751         .owner = THIS_MODULE,
1752         .driver_name = "msm_serial",
1753         .dev_name = "ttyMSM",
1754         .nr = UART_NR,
1755         .cons = MSM_CONSOLE,
1756 };
1757
1758 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1759
1760 static const struct of_device_id msm_uartdm_table[] = {
1761         { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1762         { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1763         { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1764         { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1765         { }
1766 };
1767
1768 static int msm_serial_probe(struct platform_device *pdev)
1769 {
1770         struct msm_port *msm_port;
1771         struct resource *resource;
1772         struct uart_port *port;
1773         const struct of_device_id *id;
1774         int irq, line;
1775
1776         if (pdev->dev.of_node)
1777                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1778         else
1779                 line = pdev->id;
1780
1781         if (line < 0)
1782                 line = atomic_inc_return(&msm_uart_next_id) - 1;
1783
1784         if (unlikely(line < 0 || line >= UART_NR))
1785                 return -ENXIO;
1786
1787         dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1788
1789         port = msm_get_port_from_line(line);
1790         port->dev = &pdev->dev;
1791         msm_port = UART_TO_MSM(port);
1792
1793         id = of_match_device(msm_uartdm_table, &pdev->dev);
1794         if (id)
1795                 msm_port->is_uartdm = (unsigned long)id->data;
1796         else
1797                 msm_port->is_uartdm = 0;
1798
1799         msm_port->clk = devm_clk_get(&pdev->dev, "core");
1800         if (IS_ERR(msm_port->clk))
1801                 return PTR_ERR(msm_port->clk);
1802
1803         if (msm_port->is_uartdm) {
1804                 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1805                 if (IS_ERR(msm_port->pclk))
1806                         return PTR_ERR(msm_port->pclk);
1807         }
1808
1809         port->uartclk = clk_get_rate(msm_port->clk);
1810         dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1811
1812         resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1813         if (unlikely(!resource))
1814                 return -ENXIO;
1815         port->mapbase = resource->start;
1816
1817         irq = platform_get_irq(pdev, 0);
1818         if (unlikely(irq < 0))
1819                 return -ENXIO;
1820         port->irq = irq;
1821
1822         platform_set_drvdata(pdev, port);
1823
1824         return uart_add_one_port(&msm_uart_driver, port);
1825 }
1826
1827 static int msm_serial_remove(struct platform_device *pdev)
1828 {
1829         struct uart_port *port = platform_get_drvdata(pdev);
1830
1831         uart_remove_one_port(&msm_uart_driver, port);
1832
1833         return 0;
1834 }
1835
1836 static const struct of_device_id msm_match_table[] = {
1837         { .compatible = "qcom,msm-uart" },
1838         { .compatible = "qcom,msm-uartdm" },
1839         {}
1840 };
1841 MODULE_DEVICE_TABLE(of, msm_match_table);
1842
1843 static struct platform_driver msm_platform_driver = {
1844         .remove = msm_serial_remove,
1845         .probe = msm_serial_probe,
1846         .driver = {
1847                 .name = "msm_serial",
1848                 .of_match_table = msm_match_table,
1849         },
1850 };
1851
1852 static int __init msm_serial_init(void)
1853 {
1854         int ret;
1855
1856         ret = uart_register_driver(&msm_uart_driver);
1857         if (unlikely(ret))
1858                 return ret;
1859
1860         ret = platform_driver_register(&msm_platform_driver);
1861         if (unlikely(ret))
1862                 uart_unregister_driver(&msm_uart_driver);
1863
1864         pr_info("msm_serial: driver initialized\n");
1865
1866         return ret;
1867 }
1868
1869 static void __exit msm_serial_exit(void)
1870 {
1871         platform_driver_unregister(&msm_platform_driver);
1872         uart_unregister_driver(&msm_uart_driver);
1873 }
1874
1875 module_init(msm_serial_init);
1876 module_exit(msm_serial_exit);
1877
1878 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1879 MODULE_DESCRIPTION("Driver for msm7x serial device");
1880 MODULE_LICENSE("GPL");