1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for msm7k serial device and console
5 * Copyright (C) 2007 Google, Inc.
6 * Author: Robert Love <rlove@google.com>
7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
10 #include <linux/kernel.h>
11 #include <linux/atomic.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/console.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/serial_core.h>
23 #include <linux/slab.h>
24 #include <linux/clk.h>
25 #include <linux/platform_device.h>
26 #include <linux/delay.h>
28 #include <linux/of_device.h>
29 #include <linux/wait.h>
31 #define UART_MR1 0x0000
33 #define UART_MR1_AUTO_RFR_LEVEL0 0x3F
34 #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
35 #define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
36 #define UART_MR1_RX_RDY_CTL BIT(7)
37 #define UART_MR1_CTS_CTL BIT(6)
39 #define UART_MR2 0x0004
40 #define UART_MR2_ERROR_MODE BIT(6)
41 #define UART_MR2_BITS_PER_CHAR 0x30
42 #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
43 #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
44 #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
45 #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
46 #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
47 #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
48 #define UART_MR2_PARITY_MODE_NONE 0x0
49 #define UART_MR2_PARITY_MODE_ODD 0x1
50 #define UART_MR2_PARITY_MODE_EVEN 0x2
51 #define UART_MR2_PARITY_MODE_SPACE 0x3
52 #define UART_MR2_PARITY_MODE 0x3
54 #define UART_CSR 0x0008
56 #define UART_TF 0x000C
57 #define UARTDM_TF 0x0070
59 #define UART_CR 0x0010
60 #define UART_CR_CMD_NULL (0 << 4)
61 #define UART_CR_CMD_RESET_RX (1 << 4)
62 #define UART_CR_CMD_RESET_TX (2 << 4)
63 #define UART_CR_CMD_RESET_ERR (3 << 4)
64 #define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
65 #define UART_CR_CMD_START_BREAK (5 << 4)
66 #define UART_CR_CMD_STOP_BREAK (6 << 4)
67 #define UART_CR_CMD_RESET_CTS (7 << 4)
68 #define UART_CR_CMD_RESET_STALE_INT (8 << 4)
69 #define UART_CR_CMD_PACKET_MODE (9 << 4)
70 #define UART_CR_CMD_MODE_RESET (12 << 4)
71 #define UART_CR_CMD_SET_RFR (13 << 4)
72 #define UART_CR_CMD_RESET_RFR (14 << 4)
73 #define UART_CR_CMD_PROTECTION_EN (16 << 4)
74 #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
75 #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
76 #define UART_CR_CMD_FORCE_STALE (4 << 8)
77 #define UART_CR_CMD_RESET_TX_READY (3 << 8)
78 #define UART_CR_TX_DISABLE BIT(3)
79 #define UART_CR_TX_ENABLE BIT(2)
80 #define UART_CR_RX_DISABLE BIT(1)
81 #define UART_CR_RX_ENABLE BIT(0)
82 #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
84 #define UART_IMR 0x0014
85 #define UART_IMR_TXLEV BIT(0)
86 #define UART_IMR_RXSTALE BIT(3)
87 #define UART_IMR_RXLEV BIT(4)
88 #define UART_IMR_DELTA_CTS BIT(5)
89 #define UART_IMR_CURRENT_CTS BIT(6)
90 #define UART_IMR_RXBREAK_START BIT(10)
92 #define UART_IPR_RXSTALE_LAST 0x20
93 #define UART_IPR_STALE_LSB 0x1F
94 #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
95 #define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
97 #define UART_IPR 0x0018
98 #define UART_TFWR 0x001C
99 #define UART_RFWR 0x0020
100 #define UART_HCR 0x0024
102 #define UART_MREG 0x0028
103 #define UART_NREG 0x002C
104 #define UART_DREG 0x0030
105 #define UART_MNDREG 0x0034
106 #define UART_IRDA 0x0038
107 #define UART_MISR_MODE 0x0040
108 #define UART_MISR_RESET 0x0044
109 #define UART_MISR_EXPORT 0x0048
110 #define UART_MISR_VAL 0x004C
111 #define UART_TEST_CTRL 0x0050
113 #define UART_SR 0x0008
114 #define UART_SR_HUNT_CHAR BIT(7)
115 #define UART_SR_RX_BREAK BIT(6)
116 #define UART_SR_PAR_FRAME_ERR BIT(5)
117 #define UART_SR_OVERRUN BIT(4)
118 #define UART_SR_TX_EMPTY BIT(3)
119 #define UART_SR_TX_READY BIT(2)
120 #define UART_SR_RX_FULL BIT(1)
121 #define UART_SR_RX_READY BIT(0)
123 #define UART_RF 0x000C
124 #define UARTDM_RF 0x0070
125 #define UART_MISR 0x0010
126 #define UART_ISR 0x0014
127 #define UART_ISR_TX_READY BIT(7)
129 #define UARTDM_RXFS 0x50
130 #define UARTDM_RXFS_BUF_SHIFT 0x7
131 #define UARTDM_RXFS_BUF_MASK 0x7
133 #define UARTDM_DMEN 0x3C
134 #define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
135 #define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
137 #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
138 #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
140 #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
141 #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
143 #define UARTDM_DMRX 0x34
144 #define UARTDM_NCF_TX 0x40
145 #define UARTDM_RX_TOTAL_SNAP 0x38
147 #define UARTDM_BURST_SIZE 16 /* in bytes */
148 #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
149 #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
150 #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
160 struct dma_chan *chan;
161 enum dma_data_direction dir;
167 struct dma_async_tx_descriptor *desc;
171 struct uart_port uart;
177 unsigned int old_snap_state;
179 struct msm_dma tx_dma;
180 struct msm_dma rx_dma;
183 #define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
186 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
188 writel_relaxed(val, port->membase + off);
192 unsigned int msm_read(struct uart_port *port, unsigned int off)
194 return readl_relaxed(port->membase + off);
198 * Setup the MND registers to use the TCXO clock.
200 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
202 msm_write(port, 0x06, UART_MREG);
203 msm_write(port, 0xF1, UART_NREG);
204 msm_write(port, 0x0F, UART_DREG);
205 msm_write(port, 0x1A, UART_MNDREG);
206 port->uartclk = 1843200;
210 * Setup the MND registers to use the TCXO clock divided by 4.
212 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
214 msm_write(port, 0x18, UART_MREG);
215 msm_write(port, 0xF6, UART_NREG);
216 msm_write(port, 0x0F, UART_DREG);
217 msm_write(port, 0x0A, UART_MNDREG);
218 port->uartclk = 1843200;
221 static void msm_serial_set_mnd_regs(struct uart_port *port)
223 struct msm_port *msm_port = UART_TO_MSM(port);
226 * These registers don't exist so we change the clk input rate
227 * on uartdm hardware instead
229 if (msm_port->is_uartdm)
232 if (port->uartclk == 19200000)
233 msm_serial_set_mnd_regs_tcxo(port);
234 else if (port->uartclk == 4800000)
235 msm_serial_set_mnd_regs_tcxoby4(port);
238 static void msm_handle_tx(struct uart_port *port);
239 static void msm_start_rx_dma(struct msm_port *msm_port);
241 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
243 struct device *dev = port->dev;
250 dmaengine_terminate_all(dma->chan);
253 * DMA Stall happens if enqueue and flush command happens concurrently.
254 * For example before changing the baud rate/protocol configuration and
255 * sending flush command to ADM, disable the channel of UARTDM.
256 * Note: should not reset the receiver here immediately as it is not
257 * suggested to do disable/reset or reset/disable at the same time.
259 val = msm_read(port, UARTDM_DMEN);
260 val &= ~dma->enable_bit;
261 msm_write(port, val, UARTDM_DMEN);
264 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
267 static void msm_release_dma(struct msm_port *msm_port)
271 dma = &msm_port->tx_dma;
273 msm_stop_dma(&msm_port->uart, dma);
274 dma_release_channel(dma->chan);
277 memset(dma, 0, sizeof(*dma));
279 dma = &msm_port->rx_dma;
281 msm_stop_dma(&msm_port->uart, dma);
282 dma_release_channel(dma->chan);
286 memset(dma, 0, sizeof(*dma));
289 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
291 struct device *dev = msm_port->uart.dev;
292 struct dma_slave_config conf;
297 dma = &msm_port->tx_dma;
299 /* allocate DMA resources, if available */
300 dma->chan = dma_request_chan(dev, "tx");
301 if (IS_ERR(dma->chan))
304 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
306 memset(&conf, 0, sizeof(conf));
307 conf.direction = DMA_MEM_TO_DEV;
308 conf.device_fc = true;
309 conf.dst_addr = base + UARTDM_TF;
310 conf.dst_maxburst = UARTDM_BURST_SIZE;
311 conf.slave_id = crci;
313 ret = dmaengine_slave_config(dma->chan, &conf);
317 dma->dir = DMA_TO_DEVICE;
319 if (msm_port->is_uartdm < UARTDM_1P4)
320 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
322 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
327 dma_release_channel(dma->chan);
329 memset(dma, 0, sizeof(*dma));
332 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
334 struct device *dev = msm_port->uart.dev;
335 struct dma_slave_config conf;
340 dma = &msm_port->rx_dma;
342 /* allocate DMA resources, if available */
343 dma->chan = dma_request_chan(dev, "rx");
344 if (IS_ERR(dma->chan))
347 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
349 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
353 memset(&conf, 0, sizeof(conf));
354 conf.direction = DMA_DEV_TO_MEM;
355 conf.device_fc = true;
356 conf.src_addr = base + UARTDM_RF;
357 conf.src_maxburst = UARTDM_BURST_SIZE;
358 conf.slave_id = crci;
360 ret = dmaengine_slave_config(dma->chan, &conf);
364 dma->dir = DMA_FROM_DEVICE;
366 if (msm_port->is_uartdm < UARTDM_1P4)
367 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
369 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
375 dma_release_channel(dma->chan);
377 memset(dma, 0, sizeof(*dma));
380 static inline void msm_wait_for_xmitr(struct uart_port *port)
382 unsigned int timeout = 500000;
384 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
385 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
391 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
394 static void msm_stop_tx(struct uart_port *port)
396 struct msm_port *msm_port = UART_TO_MSM(port);
398 msm_port->imr &= ~UART_IMR_TXLEV;
399 msm_write(port, msm_port->imr, UART_IMR);
402 static void msm_start_tx(struct uart_port *port)
404 struct msm_port *msm_port = UART_TO_MSM(port);
405 struct msm_dma *dma = &msm_port->tx_dma;
407 /* Already started in DMA mode */
411 msm_port->imr |= UART_IMR_TXLEV;
412 msm_write(port, msm_port->imr, UART_IMR);
415 static void msm_reset_dm_count(struct uart_port *port, int count)
417 msm_wait_for_xmitr(port);
418 msm_write(port, count, UARTDM_NCF_TX);
419 msm_read(port, UARTDM_NCF_TX);
422 static void msm_complete_tx_dma(void *args)
424 struct msm_port *msm_port = args;
425 struct uart_port *port = &msm_port->uart;
426 struct circ_buf *xmit = &port->state->xmit;
427 struct msm_dma *dma = &msm_port->tx_dma;
428 struct dma_tx_state state;
429 enum dma_status status;
434 spin_lock_irqsave(&port->lock, flags);
436 /* Already stopped */
440 status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
442 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
444 val = msm_read(port, UARTDM_DMEN);
445 val &= ~dma->enable_bit;
446 msm_write(port, val, UARTDM_DMEN);
448 if (msm_port->is_uartdm > UARTDM_1P3) {
449 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
450 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
453 count = dma->count - state.residue;
454 port->icount.tx += count;
458 xmit->tail &= UART_XMIT_SIZE - 1;
460 /* Restore "Tx FIFO below watermark" interrupt */
461 msm_port->imr |= UART_IMR_TXLEV;
462 msm_write(port, msm_port->imr, UART_IMR);
464 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
465 uart_write_wakeup(port);
469 spin_unlock_irqrestore(&port->lock, flags);
472 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
474 struct circ_buf *xmit = &msm_port->uart.state->xmit;
475 struct uart_port *port = &msm_port->uart;
476 struct msm_dma *dma = &msm_port->tx_dma;
481 cpu_addr = &xmit->buf[xmit->tail];
483 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
484 ret = dma_mapping_error(port->dev, dma->phys);
488 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
489 count, DMA_MEM_TO_DEV,
497 dma->desc->callback = msm_complete_tx_dma;
498 dma->desc->callback_param = msm_port;
500 dma->cookie = dmaengine_submit(dma->desc);
501 ret = dma_submit_error(dma->cookie);
506 * Using DMA complete for Tx FIFO reload, no need for
507 * "Tx FIFO below watermark" one, disable it
509 msm_port->imr &= ~UART_IMR_TXLEV;
510 msm_write(port, msm_port->imr, UART_IMR);
514 val = msm_read(port, UARTDM_DMEN);
515 val |= dma->enable_bit;
517 if (msm_port->is_uartdm < UARTDM_1P4)
518 msm_write(port, val, UARTDM_DMEN);
520 msm_reset_dm_count(port, count);
522 if (msm_port->is_uartdm > UARTDM_1P3)
523 msm_write(port, val, UARTDM_DMEN);
525 dma_async_issue_pending(dma->chan);
528 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
532 static void msm_complete_rx_dma(void *args)
534 struct msm_port *msm_port = args;
535 struct uart_port *port = &msm_port->uart;
536 struct tty_port *tport = &port->state->port;
537 struct msm_dma *dma = &msm_port->rx_dma;
538 int count = 0, i, sysrq;
542 spin_lock_irqsave(&port->lock, flags);
544 /* Already stopped */
548 val = msm_read(port, UARTDM_DMEN);
549 val &= ~dma->enable_bit;
550 msm_write(port, val, UARTDM_DMEN);
552 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
553 port->icount.overrun++;
554 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
555 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
558 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
560 port->icount.rx += count;
564 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
566 for (i = 0; i < count; i++) {
567 char flag = TTY_NORMAL;
569 if (msm_port->break_detected && dma->virt[i] == 0) {
572 msm_port->break_detected = false;
573 if (uart_handle_break(port))
577 if (!(port->read_status_mask & UART_SR_RX_BREAK))
580 spin_unlock_irqrestore(&port->lock, flags);
581 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
582 spin_lock_irqsave(&port->lock, flags);
584 tty_insert_flip_char(tport, dma->virt[i], flag);
587 msm_start_rx_dma(msm_port);
589 spin_unlock_irqrestore(&port->lock, flags);
592 tty_flip_buffer_push(tport);
595 static void msm_start_rx_dma(struct msm_port *msm_port)
597 struct msm_dma *dma = &msm_port->rx_dma;
598 struct uart_port *uart = &msm_port->uart;
602 if (IS_ENABLED(CONFIG_CONSOLE_POLL))
608 dma->phys = dma_map_single(uart->dev, dma->virt,
609 UARTDM_RX_SIZE, dma->dir);
610 ret = dma_mapping_error(uart->dev, dma->phys);
614 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
615 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
620 dma->desc->callback = msm_complete_rx_dma;
621 dma->desc->callback_param = msm_port;
623 dma->cookie = dmaengine_submit(dma->desc);
624 ret = dma_submit_error(dma->cookie);
628 * Using DMA for FIFO off-load, no need for "Rx FIFO over
629 * watermark" or "stale" interrupts, disable them
631 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
634 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
635 * we need RXSTALE to flush input DMA fifo to memory
637 if (msm_port->is_uartdm < UARTDM_1P4)
638 msm_port->imr |= UART_IMR_RXSTALE;
640 msm_write(uart, msm_port->imr, UART_IMR);
642 dma->count = UARTDM_RX_SIZE;
644 dma_async_issue_pending(dma->chan);
646 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
647 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
649 val = msm_read(uart, UARTDM_DMEN);
650 val |= dma->enable_bit;
652 if (msm_port->is_uartdm < UARTDM_1P4)
653 msm_write(uart, val, UARTDM_DMEN);
655 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
657 if (msm_port->is_uartdm > UARTDM_1P3)
658 msm_write(uart, val, UARTDM_DMEN);
662 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
666 * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN),
667 * receiver must be reset.
669 msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR);
670 msm_write(uart, UART_CR_RX_ENABLE, UART_CR);
672 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
673 msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
674 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
676 /* Re-enable RX interrupts */
677 msm_port->imr |= (UART_IMR_RXLEV | UART_IMR_RXSTALE);
678 msm_write(uart, msm_port->imr, UART_IMR);
681 static void msm_stop_rx(struct uart_port *port)
683 struct msm_port *msm_port = UART_TO_MSM(port);
684 struct msm_dma *dma = &msm_port->rx_dma;
686 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
687 msm_write(port, msm_port->imr, UART_IMR);
690 msm_stop_dma(port, dma);
693 static void msm_enable_ms(struct uart_port *port)
695 struct msm_port *msm_port = UART_TO_MSM(port);
697 msm_port->imr |= UART_IMR_DELTA_CTS;
698 msm_write(port, msm_port->imr, UART_IMR);
701 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
702 __must_hold(&port->lock)
704 struct tty_port *tport = &port->state->port;
707 struct msm_port *msm_port = UART_TO_MSM(port);
709 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
710 port->icount.overrun++;
711 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
712 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
715 if (misr & UART_IMR_RXSTALE) {
716 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
717 msm_port->old_snap_state;
718 msm_port->old_snap_state = 0;
720 count = 4 * (msm_read(port, UART_RFWR));
721 msm_port->old_snap_state += count;
724 /* TODO: Precise error reporting */
726 port->icount.rx += count;
729 unsigned char buf[4];
730 int sysrq, r_count, i;
732 sr = msm_read(port, UART_SR);
733 if ((sr & UART_SR_RX_READY) == 0) {
734 msm_port->old_snap_state -= count;
738 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
739 r_count = min_t(int, count, sizeof(buf));
741 for (i = 0; i < r_count; i++) {
742 char flag = TTY_NORMAL;
744 if (msm_port->break_detected && buf[i] == 0) {
747 msm_port->break_detected = false;
748 if (uart_handle_break(port))
752 if (!(port->read_status_mask & UART_SR_RX_BREAK))
755 spin_unlock(&port->lock);
756 sysrq = uart_handle_sysrq_char(port, buf[i]);
757 spin_lock(&port->lock);
759 tty_insert_flip_char(tport, buf[i], flag);
764 spin_unlock(&port->lock);
765 tty_flip_buffer_push(tport);
766 spin_lock(&port->lock);
768 if (misr & (UART_IMR_RXSTALE))
769 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
770 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
771 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
774 msm_start_rx_dma(msm_port);
777 static void msm_handle_rx(struct uart_port *port)
778 __must_hold(&port->lock)
780 struct tty_port *tport = &port->state->port;
784 * Handle overrun. My understanding of the hardware is that overrun
785 * is not tied to the RX buffer, so we handle the case out of band.
787 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
788 port->icount.overrun++;
789 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
790 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
793 /* and now the main RX loop */
794 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
796 char flag = TTY_NORMAL;
799 c = msm_read(port, UART_RF);
801 if (sr & UART_SR_RX_BREAK) {
803 if (uart_handle_break(port))
805 } else if (sr & UART_SR_PAR_FRAME_ERR) {
806 port->icount.frame++;
811 /* Mask conditions we're ignorning. */
812 sr &= port->read_status_mask;
814 if (sr & UART_SR_RX_BREAK)
816 else if (sr & UART_SR_PAR_FRAME_ERR)
819 spin_unlock(&port->lock);
820 sysrq = uart_handle_sysrq_char(port, c);
821 spin_lock(&port->lock);
823 tty_insert_flip_char(tport, c, flag);
826 spin_unlock(&port->lock);
827 tty_flip_buffer_push(tport);
828 spin_lock(&port->lock);
831 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
833 struct circ_buf *xmit = &port->state->xmit;
834 struct msm_port *msm_port = UART_TO_MSM(port);
835 unsigned int num_chars;
836 unsigned int tf_pointer = 0;
839 if (msm_port->is_uartdm)
840 tf = port->membase + UARTDM_TF;
842 tf = port->membase + UART_TF;
844 if (tx_count && msm_port->is_uartdm)
845 msm_reset_dm_count(port, tx_count);
847 while (tf_pointer < tx_count) {
851 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
854 if (msm_port->is_uartdm)
855 num_chars = min(tx_count - tf_pointer,
856 (unsigned int)sizeof(buf));
860 for (i = 0; i < num_chars; i++) {
861 buf[i] = xmit->buf[xmit->tail + i];
865 iowrite32_rep(tf, buf, 1);
866 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
867 tf_pointer += num_chars;
870 /* disable tx interrupts if nothing more to send */
871 if (uart_circ_empty(xmit))
874 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
875 uart_write_wakeup(port);
878 static void msm_handle_tx(struct uart_port *port)
880 struct msm_port *msm_port = UART_TO_MSM(port);
881 struct circ_buf *xmit = &msm_port->uart.state->xmit;
882 struct msm_dma *dma = &msm_port->tx_dma;
883 unsigned int pio_count, dma_count, dma_min;
889 if (msm_port->is_uartdm)
890 tf = port->membase + UARTDM_TF;
892 tf = port->membase + UART_TF;
894 buf[0] = port->x_char;
896 if (msm_port->is_uartdm)
897 msm_reset_dm_count(port, 1);
899 iowrite32_rep(tf, buf, 1);
905 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
910 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
911 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
913 dma_min = 1; /* Always DMA */
914 if (msm_port->is_uartdm > UARTDM_1P3) {
915 dma_count = UARTDM_TX_AIGN(dma_count);
916 dma_min = UARTDM_BURST_SIZE;
918 if (dma_count > UARTDM_TX_MAX)
919 dma_count = UARTDM_TX_MAX;
922 if (pio_count > port->fifosize)
923 pio_count = port->fifosize;
925 if (!dma->chan || dma_count < dma_min)
926 msm_handle_tx_pio(port, pio_count);
928 err = msm_handle_tx_dma(msm_port, dma_count);
930 if (err) /* fall back to PIO mode */
931 msm_handle_tx_pio(port, pio_count);
934 static void msm_handle_delta_cts(struct uart_port *port)
936 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
938 wake_up_interruptible(&port->state->port.delta_msr_wait);
941 static irqreturn_t msm_uart_irq(int irq, void *dev_id)
943 struct uart_port *port = dev_id;
944 struct msm_port *msm_port = UART_TO_MSM(port);
945 struct msm_dma *dma = &msm_port->rx_dma;
950 spin_lock_irqsave(&port->lock, flags);
951 misr = msm_read(port, UART_MISR);
952 msm_write(port, 0, UART_IMR); /* disable interrupt */
954 if (misr & UART_IMR_RXBREAK_START) {
955 msm_port->break_detected = true;
956 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
959 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
961 val = UART_CR_CMD_STALE_EVENT_DISABLE;
962 msm_write(port, val, UART_CR);
963 val = UART_CR_CMD_RESET_STALE_INT;
964 msm_write(port, val, UART_CR);
966 * Flush DMA input fifo to memory, this will also
967 * trigger DMA RX completion
969 dmaengine_terminate_all(dma->chan);
970 } else if (msm_port->is_uartdm) {
971 msm_handle_rx_dm(port, misr);
976 if (misr & UART_IMR_TXLEV)
978 if (misr & UART_IMR_DELTA_CTS)
979 msm_handle_delta_cts(port);
981 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
982 spin_unlock_irqrestore(&port->lock, flags);
987 static unsigned int msm_tx_empty(struct uart_port *port)
989 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
992 static unsigned int msm_get_mctrl(struct uart_port *port)
994 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
997 static void msm_reset(struct uart_port *port)
999 struct msm_port *msm_port = UART_TO_MSM(port);
1002 /* reset everything */
1003 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
1004 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
1005 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
1006 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
1007 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
1008 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1009 mr = msm_read(port, UART_MR1);
1010 mr &= ~UART_MR1_RX_RDY_CTL;
1011 msm_write(port, mr, UART_MR1);
1013 /* Disable DM modes */
1014 if (msm_port->is_uartdm)
1015 msm_write(port, 0, UARTDM_DMEN);
1018 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
1022 mr = msm_read(port, UART_MR1);
1024 if (!(mctrl & TIOCM_RTS)) {
1025 mr &= ~UART_MR1_RX_RDY_CTL;
1026 msm_write(port, mr, UART_MR1);
1027 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1029 mr |= UART_MR1_RX_RDY_CTL;
1030 msm_write(port, mr, UART_MR1);
1034 static void msm_break_ctl(struct uart_port *port, int break_ctl)
1037 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1039 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1042 struct msm_baud_map {
1048 static const struct msm_baud_map *
1049 msm_find_best_baud(struct uart_port *port, unsigned int baud,
1050 unsigned long *rate)
1052 struct msm_port *msm_port = UART_TO_MSM(port);
1053 unsigned int divisor, result;
1054 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1055 const struct msm_baud_map *entry, *end, *best;
1056 static const struct msm_baud_map table[] = {
1075 best = table; /* Default to smallest divider */
1076 target = clk_round_rate(msm_port->clk, 16 * baud);
1077 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1079 end = table + ARRAY_SIZE(table);
1081 while (entry < end) {
1082 if (entry->divisor <= divisor) {
1083 result = target / entry->divisor / 16;
1084 diff = abs(result - baud);
1086 /* Keep track of best entry */
1087 if (diff < best_diff) {
1095 } else if (entry->divisor > divisor) {
1097 target = clk_round_rate(msm_port->clk, old + 1);
1099 * The rate didn't get any faster so we can't do
1100 * better at dividing it down
1105 /* Start the divisor search over at this new rate */
1107 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1117 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1118 unsigned long *saved_flags)
1120 unsigned int rxstale, watermark, mask;
1121 struct msm_port *msm_port = UART_TO_MSM(port);
1122 const struct msm_baud_map *entry;
1123 unsigned long flags, rate;
1125 flags = *saved_flags;
1126 spin_unlock_irqrestore(&port->lock, flags);
1128 entry = msm_find_best_baud(port, baud, &rate);
1129 clk_set_rate(msm_port->clk, rate);
1130 baud = rate / 16 / entry->divisor;
1132 spin_lock_irqsave(&port->lock, flags);
1133 *saved_flags = flags;
1134 port->uartclk = rate;
1136 msm_write(port, entry->code, UART_CSR);
1138 /* RX stale watermark */
1139 rxstale = entry->rxstale;
1140 watermark = UART_IPR_STALE_LSB & rxstale;
1141 if (msm_port->is_uartdm) {
1142 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1144 watermark |= UART_IPR_RXSTALE_LAST;
1145 mask = UART_IPR_STALE_TIMEOUT_MSB;
1148 watermark |= mask & (rxstale << 2);
1150 msm_write(port, watermark, UART_IPR);
1152 /* set RX watermark */
1153 watermark = (port->fifosize * 3) / 4;
1154 msm_write(port, watermark, UART_RFWR);
1156 /* set TX watermark */
1157 msm_write(port, 10, UART_TFWR);
1159 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1162 /* Enable RX and TX */
1163 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1165 /* turn on RX and CTS interrupts */
1166 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1167 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1169 msm_write(port, msm_port->imr, UART_IMR);
1171 if (msm_port->is_uartdm) {
1172 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1173 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1174 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1180 static void msm_init_clock(struct uart_port *port)
1182 struct msm_port *msm_port = UART_TO_MSM(port);
1184 clk_prepare_enable(msm_port->clk);
1185 clk_prepare_enable(msm_port->pclk);
1186 msm_serial_set_mnd_regs(port);
1189 static int msm_startup(struct uart_port *port)
1191 struct msm_port *msm_port = UART_TO_MSM(port);
1192 unsigned int data, rfr_level, mask;
1195 snprintf(msm_port->name, sizeof(msm_port->name),
1196 "msm_serial%d", port->line);
1198 msm_init_clock(port);
1200 if (likely(port->fifosize > 12))
1201 rfr_level = port->fifosize - 12;
1203 rfr_level = port->fifosize;
1205 /* set automatic RFR level */
1206 data = msm_read(port, UART_MR1);
1208 if (msm_port->is_uartdm)
1209 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1211 mask = UART_MR1_AUTO_RFR_LEVEL1;
1214 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1215 data |= mask & (rfr_level << 2);
1216 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1217 msm_write(port, data, UART_MR1);
1219 if (msm_port->is_uartdm) {
1220 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1221 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1224 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1225 msm_port->name, port);
1232 if (msm_port->is_uartdm)
1233 msm_release_dma(msm_port);
1235 clk_disable_unprepare(msm_port->pclk);
1236 clk_disable_unprepare(msm_port->clk);
1241 static void msm_shutdown(struct uart_port *port)
1243 struct msm_port *msm_port = UART_TO_MSM(port);
1246 msm_write(port, 0, UART_IMR); /* disable interrupts */
1248 if (msm_port->is_uartdm)
1249 msm_release_dma(msm_port);
1251 clk_disable_unprepare(msm_port->clk);
1253 free_irq(port->irq, port);
1256 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1257 struct ktermios *old)
1259 struct msm_port *msm_port = UART_TO_MSM(port);
1260 struct msm_dma *dma = &msm_port->rx_dma;
1261 unsigned long flags;
1262 unsigned int baud, mr;
1264 spin_lock_irqsave(&port->lock, flags);
1266 if (dma->chan) /* Terminate if any */
1267 msm_stop_dma(port, dma);
1269 /* calculate and set baud rate */
1270 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1271 baud = msm_set_baud_rate(port, baud, &flags);
1272 if (tty_termios_baud_rate(termios))
1273 tty_termios_encode_baud_rate(termios, baud, baud);
1275 /* calculate parity */
1276 mr = msm_read(port, UART_MR2);
1277 mr &= ~UART_MR2_PARITY_MODE;
1278 if (termios->c_cflag & PARENB) {
1279 if (termios->c_cflag & PARODD)
1280 mr |= UART_MR2_PARITY_MODE_ODD;
1281 else if (termios->c_cflag & CMSPAR)
1282 mr |= UART_MR2_PARITY_MODE_SPACE;
1284 mr |= UART_MR2_PARITY_MODE_EVEN;
1287 /* calculate bits per char */
1288 mr &= ~UART_MR2_BITS_PER_CHAR;
1289 switch (termios->c_cflag & CSIZE) {
1291 mr |= UART_MR2_BITS_PER_CHAR_5;
1294 mr |= UART_MR2_BITS_PER_CHAR_6;
1297 mr |= UART_MR2_BITS_PER_CHAR_7;
1301 mr |= UART_MR2_BITS_PER_CHAR_8;
1305 /* calculate stop bits */
1306 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1307 if (termios->c_cflag & CSTOPB)
1308 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1310 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1312 /* set parity, bits per char, and stop bit */
1313 msm_write(port, mr, UART_MR2);
1315 /* calculate and set hardware flow control */
1316 mr = msm_read(port, UART_MR1);
1317 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1318 if (termios->c_cflag & CRTSCTS) {
1319 mr |= UART_MR1_CTS_CTL;
1320 mr |= UART_MR1_RX_RDY_CTL;
1322 msm_write(port, mr, UART_MR1);
1324 /* Configure status bits to ignore based on termio flags. */
1325 port->read_status_mask = 0;
1326 if (termios->c_iflag & INPCK)
1327 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1328 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1329 port->read_status_mask |= UART_SR_RX_BREAK;
1331 uart_update_timeout(port, termios->c_cflag, baud);
1333 /* Try to use DMA */
1334 msm_start_rx_dma(msm_port);
1336 spin_unlock_irqrestore(&port->lock, flags);
1339 static const char *msm_type(struct uart_port *port)
1344 static void msm_release_port(struct uart_port *port)
1346 struct platform_device *pdev = to_platform_device(port->dev);
1347 struct resource *uart_resource;
1348 resource_size_t size;
1350 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1351 if (unlikely(!uart_resource))
1353 size = resource_size(uart_resource);
1355 release_mem_region(port->mapbase, size);
1356 iounmap(port->membase);
1357 port->membase = NULL;
1360 static int msm_request_port(struct uart_port *port)
1362 struct platform_device *pdev = to_platform_device(port->dev);
1363 struct resource *uart_resource;
1364 resource_size_t size;
1367 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1368 if (unlikely(!uart_resource))
1371 size = resource_size(uart_resource);
1373 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1376 port->membase = ioremap(port->mapbase, size);
1377 if (!port->membase) {
1379 goto fail_release_port;
1385 release_mem_region(port->mapbase, size);
1389 static void msm_config_port(struct uart_port *port, int flags)
1393 if (flags & UART_CONFIG_TYPE) {
1394 port->type = PORT_MSM;
1395 ret = msm_request_port(port);
1401 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1403 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1405 if (unlikely(port->irq != ser->irq))
1410 static void msm_power(struct uart_port *port, unsigned int state,
1411 unsigned int oldstate)
1413 struct msm_port *msm_port = UART_TO_MSM(port);
1417 clk_prepare_enable(msm_port->clk);
1418 clk_prepare_enable(msm_port->pclk);
1421 clk_disable_unprepare(msm_port->clk);
1422 clk_disable_unprepare(msm_port->pclk);
1425 pr_err("msm_serial: Unknown PM state %d\n", state);
1429 #ifdef CONFIG_CONSOLE_POLL
1430 static int msm_poll_get_char_single(struct uart_port *port)
1432 struct msm_port *msm_port = UART_TO_MSM(port);
1433 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1435 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1436 return NO_POLL_CHAR;
1438 return msm_read(port, rf_reg) & 0xff;
1441 static int msm_poll_get_char_dm(struct uart_port *port)
1446 unsigned char *sp = (unsigned char *)&slop;
1448 /* Check if a previous read had more than one char */
1450 c = sp[sizeof(slop) - count];
1452 /* Or if FIFO is empty */
1453 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1455 * If RX packing buffer has less than a word, force stale to
1456 * push contents into RX FIFO
1458 count = msm_read(port, UARTDM_RXFS);
1459 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1461 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1462 slop = msm_read(port, UARTDM_RF);
1465 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1466 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1467 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1472 /* FIFO has a word */
1474 slop = msm_read(port, UARTDM_RF);
1476 count = sizeof(slop) - 1;
1482 static int msm_poll_get_char(struct uart_port *port)
1486 struct msm_port *msm_port = UART_TO_MSM(port);
1488 /* Disable all interrupts */
1489 imr = msm_read(port, UART_IMR);
1490 msm_write(port, 0, UART_IMR);
1492 if (msm_port->is_uartdm)
1493 c = msm_poll_get_char_dm(port);
1495 c = msm_poll_get_char_single(port);
1497 /* Enable interrupts */
1498 msm_write(port, imr, UART_IMR);
1503 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1506 struct msm_port *msm_port = UART_TO_MSM(port);
1508 /* Disable all interrupts */
1509 imr = msm_read(port, UART_IMR);
1510 msm_write(port, 0, UART_IMR);
1512 if (msm_port->is_uartdm)
1513 msm_reset_dm_count(port, 1);
1515 /* Wait until FIFO is empty */
1516 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1519 /* Write a character */
1520 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1522 /* Wait until FIFO is empty */
1523 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1526 /* Enable interrupts */
1527 msm_write(port, imr, UART_IMR);
1531 static struct uart_ops msm_uart_pops = {
1532 .tx_empty = msm_tx_empty,
1533 .set_mctrl = msm_set_mctrl,
1534 .get_mctrl = msm_get_mctrl,
1535 .stop_tx = msm_stop_tx,
1536 .start_tx = msm_start_tx,
1537 .stop_rx = msm_stop_rx,
1538 .enable_ms = msm_enable_ms,
1539 .break_ctl = msm_break_ctl,
1540 .startup = msm_startup,
1541 .shutdown = msm_shutdown,
1542 .set_termios = msm_set_termios,
1544 .release_port = msm_release_port,
1545 .request_port = msm_request_port,
1546 .config_port = msm_config_port,
1547 .verify_port = msm_verify_port,
1549 #ifdef CONFIG_CONSOLE_POLL
1550 .poll_get_char = msm_poll_get_char,
1551 .poll_put_char = msm_poll_put_char,
1555 static struct msm_port msm_uart_ports[] = {
1559 .ops = &msm_uart_pops,
1560 .flags = UPF_BOOT_AUTOCONF,
1568 .ops = &msm_uart_pops,
1569 .flags = UPF_BOOT_AUTOCONF,
1577 .ops = &msm_uart_pops,
1578 .flags = UPF_BOOT_AUTOCONF,
1585 #define UART_NR ARRAY_SIZE(msm_uart_ports)
1587 static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1589 return &msm_uart_ports[line].uart;
1592 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1593 static void __msm_console_write(struct uart_port *port, const char *s,
1594 unsigned int count, bool is_uartdm)
1596 unsigned long flags;
1598 int num_newlines = 0;
1599 bool replaced = false;
1604 tf = port->membase + UARTDM_TF;
1606 tf = port->membase + UART_TF;
1608 /* Account for newlines that will get a carriage return added */
1609 for (i = 0; i < count; i++)
1612 count += num_newlines;
1614 local_irq_save(flags);
1618 else if (oops_in_progress)
1619 locked = spin_trylock(&port->lock);
1621 spin_lock(&port->lock);
1624 msm_reset_dm_count(port, count);
1629 unsigned int num_chars;
1630 char buf[4] = { 0 };
1633 num_chars = min(count - i, (unsigned int)sizeof(buf));
1637 for (j = 0; j < num_chars; j++) {
1640 if (c == '\n' && !replaced) {
1645 if (j < num_chars) {
1652 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1655 iowrite32_rep(tf, buf, 1);
1660 spin_unlock(&port->lock);
1662 local_irq_restore(flags);
1665 static void msm_console_write(struct console *co, const char *s,
1668 struct uart_port *port;
1669 struct msm_port *msm_port;
1671 BUG_ON(co->index < 0 || co->index >= UART_NR);
1673 port = msm_get_port_from_line(co->index);
1674 msm_port = UART_TO_MSM(port);
1676 __msm_console_write(port, s, count, msm_port->is_uartdm);
1679 static int msm_console_setup(struct console *co, char *options)
1681 struct uart_port *port;
1687 if (unlikely(co->index >= UART_NR || co->index < 0))
1690 port = msm_get_port_from_line(co->index);
1692 if (unlikely(!port->membase))
1695 msm_init_clock(port);
1698 uart_parse_options(options, &baud, &parity, &bits, &flow);
1700 pr_info("msm_serial: console setup on port #%d\n", port->line);
1702 return uart_set_options(port, co, baud, parity, bits, flow);
1706 msm_serial_early_write(struct console *con, const char *s, unsigned n)
1708 struct earlycon_device *dev = con->data;
1710 __msm_console_write(&dev->port, s, n, false);
1714 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1716 if (!device->port.membase)
1719 device->con->write = msm_serial_early_write;
1722 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1723 msm_serial_early_console_setup);
1726 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1728 struct earlycon_device *dev = con->data;
1730 __msm_console_write(&dev->port, s, n, true);
1734 msm_serial_early_console_setup_dm(struct earlycon_device *device,
1737 if (!device->port.membase)
1740 device->con->write = msm_serial_early_write_dm;
1743 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1744 msm_serial_early_console_setup_dm);
1746 static struct uart_driver msm_uart_driver;
1748 static struct console msm_console = {
1750 .write = msm_console_write,
1751 .device = uart_console_device,
1752 .setup = msm_console_setup,
1753 .flags = CON_PRINTBUFFER,
1755 .data = &msm_uart_driver,
1758 #define MSM_CONSOLE (&msm_console)
1761 #define MSM_CONSOLE NULL
1764 static struct uart_driver msm_uart_driver = {
1765 .owner = THIS_MODULE,
1766 .driver_name = "msm_serial",
1767 .dev_name = "ttyMSM",
1769 .cons = MSM_CONSOLE,
1772 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1774 static const struct of_device_id msm_uartdm_table[] = {
1775 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1776 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1777 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1778 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1782 static int msm_serial_probe(struct platform_device *pdev)
1784 struct msm_port *msm_port;
1785 struct resource *resource;
1786 struct uart_port *port;
1787 const struct of_device_id *id;
1790 if (pdev->dev.of_node)
1791 line = of_alias_get_id(pdev->dev.of_node, "serial");
1796 line = atomic_inc_return(&msm_uart_next_id) - 1;
1798 if (unlikely(line < 0 || line >= UART_NR))
1801 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1803 port = msm_get_port_from_line(line);
1804 port->dev = &pdev->dev;
1805 msm_port = UART_TO_MSM(port);
1807 id = of_match_device(msm_uartdm_table, &pdev->dev);
1809 msm_port->is_uartdm = (unsigned long)id->data;
1811 msm_port->is_uartdm = 0;
1813 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1814 if (IS_ERR(msm_port->clk))
1815 return PTR_ERR(msm_port->clk);
1817 if (msm_port->is_uartdm) {
1818 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1819 if (IS_ERR(msm_port->pclk))
1820 return PTR_ERR(msm_port->pclk);
1823 port->uartclk = clk_get_rate(msm_port->clk);
1824 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1826 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1827 if (unlikely(!resource))
1829 port->mapbase = resource->start;
1831 irq = platform_get_irq(pdev, 0);
1832 if (unlikely(irq < 0))
1835 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
1837 platform_set_drvdata(pdev, port);
1839 return uart_add_one_port(&msm_uart_driver, port);
1842 static int msm_serial_remove(struct platform_device *pdev)
1844 struct uart_port *port = platform_get_drvdata(pdev);
1846 uart_remove_one_port(&msm_uart_driver, port);
1851 static const struct of_device_id msm_match_table[] = {
1852 { .compatible = "qcom,msm-uart" },
1853 { .compatible = "qcom,msm-uartdm" },
1856 MODULE_DEVICE_TABLE(of, msm_match_table);
1858 static int __maybe_unused msm_serial_suspend(struct device *dev)
1860 struct msm_port *port = dev_get_drvdata(dev);
1862 uart_suspend_port(&msm_uart_driver, &port->uart);
1867 static int __maybe_unused msm_serial_resume(struct device *dev)
1869 struct msm_port *port = dev_get_drvdata(dev);
1871 uart_resume_port(&msm_uart_driver, &port->uart);
1876 static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1877 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1880 static struct platform_driver msm_platform_driver = {
1881 .remove = msm_serial_remove,
1882 .probe = msm_serial_probe,
1884 .name = "msm_serial",
1885 .pm = &msm_serial_dev_pm_ops,
1886 .of_match_table = msm_match_table,
1890 static int __init msm_serial_init(void)
1894 ret = uart_register_driver(&msm_uart_driver);
1898 ret = platform_driver_register(&msm_platform_driver);
1900 uart_unregister_driver(&msm_uart_driver);
1902 pr_info("msm_serial: driver initialized\n");
1907 static void __exit msm_serial_exit(void)
1909 platform_driver_unregister(&msm_platform_driver);
1910 uart_unregister_driver(&msm_uart_driver);
1913 module_init(msm_serial_init);
1914 module_exit(msm_serial_exit);
1916 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1917 MODULE_DESCRIPTION("Driver for msm7x serial device");
1918 MODULE_LICENSE("GPL");