2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
3 * GT64260, MV64340, MV64360, GT96100, ... ).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
8 * have been created by Chris Zankel (formerly of MontaVista) but there
9 * is no proper Copyright so I'm not sure. Apparently, parts were also
10 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
13 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
19 * The MPSC interface is much like a typical network controller's interface.
20 * That is, you set up separate rings of descriptors for transmitting and
21 * receiving data. There is also a pool of buffers with (one buffer per
22 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
25 * The MPSC requires two other controllers to be able to work. The Baud Rate
26 * Generator (BRG) provides a clock at programmable frequencies which determines
27 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
28 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
29 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
30 * transmit and receive "engines" going (i.e., indicate data has been
31 * transmitted or received).
35 * 1) Some chips have an erratum where several regs cannot be
36 * read. To work around that, we keep a local copy of those regs in
39 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
40 * accesses system mem with coherency enabled. For that reason, the driver
41 * assumes that coherency for that ctlr has been disabled. This means
42 * that when in a cache coherent system, the driver has to manually manage
43 * the data cache on the areas that it touches because the dma_* macro are
46 * 3) There is an erratum (on PPC) where you can't use the instruction to do
47 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
48 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
54 #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
58 #include <linux/tty.h>
59 #include <linux/tty_flip.h>
60 #include <linux/ioport.h>
61 #include <linux/init.h>
62 #include <linux/console.h>
63 #include <linux/sysrq.h>
64 #include <linux/serial.h>
65 #include <linux/serial_core.h>
66 #include <linux/delay.h>
67 #include <linux/device.h>
68 #include <linux/dma-mapping.h>
69 #include <linux/mv643xx.h>
70 #include <linux/platform_device.h>
71 #include <linux/gfp.h>
76 #define MPSC_NUM_CTLRS 2
79 * Descriptors and buffers must be cache line aligned.
80 * Buffers lengths must be multiple of cache line size.
81 * Number of Tx & Rx descriptors must be powers of 2.
83 #define MPSC_RXR_ENTRIES 32
84 #define MPSC_RXRE_SIZE dma_get_cache_alignment()
85 #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
86 #define MPSC_RXBE_SIZE dma_get_cache_alignment()
87 #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
89 #define MPSC_TXR_ENTRIES 32
90 #define MPSC_TXRE_SIZE dma_get_cache_alignment()
91 #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
92 #define MPSC_TXBE_SIZE dma_get_cache_alignment()
93 #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
95 #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
96 + MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
98 /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
105 } __attribute((packed));
107 struct mpsc_tx_desc {
113 } __attribute((packed));
116 * Some regs that have the erratum that you can't read them are are shared
117 * between the two MPSC controllers. This struct contains those shared regs.
119 struct mpsc_shared_regs {
120 phys_addr_t mpsc_routing_base_p;
121 phys_addr_t sdma_intr_base_p;
123 void __iomem *mpsc_routing_base;
124 void __iomem *sdma_intr_base;
129 u32 SDMA_INTR_CAUSE_m;
130 u32 SDMA_INTR_MASK_m;
133 /* The main driver data structure */
134 struct mpsc_port_info {
135 struct uart_port port; /* Overlay uart_port structure */
137 /* Internal driver state for this ctlr */
141 /* Info passed in from platform */
142 u8 mirror_regs; /* Need to mirror regs? */
143 u8 cache_mgmt; /* Need manual cache mgmt? */
144 u8 brg_can_tune; /* BRG has baud tuning? */
152 /* Physical addresses of various blocks of registers (from platform) */
153 phys_addr_t mpsc_base_p;
154 phys_addr_t sdma_base_p;
155 phys_addr_t brg_base_p;
157 /* Virtual addresses of various blocks of registers (from platform) */
158 void __iomem *mpsc_base;
159 void __iomem *sdma_base;
160 void __iomem *brg_base;
162 /* Descriptor ring and buffer allocations */
164 dma_addr_t dma_region_p;
166 dma_addr_t rxr; /* Rx descriptor ring */
167 dma_addr_t rxr_p; /* Phys addr of rxr */
168 u8 *rxb; /* Rx Ring I/O buf */
169 u8 *rxb_p; /* Phys addr of rxb */
170 u32 rxr_posn; /* First desc w/ Rx data */
172 dma_addr_t txr; /* Tx descriptor ring */
173 dma_addr_t txr_p; /* Phys addr of txr */
174 u8 *txb; /* Tx Ring I/O buf */
175 u8 *txb_p; /* Phys addr of txb */
176 int txr_head; /* Where new data goes */
177 int txr_tail; /* Where sent data comes off */
178 spinlock_t tx_lock; /* transmit lock */
180 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
186 struct mpsc_shared_regs *shared_regs;
189 /* Hooks to platform-specific code */
190 int mpsc_platform_register_driver(void);
191 void mpsc_platform_unregister_driver(void);
193 /* Hooks back in to mpsc common to be called by platform-specific code */
194 struct mpsc_port_info *mpsc_device_probe(int index);
195 struct mpsc_port_info *mpsc_device_remove(int index);
197 /* Main MPSC Configuration Register Offsets */
198 #define MPSC_MMCRL 0x0000
199 #define MPSC_MMCRH 0x0004
200 #define MPSC_MPCR 0x0008
201 #define MPSC_CHR_1 0x000c
202 #define MPSC_CHR_2 0x0010
203 #define MPSC_CHR_3 0x0014
204 #define MPSC_CHR_4 0x0018
205 #define MPSC_CHR_5 0x001c
206 #define MPSC_CHR_6 0x0020
207 #define MPSC_CHR_7 0x0024
208 #define MPSC_CHR_8 0x0028
209 #define MPSC_CHR_9 0x002c
210 #define MPSC_CHR_10 0x0030
211 #define MPSC_CHR_11 0x0034
213 #define MPSC_MPCR_FRZ (1 << 9)
214 #define MPSC_MPCR_CL_5 0
215 #define MPSC_MPCR_CL_6 1
216 #define MPSC_MPCR_CL_7 2
217 #define MPSC_MPCR_CL_8 3
218 #define MPSC_MPCR_SBL_1 0
219 #define MPSC_MPCR_SBL_2 1
221 #define MPSC_CHR_2_TEV (1<<1)
222 #define MPSC_CHR_2_TA (1<<7)
223 #define MPSC_CHR_2_TTCS (1<<9)
224 #define MPSC_CHR_2_REV (1<<17)
225 #define MPSC_CHR_2_RA (1<<23)
226 #define MPSC_CHR_2_CRD (1<<25)
227 #define MPSC_CHR_2_EH (1<<31)
228 #define MPSC_CHR_2_PAR_ODD 0
229 #define MPSC_CHR_2_PAR_SPACE 1
230 #define MPSC_CHR_2_PAR_EVEN 2
231 #define MPSC_CHR_2_PAR_MARK 3
233 /* MPSC Signal Routing */
234 #define MPSC_MRR 0x0000
235 #define MPSC_RCRR 0x0004
236 #define MPSC_TCRR 0x0008
238 /* Serial DMA Controller Interface Registers */
239 #define SDMA_SDC 0x0000
240 #define SDMA_SDCM 0x0008
241 #define SDMA_RX_DESC 0x0800
242 #define SDMA_RX_BUF_PTR 0x0808
243 #define SDMA_SCRDP 0x0810
244 #define SDMA_TX_DESC 0x0c00
245 #define SDMA_SCTDP 0x0c10
246 #define SDMA_SFTDP 0x0c14
248 #define SDMA_DESC_CMDSTAT_PE (1<<0)
249 #define SDMA_DESC_CMDSTAT_CDL (1<<1)
250 #define SDMA_DESC_CMDSTAT_FR (1<<3)
251 #define SDMA_DESC_CMDSTAT_OR (1<<6)
252 #define SDMA_DESC_CMDSTAT_BR (1<<9)
253 #define SDMA_DESC_CMDSTAT_MI (1<<10)
254 #define SDMA_DESC_CMDSTAT_A (1<<11)
255 #define SDMA_DESC_CMDSTAT_AM (1<<12)
256 #define SDMA_DESC_CMDSTAT_CT (1<<13)
257 #define SDMA_DESC_CMDSTAT_C (1<<14)
258 #define SDMA_DESC_CMDSTAT_ES (1<<15)
259 #define SDMA_DESC_CMDSTAT_L (1<<16)
260 #define SDMA_DESC_CMDSTAT_F (1<<17)
261 #define SDMA_DESC_CMDSTAT_P (1<<18)
262 #define SDMA_DESC_CMDSTAT_EI (1<<23)
263 #define SDMA_DESC_CMDSTAT_O (1<<31)
265 #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
266 | SDMA_DESC_CMDSTAT_EI)
268 #define SDMA_SDC_RFT (1<<0)
269 #define SDMA_SDC_SFM (1<<1)
270 #define SDMA_SDC_BLMR (1<<6)
271 #define SDMA_SDC_BLMT (1<<7)
272 #define SDMA_SDC_POVR (1<<8)
273 #define SDMA_SDC_RIFB (1<<9)
275 #define SDMA_SDCM_ERD (1<<7)
276 #define SDMA_SDCM_AR (1<<15)
277 #define SDMA_SDCM_STD (1<<16)
278 #define SDMA_SDCM_TXD (1<<23)
279 #define SDMA_SDCM_AT (1<<31)
281 #define SDMA_0_CAUSE_RXBUF (1<<0)
282 #define SDMA_0_CAUSE_RXERR (1<<1)
283 #define SDMA_0_CAUSE_TXBUF (1<<2)
284 #define SDMA_0_CAUSE_TXEND (1<<3)
285 #define SDMA_1_CAUSE_RXBUF (1<<8)
286 #define SDMA_1_CAUSE_RXERR (1<<9)
287 #define SDMA_1_CAUSE_TXBUF (1<<10)
288 #define SDMA_1_CAUSE_TXEND (1<<11)
290 #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \
291 | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
292 #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \
293 | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
295 /* SDMA Interrupt registers */
296 #define SDMA_INTR_CAUSE 0x0000
297 #define SDMA_INTR_MASK 0x0080
299 /* Baud Rate Generator Interface Registers */
300 #define BRG_BCR 0x0000
301 #define BRG_BTR 0x0004
304 * Define how this driver is known to the outside (we've been assigned a
305 * range on the "Low-density serial ports" major).
307 #define MPSC_MAJOR 204
308 #define MPSC_MINOR_START 44
309 #define MPSC_DRIVER_NAME "MPSC"
310 #define MPSC_DEV_NAME "ttyMM"
311 #define MPSC_VERSION "1.00"
313 static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
314 static struct mpsc_shared_regs mpsc_shared_regs;
315 static struct uart_driver mpsc_reg;
317 static void mpsc_start_rx(struct mpsc_port_info *pi);
318 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
319 static void mpsc_release_port(struct uart_port *port);
321 ******************************************************************************
323 * Baud Rate Generator Routines (BRG)
325 ******************************************************************************
327 static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
331 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
332 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
334 if (pi->brg_can_tune)
339 writel(v, pi->brg_base + BRG_BCR);
341 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
342 pi->brg_base + BRG_BTR);
345 static void mpsc_brg_enable(struct mpsc_port_info *pi)
349 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
354 writel(v, pi->brg_base + BRG_BCR);
357 static void mpsc_brg_disable(struct mpsc_port_info *pi)
361 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
366 writel(v, pi->brg_base + BRG_BCR);
370 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
371 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
372 * However, the input clock is divided by 16 in the MPSC b/c of how
373 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
374 * calculation by 16 to account for that. So the real calculation
375 * that accounts for the way the mpsc is set up is:
376 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
378 static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
380 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
383 mpsc_brg_disable(pi);
384 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
385 v = (v & 0xffff0000) | (cdv & 0xffff);
389 writel(v, pi->brg_base + BRG_BCR);
394 ******************************************************************************
396 * Serial DMA Routines (SDMA)
398 ******************************************************************************
401 static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
405 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
406 pi->port.line, burst_size);
408 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
411 v = 0x0; /* 1 64-bit word */
412 else if (burst_size < 4)
413 v = 0x1; /* 2 64-bit words */
414 else if (burst_size < 8)
415 v = 0x2; /* 4 64-bit words */
417 v = 0x3; /* 8 64-bit words */
419 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
420 pi->sdma_base + SDMA_SDC);
423 static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
425 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
428 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
429 pi->sdma_base + SDMA_SDC);
430 mpsc_sdma_burstsize(pi, burst_size);
433 static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
437 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
439 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
440 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
448 pi->shared_regs->SDMA_INTR_MASK_m = v;
449 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
456 static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
460 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
462 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m
463 : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
471 pi->shared_regs->SDMA_INTR_MASK_m = v;
472 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
475 static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
477 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
480 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
481 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE
485 static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi,
486 struct mpsc_rx_desc *rxre_p)
488 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
489 pi->port.line, (u32)rxre_p);
491 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
494 static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi,
495 struct mpsc_tx_desc *txre_p)
497 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
498 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
501 static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
505 v = readl(pi->sdma_base + SDMA_SDCM);
511 writel(v, pi->sdma_base + SDMA_SDCM);
515 static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi)
517 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
520 static void mpsc_sdma_start_tx(struct mpsc_port_info *pi)
522 struct mpsc_tx_desc *txre, *txre_p;
524 /* If tx isn't running & there's a desc ready to go, start it */
525 if (!mpsc_sdma_tx_active(pi)) {
526 txre = (struct mpsc_tx_desc *)(pi->txr
527 + (pi->txr_tail * MPSC_TXRE_SIZE));
528 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
530 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
531 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
532 invalidate_dcache_range((ulong)txre,
533 (ulong)txre + MPSC_TXRE_SIZE);
536 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
537 txre_p = (struct mpsc_tx_desc *)
538 (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE));
540 mpsc_sdma_set_tx_ring(pi, txre_p);
541 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
546 static void mpsc_sdma_stop(struct mpsc_port_info *pi)
548 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
550 /* Abort any SDMA transfers */
551 mpsc_sdma_cmd(pi, 0);
552 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
554 /* Clear the SDMA current and first TX and RX pointers */
555 mpsc_sdma_set_tx_ring(pi, NULL);
556 mpsc_sdma_set_rx_ring(pi, NULL);
558 /* Disable interrupts */
559 mpsc_sdma_intr_mask(pi, 0xf);
560 mpsc_sdma_intr_ack(pi);
564 ******************************************************************************
566 * Multi-Protocol Serial Controller Routines (MPSC)
568 ******************************************************************************
571 static void mpsc_hw_init(struct mpsc_port_info *pi)
575 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
577 /* Set up clock routing */
578 if (pi->mirror_regs) {
579 v = pi->shared_regs->MPSC_MRR_m;
581 pi->shared_regs->MPSC_MRR_m = v;
582 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
584 v = pi->shared_regs->MPSC_RCRR_m;
585 v = (v & ~0xf0f) | 0x100;
586 pi->shared_regs->MPSC_RCRR_m = v;
587 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
589 v = pi->shared_regs->MPSC_TCRR_m;
590 v = (v & ~0xf0f) | 0x100;
591 pi->shared_regs->MPSC_TCRR_m = v;
592 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
594 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
596 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
598 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
599 v = (v & ~0xf0f) | 0x100;
600 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
602 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
603 v = (v & ~0xf0f) | 0x100;
604 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
607 /* Put MPSC in UART mode & enabel Tx/Rx egines */
608 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
610 /* No preamble, 16x divider, low-latency, */
611 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
612 mpsc_set_baudrate(pi, pi->default_baud);
614 if (pi->mirror_regs) {
615 pi->MPSC_CHR_1_m = 0;
616 pi->MPSC_CHR_2_m = 0;
618 writel(0, pi->mpsc_base + MPSC_CHR_1);
619 writel(0, pi->mpsc_base + MPSC_CHR_2);
620 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
621 writel(0, pi->mpsc_base + MPSC_CHR_4);
622 writel(0, pi->mpsc_base + MPSC_CHR_5);
623 writel(0, pi->mpsc_base + MPSC_CHR_6);
624 writel(0, pi->mpsc_base + MPSC_CHR_7);
625 writel(0, pi->mpsc_base + MPSC_CHR_8);
626 writel(0, pi->mpsc_base + MPSC_CHR_9);
627 writel(0, pi->mpsc_base + MPSC_CHR_10);
630 static void mpsc_enter_hunt(struct mpsc_port_info *pi)
632 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
634 if (pi->mirror_regs) {
635 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
636 pi->mpsc_base + MPSC_CHR_2);
637 /* Erratum prevents reading CHR_2 so just delay for a while */
640 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
641 pi->mpsc_base + MPSC_CHR_2);
643 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
648 static void mpsc_freeze(struct mpsc_port_info *pi)
652 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
654 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
655 readl(pi->mpsc_base + MPSC_MPCR);
660 writel(v, pi->mpsc_base + MPSC_MPCR);
663 static void mpsc_unfreeze(struct mpsc_port_info *pi)
667 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
668 readl(pi->mpsc_base + MPSC_MPCR);
673 writel(v, pi->mpsc_base + MPSC_MPCR);
675 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
678 static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
682 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
684 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
685 readl(pi->mpsc_base + MPSC_MPCR);
686 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
690 writel(v, pi->mpsc_base + MPSC_MPCR);
693 static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
697 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
700 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
701 readl(pi->mpsc_base + MPSC_MPCR);
703 v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
707 writel(v, pi->mpsc_base + MPSC_MPCR);
710 static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
714 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
716 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
717 readl(pi->mpsc_base + MPSC_CHR_2);
720 v = (v & ~0xc000c) | (p << 18) | (p << 2);
723 pi->MPSC_CHR_2_m = v;
724 writel(v, pi->mpsc_base + MPSC_CHR_2);
728 ******************************************************************************
730 * Driver Init Routines
732 ******************************************************************************
735 static void mpsc_init_hw(struct mpsc_port_info *pi)
737 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
739 mpsc_brg_init(pi, pi->brg_clk_src);
741 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
746 static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
750 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
753 if (!pi->dma_region) {
754 if (!dma_set_mask(pi->port.dev, 0xffffffff)) {
755 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
757 } else if ((pi->dma_region = dma_alloc_attrs(pi->port.dev,
759 &pi->dma_region_p, GFP_KERNEL,
760 DMA_ATTR_NON_CONSISTENT))
762 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
770 static void mpsc_free_ring_mem(struct mpsc_port_info *pi)
772 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
774 if (pi->dma_region) {
775 dma_free_attrs(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
776 pi->dma_region, pi->dma_region_p,
777 DMA_ATTR_NON_CONSISTENT);
778 pi->dma_region = NULL;
779 pi->dma_region_p = (dma_addr_t)NULL;
783 static void mpsc_init_rings(struct mpsc_port_info *pi)
785 struct mpsc_rx_desc *rxre;
786 struct mpsc_tx_desc *txre;
791 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
793 BUG_ON(pi->dma_region == NULL);
795 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
798 * Descriptors & buffers are multiples of cacheline size and must be
801 dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment());
802 dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment());
805 * Partition dma region into rx ring descriptor, rx buffers,
806 * tx ring descriptors, and tx buffers.
811 dp_p += MPSC_RXR_SIZE;
814 pi->rxb_p = (u8 *)dp_p;
816 dp_p += MPSC_RXB_SIZE;
823 dp_p += MPSC_TXR_SIZE;
826 pi->txb_p = (u8 *)dp_p;
831 /* Init rx ring descriptors */
837 for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
838 rxre = (struct mpsc_rx_desc *)dp;
840 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
841 rxre->bytecnt = cpu_to_be16(0);
842 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
843 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
844 | SDMA_DESC_CMDSTAT_L);
845 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
846 rxre->buf_ptr = cpu_to_be32(bp_p);
848 dp += MPSC_RXRE_SIZE;
849 dp_p += MPSC_RXRE_SIZE;
850 bp += MPSC_RXBE_SIZE;
851 bp_p += MPSC_RXBE_SIZE;
853 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
855 /* Init tx ring descriptors */
861 for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
862 txre = (struct mpsc_tx_desc *)dp;
864 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
865 txre->buf_ptr = cpu_to_be32(bp_p);
867 dp += MPSC_TXRE_SIZE;
868 dp_p += MPSC_TXRE_SIZE;
869 bp += MPSC_TXBE_SIZE;
870 bp_p += MPSC_TXBE_SIZE;
872 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
874 dma_cache_sync(pi->port.dev, (void *)pi->dma_region,
875 MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL);
876 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
877 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
878 flush_dcache_range((ulong)pi->dma_region,
879 (ulong)pi->dma_region
880 + MPSC_DMA_ALLOC_SIZE);
886 static void mpsc_uninit_rings(struct mpsc_port_info *pi)
888 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
890 BUG_ON(pi->dma_region == NULL);
906 static int mpsc_make_ready(struct mpsc_port_info *pi)
910 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
914 rc = mpsc_alloc_ring_mem(pi);
924 #ifdef CONFIG_CONSOLE_POLL
925 static int serial_polled;
929 ******************************************************************************
931 * Interrupt Handling Routines
933 ******************************************************************************
936 static int mpsc_rx_intr(struct mpsc_port_info *pi, unsigned long *flags)
938 struct mpsc_rx_desc *rxre;
939 struct tty_port *port = &pi->port.state->port;
940 u32 cmdstat, bytes_in, i;
943 char flag = TTY_NORMAL;
945 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
947 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
949 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
951 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
952 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
953 invalidate_dcache_range((ulong)rxre,
954 (ulong)rxre + MPSC_RXRE_SIZE);
958 * Loop through Rx descriptors handling ones that have been completed.
960 while (!((cmdstat = be32_to_cpu(rxre->cmdstat))
961 & SDMA_DESC_CMDSTAT_O)) {
962 bytes_in = be16_to_cpu(rxre->bytecnt);
963 #ifdef CONFIG_CONSOLE_POLL
964 if (unlikely(serial_polled)) {
969 /* Following use of tty struct directly is deprecated */
970 if (tty_buffer_request_room(port, bytes_in) < bytes_in) {
971 if (port->low_latency) {
972 spin_unlock_irqrestore(&pi->port.lock, *flags);
973 tty_flip_buffer_push(port);
974 spin_lock_irqsave(&pi->port.lock, *flags);
977 * If this failed then we will throw away the bytes
978 * but must do so to clear interrupts.
982 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
983 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE,
985 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
986 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
987 invalidate_dcache_range((ulong)bp,
988 (ulong)bp + MPSC_RXBE_SIZE);
992 * Other than for parity error, the manual provides little
993 * info on what data will be in a frame flagged by any of
994 * these errors. For parity error, it is the last byte in
995 * the buffer that had the error. As for the rest, I guess
996 * we'll assume there is no data in the buffer.
997 * If there is...it gets lost.
999 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1000 | SDMA_DESC_CMDSTAT_FR
1001 | SDMA_DESC_CMDSTAT_OR))) {
1003 pi->port.icount.rx++;
1005 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
1006 pi->port.icount.brk++;
1008 if (uart_handle_break(&pi->port))
1010 } else if (cmdstat & SDMA_DESC_CMDSTAT_FR) {
1011 pi->port.icount.frame++;
1012 } else if (cmdstat & SDMA_DESC_CMDSTAT_OR) {
1013 pi->port.icount.overrun++;
1016 cmdstat &= pi->port.read_status_mask;
1018 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
1020 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
1022 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
1024 else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
1028 if (uart_handle_sysrq_char(&pi->port, *bp)) {
1031 #ifdef CONFIG_CONSOLE_POLL
1032 if (unlikely(serial_polled)) {
1040 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1041 | SDMA_DESC_CMDSTAT_FR
1042 | SDMA_DESC_CMDSTAT_OR)))
1043 && !(cmdstat & pi->port.ignore_status_mask)) {
1044 tty_insert_flip_char(port, *bp, flag);
1046 for (i=0; i<bytes_in; i++)
1047 tty_insert_flip_char(port, *bp++, TTY_NORMAL);
1049 pi->port.icount.rx += bytes_in;
1053 rxre->bytecnt = cpu_to_be16(0);
1055 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
1056 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
1057 | SDMA_DESC_CMDSTAT_L);
1059 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1061 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1062 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1063 flush_dcache_range((ulong)rxre,
1064 (ulong)rxre + MPSC_RXRE_SIZE);
1067 /* Advance to next descriptor */
1068 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
1069 rxre = (struct mpsc_rx_desc *)
1070 (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE));
1071 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1073 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1074 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1075 invalidate_dcache_range((ulong)rxre,
1076 (ulong)rxre + MPSC_RXRE_SIZE);
1081 /* Restart rx engine, if its stopped */
1082 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1085 spin_unlock_irqrestore(&pi->port.lock, *flags);
1086 tty_flip_buffer_push(port);
1087 spin_lock_irqsave(&pi->port.lock, *flags);
1091 static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1093 struct mpsc_tx_desc *txre;
1095 txre = (struct mpsc_tx_desc *)(pi->txr
1096 + (pi->txr_head * MPSC_TXRE_SIZE));
1098 txre->bytecnt = cpu_to_be16(count);
1099 txre->shadow = txre->bytecnt;
1100 wmb(); /* ensure cmdstat is last field updated */
1101 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F
1102 | SDMA_DESC_CMDSTAT_L
1103 | ((intr) ? SDMA_DESC_CMDSTAT_EI : 0));
1105 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1107 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1108 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1109 flush_dcache_range((ulong)txre,
1110 (ulong)txre + MPSC_TXRE_SIZE);
1114 static void mpsc_copy_tx_data(struct mpsc_port_info *pi)
1116 struct circ_buf *xmit = &pi->port.state->xmit;
1120 /* Make sure the desc ring isn't full */
1121 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES)
1122 < (MPSC_TXR_ENTRIES - 1)) {
1123 if (pi->port.x_char) {
1125 * Ideally, we should use the TCS field in
1126 * CHR_1 to put the x_char out immediately but
1127 * errata prevents us from being able to read
1128 * CHR_2 to know that its safe to write to
1129 * CHR_1. Instead, just put it in-band with
1130 * all the other Tx data.
1132 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1133 *bp = pi->port.x_char;
1134 pi->port.x_char = 0;
1136 } else if (!uart_circ_empty(xmit)
1137 && !uart_tx_stopped(&pi->port)) {
1138 i = min((u32)MPSC_TXBE_SIZE,
1139 (u32)uart_circ_chars_pending(xmit));
1140 i = min(i, (u32)CIRC_CNT_TO_END(xmit->head, xmit->tail,
1142 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1143 memcpy(bp, &xmit->buf[xmit->tail], i);
1144 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
1146 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1147 uart_write_wakeup(&pi->port);
1148 } else { /* All tx data copied into ring bufs */
1152 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1154 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1155 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1156 flush_dcache_range((ulong)bp,
1157 (ulong)bp + MPSC_TXBE_SIZE);
1159 mpsc_setup_tx_desc(pi, i, 1);
1161 /* Advance to next descriptor */
1162 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1166 static int mpsc_tx_intr(struct mpsc_port_info *pi)
1168 struct mpsc_tx_desc *txre;
1170 unsigned long iflags;
1172 spin_lock_irqsave(&pi->tx_lock, iflags);
1174 if (!mpsc_sdma_tx_active(pi)) {
1175 txre = (struct mpsc_tx_desc *)(pi->txr
1176 + (pi->txr_tail * MPSC_TXRE_SIZE));
1178 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1180 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1181 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1182 invalidate_dcache_range((ulong)txre,
1183 (ulong)txre + MPSC_TXRE_SIZE);
1186 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
1188 pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
1189 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
1191 /* If no more data to tx, fall out of loop */
1192 if (pi->txr_head == pi->txr_tail)
1195 txre = (struct mpsc_tx_desc *)(pi->txr
1196 + (pi->txr_tail * MPSC_TXRE_SIZE));
1197 dma_cache_sync(pi->port.dev, (void *)txre,
1198 MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1199 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1200 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1201 invalidate_dcache_range((ulong)txre,
1202 (ulong)txre + MPSC_TXRE_SIZE);
1206 mpsc_copy_tx_data(pi);
1207 mpsc_sdma_start_tx(pi); /* start next desc if ready */
1210 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1215 * This is the driver's interrupt handler. To avoid a race, we first clear
1216 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1217 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1219 static irqreturn_t mpsc_sdma_intr(int irq, void *dev_id)
1221 struct mpsc_port_info *pi = dev_id;
1225 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1227 spin_lock_irqsave(&pi->port.lock, iflags);
1228 mpsc_sdma_intr_ack(pi);
1229 if (mpsc_rx_intr(pi, &iflags))
1231 if (mpsc_tx_intr(pi))
1233 spin_unlock_irqrestore(&pi->port.lock, iflags);
1235 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1240 ******************************************************************************
1242 * serial_core.c Interface routines
1244 ******************************************************************************
1246 static uint mpsc_tx_empty(struct uart_port *port)
1248 struct mpsc_port_info *pi =
1249 container_of(port, struct mpsc_port_info, port);
1253 spin_lock_irqsave(&pi->port.lock, iflags);
1254 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1255 spin_unlock_irqrestore(&pi->port.lock, iflags);
1260 static void mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1262 /* Have no way to set modem control lines AFAICT */
1265 static uint mpsc_get_mctrl(struct uart_port *port)
1267 struct mpsc_port_info *pi =
1268 container_of(port, struct mpsc_port_info, port);
1271 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m
1272 : readl(pi->mpsc_base + MPSC_CHR_10);
1276 mflags |= TIOCM_CTS;
1278 mflags |= TIOCM_CAR;
1280 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1283 static void mpsc_stop_tx(struct uart_port *port)
1285 struct mpsc_port_info *pi =
1286 container_of(port, struct mpsc_port_info, port);
1288 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1293 static void mpsc_start_tx(struct uart_port *port)
1295 struct mpsc_port_info *pi =
1296 container_of(port, struct mpsc_port_info, port);
1297 unsigned long iflags;
1299 spin_lock_irqsave(&pi->tx_lock, iflags);
1302 mpsc_copy_tx_data(pi);
1303 mpsc_sdma_start_tx(pi);
1305 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1307 pr_debug("mpsc_start_tx[%d]\n", port->line);
1310 static void mpsc_start_rx(struct mpsc_port_info *pi)
1312 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1315 mpsc_enter_hunt(pi);
1316 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1320 static void mpsc_stop_rx(struct uart_port *port)
1322 struct mpsc_port_info *pi =
1323 container_of(port, struct mpsc_port_info, port);
1325 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1327 if (pi->mirror_regs) {
1328 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA,
1329 pi->mpsc_base + MPSC_CHR_2);
1330 /* Erratum prevents reading CHR_2 so just delay for a while */
1333 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA,
1334 pi->mpsc_base + MPSC_CHR_2);
1336 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA)
1340 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1343 static void mpsc_break_ctl(struct uart_port *port, int ctl)
1345 struct mpsc_port_info *pi =
1346 container_of(port, struct mpsc_port_info, port);
1350 v = ctl ? 0x00ff0000 : 0;
1352 spin_lock_irqsave(&pi->port.lock, flags);
1353 if (pi->mirror_regs)
1354 pi->MPSC_CHR_1_m = v;
1355 writel(v, pi->mpsc_base + MPSC_CHR_1);
1356 spin_unlock_irqrestore(&pi->port.lock, flags);
1359 static int mpsc_startup(struct uart_port *port)
1361 struct mpsc_port_info *pi =
1362 container_of(port, struct mpsc_port_info, port);
1366 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1367 port->line, pi->port.irq);
1369 if ((rc = mpsc_make_ready(pi)) == 0) {
1370 /* Setup IRQ handler */
1371 mpsc_sdma_intr_ack(pi);
1373 /* If irq's are shared, need to set flag */
1374 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
1377 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1379 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1382 mpsc_sdma_intr_unmask(pi, 0xf);
1383 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p
1384 + (pi->rxr_posn * MPSC_RXRE_SIZE)));
1390 static void mpsc_shutdown(struct uart_port *port)
1392 struct mpsc_port_info *pi =
1393 container_of(port, struct mpsc_port_info, port);
1395 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1398 free_irq(pi->port.irq, pi);
1401 static void mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1402 struct ktermios *old)
1404 struct mpsc_port_info *pi =
1405 container_of(port, struct mpsc_port_info, port);
1408 u32 chr_bits, stop_bits, par;
1410 switch (termios->c_cflag & CSIZE) {
1412 chr_bits = MPSC_MPCR_CL_5;
1415 chr_bits = MPSC_MPCR_CL_6;
1418 chr_bits = MPSC_MPCR_CL_7;
1422 chr_bits = MPSC_MPCR_CL_8;
1426 if (termios->c_cflag & CSTOPB)
1427 stop_bits = MPSC_MPCR_SBL_2;
1429 stop_bits = MPSC_MPCR_SBL_1;
1431 par = MPSC_CHR_2_PAR_EVEN;
1432 if (termios->c_cflag & PARENB)
1433 if (termios->c_cflag & PARODD)
1434 par = MPSC_CHR_2_PAR_ODD;
1436 if (termios->c_cflag & CMSPAR) {
1437 if (termios->c_cflag & PARODD)
1438 par = MPSC_CHR_2_PAR_MARK;
1440 par = MPSC_CHR_2_PAR_SPACE;
1444 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1446 spin_lock_irqsave(&pi->port.lock, flags);
1448 uart_update_timeout(port, termios->c_cflag, baud);
1450 mpsc_set_char_length(pi, chr_bits);
1451 mpsc_set_stop_bit_length(pi, stop_bits);
1452 mpsc_set_parity(pi, par);
1453 mpsc_set_baudrate(pi, baud);
1455 /* Characters/events to read */
1456 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1458 if (termios->c_iflag & INPCK)
1459 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE
1460 | SDMA_DESC_CMDSTAT_FR;
1462 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1463 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1465 /* Characters/events to ignore */
1466 pi->port.ignore_status_mask = 0;
1468 if (termios->c_iflag & IGNPAR)
1469 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE
1470 | SDMA_DESC_CMDSTAT_FR;
1472 if (termios->c_iflag & IGNBRK) {
1473 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1475 if (termios->c_iflag & IGNPAR)
1476 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1479 if ((termios->c_cflag & CREAD)) {
1480 if (!pi->rcv_data) {
1484 } else if (pi->rcv_data) {
1489 spin_unlock_irqrestore(&pi->port.lock, flags);
1492 static const char *mpsc_type(struct uart_port *port)
1494 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1495 return MPSC_DRIVER_NAME;
1498 static int mpsc_request_port(struct uart_port *port)
1500 /* Should make chip/platform specific call */
1504 static void mpsc_release_port(struct uart_port *port)
1506 struct mpsc_port_info *pi =
1507 container_of(port, struct mpsc_port_info, port);
1510 mpsc_uninit_rings(pi);
1511 mpsc_free_ring_mem(pi);
1516 static void mpsc_config_port(struct uart_port *port, int flags)
1520 static int mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1522 struct mpsc_port_info *pi =
1523 container_of(port, struct mpsc_port_info, port);
1526 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1528 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1530 else if (pi->port.irq != ser->irq)
1532 else if (ser->io_type != SERIAL_IO_MEM)
1534 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1536 else if ((void *)pi->port.mapbase != ser->iomem_base)
1538 else if (pi->port.iobase != ser->port)
1540 else if (ser->hub6 != 0)
1545 #ifdef CONFIG_CONSOLE_POLL
1546 /* Serial polling routines for writing and reading from the uart while
1547 * in an interrupt or debug context.
1550 static char poll_buf[2048];
1551 static int poll_ptr;
1552 static int poll_cnt;
1553 static void mpsc_put_poll_char(struct uart_port *port,
1556 static int mpsc_get_poll_char(struct uart_port *port)
1558 struct mpsc_port_info *pi =
1559 container_of(port, struct mpsc_port_info, port);
1560 struct mpsc_rx_desc *rxre;
1561 u32 cmdstat, bytes_in, i;
1567 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
1571 return poll_buf[poll_ptr++];
1576 while (poll_cnt == 0) {
1577 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1578 (pi->rxr_posn*MPSC_RXRE_SIZE));
1579 dma_cache_sync(pi->port.dev, (void *)rxre,
1580 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1581 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1582 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1583 invalidate_dcache_range((ulong)rxre,
1584 (ulong)rxre + MPSC_RXRE_SIZE);
1587 * Loop through Rx descriptors handling ones that have
1590 while (poll_cnt == 0 &&
1591 !((cmdstat = be32_to_cpu(rxre->cmdstat)) &
1592 SDMA_DESC_CMDSTAT_O)){
1593 bytes_in = be16_to_cpu(rxre->bytecnt);
1594 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1595 dma_cache_sync(pi->port.dev, (void *) bp,
1596 MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
1597 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1598 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1599 invalidate_dcache_range((ulong)bp,
1600 (ulong)bp + MPSC_RXBE_SIZE);
1602 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1603 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
1604 !(cmdstat & pi->port.ignore_status_mask)) {
1605 poll_buf[poll_cnt] = *bp;
1608 for (i = 0; i < bytes_in; i++) {
1609 poll_buf[poll_cnt] = *bp++;
1612 pi->port.icount.rx += bytes_in;
1614 rxre->bytecnt = cpu_to_be16(0);
1616 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
1617 SDMA_DESC_CMDSTAT_EI |
1618 SDMA_DESC_CMDSTAT_F |
1619 SDMA_DESC_CMDSTAT_L);
1621 dma_cache_sync(pi->port.dev, (void *)rxre,
1622 MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
1623 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1624 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1625 flush_dcache_range((ulong)rxre,
1626 (ulong)rxre + MPSC_RXRE_SIZE);
1629 /* Advance to next descriptor */
1630 pi->rxr_posn = (pi->rxr_posn + 1) &
1631 (MPSC_RXR_ENTRIES - 1);
1632 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1633 (pi->rxr_posn * MPSC_RXRE_SIZE));
1634 dma_cache_sync(pi->port.dev, (void *)rxre,
1635 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1636 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1637 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1638 invalidate_dcache_range((ulong)rxre,
1639 (ulong)rxre + MPSC_RXRE_SIZE);
1643 /* Restart rx engine, if its stopped */
1644 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1649 return poll_buf[poll_ptr++];
1656 static void mpsc_put_poll_char(struct uart_port *port,
1659 struct mpsc_port_info *pi =
1660 container_of(port, struct mpsc_port_info, port);
1663 data = readl(pi->mpsc_base + MPSC_MPCR);
1664 writeb(c, pi->mpsc_base + MPSC_CHR_1);
1666 data = readl(pi->mpsc_base + MPSC_CHR_2);
1667 data |= MPSC_CHR_2_TTCS;
1668 writel(data, pi->mpsc_base + MPSC_CHR_2);
1671 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS);
1675 static const struct uart_ops mpsc_pops = {
1676 .tx_empty = mpsc_tx_empty,
1677 .set_mctrl = mpsc_set_mctrl,
1678 .get_mctrl = mpsc_get_mctrl,
1679 .stop_tx = mpsc_stop_tx,
1680 .start_tx = mpsc_start_tx,
1681 .stop_rx = mpsc_stop_rx,
1682 .break_ctl = mpsc_break_ctl,
1683 .startup = mpsc_startup,
1684 .shutdown = mpsc_shutdown,
1685 .set_termios = mpsc_set_termios,
1687 .release_port = mpsc_release_port,
1688 .request_port = mpsc_request_port,
1689 .config_port = mpsc_config_port,
1690 .verify_port = mpsc_verify_port,
1691 #ifdef CONFIG_CONSOLE_POLL
1692 .poll_get_char = mpsc_get_poll_char,
1693 .poll_put_char = mpsc_put_poll_char,
1698 ******************************************************************************
1700 * Console Interface Routines
1702 ******************************************************************************
1705 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
1706 static void mpsc_console_write(struct console *co, const char *s, uint count)
1708 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1709 u8 *bp, *dp, add_cr = 0;
1711 unsigned long iflags;
1713 spin_lock_irqsave(&pi->tx_lock, iflags);
1715 while (pi->txr_head != pi->txr_tail) {
1716 while (mpsc_sdma_tx_active(pi))
1718 mpsc_sdma_intr_ack(pi);
1722 while (mpsc_sdma_tx_active(pi))
1726 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1728 for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1738 if (*(s++) == '\n') { /* add '\r' after '\n' */
1747 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1749 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1750 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1751 flush_dcache_range((ulong)bp,
1752 (ulong)bp + MPSC_TXBE_SIZE);
1754 mpsc_setup_tx_desc(pi, i, 0);
1755 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1756 mpsc_sdma_start_tx(pi);
1758 while (mpsc_sdma_tx_active(pi))
1761 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1764 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1767 static int __init mpsc_console_setup(struct console *co, char *options)
1769 struct mpsc_port_info *pi;
1770 int baud, bits, parity, flow;
1772 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1774 if (co->index >= MPSC_NUM_CTLRS)
1777 pi = &mpsc_ports[co->index];
1779 baud = pi->default_baud;
1780 bits = pi->default_bits;
1781 parity = pi->default_parity;
1782 flow = pi->default_flow;
1787 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1790 uart_parse_options(options, &baud, &parity, &bits, &flow);
1792 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1795 static struct console mpsc_console = {
1796 .name = MPSC_DEV_NAME,
1797 .write = mpsc_console_write,
1798 .device = uart_console_device,
1799 .setup = mpsc_console_setup,
1800 .flags = CON_PRINTBUFFER,
1805 static int __init mpsc_late_console_init(void)
1807 pr_debug("mpsc_late_console_init: Enter\n");
1809 if (!(mpsc_console.flags & CON_ENABLED))
1810 register_console(&mpsc_console);
1814 late_initcall(mpsc_late_console_init);
1816 #define MPSC_CONSOLE &mpsc_console
1818 #define MPSC_CONSOLE NULL
1821 ******************************************************************************
1823 * Dummy Platform Driver to extract & map shared register regions
1825 ******************************************************************************
1827 static void mpsc_resource_err(char *s)
1829 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1832 static int mpsc_shared_map_regs(struct platform_device *pd)
1836 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1837 MPSC_ROUTING_BASE_ORDER))
1838 && request_mem_region(r->start,
1839 MPSC_ROUTING_REG_BLOCK_SIZE,
1840 "mpsc_routing_regs")) {
1841 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
1842 MPSC_ROUTING_REG_BLOCK_SIZE);
1843 mpsc_shared_regs.mpsc_routing_base_p = r->start;
1845 mpsc_resource_err("MPSC routing base");
1849 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1850 MPSC_SDMA_INTR_BASE_ORDER))
1851 && request_mem_region(r->start,
1852 MPSC_SDMA_INTR_REG_BLOCK_SIZE,
1853 "sdma_intr_regs")) {
1854 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1855 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1856 mpsc_shared_regs.sdma_intr_base_p = r->start;
1858 iounmap(mpsc_shared_regs.mpsc_routing_base);
1859 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1860 MPSC_ROUTING_REG_BLOCK_SIZE);
1861 mpsc_resource_err("SDMA intr base");
1868 static void mpsc_shared_unmap_regs(void)
1870 if (mpsc_shared_regs.mpsc_routing_base) {
1871 iounmap(mpsc_shared_regs.mpsc_routing_base);
1872 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1873 MPSC_ROUTING_REG_BLOCK_SIZE);
1875 if (mpsc_shared_regs.sdma_intr_base) {
1876 iounmap(mpsc_shared_regs.sdma_intr_base);
1877 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
1878 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1881 mpsc_shared_regs.mpsc_routing_base = NULL;
1882 mpsc_shared_regs.sdma_intr_base = NULL;
1884 mpsc_shared_regs.mpsc_routing_base_p = 0;
1885 mpsc_shared_regs.sdma_intr_base_p = 0;
1888 static int mpsc_shared_drv_probe(struct platform_device *dev)
1890 struct mpsc_shared_pdata *pdata;
1896 rc = mpsc_shared_map_regs(dev);
1900 pdata = dev_get_platdata(&dev->dev);
1902 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1903 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1904 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1905 mpsc_shared_regs.SDMA_INTR_CAUSE_m = pdata->intr_cause_val;
1906 mpsc_shared_regs.SDMA_INTR_MASK_m = pdata->intr_mask_val;
1911 static int mpsc_shared_drv_remove(struct platform_device *dev)
1916 mpsc_shared_unmap_regs();
1917 mpsc_shared_regs.MPSC_MRR_m = 0;
1918 mpsc_shared_regs.MPSC_RCRR_m = 0;
1919 mpsc_shared_regs.MPSC_TCRR_m = 0;
1920 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1921 mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1926 static struct platform_driver mpsc_shared_driver = {
1927 .probe = mpsc_shared_drv_probe,
1928 .remove = mpsc_shared_drv_remove,
1930 .name = MPSC_SHARED_NAME,
1935 ******************************************************************************
1937 * Driver Interface Routines
1939 ******************************************************************************
1941 static struct uart_driver mpsc_reg = {
1942 .owner = THIS_MODULE,
1943 .driver_name = MPSC_DRIVER_NAME,
1944 .dev_name = MPSC_DEV_NAME,
1945 .major = MPSC_MAJOR,
1946 .minor = MPSC_MINOR_START,
1947 .nr = MPSC_NUM_CTLRS,
1948 .cons = MPSC_CONSOLE,
1951 static int mpsc_drv_map_regs(struct mpsc_port_info *pi,
1952 struct platform_device *pd)
1956 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER))
1957 && request_mem_region(r->start, MPSC_REG_BLOCK_SIZE,
1959 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1960 pi->mpsc_base_p = r->start;
1962 mpsc_resource_err("MPSC base");
1966 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1967 MPSC_SDMA_BASE_ORDER))
1968 && request_mem_region(r->start,
1969 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1970 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1971 pi->sdma_base_p = r->start;
1973 mpsc_resource_err("SDMA base");
1977 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
1978 && request_mem_region(r->start,
1979 MPSC_BRG_REG_BLOCK_SIZE, "brg_regs")) {
1980 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1981 pi->brg_base_p = r->start;
1983 mpsc_resource_err("BRG base");
1989 if (pi->sdma_base) {
1990 iounmap(pi->sdma_base);
1991 pi->sdma_base = NULL;
1993 if (pi->mpsc_base) {
1994 iounmap(pi->mpsc_base);
1995 pi->mpsc_base = NULL;
2000 static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
2002 if (pi->mpsc_base) {
2003 iounmap(pi->mpsc_base);
2004 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
2006 if (pi->sdma_base) {
2007 iounmap(pi->sdma_base);
2008 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
2011 iounmap(pi->brg_base);
2012 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
2015 pi->mpsc_base = NULL;
2016 pi->sdma_base = NULL;
2017 pi->brg_base = NULL;
2019 pi->mpsc_base_p = 0;
2020 pi->sdma_base_p = 0;
2024 static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
2025 struct platform_device *pd, int num)
2027 struct mpsc_pdata *pdata;
2029 pdata = dev_get_platdata(&pd->dev);
2031 pi->port.uartclk = pdata->brg_clk_freq;
2032 pi->port.iotype = UPIO_MEM;
2033 pi->port.line = num;
2034 pi->port.type = PORT_MPSC;
2035 pi->port.fifosize = MPSC_TXBE_SIZE;
2036 pi->port.membase = pi->mpsc_base;
2037 pi->port.mapbase = (ulong)pi->mpsc_base;
2038 pi->port.ops = &mpsc_pops;
2040 pi->mirror_regs = pdata->mirror_regs;
2041 pi->cache_mgmt = pdata->cache_mgmt;
2042 pi->brg_can_tune = pdata->brg_can_tune;
2043 pi->brg_clk_src = pdata->brg_clk_src;
2044 pi->mpsc_max_idle = pdata->max_idle;
2045 pi->default_baud = pdata->default_baud;
2046 pi->default_bits = pdata->default_bits;
2047 pi->default_parity = pdata->default_parity;
2048 pi->default_flow = pdata->default_flow;
2050 /* Initial values of mirrored regs */
2051 pi->MPSC_CHR_1_m = pdata->chr_1_val;
2052 pi->MPSC_CHR_2_m = pdata->chr_2_val;
2053 pi->MPSC_CHR_10_m = pdata->chr_10_val;
2054 pi->MPSC_MPCR_m = pdata->mpcr_val;
2055 pi->BRG_BCR_m = pdata->bcr_val;
2057 pi->shared_regs = &mpsc_shared_regs;
2059 pi->port.irq = platform_get_irq(pd, 0);
2062 static int mpsc_drv_probe(struct platform_device *dev)
2064 struct mpsc_port_info *pi;
2067 dev_dbg(&dev->dev, "mpsc_drv_probe: Adding MPSC %d\n", dev->id);
2069 if (dev->id >= MPSC_NUM_CTLRS)
2072 pi = &mpsc_ports[dev->id];
2074 rc = mpsc_drv_map_regs(pi, dev);
2078 mpsc_drv_get_platform_data(pi, dev, dev->id);
2079 pi->port.dev = &dev->dev;
2081 rc = mpsc_make_ready(pi);
2085 spin_lock_init(&pi->tx_lock);
2086 rc = uart_add_one_port(&mpsc_reg, &pi->port);
2092 mpsc_release_port(&pi->port);
2094 mpsc_drv_unmap_regs(pi);
2098 static struct platform_driver mpsc_driver = {
2099 .probe = mpsc_drv_probe,
2101 .name = MPSC_CTLR_NAME,
2102 .suppress_bind_attrs = true,
2106 static int __init mpsc_drv_init(void)
2110 printk(KERN_INFO "Serial: MPSC driver\n");
2112 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2113 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2115 rc = uart_register_driver(&mpsc_reg);
2119 rc = platform_driver_register(&mpsc_shared_driver);
2121 goto err_unreg_uart;
2123 rc = platform_driver_register(&mpsc_driver);
2125 goto err_unreg_plat;
2129 platform_driver_unregister(&mpsc_shared_driver);
2131 uart_unregister_driver(&mpsc_reg);
2134 device_initcall(mpsc_drv_init);
2137 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
2138 MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver");
2139 MODULE_LICENSE("GPL");