1 // SPDX-License-Identifier: GPL-2.0
3 * Based on meson_uart.c, by AMLOGIC, INC.
5 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
9 #include <linux/console.h>
10 #include <linux/delay.h>
11 #include <linux/init.h>
13 #include <linux/iopoll.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/serial.h>
19 #include <linux/serial_core.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
23 /* Register offsets */
24 #define AML_UART_WFIFO 0x00
25 #define AML_UART_RFIFO 0x04
26 #define AML_UART_CONTROL 0x08
27 #define AML_UART_STATUS 0x0c
28 #define AML_UART_MISC 0x10
29 #define AML_UART_REG5 0x14
31 /* AML_UART_CONTROL bits */
32 #define AML_UART_TX_EN BIT(12)
33 #define AML_UART_RX_EN BIT(13)
34 #define AML_UART_TWO_WIRE_EN BIT(15)
35 #define AML_UART_STOP_BIT_LEN_MASK (0x03 << 16)
36 #define AML_UART_STOP_BIT_1SB (0x00 << 16)
37 #define AML_UART_STOP_BIT_2SB (0x01 << 16)
38 #define AML_UART_PARITY_TYPE BIT(18)
39 #define AML_UART_PARITY_EN BIT(19)
40 #define AML_UART_TX_RST BIT(22)
41 #define AML_UART_RX_RST BIT(23)
42 #define AML_UART_CLEAR_ERR BIT(24)
43 #define AML_UART_RX_INT_EN BIT(27)
44 #define AML_UART_TX_INT_EN BIT(28)
45 #define AML_UART_DATA_LEN_MASK (0x03 << 20)
46 #define AML_UART_DATA_LEN_8BIT (0x00 << 20)
47 #define AML_UART_DATA_LEN_7BIT (0x01 << 20)
48 #define AML_UART_DATA_LEN_6BIT (0x02 << 20)
49 #define AML_UART_DATA_LEN_5BIT (0x03 << 20)
51 /* AML_UART_STATUS bits */
52 #define AML_UART_PARITY_ERR BIT(16)
53 #define AML_UART_FRAME_ERR BIT(17)
54 #define AML_UART_TX_FIFO_WERR BIT(18)
55 #define AML_UART_RX_EMPTY BIT(20)
56 #define AML_UART_TX_FULL BIT(21)
57 #define AML_UART_TX_EMPTY BIT(22)
58 #define AML_UART_XMIT_BUSY BIT(25)
59 #define AML_UART_ERR (AML_UART_PARITY_ERR | \
60 AML_UART_FRAME_ERR | \
61 AML_UART_TX_FIFO_WERR)
63 /* AML_UART_MISC bits */
64 #define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8)
65 #define AML_UART_RECV_IRQ(c) ((c) & 0xff)
67 /* AML_UART_REG5 bits */
68 #define AML_UART_BAUD_MASK 0x7fffff
69 #define AML_UART_BAUD_USE BIT(23)
70 #define AML_UART_BAUD_XTAL BIT(24)
72 #define AML_UART_PORT_NUM 12
73 #define AML_UART_PORT_OFFSET 6
74 #define AML_UART_DEV_NAME "ttyAML"
76 #define AML_UART_POLL_USEC 5
77 #define AML_UART_TIMEOUT_USEC 10000
79 static struct uart_driver meson_uart_driver;
81 static struct uart_port *meson_ports[AML_UART_PORT_NUM];
83 static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
87 static unsigned int meson_uart_get_mctrl(struct uart_port *port)
92 static unsigned int meson_uart_tx_empty(struct uart_port *port)
96 val = readl(port->membase + AML_UART_STATUS);
97 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY);
98 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0;
101 static void meson_uart_stop_tx(struct uart_port *port)
105 val = readl(port->membase + AML_UART_CONTROL);
106 val &= ~AML_UART_TX_INT_EN;
107 writel(val, port->membase + AML_UART_CONTROL);
110 static void meson_uart_stop_rx(struct uart_port *port)
114 val = readl(port->membase + AML_UART_CONTROL);
115 val &= ~AML_UART_RX_EN;
116 writel(val, port->membase + AML_UART_CONTROL);
119 static void meson_uart_shutdown(struct uart_port *port)
124 free_irq(port->irq, port);
126 spin_lock_irqsave(&port->lock, flags);
128 val = readl(port->membase + AML_UART_CONTROL);
129 val &= ~AML_UART_RX_EN;
130 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
131 writel(val, port->membase + AML_UART_CONTROL);
133 spin_unlock_irqrestore(&port->lock, flags);
136 static void meson_uart_start_tx(struct uart_port *port)
138 struct circ_buf *xmit = &port->state->xmit;
142 if (uart_tx_stopped(port)) {
143 meson_uart_stop_tx(port);
147 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
149 writel(port->x_char, port->membase + AML_UART_WFIFO);
155 if (uart_circ_empty(xmit))
158 ch = xmit->buf[xmit->tail];
159 writel(ch, port->membase + AML_UART_WFIFO);
160 xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1);
164 if (!uart_circ_empty(xmit)) {
165 val = readl(port->membase + AML_UART_CONTROL);
166 val |= AML_UART_TX_INT_EN;
167 writel(val, port->membase + AML_UART_CONTROL);
170 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
171 uart_write_wakeup(port);
174 static void meson_receive_chars(struct uart_port *port)
176 struct tty_port *tport = &port->state->port;
178 u32 ostatus, status, ch, mode;
183 ostatus = status = readl(port->membase + AML_UART_STATUS);
185 if (status & AML_UART_ERR) {
186 if (status & AML_UART_TX_FIFO_WERR)
187 port->icount.overrun++;
188 else if (status & AML_UART_FRAME_ERR)
189 port->icount.frame++;
190 else if (status & AML_UART_PARITY_ERR)
191 port->icount.frame++;
193 mode = readl(port->membase + AML_UART_CONTROL);
194 mode |= AML_UART_CLEAR_ERR;
195 writel(mode, port->membase + AML_UART_CONTROL);
197 /* It doesn't clear to 0 automatically */
198 mode &= ~AML_UART_CLEAR_ERR;
199 writel(mode, port->membase + AML_UART_CONTROL);
201 status &= port->read_status_mask;
202 if (status & AML_UART_FRAME_ERR)
204 else if (status & AML_UART_PARITY_ERR)
208 ch = readl(port->membase + AML_UART_RFIFO);
211 if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) {
214 if (uart_handle_break(port))
218 if (uart_handle_sysrq_char(port, ch))
221 if ((status & port->ignore_status_mask) == 0)
222 tty_insert_flip_char(tport, ch, flag);
224 if (status & AML_UART_TX_FIFO_WERR)
225 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
227 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
229 spin_unlock(&port->lock);
230 tty_flip_buffer_push(tport);
231 spin_lock(&port->lock);
234 static irqreturn_t meson_uart_interrupt(int irq, void *dev_id)
236 struct uart_port *port = (struct uart_port *)dev_id;
238 spin_lock(&port->lock);
240 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
241 meson_receive_chars(port);
243 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
244 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
245 meson_uart_start_tx(port);
248 spin_unlock(&port->lock);
253 static const char *meson_uart_type(struct uart_port *port)
255 return (port->type == PORT_MESON) ? "meson_uart" : NULL;
259 * This function is called only from probe() using a temporary io mapping
260 * in order to perform a reset before setting up the device. Since the
261 * temporarily mapped region was successfully requested, there can be no
262 * console on this port at this time. Hence it is not necessary for this
263 * function to acquire the port->lock. (Since there is no console on this
264 * port at this time, the port->lock is not initialized yet.)
266 static void meson_uart_reset(struct uart_port *port)
270 val = readl(port->membase + AML_UART_CONTROL);
271 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR);
272 writel(val, port->membase + AML_UART_CONTROL);
274 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR);
275 writel(val, port->membase + AML_UART_CONTROL);
278 static int meson_uart_startup(struct uart_port *port)
284 spin_lock_irqsave(&port->lock, flags);
286 val = readl(port->membase + AML_UART_CONTROL);
287 val |= AML_UART_CLEAR_ERR;
288 writel(val, port->membase + AML_UART_CONTROL);
289 val &= ~AML_UART_CLEAR_ERR;
290 writel(val, port->membase + AML_UART_CONTROL);
292 val |= (AML_UART_RX_EN | AML_UART_TX_EN);
293 writel(val, port->membase + AML_UART_CONTROL);
295 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
296 writel(val, port->membase + AML_UART_CONTROL);
298 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
299 writel(val, port->membase + AML_UART_MISC);
301 spin_unlock_irqrestore(&port->lock, flags);
303 ret = request_irq(port->irq, meson_uart_interrupt, 0,
309 static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
313 while (!meson_uart_tx_empty(port))
316 if (port->uartclk == 24000000) {
317 val = ((port->uartclk / 3) / baud) - 1;
318 val |= AML_UART_BAUD_XTAL;
320 val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;
322 val |= AML_UART_BAUD_USE;
323 writel(val, port->membase + AML_UART_REG5);
326 static void meson_uart_set_termios(struct uart_port *port,
327 struct ktermios *termios,
328 struct ktermios *old)
330 unsigned int cflags, iflags, baud;
334 spin_lock_irqsave(&port->lock, flags);
336 cflags = termios->c_cflag;
337 iflags = termios->c_iflag;
339 val = readl(port->membase + AML_UART_CONTROL);
341 val &= ~AML_UART_DATA_LEN_MASK;
342 switch (cflags & CSIZE) {
344 val |= AML_UART_DATA_LEN_8BIT;
347 val |= AML_UART_DATA_LEN_7BIT;
350 val |= AML_UART_DATA_LEN_6BIT;
353 val |= AML_UART_DATA_LEN_5BIT;
358 val |= AML_UART_PARITY_EN;
360 val &= ~AML_UART_PARITY_EN;
363 val |= AML_UART_PARITY_TYPE;
365 val &= ~AML_UART_PARITY_TYPE;
367 val &= ~AML_UART_STOP_BIT_LEN_MASK;
369 val |= AML_UART_STOP_BIT_2SB;
371 val |= AML_UART_STOP_BIT_1SB;
373 if (cflags & CRTSCTS) {
374 if (port->flags & UPF_HARD_FLOW)
375 val &= ~AML_UART_TWO_WIRE_EN;
377 termios->c_cflag &= ~CRTSCTS;
379 val |= AML_UART_TWO_WIRE_EN;
382 writel(val, port->membase + AML_UART_CONTROL);
384 baud = uart_get_baud_rate(port, termios, old, 50, 4000000);
385 meson_uart_change_speed(port, baud);
387 port->read_status_mask = AML_UART_TX_FIFO_WERR;
389 port->read_status_mask |= AML_UART_PARITY_ERR |
392 port->ignore_status_mask = 0;
394 port->ignore_status_mask |= AML_UART_PARITY_ERR |
397 uart_update_timeout(port, termios->c_cflag, baud);
398 spin_unlock_irqrestore(&port->lock, flags);
401 static int meson_uart_verify_port(struct uart_port *port,
402 struct serial_struct *ser)
406 if (port->type != PORT_MESON)
408 if (port->irq != ser->irq)
410 if (ser->baud_base < 9600)
415 static void meson_uart_release_port(struct uart_port *port)
417 devm_iounmap(port->dev, port->membase);
418 port->membase = NULL;
419 devm_release_mem_region(port->dev, port->mapbase, port->mapsize);
422 static int meson_uart_request_port(struct uart_port *port)
424 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize,
425 dev_name(port->dev))) {
426 dev_err(port->dev, "Memory region busy\n");
430 port->membase = devm_ioremap(port->dev, port->mapbase,
438 static void meson_uart_config_port(struct uart_port *port, int flags)
440 if (flags & UART_CONFIG_TYPE) {
441 port->type = PORT_MESON;
442 meson_uart_request_port(port);
446 #ifdef CONFIG_CONSOLE_POLL
448 * Console polling routines for writing and reading from the uart while
449 * in an interrupt or debug context (i.e. kgdb).
452 static int meson_uart_poll_get_char(struct uart_port *port)
457 spin_lock_irqsave(&port->lock, flags);
459 if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)
462 c = readl(port->membase + AML_UART_RFIFO);
464 spin_unlock_irqrestore(&port->lock, flags);
469 static void meson_uart_poll_put_char(struct uart_port *port, unsigned char c)
475 spin_lock_irqsave(&port->lock, flags);
477 /* Wait until FIFO is empty or timeout */
478 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
479 reg & AML_UART_TX_EMPTY,
481 AML_UART_TIMEOUT_USEC);
482 if (ret == -ETIMEDOUT) {
483 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n");
487 /* Write the character */
488 writel(c, port->membase + AML_UART_WFIFO);
490 /* Wait until FIFO is empty or timeout */
491 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
492 reg & AML_UART_TX_EMPTY,
494 AML_UART_TIMEOUT_USEC);
495 if (ret == -ETIMEDOUT)
496 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n");
499 spin_unlock_irqrestore(&port->lock, flags);
502 #endif /* CONFIG_CONSOLE_POLL */
504 static const struct uart_ops meson_uart_ops = {
505 .set_mctrl = meson_uart_set_mctrl,
506 .get_mctrl = meson_uart_get_mctrl,
507 .tx_empty = meson_uart_tx_empty,
508 .start_tx = meson_uart_start_tx,
509 .stop_tx = meson_uart_stop_tx,
510 .stop_rx = meson_uart_stop_rx,
511 .startup = meson_uart_startup,
512 .shutdown = meson_uart_shutdown,
513 .set_termios = meson_uart_set_termios,
514 .type = meson_uart_type,
515 .config_port = meson_uart_config_port,
516 .request_port = meson_uart_request_port,
517 .release_port = meson_uart_release_port,
518 .verify_port = meson_uart_verify_port,
519 #ifdef CONFIG_CONSOLE_POLL
520 .poll_get_char = meson_uart_poll_get_char,
521 .poll_put_char = meson_uart_poll_put_char,
525 #ifdef CONFIG_SERIAL_MESON_CONSOLE
526 static void meson_uart_enable_tx_engine(struct uart_port *port)
530 val = readl(port->membase + AML_UART_CONTROL);
531 val |= AML_UART_TX_EN;
532 writel(val, port->membase + AML_UART_CONTROL);
535 static void meson_console_putchar(struct uart_port *port, int ch)
540 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
542 writel(ch, port->membase + AML_UART_WFIFO);
545 static void meson_serial_port_write(struct uart_port *port, const char *s,
552 local_irq_save(flags);
555 } else if (oops_in_progress) {
556 locked = spin_trylock(&port->lock);
558 spin_lock(&port->lock);
562 val = readl(port->membase + AML_UART_CONTROL);
563 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN);
564 writel(tmp, port->membase + AML_UART_CONTROL);
566 uart_console_write(port, s, count, meson_console_putchar);
567 writel(val, port->membase + AML_UART_CONTROL);
570 spin_unlock(&port->lock);
571 local_irq_restore(flags);
574 static void meson_serial_console_write(struct console *co, const char *s,
577 struct uart_port *port;
579 port = meson_ports[co->index];
583 meson_serial_port_write(port, s, count);
586 static int meson_serial_console_setup(struct console *co, char *options)
588 struct uart_port *port;
594 if (co->index < 0 || co->index >= AML_UART_PORT_NUM)
597 port = meson_ports[co->index];
598 if (!port || !port->membase)
601 meson_uart_enable_tx_engine(port);
604 uart_parse_options(options, &baud, &parity, &bits, &flow);
606 return uart_set_options(port, co, baud, parity, bits, flow);
609 static struct console meson_serial_console = {
610 .name = AML_UART_DEV_NAME,
611 .write = meson_serial_console_write,
612 .device = uart_console_device,
613 .setup = meson_serial_console_setup,
614 .flags = CON_PRINTBUFFER,
616 .data = &meson_uart_driver,
619 static int __init meson_serial_console_init(void)
621 register_console(&meson_serial_console);
624 console_initcall(meson_serial_console_init);
626 static void meson_serial_early_console_write(struct console *co,
630 struct earlycon_device *dev = co->data;
632 meson_serial_port_write(&dev->port, s, count);
636 meson_serial_early_console_setup(struct earlycon_device *device, const char *opt)
638 if (!device->port.membase)
641 meson_uart_enable_tx_engine(&device->port);
642 device->con->write = meson_serial_early_console_write;
645 /* Legacy bindings, should be removed when no more used */
646 OF_EARLYCON_DECLARE(meson, "amlogic,meson-uart",
647 meson_serial_early_console_setup);
648 /* Stable bindings */
649 OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart",
650 meson_serial_early_console_setup);
652 #define MESON_SERIAL_CONSOLE (&meson_serial_console)
654 #define MESON_SERIAL_CONSOLE NULL
657 static struct uart_driver meson_uart_driver = {
658 .owner = THIS_MODULE,
659 .driver_name = "meson_uart",
660 .dev_name = AML_UART_DEV_NAME,
661 .nr = AML_UART_PORT_NUM,
662 .cons = MESON_SERIAL_CONSOLE,
665 static inline struct clk *meson_uart_probe_clock(struct device *dev,
668 struct clk *clk = NULL;
671 clk = devm_clk_get(dev, id);
675 ret = clk_prepare_enable(clk);
677 dev_err(dev, "couldn't enable clk\n");
681 devm_add_action_or_reset(dev,
682 (void(*)(void *))clk_disable_unprepare,
689 * This function gets clocks in the legacy non-stable DT bindings.
690 * This code will be remove once all the platforms switch to the
693 static int meson_uart_probe_clocks_legacy(struct platform_device *pdev,
694 struct uart_port *port)
696 struct clk *clk = NULL;
698 clk = meson_uart_probe_clock(&pdev->dev, NULL);
702 port->uartclk = clk_get_rate(clk);
707 static int meson_uart_probe_clocks(struct platform_device *pdev,
708 struct uart_port *port)
710 struct clk *clk_xtal = NULL;
711 struct clk *clk_pclk = NULL;
712 struct clk *clk_baud = NULL;
714 clk_pclk = meson_uart_probe_clock(&pdev->dev, "pclk");
715 if (IS_ERR(clk_pclk))
716 return PTR_ERR(clk_pclk);
718 clk_xtal = meson_uart_probe_clock(&pdev->dev, "xtal");
719 if (IS_ERR(clk_xtal))
720 return PTR_ERR(clk_xtal);
722 clk_baud = meson_uart_probe_clock(&pdev->dev, "baud");
723 if (IS_ERR(clk_baud))
724 return PTR_ERR(clk_baud);
726 port->uartclk = clk_get_rate(clk_baud);
731 static int meson_uart_probe(struct platform_device *pdev)
733 struct resource *res_mem;
734 struct uart_port *port;
735 u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */
740 if (pdev->dev.of_node)
741 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
746 for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) {
747 if (!meson_ports[id]) {
754 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM)
757 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
761 irq = platform_get_irq(pdev, 0);
765 of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize);
766 has_rtscts = of_property_read_bool(pdev->dev.of_node, "uart-has-rtscts");
768 if (meson_ports[pdev->id]) {
769 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
773 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL);
777 /* Use legacy way until all platforms switch to new bindings */
778 if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart"))
779 ret = meson_uart_probe_clocks_legacy(pdev, port);
781 ret = meson_uart_probe_clocks(pdev, port);
786 port->iotype = UPIO_MEM;
787 port->mapbase = res_mem->start;
788 port->mapsize = resource_size(res_mem);
790 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY;
792 port->flags |= UPF_HARD_FLOW;
793 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MESON_CONSOLE);
794 port->dev = &pdev->dev;
795 port->line = pdev->id;
796 port->type = PORT_MESON;
798 port->ops = &meson_uart_ops;
799 port->fifosize = fifosize;
801 meson_ports[pdev->id] = port;
802 platform_set_drvdata(pdev, port);
804 /* reset port before registering (and possibly registering console) */
805 if (meson_uart_request_port(port) >= 0) {
806 meson_uart_reset(port);
807 meson_uart_release_port(port);
810 ret = uart_add_one_port(&meson_uart_driver, port);
812 meson_ports[pdev->id] = NULL;
817 static int meson_uart_remove(struct platform_device *pdev)
819 struct uart_port *port;
821 port = platform_get_drvdata(pdev);
822 uart_remove_one_port(&meson_uart_driver, port);
823 meson_ports[pdev->id] = NULL;
828 static const struct of_device_id meson_uart_dt_match[] = {
829 /* Legacy bindings, should be removed when no more used */
830 { .compatible = "amlogic,meson-uart" },
831 /* Stable bindings */
832 { .compatible = "amlogic,meson6-uart" },
833 { .compatible = "amlogic,meson8-uart" },
834 { .compatible = "amlogic,meson8b-uart" },
835 { .compatible = "amlogic,meson-gx-uart" },
838 MODULE_DEVICE_TABLE(of, meson_uart_dt_match);
840 static struct platform_driver meson_uart_platform_driver = {
841 .probe = meson_uart_probe,
842 .remove = meson_uart_remove,
844 .name = "meson_uart",
845 .of_match_table = meson_uart_dt_match,
849 static int __init meson_uart_init(void)
853 ret = uart_register_driver(&meson_uart_driver);
857 ret = platform_driver_register(&meson_uart_platform_driver);
859 uart_unregister_driver(&meson_uart_driver);
864 static void __exit meson_uart_exit(void)
866 platform_driver_unregister(&meson_uart_platform_driver);
867 uart_unregister_driver(&meson_uart_driver);
870 module_init(meson_uart_init);
871 module_exit(meson_uart_exit);
873 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
874 MODULE_DESCRIPTION("Amlogic Meson serial port driver");
875 MODULE_LICENSE("GPL v2");