1 // SPDX-License-Identifier: GPL-2.0+
2 /****************************************************************************/
5 * mcf.c -- Freescale ColdFire UART driver
7 * (C) Copyright 2003-2007, Greg Ungerer <gerg@uclinux.org>
10 /****************************************************************************/
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/console.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial.h>
20 #include <linux/serial_core.h>
22 #include <linux/uaccess.h>
23 #include <linux/platform_device.h>
24 #include <asm/coldfire.h>
25 #include <asm/mcfsim.h>
26 #include <asm/mcfuart.h>
27 #include <asm/nettel.h>
29 /****************************************************************************/
32 * Some boards implement the DTR/DCD lines using GPIO lines, most
33 * don't. Dummy out the access macros for those that don't. Those
34 * that do should define these macros somewhere in there board
35 * specific inlude files.
37 #if !defined(mcf_getppdcd)
38 #define mcf_getppdcd(p) (1)
40 #if !defined(mcf_getppdtr)
41 #define mcf_getppdtr(p) (1)
43 #if !defined(mcf_setppdtr)
44 #define mcf_setppdtr(p, v) do { } while (0)
47 /****************************************************************************/
50 * Local per-uart structure.
53 struct uart_port port;
54 unsigned int sigs; /* Local copy of line sigs */
55 unsigned char imr; /* Local IMR mirror */
58 /****************************************************************************/
60 static unsigned int mcf_tx_empty(struct uart_port *port)
62 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
66 /****************************************************************************/
68 static unsigned int mcf_get_mctrl(struct uart_port *port)
70 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
73 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
75 sigs |= (pp->sigs & TIOCM_RTS);
76 sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
77 sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
82 /****************************************************************************/
84 static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
86 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
89 mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
91 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
96 /****************************************************************************/
98 static void mcf_start_tx(struct uart_port *port)
100 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
102 if (port->rs485.flags & SER_RS485_ENABLED) {
103 /* Enable Transmitter */
104 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
105 /* Manually assert RTS */
106 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
108 pp->imr |= MCFUART_UIR_TXREADY;
109 writeb(pp->imr, port->membase + MCFUART_UIMR);
112 /****************************************************************************/
114 static void mcf_stop_tx(struct uart_port *port)
116 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
118 pp->imr &= ~MCFUART_UIR_TXREADY;
119 writeb(pp->imr, port->membase + MCFUART_UIMR);
122 /****************************************************************************/
124 static void mcf_stop_rx(struct uart_port *port)
126 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
128 pp->imr &= ~MCFUART_UIR_RXREADY;
129 writeb(pp->imr, port->membase + MCFUART_UIMR);
132 /****************************************************************************/
134 static void mcf_break_ctl(struct uart_port *port, int break_state)
138 spin_lock_irqsave(&port->lock, flags);
139 if (break_state == -1)
140 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
142 writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
143 spin_unlock_irqrestore(&port->lock, flags);
146 /****************************************************************************/
148 static int mcf_startup(struct uart_port *port)
150 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
153 spin_lock_irqsave(&port->lock, flags);
155 /* Reset UART, get it into known state... */
156 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
157 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
159 /* Enable the UART transmitter and receiver */
160 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
161 port->membase + MCFUART_UCR);
163 /* Enable RX interrupts now */
164 pp->imr = MCFUART_UIR_RXREADY;
165 writeb(pp->imr, port->membase + MCFUART_UIMR);
167 spin_unlock_irqrestore(&port->lock, flags);
172 /****************************************************************************/
174 static void mcf_shutdown(struct uart_port *port)
176 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
179 spin_lock_irqsave(&port->lock, flags);
181 /* Disable all interrupts now */
183 writeb(pp->imr, port->membase + MCFUART_UIMR);
185 /* Disable UART transmitter and receiver */
186 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
187 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
189 spin_unlock_irqrestore(&port->lock, flags);
192 /****************************************************************************/
194 static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
195 struct ktermios *old)
198 unsigned int baud, baudclk;
199 #if defined(CONFIG_M5272)
202 unsigned char mr1, mr2;
204 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
205 #if defined(CONFIG_M5272)
206 baudclk = (MCF_BUSCLK / baud) / 32;
207 baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
209 baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
212 mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
215 switch (termios->c_cflag & CSIZE) {
216 case CS5: mr1 |= MCFUART_MR1_CS5; break;
217 case CS6: mr1 |= MCFUART_MR1_CS6; break;
218 case CS7: mr1 |= MCFUART_MR1_CS7; break;
220 default: mr1 |= MCFUART_MR1_CS8; break;
223 if (termios->c_cflag & PARENB) {
224 if (termios->c_cflag & CMSPAR) {
225 if (termios->c_cflag & PARODD)
226 mr1 |= MCFUART_MR1_PARITYMARK;
228 mr1 |= MCFUART_MR1_PARITYSPACE;
230 if (termios->c_cflag & PARODD)
231 mr1 |= MCFUART_MR1_PARITYODD;
233 mr1 |= MCFUART_MR1_PARITYEVEN;
236 mr1 |= MCFUART_MR1_PARITYNONE;
240 * FIXME: port->read_status_mask and port->ignore_status_mask
241 * need to be initialized based on termios settings for
242 * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
245 if (termios->c_cflag & CSTOPB)
246 mr2 |= MCFUART_MR2_STOP2;
248 mr2 |= MCFUART_MR2_STOP1;
250 if (termios->c_cflag & CRTSCTS) {
251 mr1 |= MCFUART_MR1_RXRTS;
252 mr2 |= MCFUART_MR2_TXCTS;
255 spin_lock_irqsave(&port->lock, flags);
256 if (port->rs485.flags & SER_RS485_ENABLED) {
257 dev_dbg(port->dev, "Setting UART to RS485\n");
258 mr2 |= MCFUART_MR2_TXRTS;
261 uart_update_timeout(port, termios->c_cflag, baud);
262 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
263 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
264 writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
265 writeb(mr1, port->membase + MCFUART_UMR);
266 writeb(mr2, port->membase + MCFUART_UMR);
267 writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
268 writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
269 #if defined(CONFIG_M5272)
270 writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
272 writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
273 port->membase + MCFUART_UCSR);
274 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
275 port->membase + MCFUART_UCR);
276 spin_unlock_irqrestore(&port->lock, flags);
279 /****************************************************************************/
281 static void mcf_rx_chars(struct mcf_uart *pp)
283 struct uart_port *port = &pp->port;
284 unsigned char status, ch, flag;
286 while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
287 ch = readb(port->membase + MCFUART_URB);
291 if (status & MCFUART_USR_RXERR) {
292 writeb(MCFUART_UCR_CMDRESETERR,
293 port->membase + MCFUART_UCR);
295 if (status & MCFUART_USR_RXBREAK) {
297 if (uart_handle_break(port))
299 } else if (status & MCFUART_USR_RXPARITY) {
300 port->icount.parity++;
301 } else if (status & MCFUART_USR_RXOVERRUN) {
302 port->icount.overrun++;
303 } else if (status & MCFUART_USR_RXFRAMING) {
304 port->icount.frame++;
307 status &= port->read_status_mask;
309 if (status & MCFUART_USR_RXBREAK)
311 else if (status & MCFUART_USR_RXPARITY)
313 else if (status & MCFUART_USR_RXFRAMING)
317 if (uart_handle_sysrq_char(port, ch))
319 uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
322 tty_flip_buffer_push(&port->state->port);
325 /****************************************************************************/
327 static void mcf_tx_chars(struct mcf_uart *pp)
329 struct uart_port *port = &pp->port;
330 struct circ_buf *xmit = &port->state->xmit;
333 /* Send special char - probably flow control */
334 writeb(port->x_char, port->membase + MCFUART_UTB);
340 while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
341 if (uart_circ_empty(xmit))
343 writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
344 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
348 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
349 uart_write_wakeup(port);
351 if (uart_circ_empty(xmit)) {
353 /* Disable TX to negate RTS automatically */
354 if (port->rs485.flags & SER_RS485_ENABLED)
355 writeb(MCFUART_UCR_TXDISABLE,
356 port->membase + MCFUART_UCR);
360 /****************************************************************************/
362 static irqreturn_t mcf_interrupt(int irq, void *data)
364 struct uart_port *port = data;
365 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
367 irqreturn_t ret = IRQ_NONE;
369 isr = readb(port->membase + MCFUART_UISR) & pp->imr;
371 spin_lock(&port->lock);
372 if (isr & MCFUART_UIR_RXREADY) {
376 if (isr & MCFUART_UIR_TXREADY) {
380 spin_unlock(&port->lock);
385 /****************************************************************************/
387 static void mcf_config_port(struct uart_port *port, int flags)
389 port->type = PORT_MCF;
390 port->fifosize = MCFUART_TXFIFOSIZE;
392 /* Clear mask, so no surprise interrupts. */
393 writeb(0, port->membase + MCFUART_UIMR);
395 if (request_irq(port->irq, mcf_interrupt, 0, "UART", port))
396 printk(KERN_ERR "MCF: unable to attach ColdFire UART %d "
397 "interrupt vector=%d\n", port->line, port->irq);
400 /****************************************************************************/
402 static const char *mcf_type(struct uart_port *port)
404 return (port->type == PORT_MCF) ? "ColdFire UART" : NULL;
407 /****************************************************************************/
409 static int mcf_request_port(struct uart_port *port)
411 /* UARTs always present */
415 /****************************************************************************/
417 static void mcf_release_port(struct uart_port *port)
419 /* Nothing to release... */
422 /****************************************************************************/
424 static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
426 if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
431 /****************************************************************************/
433 /* Enable or disable the RS485 support */
434 static int mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
436 unsigned char mr1, mr2;
438 /* Get mode registers */
439 mr1 = readb(port->membase + MCFUART_UMR);
440 mr2 = readb(port->membase + MCFUART_UMR);
441 if (rs485->flags & SER_RS485_ENABLED) {
442 dev_dbg(port->dev, "Setting UART to RS485\n");
443 /* Automatically negate RTS after TX completes */
444 mr2 |= MCFUART_MR2_TXRTS;
446 dev_dbg(port->dev, "Setting UART to RS232\n");
447 mr2 &= ~MCFUART_MR2_TXRTS;
449 writeb(mr1, port->membase + MCFUART_UMR);
450 writeb(mr2, port->membase + MCFUART_UMR);
451 port->rs485 = *rs485;
456 /****************************************************************************/
459 * Define the basic serial functions we support.
461 static const struct uart_ops mcf_uart_ops = {
462 .tx_empty = mcf_tx_empty,
463 .get_mctrl = mcf_get_mctrl,
464 .set_mctrl = mcf_set_mctrl,
465 .start_tx = mcf_start_tx,
466 .stop_tx = mcf_stop_tx,
467 .stop_rx = mcf_stop_rx,
468 .break_ctl = mcf_break_ctl,
469 .startup = mcf_startup,
470 .shutdown = mcf_shutdown,
471 .set_termios = mcf_set_termios,
473 .request_port = mcf_request_port,
474 .release_port = mcf_release_port,
475 .config_port = mcf_config_port,
476 .verify_port = mcf_verify_port,
479 static struct mcf_uart mcf_ports[4];
481 #define MCF_MAXPORTS ARRAY_SIZE(mcf_ports)
483 /****************************************************************************/
484 #if defined(CONFIG_SERIAL_MCF_CONSOLE)
485 /****************************************************************************/
487 int __init early_mcf_setup(struct mcf_platform_uart *platp)
489 struct uart_port *port;
492 for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
493 port = &mcf_ports[i].port;
496 port->type = PORT_MCF;
497 port->mapbase = platp[i].mapbase;
498 port->membase = (platp[i].membase) ? platp[i].membase :
499 (unsigned char __iomem *) port->mapbase;
500 port->iotype = SERIAL_IO_MEM;
501 port->irq = platp[i].irq;
502 port->uartclk = MCF_BUSCLK;
503 port->flags = UPF_BOOT_AUTOCONF;
504 port->rs485_config = mcf_config_rs485;
505 port->ops = &mcf_uart_ops;
511 /****************************************************************************/
513 static void mcf_console_putc(struct console *co, const char c)
515 struct uart_port *port = &(mcf_ports + co->index)->port;
518 for (i = 0; (i < 0x10000); i++) {
519 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
522 writeb(c, port->membase + MCFUART_UTB);
523 for (i = 0; (i < 0x10000); i++) {
524 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
529 /****************************************************************************/
531 static void mcf_console_write(struct console *co, const char *s, unsigned int count)
533 for (; (count); count--, s++) {
534 mcf_console_putc(co, *s);
536 mcf_console_putc(co, '\r');
540 /****************************************************************************/
542 static int __init mcf_console_setup(struct console *co, char *options)
544 struct uart_port *port;
545 int baud = CONFIG_SERIAL_MCF_BAUDRATE;
550 if ((co->index < 0) || (co->index >= MCF_MAXPORTS))
552 port = &mcf_ports[co->index].port;
553 if (port->membase == 0)
557 uart_parse_options(options, &baud, &parity, &bits, &flow);
559 return uart_set_options(port, co, baud, parity, bits, flow);
562 /****************************************************************************/
564 static struct uart_driver mcf_driver;
566 static struct console mcf_console = {
568 .write = mcf_console_write,
569 .device = uart_console_device,
570 .setup = mcf_console_setup,
571 .flags = CON_PRINTBUFFER,
576 static int __init mcf_console_init(void)
578 register_console(&mcf_console);
582 console_initcall(mcf_console_init);
584 #define MCF_CONSOLE &mcf_console
586 /****************************************************************************/
588 /****************************************************************************/
590 #define MCF_CONSOLE NULL
592 /****************************************************************************/
593 #endif /* CONFIG_SERIAL_MCF_CONSOLE */
594 /****************************************************************************/
597 * Define the mcf UART driver structure.
599 static struct uart_driver mcf_driver = {
600 .owner = THIS_MODULE,
601 .driver_name = "mcf",
609 /****************************************************************************/
611 static int mcf_probe(struct platform_device *pdev)
613 struct mcf_platform_uart *platp = dev_get_platdata(&pdev->dev);
614 struct uart_port *port;
617 for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
618 port = &mcf_ports[i].port;
621 port->type = PORT_MCF;
622 port->mapbase = platp[i].mapbase;
623 port->membase = (platp[i].membase) ? platp[i].membase :
624 (unsigned char __iomem *) platp[i].mapbase;
625 port->dev = &pdev->dev;
626 port->iotype = SERIAL_IO_MEM;
627 port->irq = platp[i].irq;
628 port->uartclk = MCF_BUSCLK;
629 port->ops = &mcf_uart_ops;
630 port->flags = UPF_BOOT_AUTOCONF;
631 port->rs485_config = mcf_config_rs485;
632 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MCF_CONSOLE);
634 uart_add_one_port(&mcf_driver, port);
640 /****************************************************************************/
642 static int mcf_remove(struct platform_device *pdev)
644 struct uart_port *port;
647 for (i = 0; (i < MCF_MAXPORTS); i++) {
648 port = &mcf_ports[i].port;
650 uart_remove_one_port(&mcf_driver, port);
656 /****************************************************************************/
658 static struct platform_driver mcf_platform_driver = {
660 .remove = mcf_remove,
666 /****************************************************************************/
668 static int __init mcf_init(void)
672 printk("ColdFire internal UART serial driver\n");
674 rc = uart_register_driver(&mcf_driver);
677 rc = platform_driver_register(&mcf_platform_driver);
679 uart_unregister_driver(&mcf_driver);
685 /****************************************************************************/
687 static void __exit mcf_exit(void)
689 platform_driver_unregister(&mcf_platform_driver);
690 uart_unregister_driver(&mcf_driver);
693 /****************************************************************************/
695 module_init(mcf_init);
696 module_exit(mcf_exit);
698 MODULE_AUTHOR("Greg Ungerer <gerg@uclinux.org>");
699 MODULE_DESCRIPTION("Freescale ColdFire UART driver");
700 MODULE_LICENSE("GPL");
701 MODULE_ALIAS("platform:mcfuart");
703 /****************************************************************************/