1 // SPDX-License-Identifier: GPL-2.0+
3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
9 * Based on max3107.c, by Aavamobile
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/gpio/driver.h>
17 #include <linux/i2c.h>
18 #include <linux/module.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/serial_core.h>
23 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/spi/spi.h>
27 #include <linux/uaccess.h>
29 #define MAX310X_NAME "max310x"
30 #define MAX310X_MAJOR 204
31 #define MAX310X_MINOR 209
32 #define MAX310X_UART_NRMAX 16
34 /* MAX310X register definitions */
35 #define MAX310X_RHR_REG (0x00) /* RX FIFO */
36 #define MAX310X_THR_REG (0x00) /* TX FIFO */
37 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
38 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
39 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
40 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
41 #define MAX310X_REG_05 (0x05)
42 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
43 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
44 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
45 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
46 #define MAX310X_MODE1_REG (0x09) /* MODE1 */
47 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
48 #define MAX310X_LCR_REG (0x0b) /* LCR */
49 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
50 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
51 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
52 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
53 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
54 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
55 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
56 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
57 #define MAX310X_XON1_REG (0x14) /* XON1 character */
58 #define MAX310X_XON2_REG (0x15) /* XON2 character */
59 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
60 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
61 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
62 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
63 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
64 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
65 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
66 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
67 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
68 #define MAX310X_REG_1F (0x1f)
70 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
72 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
73 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
75 /* Extended registers */
76 #define MAX310X_SPI_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
77 #define MAX310X_I2C_REVID_EXTREG (0x25) /* Revision ID */
79 /* IRQ register bits */
80 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
81 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
82 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
83 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
84 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
85 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
86 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
87 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
89 /* LSR register bits */
90 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
91 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
92 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
93 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
94 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
95 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
96 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
98 /* Special character register bits */
99 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
100 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
101 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
102 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
103 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
106 /* Status register bits */
107 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
108 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
109 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
110 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
111 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
112 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
114 /* MODE1 register bits */
115 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
116 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
117 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
118 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
119 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
120 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
121 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
122 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
124 /* MODE2 register bits */
125 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
126 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
127 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
128 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
129 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
130 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
131 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
132 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
134 /* LCR register bits */
135 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
136 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
138 * Word length bits table:
144 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
146 * STOP length bit table:
148 * 1 -> 1-1.5 stop bits if
150 * 2 stop bits otherwise
152 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
153 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
154 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
155 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
156 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
158 /* IRDA register bits */
159 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
160 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
162 /* Flow control trigger level register masks */
163 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
164 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
165 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
166 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
168 /* FIFO interrupt trigger level register masks */
169 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
170 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
171 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
172 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
174 /* Flow control register bits */
175 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
176 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
177 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
178 * are used in conjunction with
179 * XOFF2 for definition of
180 * special character */
181 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
182 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
183 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
185 * SWFLOW bits 1 & 0 table:
186 * 00 -> no transmitter flow
188 * 01 -> receiver compares
192 * 10 -> receiver compares
196 * 11 -> receiver compares
197 * XON1, XON2, XOFF1 and
201 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
202 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
204 * SWFLOW bits 3 & 2 table:
205 * 00 -> no received flow
207 * 01 -> transmitter generates
209 * 10 -> transmitter generates
211 * 11 -> transmitter generates
212 * XON1, XON2, XOFF1 and
216 /* PLL configuration register masks */
217 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
218 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
220 /* Baud rate generator configuration register bits */
221 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
222 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
224 /* Clock source register bits */
225 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
226 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
227 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
228 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
229 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
231 /* Global commands */
232 #define MAX310X_EXTREG_ENBL (0xce)
233 #define MAX310X_EXTREG_DSBL (0xcd)
235 /* Misc definitions */
236 #define MAX310X_FIFO_SIZE (128)
237 #define MAX310x_REV_MASK (0xf8)
238 #define MAX310X_WRITE_BIT 0x80
240 /* Port startup definitions */
241 #define MAX310X_PORT_STARTUP_WAIT_RETRIES 20 /* Number of retries */
242 #define MAX310X_PORT_STARTUP_WAIT_DELAY_MS 10 /* Delay between retries */
244 /* Crystal-related definitions */
245 #define MAX310X_XTAL_WAIT_RETRIES 20 /* Number of retries */
246 #define MAX310X_XTAL_WAIT_DELAY_MS 10 /* Delay between retries */
248 /* MAX3107 specific */
249 #define MAX3107_REV_ID (0xa0)
251 /* MAX3109 specific */
252 #define MAX3109_REV_ID (0xc0)
254 /* MAX14830 specific */
255 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
256 #define MAX14830_REV_ID (0xb0)
258 struct max310x_if_cfg {
259 int (*extended_reg_enable)(struct device *dev, bool enable);
261 unsigned int rev_id_reg;
264 struct max310x_devtype {
272 int (*detect)(struct device *);
273 void (*power)(struct uart_port *, int);
277 struct uart_port port;
278 struct work_struct tx_work;
279 struct work_struct md_work;
280 struct work_struct rs_work;
281 struct regmap *regmap;
283 u8 rx_buf[MAX310X_FIFO_SIZE];
285 #define to_max310x_port(_port) \
286 container_of(_port, struct max310x_one, port)
288 struct max310x_port {
289 const struct max310x_devtype *devtype;
290 const struct max310x_if_cfg *if_cfg;
291 struct regmap *regmap;
293 #ifdef CONFIG_GPIOLIB
294 struct gpio_chip gpio;
296 struct max310x_one p[0];
299 static struct uart_driver max310x_uart = {
300 .owner = THIS_MODULE,
301 .driver_name = MAX310X_NAME,
302 .dev_name = "ttyMAX",
303 .major = MAX310X_MAJOR,
304 .minor = MAX310X_MINOR,
305 .nr = MAX310X_UART_NRMAX,
308 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
310 static u8 max310x_port_read(struct uart_port *port, u8 reg)
312 struct max310x_one *one = to_max310x_port(port);
313 unsigned int val = 0;
315 regmap_read(one->regmap, reg, &val);
320 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
322 struct max310x_one *one = to_max310x_port(port);
324 regmap_write(one->regmap, reg, val);
327 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
329 struct max310x_one *one = to_max310x_port(port);
331 regmap_update_bits(one->regmap, reg, mask, val);
334 static int max3107_detect(struct device *dev)
336 struct max310x_port *s = dev_get_drvdata(dev);
337 unsigned int val = 0;
340 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
344 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
346 "%s ID 0x%02x does not match\n", s->devtype->name, val);
353 static int max3108_detect(struct device *dev)
355 struct max310x_port *s = dev_get_drvdata(dev);
356 unsigned int val = 0;
359 /* MAX3108 have not REV ID register, we just check default value
360 * from clocksource register to make sure everything works.
362 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
366 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
367 dev_err(dev, "%s not present\n", s->devtype->name);
374 static int max3109_detect(struct device *dev)
376 struct max310x_port *s = dev_get_drvdata(dev);
377 unsigned int val = 0;
380 ret = s->if_cfg->extended_reg_enable(dev, true);
384 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val);
385 s->if_cfg->extended_reg_enable(dev, false);
386 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
388 "%s ID 0x%02x does not match\n", s->devtype->name, val);
395 static void max310x_power(struct uart_port *port, int on)
397 max310x_port_update(port, MAX310X_MODE1_REG,
398 MAX310X_MODE1_FORCESLEEP_BIT,
399 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
404 static int max14830_detect(struct device *dev)
406 struct max310x_port *s = dev_get_drvdata(dev);
407 unsigned int val = 0;
410 ret = s->if_cfg->extended_reg_enable(dev, true);
414 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val);
415 s->if_cfg->extended_reg_enable(dev, false);
416 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
418 "%s ID 0x%02x does not match\n", s->devtype->name, val);
425 static void max14830_power(struct uart_port *port, int on)
427 max310x_port_update(port, MAX310X_BRGCFG_REG,
428 MAX14830_BRGCFG_CLKDIS_BIT,
429 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
434 static const struct max310x_devtype max3107_devtype = {
437 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT,
438 .detect = max3107_detect,
439 .power = max310x_power,
446 static const struct max310x_devtype max3108_devtype = {
449 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT,
450 .detect = max3108_detect,
451 .power = max310x_power,
458 static const struct max310x_devtype max3109_devtype = {
461 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT,
462 .detect = max3109_detect,
463 .power = max310x_power,
470 static const struct max310x_devtype max14830_devtype = {
473 .mode1 = MAX310X_MODE1_IRQSEL_BIT,
474 .detect = max14830_detect,
475 .power = max14830_power,
482 static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
485 case MAX310X_IRQSTS_REG:
486 case MAX310X_LSR_IRQSTS_REG:
487 case MAX310X_SPCHR_IRQSTS_REG:
488 case MAX310X_STS_IRQSTS_REG:
489 case MAX310X_TXFIFOLVL_REG:
490 case MAX310X_RXFIFOLVL_REG:
499 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
502 case MAX310X_RHR_REG:
503 case MAX310X_IRQSTS_REG:
504 case MAX310X_LSR_IRQSTS_REG:
505 case MAX310X_SPCHR_IRQSTS_REG:
506 case MAX310X_STS_IRQSTS_REG:
507 case MAX310X_TXFIFOLVL_REG:
508 case MAX310X_RXFIFOLVL_REG:
509 case MAX310X_GPIODATA_REG:
510 case MAX310X_BRGDIVLSB_REG:
521 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
524 case MAX310X_RHR_REG:
525 case MAX310X_IRQSTS_REG:
526 case MAX310X_SPCHR_IRQSTS_REG:
527 case MAX310X_STS_IRQSTS_REG:
536 static bool max310x_reg_noinc(struct device *dev, unsigned int reg)
538 return reg == MAX310X_RHR_REG;
541 static int max310x_set_baud(struct uart_port *port, int baud)
543 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
546 * Calculate the integer divisor first. Select a proper mode
547 * in case if the requested baud is too high for the pre-defined
550 div = port->uartclk / baud;
554 mode = MAX310X_BRGCFG_4XMODE_BIT;
555 } else if (div < 16) {
558 mode = MAX310X_BRGCFG_2XMODE_BIT;
563 /* Calculate the divisor in accordance with the fraction coefficient */
567 /* Calculate the baud rate fraction */
569 frac = (16*(port->uartclk % F)) / F;
573 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
574 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
575 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
577 /* Return the actual baud rate we just programmed */
578 return (16*port->uartclk) / (c*(16*div + frac));
581 static int max310x_update_best_err(unsigned long f, long *besterr)
583 /* Use baudrate 115200 for calculate error */
584 long err = f % (460800 * 16);
586 if ((*besterr < 0) || (*besterr > err)) {
594 static s32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
595 unsigned long freq, bool xtal)
597 unsigned int div, clksrc, pllcfg = 0;
599 unsigned long fdiv, fmul, bestfreq = freq;
601 /* First, update error without PLL */
602 max310x_update_best_err(freq, &besterr);
604 /* Try all possible PLL dividers */
605 for (div = 1; (div <= 63) && besterr; div++) {
606 fdiv = DIV_ROUND_CLOSEST(freq, div);
608 /* Try multiplier 6 */
610 if ((fdiv >= 500000) && (fdiv <= 800000))
611 if (!max310x_update_best_err(fmul, &besterr)) {
612 pllcfg = (0 << 6) | div;
615 /* Try multiplier 48 */
617 if ((fdiv >= 850000) && (fdiv <= 1200000))
618 if (!max310x_update_best_err(fmul, &besterr)) {
619 pllcfg = (1 << 6) | div;
622 /* Try multiplier 96 */
624 if ((fdiv >= 425000) && (fdiv <= 1000000))
625 if (!max310x_update_best_err(fmul, &besterr)) {
626 pllcfg = (2 << 6) | div;
629 /* Try multiplier 144 */
631 if ((fdiv >= 390000) && (fdiv <= 667000))
632 if (!max310x_update_best_err(fmul, &besterr)) {
633 pllcfg = (3 << 6) | div;
638 /* Configure clock source */
639 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
643 clksrc |= MAX310X_CLKSRC_PLL_BIT;
644 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
646 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
648 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
650 /* Wait for crystal */
653 unsigned int try = 0, val = 0;
656 msleep(MAX310X_XTAL_WAIT_DELAY_MS);
657 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
659 if (val & MAX310X_STS_CLKREADY_BIT)
661 } while (!stable && (++try < MAX310X_XTAL_WAIT_RETRIES));
664 return dev_err_probe(dev, -EAGAIN,
665 "clock is not stable\n");
671 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
673 struct max310x_one *one = to_max310x_port(port);
675 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len);
678 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
680 struct max310x_one *one = to_max310x_port(port);
682 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len);
685 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
687 struct max310x_one *one = to_max310x_port(port);
688 unsigned int sts, ch, flag, i;
690 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
691 /* We are just reading, happily ignoring any error conditions.
692 * Break condition, parity checking, framing errors -- they
693 * are all ignored. That means that we can do a batch-read.
695 * There is a small opportunity for race if the RX FIFO
696 * overruns while we're reading the buffer; the datasheets says
697 * that the LSR register applies to the "current" character.
698 * That's also the reason why we cannot do batched reads when
699 * asked to check the individual statuses.
702 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
703 max310x_batch_read(port, one->rx_buf, rxlen);
705 port->icount.rx += rxlen;
707 sts &= port->read_status_mask;
709 if (sts & MAX310X_LSR_RXOVR_BIT) {
710 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
711 port->icount.overrun++;
714 for (i = 0; i < (rxlen - 1); ++i)
715 uart_insert_char(port, sts, 0, one->rx_buf[i], flag);
718 * Handle the overrun case for the last character only, since
719 * the RxFIFO overflow happens after it is pushed to the FIFO
722 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT,
723 one->rx_buf[rxlen-1], flag);
726 if (unlikely(rxlen >= port->fifosize)) {
727 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
728 port->icount.buf_overrun++;
729 /* Ensure sanity of RX level */
730 rxlen = port->fifosize;
734 ch = max310x_port_read(port, MAX310X_RHR_REG);
735 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
737 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
738 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
744 if (sts & MAX310X_LSR_RXBRK_BIT) {
746 if (uart_handle_break(port))
748 } else if (sts & MAX310X_LSR_RXPAR_BIT)
749 port->icount.parity++;
750 else if (sts & MAX310X_LSR_FRERR_BIT)
751 port->icount.frame++;
752 else if (sts & MAX310X_LSR_RXOVR_BIT)
753 port->icount.overrun++;
755 sts &= port->read_status_mask;
756 if (sts & MAX310X_LSR_RXBRK_BIT)
758 else if (sts & MAX310X_LSR_RXPAR_BIT)
760 else if (sts & MAX310X_LSR_FRERR_BIT)
762 else if (sts & MAX310X_LSR_RXOVR_BIT)
766 if (uart_handle_sysrq_char(port, ch))
769 if (sts & port->ignore_status_mask)
772 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
776 tty_flip_buffer_push(&port->state->port);
779 static void max310x_handle_tx(struct uart_port *port)
781 struct circ_buf *xmit = &port->state->xmit;
782 unsigned int txlen, to_send, until_end;
784 if (unlikely(port->x_char)) {
785 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
791 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
794 /* Get length of data pending in circular buffer */
795 to_send = uart_circ_chars_pending(xmit);
796 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
797 if (likely(to_send)) {
798 /* Limit to size of TX FIFO */
799 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
800 txlen = port->fifosize - txlen;
801 to_send = (to_send > txlen) ? txlen : to_send;
803 if (until_end < to_send) {
804 /* It's a circ buffer -- wrap around.
805 * We could do that in one SPI transaction, but meh. */
806 max310x_batch_write(port, xmit->buf + xmit->tail, until_end);
807 max310x_batch_write(port, xmit->buf, to_send - until_end);
809 max310x_batch_write(port, xmit->buf + xmit->tail, to_send);
812 /* Add data to send */
813 port->icount.tx += to_send;
814 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1);
817 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
818 uart_write_wakeup(port);
821 static void max310x_start_tx(struct uart_port *port)
823 struct max310x_one *one = to_max310x_port(port);
825 schedule_work(&one->tx_work);
828 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
830 struct uart_port *port = &s->p[portno].port;
831 irqreturn_t res = IRQ_NONE;
834 unsigned int ists, lsr, rxlen;
836 /* Read IRQ status & RX FIFO level */
837 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
838 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
844 if (ists & MAX310X_IRQ_CTS_BIT) {
845 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
846 uart_handle_cts_change(port,
847 !!(lsr & MAX310X_LSR_CTS_BIT));
850 max310x_handle_rx(port, rxlen);
851 if (ists & MAX310X_IRQ_TXEMPTY_BIT)
852 max310x_start_tx(port);
857 static irqreturn_t max310x_ist(int irq, void *dev_id)
859 struct max310x_port *s = (struct max310x_port *)dev_id;
860 bool handled = false;
862 if (s->devtype->nr > 1) {
864 unsigned int val = ~0;
866 WARN_ON_ONCE(regmap_read(s->regmap,
867 MAX310X_GLOBALIRQ_REG, &val));
868 val = ((1 << s->devtype->nr) - 1) & ~val;
871 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED)
875 if (max310x_port_irq(s, 0) == IRQ_HANDLED)
879 return IRQ_RETVAL(handled);
882 static void max310x_tx_proc(struct work_struct *ws)
884 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
886 max310x_handle_tx(&one->port);
889 static unsigned int max310x_tx_empty(struct uart_port *port)
891 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
893 return lvl ? 0 : TIOCSER_TEMT;
896 static unsigned int max310x_get_mctrl(struct uart_port *port)
898 /* DCD and DSR are not wired and CTS/RTS is handled automatically
899 * so just indicate DSR and CAR asserted
901 return TIOCM_DSR | TIOCM_CAR;
904 static void max310x_md_proc(struct work_struct *ws)
906 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
908 max310x_port_update(&one->port, MAX310X_MODE2_REG,
909 MAX310X_MODE2_LOOPBACK_BIT,
910 (one->port.mctrl & TIOCM_LOOP) ?
911 MAX310X_MODE2_LOOPBACK_BIT : 0);
914 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
916 struct max310x_one *one = to_max310x_port(port);
918 schedule_work(&one->md_work);
921 static void max310x_break_ctl(struct uart_port *port, int break_state)
923 max310x_port_update(port, MAX310X_LCR_REG,
924 MAX310X_LCR_TXBREAK_BIT,
925 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
928 static void max310x_set_termios(struct uart_port *port,
929 struct ktermios *termios,
930 struct ktermios *old)
932 unsigned int lcr = 0, flow = 0;
935 /* Mask termios capabilities we don't support */
936 termios->c_cflag &= ~CMSPAR;
939 switch (termios->c_cflag & CSIZE) {
943 lcr = MAX310X_LCR_LENGTH0_BIT;
946 lcr = MAX310X_LCR_LENGTH1_BIT;
950 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
955 if (termios->c_cflag & PARENB) {
956 lcr |= MAX310X_LCR_PARITY_BIT;
957 if (!(termios->c_cflag & PARODD))
958 lcr |= MAX310X_LCR_EVENPARITY_BIT;
962 if (termios->c_cflag & CSTOPB)
963 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
965 /* Update LCR register */
966 max310x_port_write(port, MAX310X_LCR_REG, lcr);
968 /* Set read status mask */
969 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
970 if (termios->c_iflag & INPCK)
971 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
972 MAX310X_LSR_FRERR_BIT;
973 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
974 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
976 /* Set status ignore mask */
977 port->ignore_status_mask = 0;
978 if (termios->c_iflag & IGNBRK)
979 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
980 if (!(termios->c_cflag & CREAD))
981 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
982 MAX310X_LSR_RXOVR_BIT |
983 MAX310X_LSR_FRERR_BIT |
984 MAX310X_LSR_RXBRK_BIT;
986 /* Configure flow control */
987 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
988 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
990 /* Disable transmitter before enabling AutoCTS or auto transmitter
993 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) {
994 max310x_port_update(port, MAX310X_MODE1_REG,
995 MAX310X_MODE1_TXDIS_BIT,
996 MAX310X_MODE1_TXDIS_BIT);
999 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1001 if (termios->c_cflag & CRTSCTS) {
1002 /* Enable AUTORTS and AUTOCTS */
1003 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1004 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
1005 MAX310X_FLOWCTRL_AUTORTS_BIT;
1007 if (termios->c_iflag & IXON)
1008 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
1009 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
1010 if (termios->c_iflag & IXOFF) {
1011 port->status |= UPSTAT_AUTOXOFF;
1012 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
1013 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
1015 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
1017 /* Enable transmitter after disabling AutoCTS and auto transmitter
1020 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) {
1021 max310x_port_update(port, MAX310X_MODE1_REG,
1022 MAX310X_MODE1_TXDIS_BIT,
1026 /* Get baud rate generator configuration */
1027 baud = uart_get_baud_rate(port, termios, old,
1028 port->uartclk / 16 / 0xffff,
1031 /* Setup baudrate generator */
1032 baud = max310x_set_baud(port, baud);
1034 /* Update timeout according to new baud rate */
1035 uart_update_timeout(port, termios->c_cflag, baud);
1038 static void max310x_rs_proc(struct work_struct *ws)
1040 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
1041 unsigned int delay, mode1 = 0, mode2 = 0;
1043 delay = (one->port.rs485.delay_rts_before_send << 4) |
1044 one->port.rs485.delay_rts_after_send;
1045 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
1047 if (one->port.rs485.flags & SER_RS485_ENABLED) {
1048 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT;
1050 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX))
1051 mode2 = MAX310X_MODE2_ECHOSUPR_BIT;
1054 max310x_port_update(&one->port, MAX310X_MODE1_REG,
1055 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1);
1056 max310x_port_update(&one->port, MAX310X_MODE2_REG,
1057 MAX310X_MODE2_ECHOSUPR_BIT, mode2);
1060 static int max310x_rs485_config(struct uart_port *port,
1061 struct serial_rs485 *rs485)
1063 struct max310x_one *one = to_max310x_port(port);
1065 if ((rs485->delay_rts_before_send > 0x0f) ||
1066 (rs485->delay_rts_after_send > 0x0f))
1069 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX |
1071 memset(rs485->padding, 0, sizeof(rs485->padding));
1072 port->rs485 = *rs485;
1074 schedule_work(&one->rs_work);
1079 static int max310x_startup(struct uart_port *port)
1081 struct max310x_port *s = dev_get_drvdata(port->dev);
1084 s->devtype->power(port, 1);
1086 /* Configure MODE1 register */
1087 max310x_port_update(port, MAX310X_MODE1_REG,
1088 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
1090 /* Configure MODE2 register & Reset FIFOs*/
1091 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
1092 max310x_port_write(port, MAX310X_MODE2_REG, val);
1093 max310x_port_update(port, MAX310X_MODE2_REG,
1094 MAX310X_MODE2_FIFORST_BIT, 0);
1096 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */
1097 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) |
1098 clamp(port->rs485.delay_rts_after_send, 0U, 15U);
1099 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
1101 if (port->rs485.flags & SER_RS485_ENABLED) {
1102 max310x_port_update(port, MAX310X_MODE1_REG,
1103 MAX310X_MODE1_TRNSCVCTRL_BIT,
1104 MAX310X_MODE1_TRNSCVCTRL_BIT);
1106 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1107 max310x_port_update(port, MAX310X_MODE2_REG,
1108 MAX310X_MODE2_ECHOSUPR_BIT,
1109 MAX310X_MODE2_ECHOSUPR_BIT);
1112 /* Configure flow control levels */
1113 /* Flow control halt level 96, resume level 48 */
1114 max310x_port_write(port, MAX310X_FLOWLVL_REG,
1115 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
1117 /* Clear IRQ status register */
1118 max310x_port_read(port, MAX310X_IRQSTS_REG);
1120 /* Enable RX, TX, CTS change interrupts */
1121 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
1122 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
1127 static void max310x_shutdown(struct uart_port *port)
1129 struct max310x_port *s = dev_get_drvdata(port->dev);
1131 /* Disable all interrupts */
1132 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
1134 s->devtype->power(port, 0);
1137 static const char *max310x_type(struct uart_port *port)
1139 struct max310x_port *s = dev_get_drvdata(port->dev);
1141 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
1144 static int max310x_request_port(struct uart_port *port)
1150 static void max310x_config_port(struct uart_port *port, int flags)
1152 if (flags & UART_CONFIG_TYPE)
1153 port->type = PORT_MAX310X;
1156 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
1158 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
1160 if (s->irq != port->irq)
1166 static void max310x_null_void(struct uart_port *port)
1171 static const struct uart_ops max310x_ops = {
1172 .tx_empty = max310x_tx_empty,
1173 .set_mctrl = max310x_set_mctrl,
1174 .get_mctrl = max310x_get_mctrl,
1175 .stop_tx = max310x_null_void,
1176 .start_tx = max310x_start_tx,
1177 .stop_rx = max310x_null_void,
1178 .break_ctl = max310x_break_ctl,
1179 .startup = max310x_startup,
1180 .shutdown = max310x_shutdown,
1181 .set_termios = max310x_set_termios,
1182 .type = max310x_type,
1183 .request_port = max310x_request_port,
1184 .release_port = max310x_null_void,
1185 .config_port = max310x_config_port,
1186 .verify_port = max310x_verify_port,
1189 static int __maybe_unused max310x_suspend(struct device *dev)
1191 struct max310x_port *s = dev_get_drvdata(dev);
1194 for (i = 0; i < s->devtype->nr; i++) {
1195 uart_suspend_port(&max310x_uart, &s->p[i].port);
1196 s->devtype->power(&s->p[i].port, 0);
1202 static int __maybe_unused max310x_resume(struct device *dev)
1204 struct max310x_port *s = dev_get_drvdata(dev);
1207 for (i = 0; i < s->devtype->nr; i++) {
1208 s->devtype->power(&s->p[i].port, 1);
1209 uart_resume_port(&max310x_uart, &s->p[i].port);
1215 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1217 #ifdef CONFIG_GPIOLIB
1218 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1221 struct max310x_port *s = gpiochip_get_data(chip);
1222 struct uart_port *port = &s->p[offset / 4].port;
1224 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1226 return !!((val >> 4) & (1 << (offset % 4)));
1229 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1231 struct max310x_port *s = gpiochip_get_data(chip);
1232 struct uart_port *port = &s->p[offset / 4].port;
1234 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1235 value ? 1 << (offset % 4) : 0);
1238 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1240 struct max310x_port *s = gpiochip_get_data(chip);
1241 struct uart_port *port = &s->p[offset / 4].port;
1243 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1248 static int max310x_gpio_direction_output(struct gpio_chip *chip,
1249 unsigned offset, int value)
1251 struct max310x_port *s = gpiochip_get_data(chip);
1252 struct uart_port *port = &s->p[offset / 4].port;
1254 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1255 value ? 1 << (offset % 4) : 0);
1256 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1262 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
1263 unsigned long config)
1265 struct max310x_port *s = gpiochip_get_data(chip);
1266 struct uart_port *port = &s->p[offset / 4].port;
1268 switch (pinconf_to_config_param(config)) {
1269 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1270 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1271 1 << ((offset % 4) + 4),
1272 1 << ((offset % 4) + 4));
1274 case PIN_CONFIG_DRIVE_PUSH_PULL:
1275 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1276 1 << ((offset % 4) + 4), 0);
1284 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype,
1285 const struct max310x_if_cfg *if_cfg,
1286 struct regmap *regmaps[], int irq)
1288 int i, ret, fmin, fmax, freq;
1289 struct max310x_port *s;
1293 for (i = 0; i < devtype->nr; i++)
1294 if (IS_ERR(regmaps[i]))
1295 return PTR_ERR(regmaps[i]);
1297 /* Alloc port structure */
1298 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL);
1300 dev_err(dev, "Error allocating port structure\n");
1304 /* Always ask for fixed clock rate from a property. */
1305 device_property_read_u32(dev, "clock-frequency", &uartclk);
1307 s->clk = devm_clk_get_optional(dev, "osc");
1309 return PTR_ERR(s->clk);
1313 s->clk = devm_clk_get_optional(dev, "xtal");
1315 return PTR_ERR(s->clk);
1320 ret = clk_prepare_enable(s->clk);
1324 freq = clk_get_rate(s->clk);
1328 dev_err(dev, "Cannot get clock rate\n");
1341 /* Check frequency limits */
1342 if (freq < fmin || freq > fmax) {
1347 s->regmap = regmaps[0];
1348 s->devtype = devtype;
1350 dev_set_drvdata(dev, s);
1352 /* Check device to ensure we are talking to what we expect */
1353 ret = devtype->detect(dev);
1357 for (i = 0; i < devtype->nr; i++) {
1358 bool started = false;
1359 unsigned int try = 0, val = 0;
1362 regmap_write(regmaps[i], MAX310X_MODE2_REG,
1363 MAX310X_MODE2_RST_BIT);
1364 /* Clear port reset */
1365 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0);
1367 /* Wait for port startup */
1369 msleep(MAX310X_PORT_STARTUP_WAIT_DELAY_MS);
1370 regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &val);
1374 } while (!started && (++try < MAX310X_PORT_STARTUP_WAIT_RETRIES));
1377 ret = dev_err_probe(dev, -EAGAIN, "port reset failed\n");
1381 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1);
1384 uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
1390 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1392 for (i = 0; i < devtype->nr; i++) {
1395 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
1396 if (line == MAX310X_UART_NRMAX) {
1401 /* Initialize port data */
1402 s->p[i].port.line = line;
1403 s->p[i].port.dev = dev;
1404 s->p[i].port.irq = irq;
1405 s->p[i].port.type = PORT_MAX310X;
1406 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1407 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1408 s->p[i].port.iotype = UPIO_PORT;
1409 s->p[i].port.iobase = i;
1410 s->p[i].port.membase = (void __iomem *)~0;
1411 s->p[i].port.uartclk = uartclk;
1412 s->p[i].port.rs485_config = max310x_rs485_config;
1413 s->p[i].port.ops = &max310x_ops;
1414 s->p[i].regmap = regmaps[i];
1416 /* Disable all interrupts */
1417 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1418 /* Clear IRQ status register */
1419 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1420 /* Initialize queue for start TX */
1421 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc);
1422 /* Initialize queue for changing LOOPBACK mode */
1423 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1424 /* Initialize queue for changing RS485 mode */
1425 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1428 ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1430 s->p[i].port.dev = NULL;
1433 set_bit(line, max310x_lines);
1435 /* Go to suspend mode */
1436 devtype->power(&s->p[i].port, 0);
1439 #ifdef CONFIG_GPIOLIB
1440 /* Setup GPIO cotroller */
1441 s->gpio.owner = THIS_MODULE;
1442 s->gpio.parent = dev;
1443 s->gpio.label = devtype->name;
1444 s->gpio.direction_input = max310x_gpio_direction_input;
1445 s->gpio.get = max310x_gpio_get;
1446 s->gpio.direction_output= max310x_gpio_direction_output;
1447 s->gpio.set = max310x_gpio_set;
1448 s->gpio.set_config = max310x_gpio_set_config;
1450 s->gpio.ngpio = devtype->nr * 4;
1451 s->gpio.can_sleep = 1;
1452 ret = devm_gpiochip_add_data(dev, &s->gpio, s);
1457 /* Setup interrupt */
1458 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1459 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s);
1463 dev_err(dev, "Unable to request IRQ %i\n", irq);
1466 for (i = 0; i < devtype->nr; i++) {
1467 if (s->p[i].port.dev) {
1468 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1469 clear_bit(s->p[i].port.line, max310x_lines);
1474 clk_disable_unprepare(s->clk);
1479 static int max310x_remove(struct device *dev)
1481 struct max310x_port *s = dev_get_drvdata(dev);
1484 for (i = 0; i < s->devtype->nr; i++) {
1485 cancel_work_sync(&s->p[i].tx_work);
1486 cancel_work_sync(&s->p[i].md_work);
1487 cancel_work_sync(&s->p[i].rs_work);
1488 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1489 clear_bit(s->p[i].port.line, max310x_lines);
1490 s->devtype->power(&s->p[i].port, 0);
1493 clk_disable_unprepare(s->clk);
1498 static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1499 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1500 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1501 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1502 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1505 MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1507 static struct regmap_config regcfg = {
1510 .write_flag_mask = MAX310X_WRITE_BIT,
1511 .cache_type = REGCACHE_RBTREE,
1512 .max_register = MAX310X_REG_1F,
1513 .writeable_reg = max310x_reg_writeable,
1514 .volatile_reg = max310x_reg_volatile,
1515 .precious_reg = max310x_reg_precious,
1516 .writeable_noinc_reg = max310x_reg_noinc,
1517 .readable_noinc_reg = max310x_reg_noinc,
1518 .max_raw_read = MAX310X_FIFO_SIZE,
1519 .max_raw_write = MAX310X_FIFO_SIZE,
1522 #ifdef CONFIG_SPI_MASTER
1523 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable)
1525 struct max310x_port *s = dev_get_drvdata(dev);
1527 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
1528 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL);
1531 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = {
1532 .extended_reg_enable = max310x_spi_extended_reg_enable,
1533 .rev_id_reg = MAX310X_SPI_REVID_EXTREG,
1536 static int max310x_spi_probe(struct spi_device *spi)
1538 const struct max310x_devtype *devtype;
1539 struct regmap *regmaps[4];
1544 spi->bits_per_word = 8;
1545 spi->mode = spi->mode ? : SPI_MODE_0;
1546 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1547 ret = spi_setup(spi);
1551 devtype = device_get_match_data(&spi->dev);
1553 devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data;
1555 for (i = 0; i < devtype->nr; i++) {
1556 u8 port_mask = i * 0x20;
1557 regcfg.read_flag_mask = port_mask;
1558 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT;
1559 regmaps[i] = devm_regmap_init_spi(spi, ®cfg);
1562 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq);
1565 static int max310x_spi_remove(struct spi_device *spi)
1567 return max310x_remove(&spi->dev);
1570 static const struct spi_device_id max310x_id_table[] = {
1571 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1572 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1573 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1574 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1577 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1579 static struct spi_driver max310x_spi_driver = {
1581 .name = MAX310X_NAME,
1582 .of_match_table = max310x_dt_ids,
1583 .pm = &max310x_pm_ops,
1585 .probe = max310x_spi_probe,
1586 .remove = max310x_spi_remove,
1587 .id_table = max310x_id_table,
1592 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable)
1597 static struct regmap_config regcfg_i2c = {
1600 .cache_type = REGCACHE_RBTREE,
1601 .writeable_reg = max310x_reg_writeable,
1602 .volatile_reg = max310x_reg_volatile,
1603 .precious_reg = max310x_reg_precious,
1604 .max_register = MAX310X_I2C_REVID_EXTREG,
1605 .writeable_noinc_reg = max310x_reg_noinc,
1606 .readable_noinc_reg = max310x_reg_noinc,
1607 .max_raw_read = MAX310X_FIFO_SIZE,
1608 .max_raw_write = MAX310X_FIFO_SIZE,
1611 static const struct max310x_if_cfg max310x_i2c_if_cfg = {
1612 .extended_reg_enable = max310x_i2c_extended_reg_enable,
1613 .rev_id_reg = MAX310X_I2C_REVID_EXTREG,
1616 static unsigned short max310x_i2c_slave_addr(unsigned short addr,
1620 * For MAX14830 and MAX3109, the slave address depends on what the
1621 * A0 and A1 pins are tied to.
1622 * See Table I2C Address Map of the datasheet.
1623 * Based on that table, the following formulas were determined.
1624 * UART1 - UART0 = 0x10
1625 * UART2 - UART1 = 0x20 + 0x10
1626 * UART3 - UART2 = 0x10
1637 static int max310x_i2c_probe(struct i2c_client *client)
1639 const struct max310x_devtype *devtype;
1640 struct i2c_client *port_client;
1641 struct regmap *regmaps[4];
1645 devtype = device_get_match_data(&client->dev);
1647 return dev_err_probe(&client->dev, -ENODEV, "Failed to match device\n");
1649 if (client->addr < devtype->slave_addr.min ||
1650 client->addr > devtype->slave_addr.max)
1651 return dev_err_probe(&client->dev, -EINVAL,
1652 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n",
1653 client->addr, devtype->slave_addr.min,
1654 devtype->slave_addr.max);
1656 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c);
1658 for (i = 1; i < devtype->nr; i++) {
1659 port_addr = max310x_i2c_slave_addr(client->addr, i);
1660 port_client = devm_i2c_new_dummy_device(&client->dev,
1664 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c);
1667 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg,
1668 regmaps, client->irq);
1671 static int max310x_i2c_remove(struct i2c_client *client)
1673 max310x_remove(&client->dev);
1678 static struct i2c_driver max310x_i2c_driver = {
1680 .name = MAX310X_NAME,
1681 .of_match_table = max310x_dt_ids,
1682 .pm = &max310x_pm_ops,
1684 .probe_new = max310x_i2c_probe,
1685 .remove = max310x_i2c_remove,
1689 static int __init max310x_uart_init(void)
1693 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
1695 ret = uart_register_driver(&max310x_uart);
1699 #ifdef CONFIG_SPI_MASTER
1700 ret = spi_register_driver(&max310x_spi_driver);
1702 goto err_spi_register;
1706 ret = i2c_add_driver(&max310x_i2c_driver);
1708 goto err_i2c_register;
1715 spi_unregister_driver(&max310x_spi_driver);
1719 uart_unregister_driver(&max310x_uart);
1723 module_init(max310x_uart_init);
1725 static void __exit max310x_uart_exit(void)
1728 i2c_del_driver(&max310x_i2c_driver);
1731 #ifdef CONFIG_SPI_MASTER
1732 spi_unregister_driver(&max310x_spi_driver);
1735 uart_unregister_driver(&max310x_uart);
1737 module_exit(max310x_uart_exit);
1739 MODULE_LICENSE("GPL");
1740 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1741 MODULE_DESCRIPTION("MAX310X serial driver");