drivers/tty/serial/lpc32xx_hs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * High Speed Serial Ports on NXP LPC32xx SoC
   4  *
   5  * Authors: Kevin Wells <kevin.wells@nxp.com>
   6  *          Roland Stigge <stigge@antcom.de>
   7  *
   8  * Copyright (C) 2010 NXP Semiconductors
   9  * Copyright (C) 2012 Roland Stigge
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/ioport.h>
  14 #include <linux/init.h>
  15 #include <linux/console.h>
  16 #include <linux/sysrq.h>
  17 #include <linux/tty.h>
  18 #include <linux/tty_flip.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/serial.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/delay.h>
  23 #include <linux/nmi.h>
  24 #include <linux/io.h>
  25 #include <linux/irq.h>
  26 #include <linux/of.h>
  27 #include <linux/sizes.h>
  28 #include <linux/soc/nxp/lpc32xx-misc.h>
  29
  30 /*
  31  * High Speed UART register offsets
  32  */
  33 #define LPC32XX_HSUART_FIFO(x)                  ((x) + 0x00)
  34 #define LPC32XX_HSUART_LEVEL(x)                 ((x) + 0x04)
  35 #define LPC32XX_HSUART_IIR(x)                   ((x) + 0x08)
  36 #define LPC32XX_HSUART_CTRL(x)                  ((x) + 0x0C)
  37 #define LPC32XX_HSUART_RATE(x)                  ((x) + 0x10)
  38
  39 #define LPC32XX_HSU_BREAK_DATA                  (1 << 10)
  40 #define LPC32XX_HSU_ERROR_DATA                  (1 << 9)
  41 #define LPC32XX_HSU_RX_EMPTY                    (1 << 8)
  42
  43 #define LPC32XX_HSU_TX_LEV(n)                   (((n) >> 8) & 0xFF)
  44 #define LPC32XX_HSU_RX_LEV(n)                   ((n) & 0xFF)
  45
  46 #define LPC32XX_HSU_TX_INT_SET                  (1 << 6)
  47 #define LPC32XX_HSU_RX_OE_INT                   (1 << 5)
  48 #define LPC32XX_HSU_BRK_INT                     (1 << 4)
  49 #define LPC32XX_HSU_FE_INT                      (1 << 3)
  50 #define LPC32XX_HSU_RX_TIMEOUT_INT              (1 << 2)
  51 #define LPC32XX_HSU_RX_TRIG_INT                 (1 << 1)
  52 #define LPC32XX_HSU_TX_INT                      (1 << 0)
  53
  54 #define LPC32XX_HSU_HRTS_INV                    (1 << 21)
  55 #define LPC32XX_HSU_HRTS_TRIG_8B                (0x0 << 19)
  56 #define LPC32XX_HSU_HRTS_TRIG_16B               (0x1 << 19)
  57 #define LPC32XX_HSU_HRTS_TRIG_32B               (0x2 << 19)
  58 #define LPC32XX_HSU_HRTS_TRIG_48B               (0x3 << 19)
  59 #define LPC32XX_HSU_HRTS_EN                     (1 << 18)
  60 #define LPC32XX_HSU_TMO_DISABLED                (0x0 << 16)
  61 #define LPC32XX_HSU_TMO_INACT_4B                (0x1 << 16)
  62 #define LPC32XX_HSU_TMO_INACT_8B                (0x2 << 16)
  63 #define LPC32XX_HSU_TMO_INACT_16B               (0x3 << 16)
  64 #define LPC32XX_HSU_HCTS_INV                    (1 << 15)
  65 #define LPC32XX_HSU_HCTS_EN                     (1 << 14)
  66 #define LPC32XX_HSU_OFFSET(n)                   ((n) << 9)
  67 #define LPC32XX_HSU_BREAK                       (1 << 8)
  68 #define LPC32XX_HSU_ERR_INT_EN                  (1 << 7)
  69 #define LPC32XX_HSU_RX_INT_EN                   (1 << 6)
  70 #define LPC32XX_HSU_TX_INT_EN                   (1 << 5)
  71 #define LPC32XX_HSU_RX_TL1B                     (0x0 << 2)
  72 #define LPC32XX_HSU_RX_TL4B                     (0x1 << 2)
  73 #define LPC32XX_HSU_RX_TL8B                     (0x2 << 2)
  74 #define LPC32XX_HSU_RX_TL16B                    (0x3 << 2)
  75 #define LPC32XX_HSU_RX_TL32B                    (0x4 << 2)
  76 #define LPC32XX_HSU_RX_TL48B                    (0x5 << 2)
  77 #define LPC32XX_HSU_TX_TLEMPTY                  (0x0 << 0)
  78 #define LPC32XX_HSU_TX_TL0B                     (0x0 << 0)
  79 #define LPC32XX_HSU_TX_TL4B                     (0x1 << 0)
  80 #define LPC32XX_HSU_TX_TL8B                     (0x2 << 0)
  81 #define LPC32XX_HSU_TX_TL16B                    (0x3 << 0)
  82
  83 #define LPC32XX_MAIN_OSC_FREQ                   13000000
  84
  85 #define MODNAME "lpc32xx_hsuart"
  86
  87 struct lpc32xx_hsuart_port {
  88         struct uart_port port;
  89 };
  90
  91 #define FIFO_READ_LIMIT 128
  92 #define MAX_PORTS 3
  93 #define LPC32XX_TTY_NAME "ttyTX"
  94 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
  95
  96 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
  97 static void wait_for_xmit_empty(struct uart_port *port)
  98 {
  99         unsigned int timeout = 10000;
 100
 101         do {
 102                 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
 103                                                         port->membase))) == 0)
 104                         break;
 105                 if (--timeout == 0)
 106                         break;
 107                 udelay(1);
 108         } while (1);
 109 }
 110
 111 static void wait_for_xmit_ready(struct uart_port *port)
 112 {
 113         unsigned int timeout = 10000;
 114
 115         while (1) {
 116                 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
 117                                                         port->membase))) < 32)
 118                         break;
 119                 if (--timeout == 0)
 120                         break;
 121                 udelay(1);
 122         }
 123 }
 124
 125 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
 126 {
 127         wait_for_xmit_ready(port);
 128         writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
 129 }
 130
 131 static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
 132                                          unsigned int count)
 133 {
 134         struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
 135         unsigned long flags;
 136         int locked = 1;
 137
 138         touch_nmi_watchdog();
 139         local_irq_save(flags);
 140         if (up->port.sysrq)
 141                 locked = 0;
 142         else if (oops_in_progress)
 143                 locked = spin_trylock(&up->port.lock);
 144         else
 145                 spin_lock(&up->port.lock);
 146
 147         uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
 148         wait_for_xmit_empty(&up->port);
 149
 150         if (locked)
 151                 spin_unlock(&up->port.lock);
 152         local_irq_restore(flags);
 153 }
 154
 155 static int __init lpc32xx_hsuart_console_setup(struct console *co,
 156                                                char *options)
 157 {
 158         struct uart_port *port;
 159         int baud = 115200;
 160         int bits = 8;
 161         int parity = 'n';
 162         int flow = 'n';
 163
 164         if (co->index >= MAX_PORTS)
 165                 co->index = 0;
 166
 167         port = &lpc32xx_hs_ports[co->index].port;
 168         if (!port->membase)
 169                 return -ENODEV;
 170
 171         if (options)
 172                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 173
 174         lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
 175
 176         return uart_set_options(port, co, baud, parity, bits, flow);
 177 }
 178
 179 static struct uart_driver lpc32xx_hsuart_reg;
 180 static struct console lpc32xx_hsuart_console = {
 181         .name           = LPC32XX_TTY_NAME,
 182         .write          = lpc32xx_hsuart_console_write,
 183         .device         = uart_console_device,
 184         .setup          = lpc32xx_hsuart_console_setup,
 185         .flags          = CON_PRINTBUFFER,
 186         .index          = -1,
 187         .data           = &lpc32xx_hsuart_reg,
 188 };
 189
 190 static int __init lpc32xx_hsuart_console_init(void)
 191 {
 192         register_console(&lpc32xx_hsuart_console);
 193         return 0;
 194 }
 195 console_initcall(lpc32xx_hsuart_console_init);
 196
 197 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
 198 #else
 199 #define LPC32XX_HSUART_CONSOLE NULL
 200 #endif
 201
 202 static struct uart_driver lpc32xx_hs_reg = {
 203         .owner          = THIS_MODULE,
 204         .driver_name    = MODNAME,
 205         .dev_name       = LPC32XX_TTY_NAME,
 206         .nr             = MAX_PORTS,
 207         .cons           = LPC32XX_HSUART_CONSOLE,
 208 };
 209 static int uarts_registered;
 210
 211 static unsigned int __serial_get_clock_div(unsigned long uartclk,
 212                                            unsigned long rate)
 213 {
 214         u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
 215         u32 rate_diff;
 216
 217         /* Find the closest divider to get the desired clock rate */
 218         div = uartclk / rate;
 219         goodrate = hsu_rate = (div / 14) - 1;
 220         if (hsu_rate != 0)
 221                 hsu_rate--;
 222
 223         /* Tweak divider */
 224         l_hsu_rate = hsu_rate + 3;
 225         rate_diff = 0xFFFFFFFF;
 226
 227         while (hsu_rate < l_hsu_rate) {
 228                 comprate = uartclk / ((hsu_rate + 1) * 14);
 229                 if (abs(comprate - rate) < rate_diff) {
 230                         goodrate = hsu_rate;
 231                         rate_diff = abs(comprate - rate);
 232                 }
 233
 234                 hsu_rate++;
 235         }
 236         if (hsu_rate > 0xFF)
 237                 hsu_rate = 0xFF;
 238
 239         return goodrate;
 240 }
 241
 242 static void __serial_uart_flush(struct uart_port *port)
 243 {
 244         u32 tmp;
 245         int cnt = 0;
 246
 247         while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
 248                (cnt++ < FIFO_READ_LIMIT))
 249                 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
 250 }
 251
 252 static void __serial_lpc32xx_rx(struct uart_port *port)
 253 {
 254         struct tty_port *tport = &port->state->port;
 255         unsigned int tmp, flag;
 256
 257         /* Read data from FIFO and push into terminal */
 258         tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
 259         while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
 260                 flag = TTY_NORMAL;
 261                 port->icount.rx++;
 262
 263                 if (tmp & LPC32XX_HSU_ERROR_DATA) {
 264                         /* Framing error */
 265                         writel(LPC32XX_HSU_FE_INT,
 266                                LPC32XX_HSUART_IIR(port->membase));
 267                         port->icount.frame++;
 268                         flag = TTY_FRAME;
 269                         tty_insert_flip_char(tport, 0, TTY_FRAME);
 270                 }
 271
 272                 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
 273
 274                 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
 275         }
 276
 277         spin_unlock(&port->lock);
 278         tty_flip_buffer_push(tport);
 279         spin_lock(&port->lock);
 280 }
 281
 282 static void __serial_lpc32xx_tx(struct uart_port *port)
 283 {
 284         struct circ_buf *xmit = &port->state->xmit;
 285         unsigned int tmp;
 286
 287         if (port->x_char) {
 288                 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
 289                 port->icount.tx++;
 290                 port->x_char = 0;
 291                 return;
 292         }
 293
 294         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 295                 goto exit_tx;
 296
 297         /* Transfer data */
 298         while (LPC32XX_HSU_TX_LEV(readl(
 299                 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
 300                 writel((u32) xmit->buf[xmit->tail],
 301                        LPC32XX_HSUART_FIFO(port->membase));
 302                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 303                 port->icount.tx++;
 304                 if (uart_circ_empty(xmit))
 305                         break;
 306         }
 307
 308         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 309                 uart_write_wakeup(port);
 310
 311 exit_tx:
 312         if (uart_circ_empty(xmit)) {
 313                 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 314                 tmp &= ~LPC32XX_HSU_TX_INT_EN;
 315                 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 316         }
 317 }
 318
 319 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
 320 {
 321         struct uart_port *port = dev_id;
 322         struct tty_port *tport = &port->state->port;
 323         u32 status;
 324
 325         spin_lock(&port->lock);
 326
 327         /* Read UART status and clear latched interrupts */
 328         status = readl(LPC32XX_HSUART_IIR(port->membase));
 329
 330         if (status & LPC32XX_HSU_BRK_INT) {
 331                 /* Break received */
 332                 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
 333                 port->icount.brk++;
 334                 uart_handle_break(port);
 335         }
 336
 337         /* Framing error */
 338         if (status & LPC32XX_HSU_FE_INT)
 339                 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
 340
 341         if (status & LPC32XX_HSU_RX_OE_INT) {
 342                 /* Receive FIFO overrun */
 343                 writel(LPC32XX_HSU_RX_OE_INT,
 344                        LPC32XX_HSUART_IIR(port->membase));
 345                 port->icount.overrun++;
 346                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 347                 tty_flip_buffer_push(tport);
 348         }
 349
 350         /* Data received? */
 351         if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
 352                 __serial_lpc32xx_rx(port);
 353
 354         /* Transmit data request? */
 355         if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
 356                 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
 357                 __serial_lpc32xx_tx(port);
 358         }
 359
 360         spin_unlock(&port->lock);
 361
 362         return IRQ_HANDLED;
 363 }
 364
 365 /* port->lock is not held.  */
 366 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
 367 {
 368         unsigned int ret = 0;
 369
 370         if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
 371                 ret = TIOCSER_TEMT;
 372
 373         return ret;
 374 }
 375
 376 /* port->lock held by caller.  */
 377 static void serial_lpc32xx_set_mctrl(struct uart_port *port,
 378                                      unsigned int mctrl)
 379 {
 380         /* No signals are supported on HS UARTs */
 381 }
 382
 383 /* port->lock is held by caller and interrupts are disabled.  */
 384 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
 385 {
 386         /* No signals are supported on HS UARTs */
 387         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 388 }
 389
 390 /* port->lock held by caller.  */
 391 static void serial_lpc32xx_stop_tx(struct uart_port *port)
 392 {
 393         u32 tmp;
 394
 395         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 396         tmp &= ~LPC32XX_HSU_TX_INT_EN;
 397         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 398 }
 399
 400 /* port->lock held by caller.  */
 401 static void serial_lpc32xx_start_tx(struct uart_port *port)
 402 {
 403         u32 tmp;
 404
 405         __serial_lpc32xx_tx(port);
 406         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 407         tmp |= LPC32XX_HSU_TX_INT_EN;
 408         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 409 }
 410
 411 /* port->lock held by caller.  */
 412 static void serial_lpc32xx_stop_rx(struct uart_port *port)
 413 {
 414         u32 tmp;
 415
 416         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 417         tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
 418         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 419
 420         writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
 421                 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
 422 }
 423
 424 /* port->lock is not held.  */
 425 static void serial_lpc32xx_break_ctl(struct uart_port *port,
 426                                      int break_state)
 427 {
 428         unsigned long flags;
 429         u32 tmp;
 430
 431         spin_lock_irqsave(&port->lock, flags);
 432         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 433         if (break_state != 0)
 434                 tmp |= LPC32XX_HSU_BREAK;
 435         else
 436                 tmp &= ~LPC32XX_HSU_BREAK;
 437         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 438         spin_unlock_irqrestore(&port->lock, flags);
 439 }
 440
 441 /* port->lock is not held.  */
 442 static int serial_lpc32xx_startup(struct uart_port *port)
 443 {
 444         int retval;
 445         unsigned long flags;
 446         u32 tmp;
 447
 448         spin_lock_irqsave(&port->lock, flags);
 449
 450         __serial_uart_flush(port);
 451
 452         writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
 453                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
 454                LPC32XX_HSUART_IIR(port->membase));
 455
 456         writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
 457
 458         /*
 459          * Set receiver timeout, HSU offset of 20, no break, no interrupts,
 460          * and default FIFO trigger levels
 461          */
 462         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
 463                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
 464         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 465
 466         lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
 467
 468         spin_unlock_irqrestore(&port->lock, flags);
 469
 470         retval = request_irq(port->irq, serial_lpc32xx_interrupt,
 471                              0, MODNAME, port);
 472         if (!retval)
 473                 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
 474                        LPC32XX_HSUART_CTRL(port->membase));
 475
 476         return retval;
 477 }
 478
 479 /* port->lock is not held.  */
 480 static void serial_lpc32xx_shutdown(struct uart_port *port)
 481 {
 482         u32 tmp;
 483         unsigned long flags;
 484
 485         spin_lock_irqsave(&port->lock, flags);
 486
 487         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
 488                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
 489         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 490
 491         lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
 492
 493         spin_unlock_irqrestore(&port->lock, flags);
 494
 495         free_irq(port->irq, port);
 496 }
 497
 498 /* port->lock is not held.  */
 499 static void serial_lpc32xx_set_termios(struct uart_port *port,
 500                                        struct ktermios *termios,
 501                                        struct ktermios *old)
 502 {
 503         unsigned long flags;
 504         unsigned int baud, quot;
 505         u32 tmp;
 506
 507         /* Always 8-bit, no parity, 1 stop bit */
 508         termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
 509         termios->c_cflag |= CS8;
 510
 511         termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
 512
 513         baud = uart_get_baud_rate(port, termios, old, 0,
 514                                   port->uartclk / 14);
 515
 516         quot = __serial_get_clock_div(port->uartclk, baud);
 517
 518         spin_lock_irqsave(&port->lock, flags);
 519
 520         /* Ignore characters? */
 521         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
 522         if ((termios->c_cflag & CREAD) == 0)
 523                 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
 524         else
 525                 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
 526         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
 527
 528         writel(quot, LPC32XX_HSUART_RATE(port->membase));
 529
 530         uart_update_timeout(port, termios->c_cflag, baud);
 531
 532         spin_unlock_irqrestore(&port->lock, flags);
 533
 534         /* Don't rewrite B0 */
 535         if (tty_termios_baud_rate(termios))
 536                 tty_termios_encode_baud_rate(termios, baud, baud);
 537 }
 538
 539 static const char *serial_lpc32xx_type(struct uart_port *port)
 540 {
 541         return MODNAME;
 542 }
 543
 544 static void serial_lpc32xx_release_port(struct uart_port *port)
 545 {
 546         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
 547                 if (port->flags & UPF_IOREMAP) {
 548                         iounmap(port->membase);
 549                         port->membase = NULL;
 550                 }
 551
 552                 release_mem_region(port->mapbase, SZ_4K);
 553         }
 554 }
 555
 556 static int serial_lpc32xx_request_port(struct uart_port *port)
 557 {
 558         int ret = -ENODEV;
 559
 560         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
 561                 ret = 0;
 562
 563                 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
 564                         ret = -EBUSY;
 565                 else if (port->flags & UPF_IOREMAP) {
 566                         port->membase = ioremap(port->mapbase, SZ_4K);
 567                         if (!port->membase) {
 568                                 release_mem_region(port->mapbase, SZ_4K);
 569                                 ret = -ENOMEM;
 570                         }
 571                 }
 572         }
 573
 574         return ret;
 575 }
 576
 577 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
 578 {
 579         int ret;
 580
 581         ret = serial_lpc32xx_request_port(port);
 582         if (ret < 0)
 583                 return;
 584         port->type = PORT_UART00;
 585         port->fifosize = 64;
 586
 587         __serial_uart_flush(port);
 588
 589         writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
 590                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
 591                LPC32XX_HSUART_IIR(port->membase));
 592
 593         writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
 594
 595         /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
 596            and default FIFO trigger levels */
 597         writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
 598                LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
 599                LPC32XX_HSUART_CTRL(port->membase));
 600 }
 601
 602 static int serial_lpc32xx_verify_port(struct uart_port *port,
 603                                       struct serial_struct *ser)
 604 {
 605         int ret = 0;
 606
 607         if (ser->type != PORT_UART00)
 608                 ret = -EINVAL;
 609
 610         return ret;
 611 }
 612
 613 static const struct uart_ops serial_lpc32xx_pops = {
 614         .tx_empty       = serial_lpc32xx_tx_empty,
 615         .set_mctrl      = serial_lpc32xx_set_mctrl,
 616         .get_mctrl      = serial_lpc32xx_get_mctrl,
 617         .stop_tx        = serial_lpc32xx_stop_tx,
 618         .start_tx       = serial_lpc32xx_start_tx,
 619         .stop_rx        = serial_lpc32xx_stop_rx,
 620         .break_ctl      = serial_lpc32xx_break_ctl,
 621         .startup        = serial_lpc32xx_startup,
 622         .shutdown       = serial_lpc32xx_shutdown,
 623         .set_termios    = serial_lpc32xx_set_termios,
 624         .type           = serial_lpc32xx_type,
 625         .release_port   = serial_lpc32xx_release_port,
 626         .request_port   = serial_lpc32xx_request_port,
 627         .config_port    = serial_lpc32xx_config_port,
 628         .verify_port    = serial_lpc32xx_verify_port,
 629 };
 630
 631 /*
 632  * Register a set of serial devices attached to a platform device
 633  */
 634 static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
 635 {
 636         struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
 637         int ret = 0;
 638         struct resource *res;
 639
 640         if (uarts_registered >= MAX_PORTS) {
 641                 dev_err(&pdev->dev,
 642                         "Error: Number of possible ports exceeded (%d)!\n",
 643                         uarts_registered + 1);
 644                 return -ENXIO;
 645         }
 646
 647         memset(p, 0, sizeof(*p));
 648
 649         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 650         if (!res) {
 651                 dev_err(&pdev->dev,
 652                         "Error getting mem resource for HS UART port %d\n",
 653                         uarts_registered);
 654                 return -ENXIO;
 655         }
 656         p->port.mapbase = res->start;
 657         p->port.membase = NULL;
 658
 659         ret = platform_get_irq(pdev, 0);
 660         if (ret < 0)
 661                 return ret;
 662         p->port.irq = ret;
 663
 664         p->port.iotype = UPIO_MEM32;
 665         p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
 666         p->port.regshift = 2;
 667         p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
 668         p->port.dev = &pdev->dev;
 669         p->port.ops = &serial_lpc32xx_pops;
 670         p->port.line = uarts_registered++;
 671         spin_lock_init(&p->port.lock);
 672
 673         /* send port to loopback mode by default */
 674         lpc32xx_loopback_set(p->port.mapbase, 1);
 675
 676         ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
 677
 678         platform_set_drvdata(pdev, p);
 679
 680         return ret;
 681 }
 682
 683 /*
 684  * Remove serial ports registered against a platform device.
 685  */
 686 static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
 687 {
 688         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
 689
 690         uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
 691
 692         return 0;
 693 }
 694
 695
 696 #ifdef CONFIG_PM
 697 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
 698                                      pm_message_t state)
 699 {
 700         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
 701
 702         uart_suspend_port(&lpc32xx_hs_reg, &p->port);
 703
 704         return 0;
 705 }
 706
 707 static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
 708 {
 709         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
 710
 711         uart_resume_port(&lpc32xx_hs_reg, &p->port);
 712
 713         return 0;
 714 }
 715 #else
 716 #define serial_hs_lpc32xx_suspend       NULL
 717 #define serial_hs_lpc32xx_resume        NULL
 718 #endif
 719
 720 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
 721         { .compatible = "nxp,lpc3220-hsuart" },
 722         { /* sentinel */ }
 723 };
 724
 725 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
 726
 727 static struct platform_driver serial_hs_lpc32xx_driver = {
 728         .probe          = serial_hs_lpc32xx_probe,
 729         .remove         = serial_hs_lpc32xx_remove,
 730         .suspend        = serial_hs_lpc32xx_suspend,
 731         .resume         = serial_hs_lpc32xx_resume,
 732         .driver         = {
 733                 .name   = MODNAME,
 734                 .of_match_table = serial_hs_lpc32xx_dt_ids,
 735         },
 736 };
 737
 738 static int __init lpc32xx_hsuart_init(void)
 739 {
 740         int ret;
 741
 742         ret = uart_register_driver(&lpc32xx_hs_reg);
 743         if (ret)
 744                 return ret;
 745
 746         ret = platform_driver_register(&serial_hs_lpc32xx_driver);
 747         if (ret)
 748                 uart_unregister_driver(&lpc32xx_hs_reg);
 749
 750         return ret;
 751 }
 752
 753 static void __exit lpc32xx_hsuart_exit(void)
 754 {
 755         platform_driver_unregister(&serial_hs_lpc32xx_driver);
 756         uart_unregister_driver(&lpc32xx_hs_reg);
 757 }
 758
 759 module_init(lpc32xx_hsuart_init);
 760 module_exit(lpc32xx_hsuart_exit);
 761
 762 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
 763 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
 764 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
 765 MODULE_LICENSE("GPL");