2 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 * Copyright (C) 2004 Infineon IFAP DC COM CPE
18 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
19 * Copyright (C) 2007 John Crispin <john@phrozen.org>
20 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
23 #include <linux/slab.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/device.h>
29 #include <linux/tty.h>
30 #include <linux/tty_flip.h>
31 #include <linux/serial_core.h>
32 #include <linux/serial.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
37 #include <linux/clk.h>
38 #include <linux/gpio.h>
40 #include <lantiq_soc.h>
42 #define PORT_LTQ_ASC 111
44 #define UART_DUMMY_UER_RX 1
45 #define DRVNAME "lantiq,asc"
47 #define LTQ_ASC_TBUF (0x0020 + 3)
48 #define LTQ_ASC_RBUF (0x0024 + 3)
50 #define LTQ_ASC_TBUF 0x0020
51 #define LTQ_ASC_RBUF 0x0024
53 #define LTQ_ASC_FSTAT 0x0048
54 #define LTQ_ASC_WHBSTATE 0x0018
55 #define LTQ_ASC_STATE 0x0014
56 #define LTQ_ASC_IRNCR 0x00F8
57 #define LTQ_ASC_CLC 0x0000
58 #define LTQ_ASC_ID 0x0008
59 #define LTQ_ASC_PISEL 0x0004
60 #define LTQ_ASC_TXFCON 0x0044
61 #define LTQ_ASC_RXFCON 0x0040
62 #define LTQ_ASC_CON 0x0010
63 #define LTQ_ASC_BG 0x0050
64 #define LTQ_ASC_IRNREN 0x00F4
66 #define ASC_IRNREN_TX 0x1
67 #define ASC_IRNREN_RX 0x2
68 #define ASC_IRNREN_ERR 0x4
69 #define ASC_IRNREN_TX_BUF 0x8
70 #define ASC_IRNCR_TIR 0x1
71 #define ASC_IRNCR_RIR 0x2
72 #define ASC_IRNCR_EIR 0x4
74 #define ASCOPT_CSIZE 0x3
77 #define ASCCLC_DISS 0x2
78 #define ASCCLC_RMCMASK 0x0000FF00
79 #define ASCCLC_RMCOFFSET 8
80 #define ASCCON_M_8ASYNC 0x0
81 #define ASCCON_M_7ASYNC 0x2
82 #define ASCCON_ODD 0x00000020
83 #define ASCCON_STP 0x00000080
84 #define ASCCON_BRS 0x00000100
85 #define ASCCON_FDE 0x00000200
86 #define ASCCON_R 0x00008000
87 #define ASCCON_FEN 0x00020000
88 #define ASCCON_ROEN 0x00080000
89 #define ASCCON_TOEN 0x00100000
90 #define ASCSTATE_PE 0x00010000
91 #define ASCSTATE_FE 0x00020000
92 #define ASCSTATE_ROE 0x00080000
93 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
94 #define ASCWHBSTATE_CLRREN 0x00000001
95 #define ASCWHBSTATE_SETREN 0x00000002
96 #define ASCWHBSTATE_CLRPE 0x00000004
97 #define ASCWHBSTATE_CLRFE 0x00000008
98 #define ASCWHBSTATE_CLRROE 0x00000020
99 #define ASCTXFCON_TXFEN 0x0001
100 #define ASCTXFCON_TXFFLU 0x0002
101 #define ASCTXFCON_TXFITLMASK 0x3F00
102 #define ASCTXFCON_TXFITLOFF 8
103 #define ASCRXFCON_RXFEN 0x0001
104 #define ASCRXFCON_RXFFLU 0x0002
105 #define ASCRXFCON_RXFITLMASK 0x3F00
106 #define ASCRXFCON_RXFITLOFF 8
107 #define ASCFSTAT_RXFFLMASK 0x003F
108 #define ASCFSTAT_TXFFLMASK 0x3F00
109 #define ASCFSTAT_TXFREEMASK 0x3F000000
110 #define ASCFSTAT_TXFREEOFF 24
112 static void lqasc_tx_chars(struct uart_port *port);
113 static struct ltq_uart_port *lqasc_port[MAXPORTS];
114 static struct uart_driver lqasc_reg;
115 static DEFINE_SPINLOCK(ltq_asc_lock);
117 struct ltq_uart_port {
118 struct uart_port port;
119 /* clock used to derive divider */
121 /* clock gating of the ASC core */
125 unsigned int err_irq;
129 ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
131 return container_of(port, struct ltq_uart_port, port);
135 lqasc_stop_tx(struct uart_port *port)
141 lqasc_start_tx(struct uart_port *port)
144 spin_lock_irqsave(<q_asc_lock, flags);
145 lqasc_tx_chars(port);
146 spin_unlock_irqrestore(<q_asc_lock, flags);
151 lqasc_stop_rx(struct uart_port *port)
153 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
157 lqasc_rx_chars(struct uart_port *port)
159 struct tty_port *tport = &port->state->port;
160 unsigned int ch = 0, rsr = 0, fifocnt;
162 fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
164 u8 flag = TTY_NORMAL;
165 ch = ltq_r8(port->membase + LTQ_ASC_RBUF);
166 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE)
167 & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
168 tty_flip_buffer_push(tport);
172 * Note that the error handling code is
173 * out of the main execution path
175 if (rsr & ASCSTATE_ANY) {
176 if (rsr & ASCSTATE_PE) {
177 port->icount.parity++;
178 ltq_w32_mask(0, ASCWHBSTATE_CLRPE,
179 port->membase + LTQ_ASC_WHBSTATE);
180 } else if (rsr & ASCSTATE_FE) {
181 port->icount.frame++;
182 ltq_w32_mask(0, ASCWHBSTATE_CLRFE,
183 port->membase + LTQ_ASC_WHBSTATE);
185 if (rsr & ASCSTATE_ROE) {
186 port->icount.overrun++;
187 ltq_w32_mask(0, ASCWHBSTATE_CLRROE,
188 port->membase + LTQ_ASC_WHBSTATE);
191 rsr &= port->read_status_mask;
193 if (rsr & ASCSTATE_PE)
195 else if (rsr & ASCSTATE_FE)
199 if ((rsr & port->ignore_status_mask) == 0)
200 tty_insert_flip_char(tport, ch, flag);
202 if (rsr & ASCSTATE_ROE)
204 * Overrun is special, since it's reported
205 * immediately, and doesn't affect the current
208 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
212 tty_flip_buffer_push(tport);
218 lqasc_tx_chars(struct uart_port *port)
220 struct circ_buf *xmit = &port->state->xmit;
221 if (uart_tx_stopped(port)) {
226 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) &
227 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
229 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF);
235 if (uart_circ_empty(xmit))
238 ltq_w8(port->state->xmit.buf[port->state->xmit.tail],
239 port->membase + LTQ_ASC_TBUF);
240 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
244 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
245 uart_write_wakeup(port);
249 lqasc_tx_int(int irq, void *_port)
252 struct uart_port *port = (struct uart_port *)_port;
253 spin_lock_irqsave(<q_asc_lock, flags);
254 ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
255 spin_unlock_irqrestore(<q_asc_lock, flags);
256 lqasc_start_tx(port);
261 lqasc_err_int(int irq, void *_port)
264 struct uart_port *port = (struct uart_port *)_port;
265 spin_lock_irqsave(<q_asc_lock, flags);
266 ltq_w32(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR);
267 /* clear any pending interrupts */
268 ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
269 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
270 spin_unlock_irqrestore(<q_asc_lock, flags);
275 lqasc_rx_int(int irq, void *_port)
278 struct uart_port *port = (struct uart_port *)_port;
279 spin_lock_irqsave(<q_asc_lock, flags);
280 ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
281 lqasc_rx_chars(port);
282 spin_unlock_irqrestore(<q_asc_lock, flags);
287 lqasc_tx_empty(struct uart_port *port)
290 status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
291 return status ? 0 : TIOCSER_TEMT;
295 lqasc_get_mctrl(struct uart_port *port)
297 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
301 lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
306 lqasc_break_ctl(struct uart_port *port, int break_state)
311 lqasc_startup(struct uart_port *port)
313 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
316 if (!IS_ERR(ltq_port->clk))
317 clk_enable(ltq_port->clk);
318 port->uartclk = clk_get_rate(ltq_port->fpiclk);
320 ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
321 port->membase + LTQ_ASC_CLC);
323 ltq_w32(0, port->membase + LTQ_ASC_PISEL);
325 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
326 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
327 port->membase + LTQ_ASC_TXFCON);
329 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
330 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
331 port->membase + LTQ_ASC_RXFCON);
332 /* make sure other settings are written to hardware before
333 * setting enable bits
336 ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
337 ASCCON_ROEN, port->membase + LTQ_ASC_CON);
339 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
342 pr_err("failed to request lqasc_tx_int\n");
346 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
349 pr_err("failed to request lqasc_rx_int\n");
353 retval = request_irq(ltq_port->err_irq, lqasc_err_int,
356 pr_err("failed to request lqasc_err_int\n");
360 ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
361 port->membase + LTQ_ASC_IRNREN);
365 free_irq(ltq_port->rx_irq, port);
367 free_irq(ltq_port->tx_irq, port);
372 lqasc_shutdown(struct uart_port *port)
374 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
375 free_irq(ltq_port->tx_irq, port);
376 free_irq(ltq_port->rx_irq, port);
377 free_irq(ltq_port->err_irq, port);
379 ltq_w32(0, port->membase + LTQ_ASC_CON);
380 ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
381 port->membase + LTQ_ASC_RXFCON);
382 ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
383 port->membase + LTQ_ASC_TXFCON);
384 if (!IS_ERR(ltq_port->clk))
385 clk_disable(ltq_port->clk);
389 lqasc_set_termios(struct uart_port *port,
390 struct ktermios *new, struct ktermios *old)
394 unsigned int divisor;
396 unsigned int con = 0;
399 cflag = new->c_cflag;
400 iflag = new->c_iflag;
402 switch (cflag & CSIZE) {
404 con = ASCCON_M_7ASYNC;
410 new->c_cflag &= ~ CSIZE;
412 con = ASCCON_M_8ASYNC;
416 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
421 if (cflag & PARENB) {
422 if (!(cflag & PARODD))
428 port->read_status_mask = ASCSTATE_ROE;
430 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
432 port->ignore_status_mask = 0;
434 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
436 if (iflag & IGNBRK) {
438 * If we're ignoring parity and break indicators,
439 * ignore overruns too (for real raw support).
442 port->ignore_status_mask |= ASCSTATE_ROE;
445 if ((cflag & CREAD) == 0)
446 port->ignore_status_mask |= UART_DUMMY_UER_RX;
448 /* set error signals - framing, parity and overrun, enable receiver */
449 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
451 spin_lock_irqsave(<q_asc_lock, flags);
454 ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON);
456 /* Set baud rate - take a divider of 2 into account */
457 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
458 divisor = uart_get_divisor(port, baud);
459 divisor = divisor / 2 - 1;
461 /* disable the baudrate generator */
462 ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
464 /* make sure the fractional divider is off */
465 ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
467 /* set up to use divisor of 2 */
468 ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
470 /* now we can write the new baudrate into the register */
471 ltq_w32(divisor, port->membase + LTQ_ASC_BG);
473 /* turn the baudrate generator back on */
474 ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON);
477 ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
479 spin_unlock_irqrestore(<q_asc_lock, flags);
481 /* Don't rewrite B0 */
482 if (tty_termios_baud_rate(new))
483 tty_termios_encode_baud_rate(new, baud, baud);
485 uart_update_timeout(port, cflag, baud);
489 lqasc_type(struct uart_port *port)
491 if (port->type == PORT_LTQ_ASC)
498 lqasc_release_port(struct uart_port *port)
500 struct platform_device *pdev = to_platform_device(port->dev);
502 if (port->flags & UPF_IOREMAP) {
503 devm_iounmap(&pdev->dev, port->membase);
504 port->membase = NULL;
509 lqasc_request_port(struct uart_port *port)
511 struct platform_device *pdev = to_platform_device(port->dev);
512 struct resource *res;
515 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
517 dev_err(&pdev->dev, "cannot obtain I/O memory region");
520 size = resource_size(res);
522 res = devm_request_mem_region(&pdev->dev, res->start,
523 size, dev_name(&pdev->dev));
525 dev_err(&pdev->dev, "cannot request I/O memory region");
529 if (port->flags & UPF_IOREMAP) {
530 port->membase = devm_ioremap_nocache(&pdev->dev,
531 port->mapbase, size);
532 if (port->membase == NULL)
539 lqasc_config_port(struct uart_port *port, int flags)
541 if (flags & UART_CONFIG_TYPE) {
542 port->type = PORT_LTQ_ASC;
543 lqasc_request_port(port);
548 lqasc_verify_port(struct uart_port *port,
549 struct serial_struct *ser)
552 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
554 if (ser->irq < 0 || ser->irq >= NR_IRQS)
556 if (ser->baud_base < 9600)
561 static const struct uart_ops lqasc_pops = {
562 .tx_empty = lqasc_tx_empty,
563 .set_mctrl = lqasc_set_mctrl,
564 .get_mctrl = lqasc_get_mctrl,
565 .stop_tx = lqasc_stop_tx,
566 .start_tx = lqasc_start_tx,
567 .stop_rx = lqasc_stop_rx,
568 .break_ctl = lqasc_break_ctl,
569 .startup = lqasc_startup,
570 .shutdown = lqasc_shutdown,
571 .set_termios = lqasc_set_termios,
573 .release_port = lqasc_release_port,
574 .request_port = lqasc_request_port,
575 .config_port = lqasc_config_port,
576 .verify_port = lqasc_verify_port,
580 lqasc_console_putchar(struct uart_port *port, int ch)
588 fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT)
589 & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
590 } while (fifofree == 0);
591 ltq_w8(ch, port->membase + LTQ_ASC_TBUF);
594 static void lqasc_serial_port_write(struct uart_port *port, const char *s,
599 spin_lock_irqsave(<q_asc_lock, flags);
600 uart_console_write(port, s, count, lqasc_console_putchar);
601 spin_unlock_irqrestore(<q_asc_lock, flags);
605 lqasc_console_write(struct console *co, const char *s, u_int count)
607 struct ltq_uart_port *ltq_port;
609 if (co->index >= MAXPORTS)
612 ltq_port = lqasc_port[co->index];
616 lqasc_serial_port_write(<q_port->port, s, count);
620 lqasc_console_setup(struct console *co, char *options)
622 struct ltq_uart_port *ltq_port;
623 struct uart_port *port;
629 if (co->index >= MAXPORTS)
632 ltq_port = lqasc_port[co->index];
636 port = <q_port->port;
638 if (!IS_ERR(ltq_port->clk))
639 clk_enable(ltq_port->clk);
641 port->uartclk = clk_get_rate(ltq_port->fpiclk);
644 uart_parse_options(options, &baud, &parity, &bits, &flow);
645 return uart_set_options(port, co, baud, parity, bits, flow);
648 static struct console lqasc_console = {
650 .write = lqasc_console_write,
651 .device = uart_console_device,
652 .setup = lqasc_console_setup,
653 .flags = CON_PRINTBUFFER,
659 lqasc_console_init(void)
661 register_console(&lqasc_console);
664 console_initcall(lqasc_console_init);
666 static void lqasc_serial_early_console_write(struct console *co,
670 struct earlycon_device *dev = co->data;
672 lqasc_serial_port_write(&dev->port, s, count);
676 lqasc_serial_early_console_setup(struct earlycon_device *device,
679 if (!device->port.membase)
682 device->con->write = lqasc_serial_early_console_write;
685 OF_EARLYCON_DECLARE(lantiq, DRVNAME, lqasc_serial_early_console_setup);
687 static struct uart_driver lqasc_reg = {
688 .owner = THIS_MODULE,
689 .driver_name = DRVNAME,
690 .dev_name = "ttyLTQ",
694 .cons = &lqasc_console,
698 lqasc_probe(struct platform_device *pdev)
700 struct device_node *node = pdev->dev.of_node;
701 struct ltq_uart_port *ltq_port;
702 struct uart_port *port;
703 struct resource *mmres, irqres[3];
707 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
708 ret = of_irq_to_resource_table(node, irqres, 3);
709 if (!mmres || (ret != 3)) {
711 "failed to get memory/irq for serial port\n");
715 /* check if this is the console port */
716 if (mmres->start != CPHYSADDR(LTQ_EARLY_ASC))
719 if (lqasc_port[line]) {
720 dev_err(&pdev->dev, "port %d already allocated\n", line);
724 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
729 port = <q_port->port;
731 port->iotype = SERIAL_IO_MEM;
732 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
733 port->ops = &lqasc_pops;
735 port->type = PORT_LTQ_ASC,
737 port->dev = &pdev->dev;
738 /* unused, just to be backward-compatible */
739 port->irq = irqres[0].start;
740 port->mapbase = mmres->start;
742 ltq_port->fpiclk = clk_get_fpi();
743 if (IS_ERR(ltq_port->fpiclk)) {
744 pr_err("failed to get fpi clk\n");
748 /* not all asc ports have clock gates, lets ignore the return code */
749 ltq_port->clk = clk_get(&pdev->dev, NULL);
751 ltq_port->tx_irq = irqres[0].start;
752 ltq_port->rx_irq = irqres[1].start;
753 ltq_port->err_irq = irqres[2].start;
755 lqasc_port[line] = ltq_port;
756 platform_set_drvdata(pdev, ltq_port);
758 ret = uart_add_one_port(&lqasc_reg, port);
763 static const struct of_device_id ltq_asc_match[] = {
764 { .compatible = DRVNAME },
768 static struct platform_driver lqasc_driver = {
771 .of_match_table = ltq_asc_match,
780 ret = uart_register_driver(&lqasc_reg);
784 ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
786 uart_unregister_driver(&lqasc_reg);
790 device_initcall(init_lqasc);