1 // SPDX-License-Identifier: GPL-2.0
3 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Copyright (C) 2004 Infineon IFAP DC COM CPE
6 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
7 * Copyright (C) 2007 John Crispin <john@phrozen.org>
8 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
11 #include <linux/clk.h>
12 #include <linux/console.h>
13 #include <linux/device.h>
14 #include <linux/init.h>
16 #include <linux/ioport.h>
17 #include <linux/lantiq.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/serial.h>
23 #include <linux/serial_core.h>
24 #include <linux/slab.h>
25 #include <linux/sysrq.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
29 #define PORT_LTQ_ASC 111
31 #define UART_DUMMY_UER_RX 1
32 #define DRVNAME "lantiq,asc"
34 #define LTQ_ASC_TBUF (0x0020 + 3)
35 #define LTQ_ASC_RBUF (0x0024 + 3)
37 #define LTQ_ASC_TBUF 0x0020
38 #define LTQ_ASC_RBUF 0x0024
40 #define LTQ_ASC_FSTAT 0x0048
41 #define LTQ_ASC_WHBSTATE 0x0018
42 #define LTQ_ASC_STATE 0x0014
43 #define LTQ_ASC_IRNCR 0x00F8
44 #define LTQ_ASC_CLC 0x0000
45 #define LTQ_ASC_ID 0x0008
46 #define LTQ_ASC_PISEL 0x0004
47 #define LTQ_ASC_TXFCON 0x0044
48 #define LTQ_ASC_RXFCON 0x0040
49 #define LTQ_ASC_CON 0x0010
50 #define LTQ_ASC_BG 0x0050
51 #define LTQ_ASC_IRNREN 0x00F4
53 #define ASC_IRNREN_TX 0x1
54 #define ASC_IRNREN_RX 0x2
55 #define ASC_IRNREN_ERR 0x4
56 #define ASC_IRNREN_TX_BUF 0x8
57 #define ASC_IRNCR_TIR 0x1
58 #define ASC_IRNCR_RIR 0x2
59 #define ASC_IRNCR_EIR 0x4
60 #define ASC_IRNCR_MASK GENMASK(2, 0)
62 #define ASCOPT_CSIZE 0x3
65 #define ASCCLC_DISS 0x2
66 #define ASCCLC_RMCMASK 0x0000FF00
67 #define ASCCLC_RMCOFFSET 8
68 #define ASCCON_M_8ASYNC 0x0
69 #define ASCCON_M_7ASYNC 0x2
70 #define ASCCON_ODD 0x00000020
71 #define ASCCON_STP 0x00000080
72 #define ASCCON_BRS 0x00000100
73 #define ASCCON_FDE 0x00000200
74 #define ASCCON_R 0x00008000
75 #define ASCCON_FEN 0x00020000
76 #define ASCCON_ROEN 0x00080000
77 #define ASCCON_TOEN 0x00100000
78 #define ASCSTATE_PE 0x00010000
79 #define ASCSTATE_FE 0x00020000
80 #define ASCSTATE_ROE 0x00080000
81 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
82 #define ASCWHBSTATE_CLRREN 0x00000001
83 #define ASCWHBSTATE_SETREN 0x00000002
84 #define ASCWHBSTATE_CLRPE 0x00000004
85 #define ASCWHBSTATE_CLRFE 0x00000008
86 #define ASCWHBSTATE_CLRROE 0x00000020
87 #define ASCTXFCON_TXFEN 0x0001
88 #define ASCTXFCON_TXFFLU 0x0002
89 #define ASCTXFCON_TXFITLMASK 0x3F00
90 #define ASCTXFCON_TXFITLOFF 8
91 #define ASCRXFCON_RXFEN 0x0001
92 #define ASCRXFCON_RXFFLU 0x0002
93 #define ASCRXFCON_RXFITLMASK 0x3F00
94 #define ASCRXFCON_RXFITLOFF 8
95 #define ASCFSTAT_RXFFLMASK 0x003F
96 #define ASCFSTAT_TXFFLMASK 0x3F00
97 #define ASCFSTAT_TXFREEMASK 0x3F000000
98 #define ASCFSTAT_TXFREEOFF 24
100 static void lqasc_tx_chars(struct uart_port *port);
101 static struct ltq_uart_port *lqasc_port[MAXPORTS];
102 static struct uart_driver lqasc_reg;
104 struct ltq_soc_data {
105 int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port);
106 int (*request_irq)(struct uart_port *port);
107 void (*free_irq)(struct uart_port *port);
110 struct ltq_uart_port {
111 struct uart_port port;
112 /* clock used to derive divider */
114 /* clock gating of the ASC core */
118 unsigned int err_irq;
119 unsigned int common_irq;
120 spinlock_t lock; /* exclusive access for multi core */
122 const struct ltq_soc_data *soc;
125 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
127 u32 tmp = __raw_readl(reg);
129 __raw_writel((tmp & ~clear) | set, reg);
133 ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
135 return container_of(port, struct ltq_uart_port, port);
139 lqasc_stop_tx(struct uart_port *port)
145 lqasc_start_tx(struct uart_port *port)
148 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
150 spin_lock_irqsave(<q_port->lock, flags);
151 lqasc_tx_chars(port);
152 spin_unlock_irqrestore(<q_port->lock, flags);
157 lqasc_stop_rx(struct uart_port *port)
159 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
163 lqasc_rx_chars(struct uart_port *port)
165 struct tty_port *tport = &port->state->port;
166 unsigned int ch = 0, rsr = 0, fifocnt;
168 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
171 u8 flag = TTY_NORMAL;
172 ch = readb(port->membase + LTQ_ASC_RBUF);
173 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
174 & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
175 tty_flip_buffer_push(tport);
179 * Note that the error handling code is
180 * out of the main execution path
182 if (rsr & ASCSTATE_ANY) {
183 if (rsr & ASCSTATE_PE) {
184 port->icount.parity++;
185 asc_update_bits(0, ASCWHBSTATE_CLRPE,
186 port->membase + LTQ_ASC_WHBSTATE);
187 } else if (rsr & ASCSTATE_FE) {
188 port->icount.frame++;
189 asc_update_bits(0, ASCWHBSTATE_CLRFE,
190 port->membase + LTQ_ASC_WHBSTATE);
192 if (rsr & ASCSTATE_ROE) {
193 port->icount.overrun++;
194 asc_update_bits(0, ASCWHBSTATE_CLRROE,
195 port->membase + LTQ_ASC_WHBSTATE);
198 rsr &= port->read_status_mask;
200 if (rsr & ASCSTATE_PE)
202 else if (rsr & ASCSTATE_FE)
206 if ((rsr & port->ignore_status_mask) == 0)
207 tty_insert_flip_char(tport, ch, flag);
209 if (rsr & ASCSTATE_ROE)
211 * Overrun is special, since it's reported
212 * immediately, and doesn't affect the current
215 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
219 tty_flip_buffer_push(tport);
225 lqasc_tx_chars(struct uart_port *port)
227 struct circ_buf *xmit = &port->state->xmit;
228 if (uart_tx_stopped(port)) {
233 while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) &
234 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
236 writeb(port->x_char, port->membase + LTQ_ASC_TBUF);
242 if (uart_circ_empty(xmit))
245 writeb(port->state->xmit.buf[port->state->xmit.tail],
246 port->membase + LTQ_ASC_TBUF);
247 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
251 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
252 uart_write_wakeup(port);
256 lqasc_tx_int(int irq, void *_port)
259 struct uart_port *port = (struct uart_port *)_port;
260 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
262 spin_lock_irqsave(<q_port->lock, flags);
263 __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
264 spin_unlock_irqrestore(<q_port->lock, flags);
265 lqasc_start_tx(port);
270 lqasc_err_int(int irq, void *_port)
273 struct uart_port *port = (struct uart_port *)_port;
274 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
276 spin_lock_irqsave(<q_port->lock, flags);
277 __raw_writel(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR);
278 /* clear any pending interrupts */
279 asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
280 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
281 spin_unlock_irqrestore(<q_port->lock, flags);
286 lqasc_rx_int(int irq, void *_port)
289 struct uart_port *port = (struct uart_port *)_port;
290 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
292 spin_lock_irqsave(<q_port->lock, flags);
293 __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
294 lqasc_rx_chars(port);
295 spin_unlock_irqrestore(<q_port->lock, flags);
299 static irqreturn_t lqasc_irq(int irq, void *p)
303 struct uart_port *port = p;
304 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
306 spin_lock_irqsave(<q_port->lock, flags);
307 stat = readl(port->membase + LTQ_ASC_IRNCR);
308 spin_unlock_irqrestore(<q_port->lock, flags);
309 if (!(stat & ASC_IRNCR_MASK))
312 if (stat & ASC_IRNCR_TIR)
313 lqasc_tx_int(irq, p);
315 if (stat & ASC_IRNCR_RIR)
316 lqasc_rx_int(irq, p);
318 if (stat & ASC_IRNCR_EIR)
319 lqasc_err_int(irq, p);
325 lqasc_tx_empty(struct uart_port *port)
328 status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
330 return status ? 0 : TIOCSER_TEMT;
334 lqasc_get_mctrl(struct uart_port *port)
336 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
340 lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
345 lqasc_break_ctl(struct uart_port *port, int break_state)
350 lqasc_startup(struct uart_port *port)
352 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
356 if (!IS_ERR(ltq_port->clk))
357 clk_prepare_enable(ltq_port->clk);
358 port->uartclk = clk_get_rate(ltq_port->freqclk);
360 spin_lock_irqsave(<q_port->lock, flags);
361 asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
362 port->membase + LTQ_ASC_CLC);
364 __raw_writel(0, port->membase + LTQ_ASC_PISEL);
366 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
367 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
368 port->membase + LTQ_ASC_TXFCON);
370 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
371 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
372 port->membase + LTQ_ASC_RXFCON);
373 /* make sure other settings are written to hardware before
374 * setting enable bits
377 asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
378 ASCCON_ROEN, port->membase + LTQ_ASC_CON);
380 spin_unlock_irqrestore(<q_port->lock, flags);
382 retval = ltq_port->soc->request_irq(port);
386 __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
387 port->membase + LTQ_ASC_IRNREN);
392 lqasc_shutdown(struct uart_port *port)
394 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
397 ltq_port->soc->free_irq(port);
399 spin_lock_irqsave(<q_port->lock, flags);
400 __raw_writel(0, port->membase + LTQ_ASC_CON);
401 asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
402 port->membase + LTQ_ASC_RXFCON);
403 asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
404 port->membase + LTQ_ASC_TXFCON);
405 spin_unlock_irqrestore(<q_port->lock, flags);
406 if (!IS_ERR(ltq_port->clk))
407 clk_disable_unprepare(ltq_port->clk);
411 lqasc_set_termios(struct uart_port *port,
412 struct ktermios *new, struct ktermios *old)
416 unsigned int divisor;
418 unsigned int con = 0;
420 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
422 cflag = new->c_cflag;
423 iflag = new->c_iflag;
425 switch (cflag & CSIZE) {
427 con = ASCCON_M_7ASYNC;
433 new->c_cflag &= ~ CSIZE;
435 con = ASCCON_M_8ASYNC;
439 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
444 if (cflag & PARENB) {
445 if (!(cflag & PARODD))
451 port->read_status_mask = ASCSTATE_ROE;
453 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
455 port->ignore_status_mask = 0;
457 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
459 if (iflag & IGNBRK) {
461 * If we're ignoring parity and break indicators,
462 * ignore overruns too (for real raw support).
465 port->ignore_status_mask |= ASCSTATE_ROE;
468 if ((cflag & CREAD) == 0)
469 port->ignore_status_mask |= UART_DUMMY_UER_RX;
471 /* set error signals - framing, parity and overrun, enable receiver */
472 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
474 spin_lock_irqsave(<q_port->lock, flags);
477 asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
479 /* Set baud rate - take a divider of 2 into account */
480 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
481 divisor = uart_get_divisor(port, baud);
482 divisor = divisor / 2 - 1;
484 /* disable the baudrate generator */
485 asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
487 /* make sure the fractional divider is off */
488 asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
490 /* set up to use divisor of 2 */
491 asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
493 /* now we can write the new baudrate into the register */
494 __raw_writel(divisor, port->membase + LTQ_ASC_BG);
496 /* turn the baudrate generator back on */
497 asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
500 __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
502 spin_unlock_irqrestore(<q_port->lock, flags);
504 /* Don't rewrite B0 */
505 if (tty_termios_baud_rate(new))
506 tty_termios_encode_baud_rate(new, baud, baud);
508 uart_update_timeout(port, cflag, baud);
512 lqasc_type(struct uart_port *port)
514 if (port->type == PORT_LTQ_ASC)
521 lqasc_release_port(struct uart_port *port)
523 struct platform_device *pdev = to_platform_device(port->dev);
525 if (port->flags & UPF_IOREMAP) {
526 devm_iounmap(&pdev->dev, port->membase);
527 port->membase = NULL;
532 lqasc_request_port(struct uart_port *port)
534 struct platform_device *pdev = to_platform_device(port->dev);
535 struct resource *res;
538 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
540 dev_err(&pdev->dev, "cannot obtain I/O memory region");
543 size = resource_size(res);
545 res = devm_request_mem_region(&pdev->dev, res->start,
546 size, dev_name(&pdev->dev));
548 dev_err(&pdev->dev, "cannot request I/O memory region");
552 if (port->flags & UPF_IOREMAP) {
553 port->membase = devm_ioremap(&pdev->dev,
554 port->mapbase, size);
555 if (port->membase == NULL)
562 lqasc_config_port(struct uart_port *port, int flags)
564 if (flags & UART_CONFIG_TYPE) {
565 port->type = PORT_LTQ_ASC;
566 lqasc_request_port(port);
571 lqasc_verify_port(struct uart_port *port,
572 struct serial_struct *ser)
575 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
577 if (ser->irq < 0 || ser->irq >= NR_IRQS)
579 if (ser->baud_base < 9600)
584 static const struct uart_ops lqasc_pops = {
585 .tx_empty = lqasc_tx_empty,
586 .set_mctrl = lqasc_set_mctrl,
587 .get_mctrl = lqasc_get_mctrl,
588 .stop_tx = lqasc_stop_tx,
589 .start_tx = lqasc_start_tx,
590 .stop_rx = lqasc_stop_rx,
591 .break_ctl = lqasc_break_ctl,
592 .startup = lqasc_startup,
593 .shutdown = lqasc_shutdown,
594 .set_termios = lqasc_set_termios,
596 .release_port = lqasc_release_port,
597 .request_port = lqasc_request_port,
598 .config_port = lqasc_config_port,
599 .verify_port = lqasc_verify_port,
602 #ifdef CONFIG_SERIAL_LANTIQ_CONSOLE
604 lqasc_console_putchar(struct uart_port *port, int ch)
612 fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT)
613 & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
614 } while (fifofree == 0);
615 writeb(ch, port->membase + LTQ_ASC_TBUF);
618 static void lqasc_serial_port_write(struct uart_port *port, const char *s,
621 uart_console_write(port, s, count, lqasc_console_putchar);
625 lqasc_console_write(struct console *co, const char *s, u_int count)
627 struct ltq_uart_port *ltq_port;
630 if (co->index >= MAXPORTS)
633 ltq_port = lqasc_port[co->index];
637 spin_lock_irqsave(<q_port->lock, flags);
638 lqasc_serial_port_write(<q_port->port, s, count);
639 spin_unlock_irqrestore(<q_port->lock, flags);
643 lqasc_console_setup(struct console *co, char *options)
645 struct ltq_uart_port *ltq_port;
646 struct uart_port *port;
652 if (co->index >= MAXPORTS)
655 ltq_port = lqasc_port[co->index];
659 port = <q_port->port;
661 if (!IS_ERR(ltq_port->clk))
662 clk_prepare_enable(ltq_port->clk);
664 port->uartclk = clk_get_rate(ltq_port->freqclk);
667 uart_parse_options(options, &baud, &parity, &bits, &flow);
668 return uart_set_options(port, co, baud, parity, bits, flow);
671 static struct console lqasc_console = {
673 .write = lqasc_console_write,
674 .device = uart_console_device,
675 .setup = lqasc_console_setup,
676 .flags = CON_PRINTBUFFER,
682 lqasc_console_init(void)
684 register_console(&lqasc_console);
687 console_initcall(lqasc_console_init);
689 static void lqasc_serial_early_console_write(struct console *co,
693 struct earlycon_device *dev = co->data;
695 lqasc_serial_port_write(&dev->port, s, count);
699 lqasc_serial_early_console_setup(struct earlycon_device *device,
702 if (!device->port.membase)
705 device->con->write = lqasc_serial_early_console_write;
708 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
709 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
711 #define LANTIQ_SERIAL_CONSOLE (&lqasc_console)
715 #define LANTIQ_SERIAL_CONSOLE NULL
717 #endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */
719 static struct uart_driver lqasc_reg = {
720 .owner = THIS_MODULE,
721 .driver_name = DRVNAME,
722 .dev_name = "ttyLTQ",
726 .cons = LANTIQ_SERIAL_CONSOLE,
729 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
731 struct uart_port *port = <q_port->port;
732 struct resource irqres[3];
735 ret = of_irq_to_resource_table(dev->of_node, irqres, 3);
738 "failed to get IRQs for serial port\n");
741 ltq_port->tx_irq = irqres[0].start;
742 ltq_port->rx_irq = irqres[1].start;
743 ltq_port->err_irq = irqres[2].start;
744 port->irq = irqres[0].start;
749 static int request_irq_lantiq(struct uart_port *port)
751 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
754 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
757 dev_err(port->dev, "failed to request asc_tx\n");
761 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
764 dev_err(port->dev, "failed to request asc_rx\n");
768 retval = request_irq(ltq_port->err_irq, lqasc_err_int,
771 dev_err(port->dev, "failed to request asc_err\n");
777 free_irq(ltq_port->rx_irq, port);
779 free_irq(ltq_port->tx_irq, port);
783 static void free_irq_lantiq(struct uart_port *port)
785 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
787 free_irq(ltq_port->tx_irq, port);
788 free_irq(ltq_port->rx_irq, port);
789 free_irq(ltq_port->err_irq, port);
792 static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port)
794 struct uart_port *port = <q_port->port;
797 ret = of_irq_get(dev->of_node, 0);
799 dev_err(dev, "failed to fetch IRQ for serial port\n");
802 ltq_port->common_irq = ret;
808 static int request_irq_intel(struct uart_port *port)
810 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
813 retval = request_irq(ltq_port->common_irq, lqasc_irq, 0,
816 dev_err(port->dev, "failed to request asc_irq\n");
821 static void free_irq_intel(struct uart_port *port)
823 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
825 free_irq(ltq_port->common_irq, port);
828 static int lqasc_probe(struct platform_device *pdev)
830 struct device_node *node = pdev->dev.of_node;
831 struct ltq_uart_port *ltq_port;
832 struct uart_port *port;
833 struct resource *mmres;
837 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
840 "failed to get memory for serial port\n");
844 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
849 port = <q_port->port;
851 ltq_port->soc = of_device_get_match_data(&pdev->dev);
852 ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port);
857 line = of_alias_get_id(node, "serial");
859 if (IS_ENABLED(CONFIG_LANTIQ)) {
860 if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))
865 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
871 if (lqasc_port[line]) {
872 dev_err(&pdev->dev, "port %d already allocated\n", line);
876 port->iotype = SERIAL_IO_MEM;
877 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
878 port->ops = &lqasc_pops;
880 port->type = PORT_LTQ_ASC,
882 port->dev = &pdev->dev;
883 /* unused, just to be backward-compatible */
884 port->mapbase = mmres->start;
886 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
887 ltq_port->freqclk = clk_get_fpi();
889 ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq");
892 if (IS_ERR(ltq_port->freqclk)) {
893 pr_err("failed to get fpi clk\n");
897 /* not all asc ports have clock gates, lets ignore the return code */
898 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
899 ltq_port->clk = clk_get(&pdev->dev, NULL);
901 ltq_port->clk = devm_clk_get(&pdev->dev, "asc");
903 spin_lock_init(<q_port->lock);
904 lqasc_port[line] = ltq_port;
905 platform_set_drvdata(pdev, ltq_port);
907 ret = uart_add_one_port(&lqasc_reg, port);
912 static int lqasc_remove(struct platform_device *pdev)
914 struct uart_port *port = platform_get_drvdata(pdev);
916 return uart_remove_one_port(&lqasc_reg, port);
919 static const struct ltq_soc_data soc_data_lantiq = {
920 .fetch_irq = fetch_irq_lantiq,
921 .request_irq = request_irq_lantiq,
922 .free_irq = free_irq_lantiq,
925 static const struct ltq_soc_data soc_data_intel = {
926 .fetch_irq = fetch_irq_intel,
927 .request_irq = request_irq_intel,
928 .free_irq = free_irq_intel,
931 static const struct of_device_id ltq_asc_match[] = {
932 { .compatible = "lantiq,asc", .data = &soc_data_lantiq },
933 { .compatible = "intel,lgm-asc", .data = &soc_data_intel },
936 MODULE_DEVICE_TABLE(of, ltq_asc_match);
938 static struct platform_driver lqasc_driver = {
939 .probe = lqasc_probe,
940 .remove = lqasc_remove,
943 .of_match_table = ltq_asc_match,
952 ret = uart_register_driver(&lqasc_reg);
956 ret = platform_driver_register(&lqasc_driver);
958 uart_unregister_driver(&lqasc_reg);
963 static void __exit exit_lqasc(void)
965 platform_driver_unregister(&lqasc_driver);
966 uart_unregister_driver(&lqasc_reg);
969 module_init(init_lqasc);
970 module_exit(exit_lqasc);
972 MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs");
973 MODULE_LICENSE("GPL v2");