1 // SPDX-License-Identifier: GPL-2.0+
2 /************************************************************************
3 * Copyright 2003 Digi International (www.digi.com)
5 * Copyright (C) 2004 IBM Corporation. All rights reserved.
8 * Scott H Kilau <Scott_Kilau@digi.com>
9 * Wendy Xiong <wendyx@us.ibm.com>
11 ***********************************************************************/
12 #include <linux/delay.h> /* For udelay */
13 #include <linux/serial_reg.h> /* For the various UART offsets */
14 #include <linux/tty.h>
15 #include <linux/pci.h>
18 #include "jsm.h" /* Driver main header file */
20 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
23 * This function allows calls to ensure that all outstanding
24 * PCI writes have been completed, by doing a PCI read against
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
28 * value of the Neo card.
30 static inline void neo_pci_posting_flush(struct jsm_board *bd)
32 readb(bd->re_map_membase + 0x8D);
35 static void neo_set_cts_flow_control(struct jsm_channel *ch)
38 ier = readb(&ch->ch_neo_uart->ier);
39 efr = readb(&ch->ch_neo_uart->efr);
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
43 /* Turn on auto CTS flow control */
44 ier |= (UART_17158_IER_CTSDSR);
45 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
47 /* Turn off auto Xon flow control */
48 efr &= ~(UART_17158_EFR_IXON);
50 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
51 writeb(0, &ch->ch_neo_uart->efr);
53 /* Turn on UART enhanced bits */
54 writeb(efr, &ch->ch_neo_uart->efr);
56 /* Turn on table D, with 8 char hi/low watermarks */
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
59 /* Feed the UART our trigger levels */
60 writeb(8, &ch->ch_neo_uart->tfifo);
63 writeb(ier, &ch->ch_neo_uart->ier);
66 static void neo_set_rts_flow_control(struct jsm_channel *ch)
69 ier = readb(&ch->ch_neo_uart->ier);
70 efr = readb(&ch->ch_neo_uart->efr);
72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
74 /* Turn on auto RTS flow control */
75 ier |= (UART_17158_IER_RTSDTR);
76 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
78 /* Turn off auto Xoff flow control */
79 ier &= ~(UART_17158_IER_XOFF);
80 efr &= ~(UART_17158_EFR_IXOFF);
82 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
83 writeb(0, &ch->ch_neo_uart->efr);
85 /* Turn on UART enhanced bits */
86 writeb(efr, &ch->ch_neo_uart->efr);
88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
89 ch->ch_r_watermark = 4;
91 writeb(56, &ch->ch_neo_uart->rfifo);
94 writeb(ier, &ch->ch_neo_uart->ier);
97 * From the Neo UART spec sheet:
98 * The auto RTS/DTR function must be started by asserting
99 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
102 ch->ch_mostat |= (UART_MCR_RTS);
106 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
109 ier = readb(&ch->ch_neo_uart->ier);
110 efr = readb(&ch->ch_neo_uart->efr);
112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
114 /* Turn off auto CTS flow control */
115 ier &= ~(UART_17158_IER_CTSDSR);
116 efr &= ~(UART_17158_EFR_CTSDSR);
118 /* Turn on auto Xon flow control */
119 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
121 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
122 writeb(0, &ch->ch_neo_uart->efr);
124 /* Turn on UART enhanced bits */
125 writeb(efr, &ch->ch_neo_uart->efr);
127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
128 ch->ch_r_watermark = 4;
130 writeb(32, &ch->ch_neo_uart->rfifo);
131 ch->ch_r_tlevel = 32;
133 /* Tell UART what start/stop chars it should be looking for */
134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
135 writeb(0, &ch->ch_neo_uart->xonchar2);
137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
138 writeb(0, &ch->ch_neo_uart->xoffchar2);
140 writeb(ier, &ch->ch_neo_uart->ier);
143 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
146 ier = readb(&ch->ch_neo_uart->ier);
147 efr = readb(&ch->ch_neo_uart->efr);
149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
151 /* Turn off auto RTS flow control */
152 ier &= ~(UART_17158_IER_RTSDTR);
153 efr &= ~(UART_17158_EFR_RTSDTR);
155 /* Turn on auto Xoff flow control */
156 ier |= (UART_17158_IER_XOFF);
157 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
159 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
160 writeb(0, &ch->ch_neo_uart->efr);
162 /* Turn on UART enhanced bits */
163 writeb(efr, &ch->ch_neo_uart->efr);
165 /* Turn on table D, with 8 char hi/low watermarks */
166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
168 writeb(8, &ch->ch_neo_uart->tfifo);
171 /* Tell UART what start/stop chars it should be looking for */
172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
173 writeb(0, &ch->ch_neo_uart->xonchar2);
175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
176 writeb(0, &ch->ch_neo_uart->xoffchar2);
178 writeb(ier, &ch->ch_neo_uart->ier);
181 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
184 ier = readb(&ch->ch_neo_uart->ier);
185 efr = readb(&ch->ch_neo_uart->efr);
187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
189 /* Turn off auto RTS flow control */
190 ier &= ~(UART_17158_IER_RTSDTR);
191 efr &= ~(UART_17158_EFR_RTSDTR);
193 /* Turn off auto Xoff flow control */
194 ier &= ~(UART_17158_IER_XOFF);
195 if (ch->ch_c_iflag & IXON)
196 efr &= ~(UART_17158_EFR_IXOFF);
198 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
200 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
201 writeb(0, &ch->ch_neo_uart->efr);
203 /* Turn on UART enhanced bits */
204 writeb(efr, &ch->ch_neo_uart->efr);
206 /* Turn on table D, with 8 char hi/low watermarks */
207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
209 ch->ch_r_watermark = 0;
211 writeb(16, &ch->ch_neo_uart->tfifo);
212 ch->ch_t_tlevel = 16;
214 writeb(16, &ch->ch_neo_uart->rfifo);
215 ch->ch_r_tlevel = 16;
217 writeb(ier, &ch->ch_neo_uart->ier);
220 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
223 ier = readb(&ch->ch_neo_uart->ier);
224 efr = readb(&ch->ch_neo_uart->efr);
226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
228 /* Turn off auto CTS flow control */
229 ier &= ~(UART_17158_IER_CTSDSR);
230 efr &= ~(UART_17158_EFR_CTSDSR);
232 /* Turn off auto Xon flow control */
233 if (ch->ch_c_iflag & IXOFF)
234 efr &= ~(UART_17158_EFR_IXON);
236 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
238 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
239 writeb(0, &ch->ch_neo_uart->efr);
241 /* Turn on UART enhanced bits */
242 writeb(efr, &ch->ch_neo_uart->efr);
244 /* Turn on table D, with 8 char hi/low watermarks */
245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
247 ch->ch_r_watermark = 0;
249 writeb(16, &ch->ch_neo_uart->tfifo);
250 ch->ch_t_tlevel = 16;
252 writeb(16, &ch->ch_neo_uart->rfifo);
253 ch->ch_r_tlevel = 16;
255 writeb(ier, &ch->ch_neo_uart->ier);
258 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
261 /* if hardware flow control is set, then skip this whole thing */
262 if (ch->ch_c_cflag & CRTSCTS)
265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n");
267 /* Tell UART what start/stop chars it should be looking for */
268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
269 writeb(0, &ch->ch_neo_uart->xonchar2);
271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
272 writeb(0, &ch->ch_neo_uart->xoffchar2);
275 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
285 /* cache head and tail of queue */
286 head = ch->ch_r_head & RQUEUEMASK;
287 tail = ch->ch_r_tail & RQUEUEMASK;
289 /* Get our cached LSR */
290 linestatus = ch->ch_cached_lsr;
291 ch->ch_cached_lsr = 0;
293 /* Store how much space we have left in the queue */
294 if ((qleft = tail - head - 1) < 0)
295 qleft += RQUEUEMASK + 1;
298 * If the UART is not in FIFO mode, force the FIFO copy to
299 * NOT be run, by setting total to 0.
301 * On the other hand, if the UART IS in FIFO mode, then ask
302 * the UART to give us an approximation of data it has RX'ed.
304 if (!(ch->ch_flags & CH_FIFO_ENABLED))
307 total = readb(&ch->ch_neo_uart->rfifo);
310 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
312 * This resolves a problem/bug with the Exar chip that sometimes
313 * returns a bogus value in the rfifo register.
314 * The count can be any where from 0-3 bytes "off".
321 * Finally, bound the copy to make sure we don't overflow
323 * The byte by byte copy loop below this loop this will
324 * deal with the queue overflow possibility.
326 total = min(total, qleft);
330 * Grab the linestatus register, we need to check
331 * to see if there are any errors in the FIFO.
333 linestatus = readb(&ch->ch_neo_uart->lsr);
336 * Break out if there is a FIFO error somewhere.
337 * This will allow us to go byte by byte down below,
338 * finding the exact location of the error.
340 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
343 /* Make sure we don't go over the end of our queue */
344 n = min(((u32) total), (RQUEUESIZE - (u32) head));
347 * Cut down n even further if needed, this is to fix
348 * a problem with memcpy_fromio() with the Neo on the
349 * IBM pSeries platform.
350 * 15 bytes max appears to be the magic number.
352 n = min((u32) n, (u32) 12);
355 * Since we are grabbing the linestatus register, which
356 * will reset some bits after our read, we need to ensure
357 * we don't miss our TX FIFO emptys.
359 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
360 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
364 /* Copy data from uart to the queue */
365 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
367 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
368 * that all the data currently in the FIFO is free of
369 * breaks and parity/frame/orun errors.
371 memset(ch->ch_equeue + head, 0, n);
373 /* Add to and flip head if needed */
374 head = (head + n) & RQUEUEMASK;
381 * Create a mask to determine whether we should
382 * insert the character (if any) into our queue.
384 if (ch->ch_c_iflag & IGNBRK)
385 error_mask |= UART_LSR_BI;
388 * Now cleanup any leftover bytes still in the UART.
389 * Also deal with any possible queue overflow here as well.
394 * Its possible we have a linestatus from the loop above
395 * this, so we "OR" on any extra bits.
397 linestatus |= readb(&ch->ch_neo_uart->lsr);
400 * If the chip tells us there is no more data pending to
401 * be read, we can then leave.
402 * But before we do, cache the linestatus, just in case.
404 if (!(linestatus & UART_LSR_DR)) {
405 ch->ch_cached_lsr = linestatus;
409 /* No need to store this bit */
410 linestatus &= ~UART_LSR_DR;
413 * Since we are grabbing the linestatus register, which
414 * will reset some bits after our read, we need to ensure
415 * we don't miss our TX FIFO emptys.
417 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
418 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
419 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
423 * Discard character if we are ignoring the error mask.
425 if (linestatus & error_mask) {
428 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
433 * If our queue is full, we have no choice but to drop some data.
434 * The assumption is that HWFLOW or SWFLOW should have stopped
435 * things way way before we got to this point.
437 * I decided that I wanted to ditch the oldest data first,
438 * I hope thats okay with everyone? Yes? Good.
441 jsm_dbg(READ, &ch->ch_bd->pci_dev,
442 "Queue full, dropping DATA:%x LSR:%x\n",
443 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
445 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
446 ch->ch_err_overrun++;
450 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
451 ch->ch_equeue[head] = (u8) linestatus;
453 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n",
454 ch->ch_rqueue[head], ch->ch_equeue[head]);
456 /* Ditch any remaining linestatus value. */
459 /* Add to and flip head if needed */
460 head = (head + 1) & RQUEUEMASK;
467 * Write new final heads to channel structure.
469 ch->ch_r_head = head & RQUEUEMASK;
470 ch->ch_e_head = head & EQUEUEMASK;
474 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
482 struct circ_buf *circ;
487 circ = &ch->uart_port.state->xmit;
489 /* No data to write to the UART */
490 if (uart_circ_empty(circ))
493 /* If port is "stopped", don't send any data to the UART */
494 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
497 * If FIFOs are disabled. Send data directly to txrx register
499 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
500 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
502 ch->ch_cached_lsr |= lsrbits;
503 if (ch->ch_cached_lsr & UART_LSR_THRE) {
504 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
506 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx);
507 jsm_dbg(WRITE, &ch->ch_bd->pci_dev,
508 "Tx data: %x\n", circ->buf[circ->tail]);
509 circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1);
516 * We have to do it this way, because of the EXAR TXFIFO count bug.
518 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
521 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
523 /* cache head and tail of queue */
524 head = circ->head & (UART_XMIT_SIZE - 1);
525 tail = circ->tail & (UART_XMIT_SIZE - 1);
526 qlen = uart_circ_chars_pending(circ);
528 /* Find minimum of the FIFO space, versus queue length */
533 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
539 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s);
540 /* Add and flip queue if needed */
541 tail = (tail + s) & (UART_XMIT_SIZE - 1);
547 /* Update the final tail */
548 circ->tail = tail & (UART_XMIT_SIZE - 1);
550 if (len_written >= ch->ch_t_tlevel)
551 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
553 if (uart_circ_empty(circ))
554 uart_write_wakeup(&ch->uart_port);
557 static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
559 u8 msignals = signals;
561 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
562 "neo_parse_modem: port: %d msignals: %x\n",
563 ch->ch_portnum, msignals);
565 /* Scrub off lower bits. They signify delta's, which I don't care about */
566 /* Keep DDCD and DDSR though */
569 if (msignals & UART_MSR_DDCD)
570 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
571 if (msignals & UART_MSR_DDSR)
572 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
573 if (msignals & UART_MSR_DCD)
574 ch->ch_mistat |= UART_MSR_DCD;
576 ch->ch_mistat &= ~UART_MSR_DCD;
578 if (msignals & UART_MSR_DSR)
579 ch->ch_mistat |= UART_MSR_DSR;
581 ch->ch_mistat &= ~UART_MSR_DSR;
583 if (msignals & UART_MSR_RI)
584 ch->ch_mistat |= UART_MSR_RI;
586 ch->ch_mistat &= ~UART_MSR_RI;
588 if (msignals & UART_MSR_CTS)
589 ch->ch_mistat |= UART_MSR_CTS;
591 ch->ch_mistat &= ~UART_MSR_CTS;
593 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
594 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
596 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
597 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
598 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
599 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
600 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
601 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
604 /* Make the UART raise any of the output signals we want up */
605 static void neo_assert_modem_signals(struct jsm_channel *ch)
610 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
612 /* flush write operation */
613 neo_pci_posting_flush(ch->ch_bd);
617 * Flush the WRITE FIFO on the Neo.
619 * NOTE: Channel lock MUST be held before calling this function!
621 static void neo_flush_uart_write(struct jsm_channel *ch)
629 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
631 for (i = 0; i < 10; i++) {
633 /* Check to see if the UART feels it completely flushed the FIFO. */
634 tmp = readb(&ch->ch_neo_uart->isr_fcr);
635 if (tmp & UART_FCR_CLEAR_XMIT) {
636 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
637 "Still flushing TX UART... i: %d\n", i);
644 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
649 * Flush the READ FIFO on the Neo.
651 * NOTE: Channel lock MUST be held before calling this function!
653 static void neo_flush_uart_read(struct jsm_channel *ch)
661 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
663 for (i = 0; i < 10; i++) {
665 /* Check to see if the UART feels it completely flushed the FIFO. */
666 tmp = readb(&ch->ch_neo_uart->isr_fcr);
668 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
669 "Still flushing RX UART... i: %d\n", i);
678 * No locks are assumed to be held when calling this function.
680 static void neo_clear_break(struct jsm_channel *ch)
682 unsigned long lock_flags;
684 spin_lock_irqsave(&ch->ch_lock, lock_flags);
686 /* Turn break off, and unset some variables */
687 if (ch->ch_flags & CH_BREAK_SENDING) {
688 u8 temp = readb(&ch->ch_neo_uart->lcr);
689 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
691 ch->ch_flags &= ~(CH_BREAK_SENDING);
692 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
693 "clear break Finishing UART_LCR_SBC! finished: %lx\n",
696 /* flush write operation */
697 neo_pci_posting_flush(ch->ch_bd);
699 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
703 * Parse the ISR register.
705 static void neo_parse_isr(struct jsm_board *brd, u32 port)
707 struct jsm_channel *ch;
710 unsigned long lock_flags;
715 if (port >= brd->maxports)
718 ch = brd->channels[port];
722 /* Here we try to figure out what caused the interrupt to happen */
725 isr = readb(&ch->ch_neo_uart->isr_fcr);
727 /* Bail if no pending interrupt */
728 if (isr & UART_IIR_NO_INT)
732 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
734 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
736 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n",
737 __FILE__, __LINE__, isr);
739 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
740 /* Read data from uart -> queue */
741 neo_copy_data_from_uart_to_queue(ch);
743 /* Call our tty layer to enforce queue flow control if needed. */
744 spin_lock_irqsave(&ch->ch_lock, lock_flags);
745 jsm_check_queue_flow_control(ch);
746 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
749 if (isr & UART_IIR_THRI) {
750 /* Transfer data (if any) from Write Queue -> UART. */
751 spin_lock_irqsave(&ch->ch_lock, lock_flags);
752 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
753 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
754 neo_copy_data_from_queue_to_uart(ch);
757 if (isr & UART_17158_IIR_XONXOFF) {
758 cause = readb(&ch->ch_neo_uart->xoffchar1);
760 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
761 "Port %d. Got ISR_XONXOFF: cause:%x\n",
765 * Since the UART detected either an XON or
766 * XOFF match, we need to figure out which
767 * one it was, so we can suspend or resume data flow.
769 spin_lock_irqsave(&ch->ch_lock, lock_flags);
770 if (cause == UART_17158_XON_DETECT) {
771 /* Is output stopped right now, if so, resume it */
772 if (brd->channels[port]->ch_flags & CH_STOP) {
773 ch->ch_flags &= ~(CH_STOP);
775 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
776 "Port %d. XON detected in incoming data\n",
779 else if (cause == UART_17158_XOFF_DETECT) {
780 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
781 ch->ch_flags |= CH_STOP;
782 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
783 "Setting CH_STOP\n");
785 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
786 "Port: %d. XOFF detected in incoming data\n",
789 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
792 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
794 * If we get here, this means the hardware is doing auto flow control.
795 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
797 cause = readb(&ch->ch_neo_uart->mcr);
799 /* Which pin is doing auto flow? RTS or DTR? */
800 spin_lock_irqsave(&ch->ch_lock, lock_flags);
801 if ((cause & 0x4) == 0) {
802 if (cause & UART_MCR_RTS)
803 ch->ch_mostat |= UART_MCR_RTS;
805 ch->ch_mostat &= ~(UART_MCR_RTS);
807 if (cause & UART_MCR_DTR)
808 ch->ch_mostat |= UART_MCR_DTR;
810 ch->ch_mostat &= ~(UART_MCR_DTR);
812 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
815 /* Parse any modem signal changes */
816 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
817 "MOD_STAT: sending to parse_modem_sigs\n");
818 spin_lock_irqsave(&ch->uart_port.lock, lock_flags);
819 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
820 spin_unlock_irqrestore(&ch->uart_port.lock, lock_flags);
824 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
826 struct jsm_channel *ch;
828 unsigned long lock_flags;
833 if (port >= brd->maxports)
836 ch = brd->channels[port];
840 linestatus = readb(&ch->ch_neo_uart->lsr);
842 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
843 __FILE__, __LINE__, port, linestatus);
845 ch->ch_cached_lsr |= linestatus;
847 if (ch->ch_cached_lsr & UART_LSR_DR) {
848 /* Read data from uart -> queue */
849 neo_copy_data_from_uart_to_queue(ch);
850 spin_lock_irqsave(&ch->ch_lock, lock_flags);
851 jsm_check_queue_flow_control(ch);
852 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
856 * This is a special flag. It indicates that at least 1
857 * RX error (parity, framing, or break) has happened.
858 * Mark this in our struct, which will tell me that I have
859 *to do the special RX+LSR read for this FIFO load.
861 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
862 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
863 "%s:%d Port: %d Got an RX error, need to parse LSR\n",
864 __FILE__, __LINE__, port);
867 * The next 3 tests should *NOT* happen, as the above test
868 * should encapsulate all 3... At least, thats what Exar says.
871 if (linestatus & UART_LSR_PE) {
873 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n",
874 __FILE__, __LINE__, port);
877 if (linestatus & UART_LSR_FE) {
879 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n",
880 __FILE__, __LINE__, port);
883 if (linestatus & UART_LSR_BI) {
885 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
886 "%s:%d Port: %d. BRK INTR!\n",
887 __FILE__, __LINE__, port);
890 if (linestatus & UART_LSR_OE) {
892 * Rx Oruns. Exar says that an orun will NOT corrupt
893 * the FIFO. It will just replace the holding register
894 * with this new data byte. So basically just ignore this.
895 * Probably we should eventually have an orun stat in our driver...
897 ch->ch_err_overrun++;
898 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
899 "%s:%d Port: %d. Rx Overrun!\n",
900 __FILE__, __LINE__, port);
903 if (linestatus & UART_LSR_THRE) {
904 spin_lock_irqsave(&ch->ch_lock, lock_flags);
905 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
906 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
908 /* Transfer data (if any) from Write Queue -> UART. */
909 neo_copy_data_from_queue_to_uart(ch);
911 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
912 spin_lock_irqsave(&ch->ch_lock, lock_flags);
913 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
914 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
916 /* Transfer data (if any) from Write Queue -> UART. */
917 neo_copy_data_from_queue_to_uart(ch);
923 * Send any/all changes to the line to the UART.
925 static void neo_param(struct jsm_channel *ch)
931 struct jsm_board *bd;
938 * If baud rate is zero, flush queues, and set mval to drop DTR.
940 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
941 ch->ch_r_head = ch->ch_r_tail = 0;
942 ch->ch_e_head = ch->ch_e_tail = 0;
944 neo_flush_uart_write(ch);
945 neo_flush_uart_read(ch);
947 ch->ch_flags |= (CH_BAUD0);
948 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
949 neo_assert_modem_signals(ch);
980 cflag = C_BAUD(ch->uart_port.state->port.tty);
982 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
983 if (baud_rates[i].cflag == cflag) {
984 baud = baud_rates[i].rate;
989 if (ch->ch_flags & CH_BAUD0)
990 ch->ch_flags &= ~(CH_BAUD0);
993 if (ch->ch_c_cflag & PARENB)
994 lcr |= UART_LCR_PARITY;
996 if (!(ch->ch_c_cflag & PARODD))
997 lcr |= UART_LCR_EPAR;
1000 * Not all platforms support mark/space parity,
1001 * so this will hide behind an ifdef.
1004 if (ch->ch_c_cflag & CMSPAR)
1005 lcr |= UART_LCR_SPAR;
1008 if (ch->ch_c_cflag & CSTOPB)
1009 lcr |= UART_LCR_STOP;
1011 switch (ch->ch_c_cflag & CSIZE) {
1013 lcr |= UART_LCR_WLEN5;
1016 lcr |= UART_LCR_WLEN6;
1019 lcr |= UART_LCR_WLEN7;
1023 lcr |= UART_LCR_WLEN8;
1027 ier = readb(&ch->ch_neo_uart->ier);
1028 uart_lcr = readb(&ch->ch_neo_uart->lcr);
1030 quot = ch->ch_bd->bd_dividend / baud;
1033 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1034 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1035 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1036 writeb(lcr, &ch->ch_neo_uart->lcr);
1039 if (uart_lcr != lcr)
1040 writeb(lcr, &ch->ch_neo_uart->lcr);
1042 if (ch->ch_c_cflag & CREAD)
1043 ier |= (UART_IER_RDI | UART_IER_RLSI);
1045 ier |= (UART_IER_THRI | UART_IER_MSI);
1047 writeb(ier, &ch->ch_neo_uart->ier);
1049 /* Set new start/stop chars */
1050 neo_set_new_start_stop_chars(ch);
1052 if (ch->ch_c_cflag & CRTSCTS)
1053 neo_set_cts_flow_control(ch);
1054 else if (ch->ch_c_iflag & IXON) {
1055 /* If start/stop is set to disable, then we should disable flow control */
1056 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1057 neo_set_no_output_flow_control(ch);
1059 neo_set_ixon_flow_control(ch);
1062 neo_set_no_output_flow_control(ch);
1064 if (ch->ch_c_cflag & CRTSCTS)
1065 neo_set_rts_flow_control(ch);
1066 else if (ch->ch_c_iflag & IXOFF) {
1067 /* If start/stop is set to disable, then we should disable flow control */
1068 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1069 neo_set_no_input_flow_control(ch);
1071 neo_set_ixoff_flow_control(ch);
1074 neo_set_no_input_flow_control(ch);
1076 * Adjust the RX FIFO Trigger level if baud is less than 9600.
1077 * Not exactly elegant, but this is needed because of the Exar chip's
1078 * delay on firing off the RX FIFO interrupt on slower baud rates.
1081 writeb(1, &ch->ch_neo_uart->rfifo);
1082 ch->ch_r_tlevel = 1;
1085 neo_assert_modem_signals(ch);
1087 /* Get current status of the modem signals now */
1088 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1095 * Neo specific interrupt handler.
1097 static irqreturn_t neo_intr(int irq, void *voidbrd)
1099 struct jsm_board *brd = voidbrd;
1100 struct jsm_channel *ch;
1106 unsigned long lock_flags;
1107 unsigned long lock_flags2;
1108 int outofloop_count = 0;
1110 /* Lock out the slow poller from running on this board. */
1111 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1114 * Read in "extended" IRQ information from the 32bit Neo register.
1115 * Bits 0-7: What port triggered the interrupt.
1116 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1118 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1120 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",
1121 __FILE__, __LINE__, uart_poll);
1124 jsm_dbg(INTR, &brd->pci_dev,
1125 "Kernel interrupted to me, but no pending interrupts...\n");
1126 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1130 /* At this point, we have at least SOMETHING to service, dig further... */
1134 /* Loop on each port */
1135 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1140 /* Check current port to see if it has interrupt pending */
1141 if ((tmp & jsm_offset_table[current_port]) != 0) {
1142 port = current_port;
1143 type = tmp >> (8 + (port * 3));
1150 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n",
1151 __FILE__, __LINE__, port, type);
1153 /* Remove this port + type from uart_poll */
1154 uart_poll &= ~(jsm_offset_table[port]);
1157 /* If no type, just ignore it, and move onto next port */
1158 jsm_dbg(INTR, &brd->pci_dev,
1159 "Interrupt with no type! port: %d\n", port);
1163 /* Switch on type of interrupt we have */
1166 case UART_17158_RXRDY_TIMEOUT:
1168 * RXRDY Time-out is cleared by reading data in the
1169 * RX FIFO until it falls below the trigger level.
1172 /* Verify the port is in range. */
1173 if (port >= brd->nasync)
1176 ch = brd->channels[port];
1180 neo_copy_data_from_uart_to_queue(ch);
1182 /* Call our tty layer to enforce queue flow control if needed. */
1183 spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1184 jsm_check_queue_flow_control(ch);
1185 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1189 case UART_17158_RX_LINE_STATUS:
1191 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1193 neo_parse_lsr(brd, port);
1196 case UART_17158_TXRDY:
1198 * TXRDY interrupt clears after reading ISR register for the UART channel.
1202 * Yes, this is odd...
1203 * Why would I check EVERY possibility of type of
1204 * interrupt, when we know its TXRDY???
1205 * Becuz for some reason, even tho we got triggered for TXRDY,
1206 * it seems to be occasionally wrong. Instead of TX, which
1207 * it should be, I was getting things like RXDY too. Weird.
1209 neo_parse_isr(brd, port);
1212 case UART_17158_MSR:
1214 * MSR or flow control was seen.
1216 neo_parse_isr(brd, port);
1221 * The UART triggered us with a bogus interrupt type.
1222 * It appears the Exar chip, when REALLY bogged down, will throw
1223 * these once and awhile.
1224 * Its harmless, just ignore it and move on.
1226 jsm_dbg(INTR, &brd->pci_dev,
1227 "%s:%d Unknown Interrupt type: %x\n",
1228 __FILE__, __LINE__, type);
1233 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1235 jsm_dbg(INTR, &brd->pci_dev, "finish\n");
1240 * Neo specific way of turning off the receiver.
1241 * Used as a way to enforce queue flow control when in
1242 * hardware flow control mode.
1244 static void neo_disable_receiver(struct jsm_channel *ch)
1246 u8 tmp = readb(&ch->ch_neo_uart->ier);
1247 tmp &= ~(UART_IER_RDI);
1248 writeb(tmp, &ch->ch_neo_uart->ier);
1250 /* flush write operation */
1251 neo_pci_posting_flush(ch->ch_bd);
1256 * Neo specific way of turning on the receiver.
1257 * Used as a way to un-enforce queue flow control when in
1258 * hardware flow control mode.
1260 static void neo_enable_receiver(struct jsm_channel *ch)
1262 u8 tmp = readb(&ch->ch_neo_uart->ier);
1263 tmp |= (UART_IER_RDI);
1264 writeb(tmp, &ch->ch_neo_uart->ier);
1266 /* flush write operation */
1267 neo_pci_posting_flush(ch->ch_bd);
1270 static void neo_send_start_character(struct jsm_channel *ch)
1275 if (ch->ch_startc != __DISABLED_CHAR) {
1277 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1279 /* flush write operation */
1280 neo_pci_posting_flush(ch->ch_bd);
1284 static void neo_send_stop_character(struct jsm_channel *ch)
1289 if (ch->ch_stopc != __DISABLED_CHAR) {
1290 ch->ch_xoff_sends++;
1291 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1293 /* flush write operation */
1294 neo_pci_posting_flush(ch->ch_bd);
1301 static void neo_uart_init(struct jsm_channel *ch)
1303 writeb(0, &ch->ch_neo_uart->ier);
1304 writeb(0, &ch->ch_neo_uart->efr);
1305 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1307 /* Clear out UART and FIFO */
1308 readb(&ch->ch_neo_uart->txrx);
1309 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1310 readb(&ch->ch_neo_uart->lsr);
1311 readb(&ch->ch_neo_uart->msr);
1313 ch->ch_flags |= CH_FIFO_ENABLED;
1315 /* Assert any signals we want up */
1316 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1320 * Make the UART completely turn off.
1322 static void neo_uart_off(struct jsm_channel *ch)
1324 /* Turn off UART enhanced bits */
1325 writeb(0, &ch->ch_neo_uart->efr);
1327 /* Stop all interrupts from occurring. */
1328 writeb(0, &ch->ch_neo_uart->ier);
1331 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1334 u8 lsr = readb(&ch->ch_neo_uart->lsr);
1336 /* We must cache the LSR as some of the bits get reset once read... */
1337 ch->ch_cached_lsr |= lsr;
1339 /* Determine whether the Transmitter is empty or not */
1340 if (!(lsr & UART_LSR_TEMT))
1343 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1350 /* Channel lock MUST be held by the calling function! */
1351 static void neo_send_break(struct jsm_channel *ch)
1354 * Set the time we should stop sending the break.
1355 * If we are already sending a break, toss away the existing
1356 * time to stop, and use this new value instead.
1359 /* Tell the UART to start sending the break */
1360 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1361 u8 temp = readb(&ch->ch_neo_uart->lcr);
1362 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1363 ch->ch_flags |= (CH_BREAK_SENDING);
1365 /* flush write operation */
1366 neo_pci_posting_flush(ch->ch_bd);
1371 * neo_send_immediate_char.
1373 * Sends a specific character as soon as possible to the UART,
1374 * jumping over any bytes that might be in the write queue.
1376 * The channel lock MUST be held by the calling function.
1378 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1383 writeb(c, &ch->ch_neo_uart->txrx);
1385 /* flush write operation */
1386 neo_pci_posting_flush(ch->ch_bd);
1389 struct board_ops jsm_neo_ops = {
1391 .uart_init = neo_uart_init,
1392 .uart_off = neo_uart_off,
1394 .assert_modem_signals = neo_assert_modem_signals,
1395 .flush_uart_write = neo_flush_uart_write,
1396 .flush_uart_read = neo_flush_uart_read,
1397 .disable_receiver = neo_disable_receiver,
1398 .enable_receiver = neo_enable_receiver,
1399 .send_break = neo_send_break,
1400 .clear_break = neo_clear_break,
1401 .send_start_character = neo_send_start_character,
1402 .send_stop_character = neo_send_stop_character,
1403 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
1404 .get_uart_bytes_left = neo_get_uart_bytes_left,
1405 .send_immediate_char = neo_send_immediate_char