2 * Freescale lpuart serial port driver
4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dmapool.h>
22 #include <linux/irq.h>
23 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_dma.h>
27 #include <linux/serial_core.h>
28 #include <linux/slab.h>
29 #include <linux/tty_flip.h>
31 /* All registers are 8-bit width */
41 #define UARTMODEM 0x0d
42 #define UARTPFIFO 0x10
43 #define UARTCFIFO 0x11
44 #define UARTSFIFO 0x12
45 #define UARTTWFIFO 0x13
46 #define UARTTCFIFO 0x14
47 #define UARTRWFIFO 0x15
49 #define UARTBDH_LBKDIE 0x80
50 #define UARTBDH_RXEDGIE 0x40
51 #define UARTBDH_SBR_MASK 0x1f
53 #define UARTCR1_LOOPS 0x80
54 #define UARTCR1_RSRC 0x20
55 #define UARTCR1_M 0x10
56 #define UARTCR1_WAKE 0x08
57 #define UARTCR1_ILT 0x04
58 #define UARTCR1_PE 0x02
59 #define UARTCR1_PT 0x01
61 #define UARTCR2_TIE 0x80
62 #define UARTCR2_TCIE 0x40
63 #define UARTCR2_RIE 0x20
64 #define UARTCR2_ILIE 0x10
65 #define UARTCR2_TE 0x08
66 #define UARTCR2_RE 0x04
67 #define UARTCR2_RWU 0x02
68 #define UARTCR2_SBK 0x01
70 #define UARTSR1_TDRE 0x80
71 #define UARTSR1_TC 0x40
72 #define UARTSR1_RDRF 0x20
73 #define UARTSR1_IDLE 0x10
74 #define UARTSR1_OR 0x08
75 #define UARTSR1_NF 0x04
76 #define UARTSR1_FE 0x02
77 #define UARTSR1_PE 0x01
79 #define UARTCR3_R8 0x80
80 #define UARTCR3_T8 0x40
81 #define UARTCR3_TXDIR 0x20
82 #define UARTCR3_TXINV 0x10
83 #define UARTCR3_ORIE 0x08
84 #define UARTCR3_NEIE 0x04
85 #define UARTCR3_FEIE 0x02
86 #define UARTCR3_PEIE 0x01
88 #define UARTCR4_MAEN1 0x80
89 #define UARTCR4_MAEN2 0x40
90 #define UARTCR4_M10 0x20
91 #define UARTCR4_BRFA_MASK 0x1f
92 #define UARTCR4_BRFA_OFF 0
94 #define UARTCR5_TDMAS 0x80
95 #define UARTCR5_RDMAS 0x20
97 #define UARTMODEM_RXRTSE 0x08
98 #define UARTMODEM_TXRTSPOL 0x04
99 #define UARTMODEM_TXRTSE 0x02
100 #define UARTMODEM_TXCTSE 0x01
102 #define UARTPFIFO_TXFE 0x80
103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
104 #define UARTPFIFO_TXSIZE_OFF 4
105 #define UARTPFIFO_RXFE 0x08
106 #define UARTPFIFO_RXSIZE_OFF 0
108 #define UARTCFIFO_TXFLUSH 0x80
109 #define UARTCFIFO_RXFLUSH 0x40
110 #define UARTCFIFO_RXOFE 0x04
111 #define UARTCFIFO_TXOFE 0x02
112 #define UARTCFIFO_RXUFE 0x01
114 #define UARTSFIFO_TXEMPT 0x80
115 #define UARTSFIFO_RXEMPT 0x40
116 #define UARTSFIFO_RXOF 0x04
117 #define UARTSFIFO_TXOF 0x02
118 #define UARTSFIFO_RXUF 0x01
120 /* 32-bit register defination */
121 #define UARTBAUD 0x00
122 #define UARTSTAT 0x04
123 #define UARTCTRL 0x08
124 #define UARTDATA 0x0C
125 #define UARTMATCH 0x10
126 #define UARTMODIR 0x14
127 #define UARTFIFO 0x18
128 #define UARTWATER 0x1c
130 #define UARTBAUD_MAEN1 0x80000000
131 #define UARTBAUD_MAEN2 0x40000000
132 #define UARTBAUD_M10 0x20000000
133 #define UARTBAUD_TDMAE 0x00800000
134 #define UARTBAUD_RDMAE 0x00200000
135 #define UARTBAUD_MATCFG 0x00400000
136 #define UARTBAUD_BOTHEDGE 0x00020000
137 #define UARTBAUD_RESYNCDIS 0x00010000
138 #define UARTBAUD_LBKDIE 0x00008000
139 #define UARTBAUD_RXEDGIE 0x00004000
140 #define UARTBAUD_SBNS 0x00002000
141 #define UARTBAUD_SBR 0x00000000
142 #define UARTBAUD_SBR_MASK 0x1fff
144 #define UARTSTAT_LBKDIF 0x80000000
145 #define UARTSTAT_RXEDGIF 0x40000000
146 #define UARTSTAT_MSBF 0x20000000
147 #define UARTSTAT_RXINV 0x10000000
148 #define UARTSTAT_RWUID 0x08000000
149 #define UARTSTAT_BRK13 0x04000000
150 #define UARTSTAT_LBKDE 0x02000000
151 #define UARTSTAT_RAF 0x01000000
152 #define UARTSTAT_TDRE 0x00800000
153 #define UARTSTAT_TC 0x00400000
154 #define UARTSTAT_RDRF 0x00200000
155 #define UARTSTAT_IDLE 0x00100000
156 #define UARTSTAT_OR 0x00080000
157 #define UARTSTAT_NF 0x00040000
158 #define UARTSTAT_FE 0x00020000
159 #define UARTSTAT_PE 0x00010000
160 #define UARTSTAT_MA1F 0x00008000
161 #define UARTSTAT_M21F 0x00004000
163 #define UARTCTRL_R8T9 0x80000000
164 #define UARTCTRL_R9T8 0x40000000
165 #define UARTCTRL_TXDIR 0x20000000
166 #define UARTCTRL_TXINV 0x10000000
167 #define UARTCTRL_ORIE 0x08000000
168 #define UARTCTRL_NEIE 0x04000000
169 #define UARTCTRL_FEIE 0x02000000
170 #define UARTCTRL_PEIE 0x01000000
171 #define UARTCTRL_TIE 0x00800000
172 #define UARTCTRL_TCIE 0x00400000
173 #define UARTCTRL_RIE 0x00200000
174 #define UARTCTRL_ILIE 0x00100000
175 #define UARTCTRL_TE 0x00080000
176 #define UARTCTRL_RE 0x00040000
177 #define UARTCTRL_RWU 0x00020000
178 #define UARTCTRL_SBK 0x00010000
179 #define UARTCTRL_MA1IE 0x00008000
180 #define UARTCTRL_MA2IE 0x00004000
181 #define UARTCTRL_IDLECFG 0x00000100
182 #define UARTCTRL_LOOPS 0x00000080
183 #define UARTCTRL_DOZEEN 0x00000040
184 #define UARTCTRL_RSRC 0x00000020
185 #define UARTCTRL_M 0x00000010
186 #define UARTCTRL_WAKE 0x00000008
187 #define UARTCTRL_ILT 0x00000004
188 #define UARTCTRL_PE 0x00000002
189 #define UARTCTRL_PT 0x00000001
191 #define UARTDATA_NOISY 0x00008000
192 #define UARTDATA_PARITYE 0x00004000
193 #define UARTDATA_FRETSC 0x00002000
194 #define UARTDATA_RXEMPT 0x00001000
195 #define UARTDATA_IDLINE 0x00000800
196 #define UARTDATA_MASK 0x3ff
198 #define UARTMODIR_IREN 0x00020000
199 #define UARTMODIR_TXCTSSRC 0x00000020
200 #define UARTMODIR_TXCTSC 0x00000010
201 #define UARTMODIR_RXRTSE 0x00000008
202 #define UARTMODIR_TXRTSPOL 0x00000004
203 #define UARTMODIR_TXRTSE 0x00000002
204 #define UARTMODIR_TXCTSE 0x00000001
206 #define UARTFIFO_TXEMPT 0x00800000
207 #define UARTFIFO_RXEMPT 0x00400000
208 #define UARTFIFO_TXOF 0x00020000
209 #define UARTFIFO_RXUF 0x00010000
210 #define UARTFIFO_TXFLUSH 0x00008000
211 #define UARTFIFO_RXFLUSH 0x00004000
212 #define UARTFIFO_TXOFE 0x00000200
213 #define UARTFIFO_RXUFE 0x00000100
214 #define UARTFIFO_TXFE 0x00000080
215 #define UARTFIFO_FIFOSIZE_MASK 0x7
216 #define UARTFIFO_TXSIZE_OFF 4
217 #define UARTFIFO_RXFE 0x00000008
218 #define UARTFIFO_RXSIZE_OFF 0
220 #define UARTWATER_COUNT_MASK 0xff
221 #define UARTWATER_TXCNT_OFF 8
222 #define UARTWATER_RXCNT_OFF 24
223 #define UARTWATER_WATER_MASK 0xff
224 #define UARTWATER_TXWATER_OFF 0
225 #define UARTWATER_RXWATER_OFF 16
227 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
228 #define DMA_RX_TIMEOUT (10)
230 #define DRIVER_NAME "fsl-lpuart"
231 #define DEV_NAME "ttyLP"
235 struct uart_port port;
237 unsigned int txfifo_size;
238 unsigned int rxfifo_size;
241 bool lpuart_dma_tx_use;
242 bool lpuart_dma_rx_use;
243 struct dma_chan *dma_tx_chan;
244 struct dma_chan *dma_rx_chan;
245 struct dma_async_tx_descriptor *dma_tx_desc;
246 struct dma_async_tx_descriptor *dma_rx_desc;
247 dma_cookie_t dma_tx_cookie;
248 dma_cookie_t dma_rx_cookie;
249 unsigned int dma_tx_bytes;
250 unsigned int dma_rx_bytes;
251 bool dma_tx_in_progress;
252 unsigned int dma_rx_timeout;
253 struct timer_list lpuart_timer;
254 struct scatterlist rx_sgl, tx_sgl[2];
255 struct circ_buf rx_ring;
256 int rx_dma_rng_buf_len;
257 unsigned int dma_tx_nents;
258 wait_queue_head_t dma_wait;
261 static const struct of_device_id lpuart_dt_ids[] = {
263 .compatible = "fsl,vf610-lpuart",
266 .compatible = "fsl,ls1021a-lpuart",
270 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
272 /* Forward declare this for the dma callbacks*/
273 static void lpuart_dma_tx_complete(void *arg);
275 static u32 lpuart32_read(void __iomem *addr)
277 return ioread32be(addr);
280 static void lpuart32_write(u32 val, void __iomem *addr)
282 iowrite32be(val, addr);
285 static void lpuart_stop_tx(struct uart_port *port)
289 temp = readb(port->membase + UARTCR2);
290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
291 writeb(temp, port->membase + UARTCR2);
294 static void lpuart32_stop_tx(struct uart_port *port)
298 temp = lpuart32_read(port->membase + UARTCTRL);
299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
300 lpuart32_write(temp, port->membase + UARTCTRL);
303 static void lpuart_stop_rx(struct uart_port *port)
307 temp = readb(port->membase + UARTCR2);
308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
311 static void lpuart32_stop_rx(struct uart_port *port)
315 temp = lpuart32_read(port->membase + UARTCTRL);
316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
319 static void lpuart_dma_tx(struct lpuart_port *sport)
321 struct circ_buf *xmit = &sport->port.state->xmit;
322 struct scatterlist *sgl = sport->tx_sgl;
323 struct device *dev = sport->port.dev;
326 if (sport->dma_tx_in_progress)
329 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
331 if (xmit->tail < xmit->head || xmit->head == 0) {
332 sport->dma_tx_nents = 1;
333 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
335 sport->dma_tx_nents = 2;
336 sg_init_table(sgl, 2);
337 sg_set_buf(sgl, xmit->buf + xmit->tail,
338 UART_XMIT_SIZE - xmit->tail);
339 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
342 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
344 dev_err(dev, "DMA mapping error for TX.\n");
348 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
351 if (!sport->dma_tx_desc) {
352 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
353 dev_err(dev, "Cannot prepare TX slave DMA!\n");
357 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
358 sport->dma_tx_desc->callback_param = sport;
359 sport->dma_tx_in_progress = true;
360 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
361 dma_async_issue_pending(sport->dma_tx_chan);
364 static void lpuart_dma_tx_complete(void *arg)
366 struct lpuart_port *sport = arg;
367 struct scatterlist *sgl = &sport->tx_sgl[0];
368 struct circ_buf *xmit = &sport->port.state->xmit;
371 spin_lock_irqsave(&sport->port.lock, flags);
373 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
375 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
377 sport->port.icount.tx += sport->dma_tx_bytes;
378 sport->dma_tx_in_progress = false;
379 spin_unlock_irqrestore(&sport->port.lock, flags);
381 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
382 uart_write_wakeup(&sport->port);
384 if (waitqueue_active(&sport->dma_wait)) {
385 wake_up(&sport->dma_wait);
389 spin_lock_irqsave(&sport->port.lock, flags);
391 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
392 lpuart_dma_tx(sport);
394 spin_unlock_irqrestore(&sport->port.lock, flags);
397 static int lpuart_dma_tx_request(struct uart_port *port)
399 struct lpuart_port *sport = container_of(port,
400 struct lpuart_port, port);
401 struct dma_slave_config dma_tx_sconfig = {};
404 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
405 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
406 dma_tx_sconfig.dst_maxburst = 1;
407 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
408 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
411 dev_err(sport->port.dev,
412 "DMA slave config failed, err = %d\n", ret);
419 static void lpuart_flush_buffer(struct uart_port *port)
421 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
423 if (sport->lpuart_dma_tx_use) {
424 if (sport->dma_tx_in_progress) {
425 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
426 sport->dma_tx_nents, DMA_TO_DEVICE);
427 sport->dma_tx_in_progress = false;
429 dmaengine_terminate_all(sport->dma_tx_chan);
433 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
435 struct circ_buf *xmit = &sport->port.state->xmit;
437 while (!uart_circ_empty(xmit) &&
438 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
439 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
440 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
441 sport->port.icount.tx++;
444 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
445 uart_write_wakeup(&sport->port);
447 if (uart_circ_empty(xmit))
448 lpuart_stop_tx(&sport->port);
451 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
453 struct circ_buf *xmit = &sport->port.state->xmit;
456 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
457 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
458 txcnt &= UARTWATER_COUNT_MASK;
459 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
460 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
461 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
462 sport->port.icount.tx++;
463 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
464 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
465 txcnt &= UARTWATER_COUNT_MASK;
468 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
469 uart_write_wakeup(&sport->port);
471 if (uart_circ_empty(xmit))
472 lpuart32_stop_tx(&sport->port);
475 static void lpuart_start_tx(struct uart_port *port)
477 struct lpuart_port *sport = container_of(port,
478 struct lpuart_port, port);
479 struct circ_buf *xmit = &sport->port.state->xmit;
482 temp = readb(port->membase + UARTCR2);
483 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
485 if (sport->lpuart_dma_tx_use) {
486 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
487 lpuart_dma_tx(sport);
489 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
490 lpuart_transmit_buffer(sport);
494 static void lpuart32_start_tx(struct uart_port *port)
496 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
499 temp = lpuart32_read(port->membase + UARTCTRL);
500 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
502 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
503 lpuart32_transmit_buffer(sport);
506 /* return TIOCSER_TEMT when transmitter is not busy */
507 static unsigned int lpuart_tx_empty(struct uart_port *port)
509 struct lpuart_port *sport = container_of(port,
510 struct lpuart_port, port);
511 unsigned char sr1 = readb(port->membase + UARTSR1);
512 unsigned char sfifo = readb(port->membase + UARTSFIFO);
514 if (sport->dma_tx_in_progress)
517 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
523 static unsigned int lpuart32_tx_empty(struct uart_port *port)
525 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
529 static irqreturn_t lpuart_txint(int irq, void *dev_id)
531 struct lpuart_port *sport = dev_id;
532 struct circ_buf *xmit = &sport->port.state->xmit;
535 spin_lock_irqsave(&sport->port.lock, flags);
536 if (sport->port.x_char) {
538 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
540 writeb(sport->port.x_char, sport->port.membase + UARTDR);
544 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
546 lpuart32_stop_tx(&sport->port);
548 lpuart_stop_tx(&sport->port);
553 lpuart32_transmit_buffer(sport);
555 lpuart_transmit_buffer(sport);
557 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
558 uart_write_wakeup(&sport->port);
561 spin_unlock_irqrestore(&sport->port.lock, flags);
565 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
567 struct lpuart_port *sport = dev_id;
568 unsigned int flg, ignored = 0;
569 struct tty_port *port = &sport->port.state->port;
571 unsigned char rx, sr;
573 spin_lock_irqsave(&sport->port.lock, flags);
575 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
577 sport->port.icount.rx++;
579 * to clear the FE, OR, NF, FE, PE flags,
580 * read SR1 then read DR
582 sr = readb(sport->port.membase + UARTSR1);
583 rx = readb(sport->port.membase + UARTDR);
585 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
588 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
590 sport->port.icount.parity++;
591 else if (sr & UARTSR1_FE)
592 sport->port.icount.frame++;
595 sport->port.icount.overrun++;
597 if (sr & sport->port.ignore_status_mask) {
603 sr &= sport->port.read_status_mask;
607 else if (sr & UARTSR1_FE)
614 sport->port.sysrq = 0;
618 tty_insert_flip_char(port, rx, flg);
622 spin_unlock_irqrestore(&sport->port.lock, flags);
624 tty_flip_buffer_push(port);
628 static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
630 struct lpuart_port *sport = dev_id;
631 unsigned int flg, ignored = 0;
632 struct tty_port *port = &sport->port.state->port;
634 unsigned long rx, sr;
636 spin_lock_irqsave(&sport->port.lock, flags);
638 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
640 sport->port.icount.rx++;
642 * to clear the FE, OR, NF, FE, PE flags,
643 * read STAT then read DATA reg
645 sr = lpuart32_read(sport->port.membase + UARTSTAT);
646 rx = lpuart32_read(sport->port.membase + UARTDATA);
649 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
652 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
653 if (sr & UARTSTAT_PE)
654 sport->port.icount.parity++;
655 else if (sr & UARTSTAT_FE)
656 sport->port.icount.frame++;
658 if (sr & UARTSTAT_OR)
659 sport->port.icount.overrun++;
661 if (sr & sport->port.ignore_status_mask) {
667 sr &= sport->port.read_status_mask;
669 if (sr & UARTSTAT_PE)
671 else if (sr & UARTSTAT_FE)
674 if (sr & UARTSTAT_OR)
678 sport->port.sysrq = 0;
682 tty_insert_flip_char(port, rx, flg);
686 spin_unlock_irqrestore(&sport->port.lock, flags);
688 tty_flip_buffer_push(port);
692 static irqreturn_t lpuart_int(int irq, void *dev_id)
694 struct lpuart_port *sport = dev_id;
697 sts = readb(sport->port.membase + UARTSR1);
699 if (sts & UARTSR1_RDRF)
700 lpuart_rxint(irq, dev_id);
702 if (sts & UARTSR1_TDRE)
703 lpuart_txint(irq, dev_id);
708 static irqreturn_t lpuart32_int(int irq, void *dev_id)
710 struct lpuart_port *sport = dev_id;
711 unsigned long sts, rxcount;
713 sts = lpuart32_read(sport->port.membase + UARTSTAT);
714 rxcount = lpuart32_read(sport->port.membase + UARTWATER);
715 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
717 if (sts & UARTSTAT_RDRF || rxcount > 0)
718 lpuart32_rxint(irq, dev_id);
720 if ((sts & UARTSTAT_TDRE) &&
721 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
722 lpuart_txint(irq, dev_id);
724 lpuart32_write(sts, sport->port.membase + UARTSTAT);
728 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
730 struct tty_port *port = &sport->port.state->port;
731 struct dma_tx_state state;
732 enum dma_status dmastat;
733 struct circ_buf *ring = &sport->rx_ring;
738 sr = readb(sport->port.membase + UARTSR1);
740 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
741 /* Read DR to clear the error flags */
742 readb(sport->port.membase + UARTDR);
745 sport->port.icount.parity++;
746 else if (sr & UARTSR1_FE)
747 sport->port.icount.frame++;
750 async_tx_ack(sport->dma_rx_desc);
752 spin_lock_irqsave(&sport->port.lock, flags);
754 dmastat = dmaengine_tx_status(sport->dma_rx_chan,
755 sport->dma_rx_cookie,
758 if (dmastat == DMA_ERROR) {
759 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
760 spin_unlock_irqrestore(&sport->port.lock, flags);
764 /* CPU claims ownership of RX DMA buffer */
765 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
768 * ring->head points to the end of data already written by the DMA.
769 * ring->tail points to the beginning of data to be read by the
771 * The current transfer size should not be larger than the dma buffer
774 ring->head = sport->rx_sgl.length - state.residue;
775 BUG_ON(ring->head > sport->rx_sgl.length);
777 * At this point ring->head may point to the first byte right after the
778 * last byte of the dma buffer:
779 * 0 <= ring->head <= sport->rx_sgl.length
781 * However ring->tail must always points inside the dma buffer:
782 * 0 <= ring->tail <= sport->rx_sgl.length - 1
784 * Since we use a ring buffer, we have to handle the case
785 * where head is lower than tail. In such a case, we first read from
786 * tail to the end of the buffer then reset tail.
788 if (ring->head < ring->tail) {
789 count = sport->rx_sgl.length - ring->tail;
791 tty_insert_flip_string(port, ring->buf + ring->tail, count);
793 sport->port.icount.rx += count;
796 /* Finally we read data from tail to head */
797 if (ring->tail < ring->head) {
798 count = ring->head - ring->tail;
799 tty_insert_flip_string(port, ring->buf + ring->tail, count);
800 /* Wrap ring->head if needed */
801 if (ring->head >= sport->rx_sgl.length)
803 ring->tail = ring->head;
804 sport->port.icount.rx += count;
807 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
810 spin_unlock_irqrestore(&sport->port.lock, flags);
812 tty_flip_buffer_push(port);
813 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
816 static void lpuart_dma_rx_complete(void *arg)
818 struct lpuart_port *sport = arg;
820 lpuart_copy_rx_to_tty(sport);
823 static void lpuart_timer_func(unsigned long data)
825 struct lpuart_port *sport = (struct lpuart_port *)data;
827 lpuart_copy_rx_to_tty(sport);
830 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
832 struct dma_slave_config dma_rx_sconfig = {};
833 struct circ_buf *ring = &sport->rx_ring;
836 struct tty_port *port = &sport->port.state->port;
837 struct tty_struct *tty = port->tty;
838 struct ktermios *termios = &tty->termios;
840 baud = tty_get_baud_rate(tty);
842 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
843 if (termios->c_cflag & PARENB)
847 * Calculate length of one DMA buffer size to keep latency below
848 * 10ms at any baud rate.
850 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
851 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
852 if (sport->rx_dma_rng_buf_len < 16)
853 sport->rx_dma_rng_buf_len = 16;
855 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
857 dev_err(sport->port.dev, "Ring buf alloc failed\n");
861 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
862 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
863 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
866 dev_err(sport->port.dev, "DMA Rx mapping error\n");
870 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
871 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
872 dma_rx_sconfig.src_maxburst = 1;
873 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
874 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
877 dev_err(sport->port.dev,
878 "DMA Rx slave config failed, err = %d\n", ret);
882 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
883 sg_dma_address(&sport->rx_sgl),
884 sport->rx_sgl.length,
885 sport->rx_sgl.length / 2,
888 if (!sport->dma_rx_desc) {
889 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
893 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
894 sport->dma_rx_desc->callback_param = sport;
895 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
896 dma_async_issue_pending(sport->dma_rx_chan);
898 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
899 sport->port.membase + UARTCR5);
904 static void lpuart_dma_rx_free(struct uart_port *port)
906 struct lpuart_port *sport = container_of(port,
907 struct lpuart_port, port);
909 if (sport->dma_rx_chan)
910 dmaengine_terminate_all(sport->dma_rx_chan);
912 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
913 kfree(sport->rx_ring.buf);
914 sport->rx_ring.tail = 0;
915 sport->rx_ring.head = 0;
916 sport->dma_rx_desc = NULL;
917 sport->dma_rx_cookie = -EINVAL;
920 static int lpuart_config_rs485(struct uart_port *port,
921 struct serial_rs485 *rs485)
923 struct lpuart_port *sport = container_of(port,
924 struct lpuart_port, port);
926 u8 modem = readb(sport->port.membase + UARTMODEM) &
927 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
928 writeb(modem, sport->port.membase + UARTMODEM);
930 if (rs485->flags & SER_RS485_ENABLED) {
931 /* Enable auto RS-485 RTS mode */
932 modem |= UARTMODEM_TXRTSE;
935 * RTS needs to be logic HIGH either during transer _or_ after
936 * transfer, other variants are not supported by the hardware.
939 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
940 SER_RS485_RTS_AFTER_SEND)))
941 rs485->flags |= SER_RS485_RTS_ON_SEND;
943 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
944 rs485->flags & SER_RS485_RTS_AFTER_SEND)
945 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
948 * The hardware defaults to RTS logic HIGH while transfer.
949 * Switch polarity in case RTS shall be logic HIGH
951 * Note: UART is assumed to be active high.
953 if (rs485->flags & SER_RS485_RTS_ON_SEND)
954 modem |= UARTMODEM_TXRTSPOL;
955 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
956 modem &= ~UARTMODEM_TXRTSPOL;
959 /* Store the new configuration */
960 sport->port.rs485 = *rs485;
962 writeb(modem, sport->port.membase + UARTMODEM);
966 static unsigned int lpuart_get_mctrl(struct uart_port *port)
968 unsigned int temp = 0;
971 reg = readb(port->membase + UARTMODEM);
972 if (reg & UARTMODEM_TXCTSE)
975 if (reg & UARTMODEM_RXRTSE)
981 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
983 unsigned int temp = 0;
986 reg = lpuart32_read(port->membase + UARTMODIR);
987 if (reg & UARTMODIR_TXCTSE)
990 if (reg & UARTMODIR_RXRTSE)
996 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
999 struct lpuart_port *sport = container_of(port,
1000 struct lpuart_port, port);
1002 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1003 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1004 temp = readb(sport->port.membase + UARTMODEM) &
1005 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1007 if (mctrl & TIOCM_RTS)
1008 temp |= UARTMODEM_RXRTSE;
1010 if (mctrl & TIOCM_CTS)
1011 temp |= UARTMODEM_TXCTSE;
1013 writeb(temp, port->membase + UARTMODEM);
1017 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1021 temp = lpuart32_read(port->membase + UARTMODIR) &
1022 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1024 if (mctrl & TIOCM_RTS)
1025 temp |= UARTMODIR_RXRTSE;
1027 if (mctrl & TIOCM_CTS)
1028 temp |= UARTMODIR_TXCTSE;
1030 lpuart32_write(temp, port->membase + UARTMODIR);
1033 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1037 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1039 if (break_state != 0)
1040 temp |= UARTCR2_SBK;
1042 writeb(temp, port->membase + UARTCR2);
1045 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1049 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
1051 if (break_state != 0)
1052 temp |= UARTCTRL_SBK;
1054 lpuart32_write(temp, port->membase + UARTCTRL);
1057 static void lpuart_setup_watermark(struct lpuart_port *sport)
1059 unsigned char val, cr2;
1060 unsigned char cr2_saved;
1062 cr2 = readb(sport->port.membase + UARTCR2);
1064 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1065 UARTCR2_RIE | UARTCR2_RE);
1066 writeb(cr2, sport->port.membase + UARTCR2);
1068 val = readb(sport->port.membase + UARTPFIFO);
1069 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1070 sport->port.membase + UARTPFIFO);
1072 /* flush Tx and Rx FIFO */
1073 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1074 sport->port.membase + UARTCFIFO);
1076 /* explicitly clear RDRF */
1077 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1078 readb(sport->port.membase + UARTDR);
1079 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1082 writeb(0, sport->port.membase + UARTTWFIFO);
1083 writeb(1, sport->port.membase + UARTRWFIFO);
1086 writeb(cr2_saved, sport->port.membase + UARTCR2);
1089 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1091 unsigned long val, ctrl;
1092 unsigned long ctrl_saved;
1094 ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1096 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1097 UARTCTRL_RIE | UARTCTRL_RE);
1098 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1100 /* enable FIFO mode */
1101 val = lpuart32_read(sport->port.membase + UARTFIFO);
1102 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1103 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1104 lpuart32_write(val, sport->port.membase + UARTFIFO);
1106 /* set the watermark */
1107 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1108 lpuart32_write(val, sport->port.membase + UARTWATER);
1111 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
1114 static void rx_dma_timer_init(struct lpuart_port *sport)
1116 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1117 (unsigned long)sport);
1118 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1119 add_timer(&sport->lpuart_timer);
1122 static int lpuart_startup(struct uart_port *port)
1124 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1126 unsigned long flags;
1129 /* determine FIFO size and enable FIFO mode */
1130 temp = readb(sport->port.membase + UARTPFIFO);
1132 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1133 UARTPFIFO_FIFOSIZE_MASK) + 1);
1135 sport->port.fifosize = sport->txfifo_size;
1137 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1138 UARTPFIFO_FIFOSIZE_MASK) + 1);
1140 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1141 DRIVER_NAME, sport);
1145 spin_lock_irqsave(&sport->port.lock, flags);
1147 lpuart_setup_watermark(sport);
1149 temp = readb(sport->port.membase + UARTCR2);
1150 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1151 writeb(temp, sport->port.membase + UARTCR2);
1153 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1154 /* set Rx DMA timeout */
1155 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1156 if (!sport->dma_rx_timeout)
1157 sport->dma_rx_timeout = 1;
1159 sport->lpuart_dma_rx_use = true;
1160 rx_dma_timer_init(sport);
1162 sport->lpuart_dma_rx_use = false;
1165 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1166 init_waitqueue_head(&sport->dma_wait);
1167 sport->lpuart_dma_tx_use = true;
1168 temp = readb(port->membase + UARTCR5);
1169 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1171 sport->lpuart_dma_tx_use = false;
1174 spin_unlock_irqrestore(&sport->port.lock, flags);
1179 static int lpuart32_startup(struct uart_port *port)
1181 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1183 unsigned long flags;
1186 /* determine FIFO size */
1187 temp = lpuart32_read(sport->port.membase + UARTFIFO);
1189 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1190 UARTFIFO_FIFOSIZE_MASK) - 1);
1192 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1193 UARTFIFO_FIFOSIZE_MASK) - 1);
1195 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1196 DRIVER_NAME, sport);
1200 spin_lock_irqsave(&sport->port.lock, flags);
1202 lpuart32_setup_watermark(sport);
1204 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1205 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1206 temp |= UARTCTRL_ILIE;
1207 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1209 spin_unlock_irqrestore(&sport->port.lock, flags);
1213 static void lpuart_shutdown(struct uart_port *port)
1215 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1217 unsigned long flags;
1219 spin_lock_irqsave(&port->lock, flags);
1221 /* disable Rx/Tx and interrupts */
1222 temp = readb(port->membase + UARTCR2);
1223 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1224 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1225 writeb(temp, port->membase + UARTCR2);
1227 spin_unlock_irqrestore(&port->lock, flags);
1229 devm_free_irq(port->dev, port->irq, sport);
1231 if (sport->lpuart_dma_rx_use) {
1232 del_timer_sync(&sport->lpuart_timer);
1233 lpuart_dma_rx_free(&sport->port);
1236 if (sport->lpuart_dma_tx_use) {
1237 if (wait_event_interruptible(sport->dma_wait,
1238 !sport->dma_tx_in_progress) != false) {
1239 sport->dma_tx_in_progress = false;
1240 dmaengine_terminate_all(sport->dma_tx_chan);
1243 lpuart_stop_tx(port);
1247 static void lpuart32_shutdown(struct uart_port *port)
1249 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1251 unsigned long flags;
1253 spin_lock_irqsave(&port->lock, flags);
1255 /* disable Rx/Tx and interrupts */
1256 temp = lpuart32_read(port->membase + UARTCTRL);
1257 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1258 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1259 lpuart32_write(temp, port->membase + UARTCTRL);
1261 spin_unlock_irqrestore(&port->lock, flags);
1263 devm_free_irq(port->dev, port->irq, sport);
1267 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1268 struct ktermios *old)
1270 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1271 unsigned long flags;
1272 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1274 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1275 unsigned int sbr, brfa;
1277 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1278 old_cr2 = readb(sport->port.membase + UARTCR2);
1279 cr3 = readb(sport->port.membase + UARTCR3);
1280 cr4 = readb(sport->port.membase + UARTCR4);
1281 bdh = readb(sport->port.membase + UARTBDH);
1282 modem = readb(sport->port.membase + UARTMODEM);
1284 * only support CS8 and CS7, and for CS7 must enable PE.
1291 while ((termios->c_cflag & CSIZE) != CS8 &&
1292 (termios->c_cflag & CSIZE) != CS7) {
1293 termios->c_cflag &= ~CSIZE;
1294 termios->c_cflag |= old_csize;
1298 if ((termios->c_cflag & CSIZE) == CS8 ||
1299 (termios->c_cflag & CSIZE) == CS7)
1300 cr1 = old_cr1 & ~UARTCR1_M;
1302 if (termios->c_cflag & CMSPAR) {
1303 if ((termios->c_cflag & CSIZE) != CS8) {
1304 termios->c_cflag &= ~CSIZE;
1305 termios->c_cflag |= CS8;
1311 * When auto RS-485 RTS mode is enabled,
1312 * hardware flow control need to be disabled.
1314 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1315 termios->c_cflag &= ~CRTSCTS;
1317 if (termios->c_cflag & CRTSCTS) {
1318 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1320 termios->c_cflag &= ~CRTSCTS;
1321 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1324 if (termios->c_cflag & CSTOPB)
1325 termios->c_cflag &= ~CSTOPB;
1327 /* parity must be enabled when CS7 to match 8-bits format */
1328 if ((termios->c_cflag & CSIZE) == CS7)
1329 termios->c_cflag |= PARENB;
1331 if ((termios->c_cflag & PARENB)) {
1332 if (termios->c_cflag & CMSPAR) {
1334 if (termios->c_cflag & PARODD)
1340 if ((termios->c_cflag & CSIZE) == CS8)
1342 if (termios->c_cflag & PARODD)
1351 /* ask the core to calculate the divisor */
1352 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1354 spin_lock_irqsave(&sport->port.lock, flags);
1356 sport->port.read_status_mask = 0;
1357 if (termios->c_iflag & INPCK)
1358 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
1359 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1360 sport->port.read_status_mask |= UARTSR1_FE;
1362 /* characters to ignore */
1363 sport->port.ignore_status_mask = 0;
1364 if (termios->c_iflag & IGNPAR)
1365 sport->port.ignore_status_mask |= UARTSR1_PE;
1366 if (termios->c_iflag & IGNBRK) {
1367 sport->port.ignore_status_mask |= UARTSR1_FE;
1369 * if we're ignoring parity and break indicators,
1370 * ignore overruns too (for real raw support).
1372 if (termios->c_iflag & IGNPAR)
1373 sport->port.ignore_status_mask |= UARTSR1_OR;
1376 /* update the per-port timeout */
1377 uart_update_timeout(port, termios->c_cflag, baud);
1379 /* wait transmit engin complete */
1380 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1383 /* disable transmit and receive */
1384 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1385 sport->port.membase + UARTCR2);
1387 sbr = sport->port.uartclk / (16 * baud);
1388 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1389 bdh &= ~UARTBDH_SBR_MASK;
1390 bdh |= (sbr >> 8) & 0x1F;
1391 cr4 &= ~UARTCR4_BRFA_MASK;
1392 brfa &= UARTCR4_BRFA_MASK;
1393 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1394 writeb(bdh, sport->port.membase + UARTBDH);
1395 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1396 writeb(cr3, sport->port.membase + UARTCR3);
1397 writeb(cr1, sport->port.membase + UARTCR1);
1398 writeb(modem, sport->port.membase + UARTMODEM);
1400 /* restore control register */
1401 writeb(old_cr2, sport->port.membase + UARTCR2);
1404 * If new baud rate is set, we will also need to update the Ring buffer
1405 * length according to the selected baud rate and restart Rx DMA path.
1408 if (sport->lpuart_dma_rx_use) {
1409 del_timer_sync(&sport->lpuart_timer);
1410 lpuart_dma_rx_free(&sport->port);
1413 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1414 sport->lpuart_dma_rx_use = true;
1415 rx_dma_timer_init(sport);
1417 sport->lpuart_dma_rx_use = false;
1421 spin_unlock_irqrestore(&sport->port.lock, flags);
1425 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1426 struct ktermios *old)
1428 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1429 unsigned long flags;
1430 unsigned long ctrl, old_ctrl, bd, modem;
1432 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1435 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1436 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1437 modem = lpuart32_read(sport->port.membase + UARTMODIR);
1439 * only support CS8 and CS7, and for CS7 must enable PE.
1446 while ((termios->c_cflag & CSIZE) != CS8 &&
1447 (termios->c_cflag & CSIZE) != CS7) {
1448 termios->c_cflag &= ~CSIZE;
1449 termios->c_cflag |= old_csize;
1453 if ((termios->c_cflag & CSIZE) == CS8 ||
1454 (termios->c_cflag & CSIZE) == CS7)
1455 ctrl = old_ctrl & ~UARTCTRL_M;
1457 if (termios->c_cflag & CMSPAR) {
1458 if ((termios->c_cflag & CSIZE) != CS8) {
1459 termios->c_cflag &= ~CSIZE;
1460 termios->c_cflag |= CS8;
1465 if (termios->c_cflag & CRTSCTS) {
1466 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1468 termios->c_cflag &= ~CRTSCTS;
1469 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1472 if (termios->c_cflag & CSTOPB)
1473 termios->c_cflag &= ~CSTOPB;
1475 /* parity must be enabled when CS7 to match 8-bits format */
1476 if ((termios->c_cflag & CSIZE) == CS7)
1477 termios->c_cflag |= PARENB;
1479 if ((termios->c_cflag & PARENB)) {
1480 if (termios->c_cflag & CMSPAR) {
1481 ctrl &= ~UARTCTRL_PE;
1485 if ((termios->c_cflag & CSIZE) == CS8)
1487 if (termios->c_cflag & PARODD)
1488 ctrl |= UARTCTRL_PT;
1490 ctrl &= ~UARTCTRL_PT;
1493 ctrl &= ~UARTCTRL_PE;
1496 /* ask the core to calculate the divisor */
1497 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
1499 spin_lock_irqsave(&sport->port.lock, flags);
1501 sport->port.read_status_mask = 0;
1502 if (termios->c_iflag & INPCK)
1503 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1504 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1505 sport->port.read_status_mask |= UARTSTAT_FE;
1507 /* characters to ignore */
1508 sport->port.ignore_status_mask = 0;
1509 if (termios->c_iflag & IGNPAR)
1510 sport->port.ignore_status_mask |= UARTSTAT_PE;
1511 if (termios->c_iflag & IGNBRK) {
1512 sport->port.ignore_status_mask |= UARTSTAT_FE;
1514 * if we're ignoring parity and break indicators,
1515 * ignore overruns too (for real raw support).
1517 if (termios->c_iflag & IGNPAR)
1518 sport->port.ignore_status_mask |= UARTSTAT_OR;
1521 /* update the per-port timeout */
1522 uart_update_timeout(port, termios->c_cflag, baud);
1524 /* wait transmit engin complete */
1525 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1528 /* disable transmit and receive */
1529 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1530 sport->port.membase + UARTCTRL);
1532 sbr = sport->port.uartclk / (16 * baud);
1533 bd &= ~UARTBAUD_SBR_MASK;
1534 bd |= sbr & UARTBAUD_SBR_MASK;
1535 bd |= UARTBAUD_BOTHEDGE;
1536 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1537 lpuart32_write(bd, sport->port.membase + UARTBAUD);
1538 lpuart32_write(modem, sport->port.membase + UARTMODIR);
1539 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1540 /* restore control register */
1542 spin_unlock_irqrestore(&sport->port.lock, flags);
1545 static const char *lpuart_type(struct uart_port *port)
1547 return "FSL_LPUART";
1550 static void lpuart_release_port(struct uart_port *port)
1555 static int lpuart_request_port(struct uart_port *port)
1560 /* configure/autoconfigure the port */
1561 static void lpuart_config_port(struct uart_port *port, int flags)
1563 if (flags & UART_CONFIG_TYPE)
1564 port->type = PORT_LPUART;
1567 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1571 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1573 if (port->irq != ser->irq)
1575 if (ser->io_type != UPIO_MEM)
1577 if (port->uartclk / 16 != ser->baud_base)
1579 if (port->iobase != ser->port)
1586 static const struct uart_ops lpuart_pops = {
1587 .tx_empty = lpuart_tx_empty,
1588 .set_mctrl = lpuart_set_mctrl,
1589 .get_mctrl = lpuart_get_mctrl,
1590 .stop_tx = lpuart_stop_tx,
1591 .start_tx = lpuart_start_tx,
1592 .stop_rx = lpuart_stop_rx,
1593 .break_ctl = lpuart_break_ctl,
1594 .startup = lpuart_startup,
1595 .shutdown = lpuart_shutdown,
1596 .set_termios = lpuart_set_termios,
1597 .type = lpuart_type,
1598 .request_port = lpuart_request_port,
1599 .release_port = lpuart_release_port,
1600 .config_port = lpuart_config_port,
1601 .verify_port = lpuart_verify_port,
1602 .flush_buffer = lpuart_flush_buffer,
1605 static const struct uart_ops lpuart32_pops = {
1606 .tx_empty = lpuart32_tx_empty,
1607 .set_mctrl = lpuart32_set_mctrl,
1608 .get_mctrl = lpuart32_get_mctrl,
1609 .stop_tx = lpuart32_stop_tx,
1610 .start_tx = lpuart32_start_tx,
1611 .stop_rx = lpuart32_stop_rx,
1612 .break_ctl = lpuart32_break_ctl,
1613 .startup = lpuart32_startup,
1614 .shutdown = lpuart32_shutdown,
1615 .set_termios = lpuart32_set_termios,
1616 .type = lpuart_type,
1617 .request_port = lpuart_request_port,
1618 .release_port = lpuart_release_port,
1619 .config_port = lpuart_config_port,
1620 .verify_port = lpuart_verify_port,
1621 .flush_buffer = lpuart_flush_buffer,
1624 static struct lpuart_port *lpuart_ports[UART_NR];
1626 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1627 static void lpuart_console_putchar(struct uart_port *port, int ch)
1629 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1632 writeb(ch, port->membase + UARTDR);
1635 static void lpuart32_console_putchar(struct uart_port *port, int ch)
1637 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1640 lpuart32_write(ch, port->membase + UARTDATA);
1644 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1646 struct lpuart_port *sport = lpuart_ports[co->index];
1647 unsigned char old_cr2, cr2;
1649 /* first save CR2 and then disable interrupts */
1650 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1651 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1652 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1653 writeb(cr2, sport->port.membase + UARTCR2);
1655 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1657 /* wait for transmitter finish complete and restore CR2 */
1658 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1661 writeb(old_cr2, sport->port.membase + UARTCR2);
1665 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1667 struct lpuart_port *sport = lpuart_ports[co->index];
1668 unsigned long old_cr, cr;
1670 /* first save CR2 and then disable interrupts */
1671 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1672 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1673 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1674 lpuart32_write(cr, sport->port.membase + UARTCTRL);
1676 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1678 /* wait for transmitter finish complete and restore CR2 */
1679 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1682 lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1686 * if the port was already initialised (eg, by a boot loader),
1687 * try to determine the current setup.
1690 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1691 int *parity, int *bits)
1693 unsigned char cr, bdh, bdl, brfa;
1694 unsigned int sbr, uartclk, baud_raw;
1696 cr = readb(sport->port.membase + UARTCR2);
1697 cr &= UARTCR2_TE | UARTCR2_RE;
1701 /* ok, the port was enabled */
1703 cr = readb(sport->port.membase + UARTCR1);
1706 if (cr & UARTCR1_PE) {
1707 if (cr & UARTCR1_PT)
1718 bdh = readb(sport->port.membase + UARTBDH);
1719 bdh &= UARTBDH_SBR_MASK;
1720 bdl = readb(sport->port.membase + UARTBDL);
1724 brfa = readb(sport->port.membase + UARTCR4);
1725 brfa &= UARTCR4_BRFA_MASK;
1727 uartclk = clk_get_rate(sport->clk);
1729 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1731 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1733 if (*baud != baud_raw)
1734 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1735 "from %d to %d\n", baud_raw, *baud);
1739 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1740 int *parity, int *bits)
1742 unsigned long cr, bd;
1743 unsigned int sbr, uartclk, baud_raw;
1745 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1746 cr &= UARTCTRL_TE | UARTCTRL_RE;
1750 /* ok, the port was enabled */
1752 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1755 if (cr & UARTCTRL_PE) {
1756 if (cr & UARTCTRL_PT)
1762 if (cr & UARTCTRL_M)
1767 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1768 bd &= UARTBAUD_SBR_MASK;
1773 uartclk = clk_get_rate(sport->clk);
1775 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1777 baud_raw = uartclk / (16 * sbr);
1779 if (*baud != baud_raw)
1780 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1781 "from %d to %d\n", baud_raw, *baud);
1784 static int __init lpuart_console_setup(struct console *co, char *options)
1786 struct lpuart_port *sport;
1793 * check whether an invalid uart number has been specified, and
1794 * if so, search for the first available port that does have
1797 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1800 sport = lpuart_ports[co->index];
1805 uart_parse_options(options, &baud, &parity, &bits, &flow);
1807 if (sport->lpuart32)
1808 lpuart32_console_get_options(sport, &baud, &parity, &bits);
1810 lpuart_console_get_options(sport, &baud, &parity, &bits);
1812 if (sport->lpuart32)
1813 lpuart32_setup_watermark(sport);
1815 lpuart_setup_watermark(sport);
1817 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1820 static struct uart_driver lpuart_reg;
1821 static struct console lpuart_console = {
1823 .write = lpuart_console_write,
1824 .device = uart_console_device,
1825 .setup = lpuart_console_setup,
1826 .flags = CON_PRINTBUFFER,
1828 .data = &lpuart_reg,
1831 static struct console lpuart32_console = {
1833 .write = lpuart32_console_write,
1834 .device = uart_console_device,
1835 .setup = lpuart_console_setup,
1836 .flags = CON_PRINTBUFFER,
1838 .data = &lpuart_reg,
1841 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
1843 struct earlycon_device *dev = con->data;
1845 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
1848 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
1850 struct earlycon_device *dev = con->data;
1852 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
1855 static int __init lpuart_early_console_setup(struct earlycon_device *device,
1858 if (!device->port.membase)
1861 device->con->write = lpuart_early_write;
1865 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
1868 if (!device->port.membase)
1871 device->con->write = lpuart32_early_write;
1875 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
1876 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
1877 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
1878 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
1880 #define LPUART_CONSOLE (&lpuart_console)
1881 #define LPUART32_CONSOLE (&lpuart32_console)
1883 #define LPUART_CONSOLE NULL
1884 #define LPUART32_CONSOLE NULL
1887 static struct uart_driver lpuart_reg = {
1888 .owner = THIS_MODULE,
1889 .driver_name = DRIVER_NAME,
1890 .dev_name = DEV_NAME,
1891 .nr = ARRAY_SIZE(lpuart_ports),
1892 .cons = LPUART_CONSOLE,
1895 static int lpuart_probe(struct platform_device *pdev)
1897 struct device_node *np = pdev->dev.of_node;
1898 struct lpuart_port *sport;
1899 struct resource *res;
1902 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1906 pdev->dev.coherent_dma_mask = 0;
1908 ret = of_alias_get_id(np, "serial");
1910 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1913 if (ret >= ARRAY_SIZE(lpuart_ports)) {
1914 dev_err(&pdev->dev, "serial%d out of range\n", ret);
1917 sport->port.line = ret;
1918 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
1920 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1921 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1922 if (IS_ERR(sport->port.membase))
1923 return PTR_ERR(sport->port.membase);
1925 sport->port.mapbase = res->start;
1926 sport->port.dev = &pdev->dev;
1927 sport->port.type = PORT_LPUART;
1928 sport->port.iotype = UPIO_MEM;
1929 ret = platform_get_irq(pdev, 0);
1931 dev_err(&pdev->dev, "cannot obtain irq\n");
1934 sport->port.irq = ret;
1936 if (sport->lpuart32)
1937 sport->port.ops = &lpuart32_pops;
1939 sport->port.ops = &lpuart_pops;
1940 sport->port.flags = UPF_BOOT_AUTOCONF;
1942 sport->port.rs485_config = lpuart_config_rs485;
1944 sport->clk = devm_clk_get(&pdev->dev, "ipg");
1945 if (IS_ERR(sport->clk)) {
1946 ret = PTR_ERR(sport->clk);
1947 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1951 ret = clk_prepare_enable(sport->clk);
1953 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1957 sport->port.uartclk = clk_get_rate(sport->clk);
1959 lpuart_ports[sport->port.line] = sport;
1961 platform_set_drvdata(pdev, &sport->port);
1963 if (sport->lpuart32)
1964 lpuart_reg.cons = LPUART32_CONSOLE;
1966 lpuart_reg.cons = LPUART_CONSOLE;
1968 ret = uart_add_one_port(&lpuart_reg, &sport->port);
1970 clk_disable_unprepare(sport->clk);
1974 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
1975 if (!sport->dma_tx_chan)
1976 dev_info(sport->port.dev, "DMA tx channel request failed, "
1977 "operating without tx DMA\n");
1979 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1980 if (!sport->dma_rx_chan)
1981 dev_info(sport->port.dev, "DMA rx channel request failed, "
1982 "operating without rx DMA\n");
1984 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) {
1985 sport->port.rs485.flags |= SER_RS485_ENABLED;
1986 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND;
1987 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM);
1993 static int lpuart_remove(struct platform_device *pdev)
1995 struct lpuart_port *sport = platform_get_drvdata(pdev);
1997 uart_remove_one_port(&lpuart_reg, &sport->port);
1999 clk_disable_unprepare(sport->clk);
2001 if (sport->dma_tx_chan)
2002 dma_release_channel(sport->dma_tx_chan);
2004 if (sport->dma_rx_chan)
2005 dma_release_channel(sport->dma_rx_chan);
2010 #ifdef CONFIG_PM_SLEEP
2011 static int lpuart_suspend(struct device *dev)
2013 struct lpuart_port *sport = dev_get_drvdata(dev);
2016 if (sport->lpuart32) {
2017 /* disable Rx/Tx and interrupts */
2018 temp = lpuart32_read(sport->port.membase + UARTCTRL);
2019 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2020 lpuart32_write(temp, sport->port.membase + UARTCTRL);
2022 /* disable Rx/Tx and interrupts */
2023 temp = readb(sport->port.membase + UARTCR2);
2024 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2025 writeb(temp, sport->port.membase + UARTCR2);
2028 uart_suspend_port(&lpuart_reg, &sport->port);
2030 if (sport->lpuart_dma_rx_use) {
2032 * EDMA driver during suspend will forcefully release any
2033 * non-idle DMA channels. If port wakeup is enabled or if port
2034 * is console port or 'no_console_suspend' is set the Rx DMA
2035 * cannot resume as as expected, hence gracefully release the
2036 * Rx DMA path before suspend and start Rx DMA path on resume.
2038 if (sport->port.irq_wake) {
2039 del_timer_sync(&sport->lpuart_timer);
2040 lpuart_dma_rx_free(&sport->port);
2043 /* Disable Rx DMA to use UART port as wakeup source */
2044 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
2045 sport->port.membase + UARTCR5);
2048 if (sport->lpuart_dma_tx_use) {
2049 sport->dma_tx_in_progress = false;
2050 dmaengine_terminate_all(sport->dma_tx_chan);
2053 if (sport->port.suspended && !sport->port.irq_wake)
2054 clk_disable_unprepare(sport->clk);
2059 static int lpuart_resume(struct device *dev)
2061 struct lpuart_port *sport = dev_get_drvdata(dev);
2064 if (sport->port.suspended && !sport->port.irq_wake)
2065 clk_prepare_enable(sport->clk);
2067 if (sport->lpuart32) {
2068 lpuart32_setup_watermark(sport);
2069 temp = lpuart32_read(sport->port.membase + UARTCTRL);
2070 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
2071 UARTCTRL_TE | UARTCTRL_ILIE);
2072 lpuart32_write(temp, sport->port.membase + UARTCTRL);
2074 lpuart_setup_watermark(sport);
2075 temp = readb(sport->port.membase + UARTCR2);
2076 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2077 writeb(temp, sport->port.membase + UARTCR2);
2080 if (sport->lpuart_dma_rx_use) {
2081 if (sport->port.irq_wake) {
2082 if (!lpuart_start_rx_dma(sport)) {
2083 sport->lpuart_dma_rx_use = true;
2084 rx_dma_timer_init(sport);
2086 sport->lpuart_dma_rx_use = false;
2091 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2092 init_waitqueue_head(&sport->dma_wait);
2093 sport->lpuart_dma_tx_use = true;
2094 writeb(readb(sport->port.membase + UARTCR5) |
2095 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2097 sport->lpuart_dma_tx_use = false;
2100 uart_resume_port(&lpuart_reg, &sport->port);
2106 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2108 static struct platform_driver lpuart_driver = {
2109 .probe = lpuart_probe,
2110 .remove = lpuart_remove,
2112 .name = "fsl-lpuart",
2113 .of_match_table = lpuart_dt_ids,
2114 .pm = &lpuart_pm_ops,
2118 static int __init lpuart_serial_init(void)
2120 int ret = uart_register_driver(&lpuart_reg);
2125 ret = platform_driver_register(&lpuart_driver);
2127 uart_unregister_driver(&lpuart_reg);
2132 static void __exit lpuart_serial_exit(void)
2134 platform_driver_unregister(&lpuart_driver);
2135 uart_unregister_driver(&lpuart_reg);
2138 module_init(lpuart_serial_init);
2139 module_exit(lpuart_serial_exit);
2141 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2142 MODULE_LICENSE("GPL v2");