1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale lpuart serial port driver
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
9 #include <linux/console.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dmapool.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/of_dma.h>
19 #include <linux/serial_core.h>
20 #include <linux/slab.h>
21 #include <linux/tty_flip.h>
23 /* All registers are 8-bit width */
33 #define UARTMODEM 0x0d
34 #define UARTPFIFO 0x10
35 #define UARTCFIFO 0x11
36 #define UARTSFIFO 0x12
37 #define UARTTWFIFO 0x13
38 #define UARTTCFIFO 0x14
39 #define UARTRWFIFO 0x15
41 #define UARTBDH_LBKDIE 0x80
42 #define UARTBDH_RXEDGIE 0x40
43 #define UARTBDH_SBR_MASK 0x1f
45 #define UARTCR1_LOOPS 0x80
46 #define UARTCR1_RSRC 0x20
47 #define UARTCR1_M 0x10
48 #define UARTCR1_WAKE 0x08
49 #define UARTCR1_ILT 0x04
50 #define UARTCR1_PE 0x02
51 #define UARTCR1_PT 0x01
53 #define UARTCR2_TIE 0x80
54 #define UARTCR2_TCIE 0x40
55 #define UARTCR2_RIE 0x20
56 #define UARTCR2_ILIE 0x10
57 #define UARTCR2_TE 0x08
58 #define UARTCR2_RE 0x04
59 #define UARTCR2_RWU 0x02
60 #define UARTCR2_SBK 0x01
62 #define UARTSR1_TDRE 0x80
63 #define UARTSR1_TC 0x40
64 #define UARTSR1_RDRF 0x20
65 #define UARTSR1_IDLE 0x10
66 #define UARTSR1_OR 0x08
67 #define UARTSR1_NF 0x04
68 #define UARTSR1_FE 0x02
69 #define UARTSR1_PE 0x01
71 #define UARTCR3_R8 0x80
72 #define UARTCR3_T8 0x40
73 #define UARTCR3_TXDIR 0x20
74 #define UARTCR3_TXINV 0x10
75 #define UARTCR3_ORIE 0x08
76 #define UARTCR3_NEIE 0x04
77 #define UARTCR3_FEIE 0x02
78 #define UARTCR3_PEIE 0x01
80 #define UARTCR4_MAEN1 0x80
81 #define UARTCR4_MAEN2 0x40
82 #define UARTCR4_M10 0x20
83 #define UARTCR4_BRFA_MASK 0x1f
84 #define UARTCR4_BRFA_OFF 0
86 #define UARTCR5_TDMAS 0x80
87 #define UARTCR5_RDMAS 0x20
89 #define UARTMODEM_RXRTSE 0x08
90 #define UARTMODEM_TXRTSPOL 0x04
91 #define UARTMODEM_TXRTSE 0x02
92 #define UARTMODEM_TXCTSE 0x01
94 #define UARTPFIFO_TXFE 0x80
95 #define UARTPFIFO_FIFOSIZE_MASK 0x7
96 #define UARTPFIFO_TXSIZE_OFF 4
97 #define UARTPFIFO_RXFE 0x08
98 #define UARTPFIFO_RXSIZE_OFF 0
100 #define UARTCFIFO_TXFLUSH 0x80
101 #define UARTCFIFO_RXFLUSH 0x40
102 #define UARTCFIFO_RXOFE 0x04
103 #define UARTCFIFO_TXOFE 0x02
104 #define UARTCFIFO_RXUFE 0x01
106 #define UARTSFIFO_TXEMPT 0x80
107 #define UARTSFIFO_RXEMPT 0x40
108 #define UARTSFIFO_RXOF 0x04
109 #define UARTSFIFO_TXOF 0x02
110 #define UARTSFIFO_RXUF 0x01
112 /* 32-bit register definition */
113 #define UARTBAUD 0x00
114 #define UARTSTAT 0x04
115 #define UARTCTRL 0x08
116 #define UARTDATA 0x0C
117 #define UARTMATCH 0x10
118 #define UARTMODIR 0x14
119 #define UARTFIFO 0x18
120 #define UARTWATER 0x1c
122 #define UARTBAUD_MAEN1 0x80000000
123 #define UARTBAUD_MAEN2 0x40000000
124 #define UARTBAUD_M10 0x20000000
125 #define UARTBAUD_TDMAE 0x00800000
126 #define UARTBAUD_RDMAE 0x00200000
127 #define UARTBAUD_MATCFG 0x00400000
128 #define UARTBAUD_BOTHEDGE 0x00020000
129 #define UARTBAUD_RESYNCDIS 0x00010000
130 #define UARTBAUD_LBKDIE 0x00008000
131 #define UARTBAUD_RXEDGIE 0x00004000
132 #define UARTBAUD_SBNS 0x00002000
133 #define UARTBAUD_SBR 0x00000000
134 #define UARTBAUD_SBR_MASK 0x1fff
135 #define UARTBAUD_OSR_MASK 0x1f
136 #define UARTBAUD_OSR_SHIFT 24
138 #define UARTSTAT_LBKDIF 0x80000000
139 #define UARTSTAT_RXEDGIF 0x40000000
140 #define UARTSTAT_MSBF 0x20000000
141 #define UARTSTAT_RXINV 0x10000000
142 #define UARTSTAT_RWUID 0x08000000
143 #define UARTSTAT_BRK13 0x04000000
144 #define UARTSTAT_LBKDE 0x02000000
145 #define UARTSTAT_RAF 0x01000000
146 #define UARTSTAT_TDRE 0x00800000
147 #define UARTSTAT_TC 0x00400000
148 #define UARTSTAT_RDRF 0x00200000
149 #define UARTSTAT_IDLE 0x00100000
150 #define UARTSTAT_OR 0x00080000
151 #define UARTSTAT_NF 0x00040000
152 #define UARTSTAT_FE 0x00020000
153 #define UARTSTAT_PE 0x00010000
154 #define UARTSTAT_MA1F 0x00008000
155 #define UARTSTAT_M21F 0x00004000
157 #define UARTCTRL_R8T9 0x80000000
158 #define UARTCTRL_R9T8 0x40000000
159 #define UARTCTRL_TXDIR 0x20000000
160 #define UARTCTRL_TXINV 0x10000000
161 #define UARTCTRL_ORIE 0x08000000
162 #define UARTCTRL_NEIE 0x04000000
163 #define UARTCTRL_FEIE 0x02000000
164 #define UARTCTRL_PEIE 0x01000000
165 #define UARTCTRL_TIE 0x00800000
166 #define UARTCTRL_TCIE 0x00400000
167 #define UARTCTRL_RIE 0x00200000
168 #define UARTCTRL_ILIE 0x00100000
169 #define UARTCTRL_TE 0x00080000
170 #define UARTCTRL_RE 0x00040000
171 #define UARTCTRL_RWU 0x00020000
172 #define UARTCTRL_SBK 0x00010000
173 #define UARTCTRL_MA1IE 0x00008000
174 #define UARTCTRL_MA2IE 0x00004000
175 #define UARTCTRL_IDLECFG 0x00000100
176 #define UARTCTRL_LOOPS 0x00000080
177 #define UARTCTRL_DOZEEN 0x00000040
178 #define UARTCTRL_RSRC 0x00000020
179 #define UARTCTRL_M 0x00000010
180 #define UARTCTRL_WAKE 0x00000008
181 #define UARTCTRL_ILT 0x00000004
182 #define UARTCTRL_PE 0x00000002
183 #define UARTCTRL_PT 0x00000001
185 #define UARTDATA_NOISY 0x00008000
186 #define UARTDATA_PARITYE 0x00004000
187 #define UARTDATA_FRETSC 0x00002000
188 #define UARTDATA_RXEMPT 0x00001000
189 #define UARTDATA_IDLINE 0x00000800
190 #define UARTDATA_MASK 0x3ff
192 #define UARTMODIR_IREN 0x00020000
193 #define UARTMODIR_TXCTSSRC 0x00000020
194 #define UARTMODIR_TXCTSC 0x00000010
195 #define UARTMODIR_RXRTSE 0x00000008
196 #define UARTMODIR_TXRTSPOL 0x00000004
197 #define UARTMODIR_TXRTSE 0x00000002
198 #define UARTMODIR_TXCTSE 0x00000001
200 #define UARTFIFO_TXEMPT 0x00800000
201 #define UARTFIFO_RXEMPT 0x00400000
202 #define UARTFIFO_TXOF 0x00020000
203 #define UARTFIFO_RXUF 0x00010000
204 #define UARTFIFO_TXFLUSH 0x00008000
205 #define UARTFIFO_RXFLUSH 0x00004000
206 #define UARTFIFO_TXOFE 0x00000200
207 #define UARTFIFO_RXUFE 0x00000100
208 #define UARTFIFO_TXFE 0x00000080
209 #define UARTFIFO_FIFOSIZE_MASK 0x7
210 #define UARTFIFO_TXSIZE_OFF 4
211 #define UARTFIFO_RXFE 0x00000008
212 #define UARTFIFO_RXSIZE_OFF 0
213 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
215 #define UARTWATER_COUNT_MASK 0xff
216 #define UARTWATER_TXCNT_OFF 8
217 #define UARTWATER_RXCNT_OFF 24
218 #define UARTWATER_WATER_MASK 0xff
219 #define UARTWATER_TXWATER_OFF 0
220 #define UARTWATER_RXWATER_OFF 16
222 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
223 #define DMA_RX_TIMEOUT (10)
225 #define DRIVER_NAME "fsl-lpuart"
226 #define DEV_NAME "ttyLP"
229 /* IMX lpuart has four extra unused regs located at the beginning */
230 #define IMX_REG_OFF 0x10
241 struct uart_port port;
242 enum lpuart_type devtype;
244 struct clk *baud_clk;
245 unsigned int txfifo_size;
246 unsigned int rxfifo_size;
248 bool lpuart_dma_tx_use;
249 bool lpuart_dma_rx_use;
250 struct dma_chan *dma_tx_chan;
251 struct dma_chan *dma_rx_chan;
252 struct dma_async_tx_descriptor *dma_tx_desc;
253 struct dma_async_tx_descriptor *dma_rx_desc;
254 dma_cookie_t dma_tx_cookie;
255 dma_cookie_t dma_rx_cookie;
256 unsigned int dma_tx_bytes;
257 unsigned int dma_rx_bytes;
258 bool dma_tx_in_progress;
259 unsigned int dma_rx_timeout;
260 struct timer_list lpuart_timer;
261 struct scatterlist rx_sgl, tx_sgl[2];
262 struct circ_buf rx_ring;
263 int rx_dma_rng_buf_len;
264 unsigned int dma_tx_nents;
265 wait_queue_head_t dma_wait;
268 struct lpuart_soc_data {
269 enum lpuart_type devtype;
274 static const struct lpuart_soc_data vf_data = {
275 .devtype = VF610_LPUART,
279 static const struct lpuart_soc_data ls1021a_data = {
280 .devtype = LS1021A_LPUART,
281 .iotype = UPIO_MEM32BE,
284 static const struct lpuart_soc_data ls1028a_data = {
285 .devtype = LS1028A_LPUART,
286 .iotype = UPIO_MEM32,
289 static struct lpuart_soc_data imx7ulp_data = {
290 .devtype = IMX7ULP_LPUART,
291 .iotype = UPIO_MEM32,
292 .reg_off = IMX_REG_OFF,
295 static struct lpuart_soc_data imx8qxp_data = {
296 .devtype = IMX8QXP_LPUART,
297 .iotype = UPIO_MEM32,
298 .reg_off = IMX_REG_OFF,
301 static const struct of_device_id lpuart_dt_ids[] = {
302 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
303 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
304 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
305 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
306 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
309 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
311 /* Forward declare this for the dma callbacks*/
312 static void lpuart_dma_tx_complete(void *arg);
314 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
316 return (sport->devtype == LS1021A_LPUART ||
317 sport->devtype == LS1028A_LPUART);
320 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
322 return sport->devtype == IMX8QXP_LPUART;
325 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
327 switch (port->iotype) {
329 return readl(port->membase + off);
331 return ioread32be(port->membase + off);
337 static inline void lpuart32_write(struct uart_port *port, u32 val,
340 switch (port->iotype) {
342 writel(val, port->membase + off);
345 iowrite32be(val, port->membase + off);
350 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
355 ret = clk_prepare_enable(sport->ipg_clk);
359 ret = clk_prepare_enable(sport->baud_clk);
361 clk_disable_unprepare(sport->ipg_clk);
365 clk_disable_unprepare(sport->baud_clk);
366 clk_disable_unprepare(sport->ipg_clk);
372 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
374 if (is_imx8qxp_lpuart(sport))
375 return clk_get_rate(sport->baud_clk);
377 return clk_get_rate(sport->ipg_clk);
380 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
381 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
383 static void lpuart_stop_tx(struct uart_port *port)
387 temp = readb(port->membase + UARTCR2);
388 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
389 writeb(temp, port->membase + UARTCR2);
392 static void lpuart32_stop_tx(struct uart_port *port)
396 temp = lpuart32_read(port, UARTCTRL);
397 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
398 lpuart32_write(port, temp, UARTCTRL);
401 static void lpuart_stop_rx(struct uart_port *port)
405 temp = readb(port->membase + UARTCR2);
406 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
409 static void lpuart32_stop_rx(struct uart_port *port)
413 temp = lpuart32_read(port, UARTCTRL);
414 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
417 static void lpuart_dma_tx(struct lpuart_port *sport)
419 struct circ_buf *xmit = &sport->port.state->xmit;
420 struct scatterlist *sgl = sport->tx_sgl;
421 struct device *dev = sport->port.dev;
422 struct dma_chan *chan = sport->dma_tx_chan;
425 if (sport->dma_tx_in_progress)
428 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
430 if (xmit->tail < xmit->head || xmit->head == 0) {
431 sport->dma_tx_nents = 1;
432 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
434 sport->dma_tx_nents = 2;
435 sg_init_table(sgl, 2);
436 sg_set_buf(sgl, xmit->buf + xmit->tail,
437 UART_XMIT_SIZE - xmit->tail);
438 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
441 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
444 dev_err(dev, "DMA mapping error for TX.\n");
448 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
451 if (!sport->dma_tx_desc) {
452 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
454 dev_err(dev, "Cannot prepare TX slave DMA!\n");
458 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
459 sport->dma_tx_desc->callback_param = sport;
460 sport->dma_tx_in_progress = true;
461 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
462 dma_async_issue_pending(chan);
465 static bool lpuart_stopped_or_empty(struct uart_port *port)
467 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
470 static void lpuart_dma_tx_complete(void *arg)
472 struct lpuart_port *sport = arg;
473 struct scatterlist *sgl = &sport->tx_sgl[0];
474 struct circ_buf *xmit = &sport->port.state->xmit;
475 struct dma_chan *chan = sport->dma_tx_chan;
478 spin_lock_irqsave(&sport->port.lock, flags);
480 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
483 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
485 sport->port.icount.tx += sport->dma_tx_bytes;
486 sport->dma_tx_in_progress = false;
487 spin_unlock_irqrestore(&sport->port.lock, flags);
489 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
490 uart_write_wakeup(&sport->port);
492 if (waitqueue_active(&sport->dma_wait)) {
493 wake_up(&sport->dma_wait);
497 spin_lock_irqsave(&sport->port.lock, flags);
499 if (!lpuart_stopped_or_empty(&sport->port))
500 lpuart_dma_tx(sport);
502 spin_unlock_irqrestore(&sport->port.lock, flags);
505 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
507 switch (sport->port.iotype) {
509 return sport->port.mapbase + UARTDATA;
511 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
513 return sport->port.mapbase + UARTDR;
516 static int lpuart_dma_tx_request(struct uart_port *port)
518 struct lpuart_port *sport = container_of(port,
519 struct lpuart_port, port);
520 struct dma_slave_config dma_tx_sconfig = {};
523 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
524 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
525 dma_tx_sconfig.dst_maxburst = 1;
526 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
527 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
530 dev_err(sport->port.dev,
531 "DMA slave config failed, err = %d\n", ret);
538 static bool lpuart_is_32(struct lpuart_port *sport)
540 return sport->port.iotype == UPIO_MEM32 ||
541 sport->port.iotype == UPIO_MEM32BE;
544 static void lpuart_flush_buffer(struct uart_port *port)
546 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
547 struct dma_chan *chan = sport->dma_tx_chan;
550 if (sport->lpuart_dma_tx_use) {
551 if (sport->dma_tx_in_progress) {
552 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
553 sport->dma_tx_nents, DMA_TO_DEVICE);
554 sport->dma_tx_in_progress = false;
556 dmaengine_terminate_all(chan);
559 if (lpuart_is_32(sport)) {
560 val = lpuart32_read(&sport->port, UARTFIFO);
561 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
562 lpuart32_write(&sport->port, val, UARTFIFO);
564 val = readb(sport->port.membase + UARTCFIFO);
565 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
566 writeb(val, sport->port.membase + UARTCFIFO);
570 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
573 while (!(readb(port->membase + offset) & bit))
577 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
580 while (!(lpuart32_read(port, offset) & bit))
584 #if defined(CONFIG_CONSOLE_POLL)
586 static int lpuart_poll_init(struct uart_port *port)
588 struct lpuart_port *sport = container_of(port,
589 struct lpuart_port, port);
593 sport->port.fifosize = 0;
595 spin_lock_irqsave(&sport->port.lock, flags);
596 /* Disable Rx & Tx */
597 writeb(0, sport->port.membase + UARTCR2);
599 temp = readb(sport->port.membase + UARTPFIFO);
600 /* Enable Rx and Tx FIFO */
601 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
602 sport->port.membase + UARTPFIFO);
604 /* flush Tx and Rx FIFO */
605 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
606 sport->port.membase + UARTCFIFO);
608 /* explicitly clear RDRF */
609 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
610 readb(sport->port.membase + UARTDR);
611 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
614 writeb(0, sport->port.membase + UARTTWFIFO);
615 writeb(1, sport->port.membase + UARTRWFIFO);
617 /* Enable Rx and Tx */
618 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
619 spin_unlock_irqrestore(&sport->port.lock, flags);
624 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
627 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
628 writeb(c, port->membase + UARTDR);
631 static int lpuart_poll_get_char(struct uart_port *port)
633 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
636 return readb(port->membase + UARTDR);
639 static int lpuart32_poll_init(struct uart_port *port)
642 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
645 sport->port.fifosize = 0;
647 spin_lock_irqsave(&sport->port.lock, flags);
649 /* Disable Rx & Tx */
650 lpuart32_write(&sport->port, 0, UARTCTRL);
652 temp = lpuart32_read(&sport->port, UARTFIFO);
654 /* Enable Rx and Tx FIFO */
655 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
657 /* flush Tx and Rx FIFO */
658 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
660 /* explicitly clear RDRF */
661 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
662 lpuart32_read(&sport->port, UARTDATA);
663 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
666 /* Enable Rx and Tx */
667 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
668 spin_unlock_irqrestore(&sport->port.lock, flags);
673 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
675 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
676 lpuart32_write(port, c, UARTDATA);
679 static int lpuart32_poll_get_char(struct uart_port *port)
681 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
684 return lpuart32_read(port, UARTDATA);
688 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
690 struct circ_buf *xmit = &sport->port.state->xmit;
692 if (sport->port.x_char) {
693 writeb(sport->port.x_char, sport->port.membase + UARTDR);
694 sport->port.icount.tx++;
695 sport->port.x_char = 0;
699 if (lpuart_stopped_or_empty(&sport->port)) {
700 lpuart_stop_tx(&sport->port);
704 while (!uart_circ_empty(xmit) &&
705 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
706 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
707 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
708 sport->port.icount.tx++;
711 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
712 uart_write_wakeup(&sport->port);
714 if (uart_circ_empty(xmit))
715 lpuart_stop_tx(&sport->port);
718 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
720 struct circ_buf *xmit = &sport->port.state->xmit;
723 if (sport->port.x_char) {
724 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
725 sport->port.icount.tx++;
726 sport->port.x_char = 0;
730 if (lpuart_stopped_or_empty(&sport->port)) {
731 lpuart32_stop_tx(&sport->port);
735 txcnt = lpuart32_read(&sport->port, UARTWATER);
736 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
737 txcnt &= UARTWATER_COUNT_MASK;
738 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
739 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
740 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
741 sport->port.icount.tx++;
742 txcnt = lpuart32_read(&sport->port, UARTWATER);
743 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
744 txcnt &= UARTWATER_COUNT_MASK;
747 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
748 uart_write_wakeup(&sport->port);
750 if (uart_circ_empty(xmit))
751 lpuart32_stop_tx(&sport->port);
754 static void lpuart_start_tx(struct uart_port *port)
756 struct lpuart_port *sport = container_of(port,
757 struct lpuart_port, port);
760 temp = readb(port->membase + UARTCR2);
761 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
763 if (sport->lpuart_dma_tx_use) {
764 if (!lpuart_stopped_or_empty(port))
765 lpuart_dma_tx(sport);
767 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
768 lpuart_transmit_buffer(sport);
772 static void lpuart32_start_tx(struct uart_port *port)
774 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
777 if (sport->lpuart_dma_tx_use) {
778 if (!lpuart_stopped_or_empty(port))
779 lpuart_dma_tx(sport);
781 temp = lpuart32_read(port, UARTCTRL);
782 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
784 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
785 lpuart32_transmit_buffer(sport);
789 /* return TIOCSER_TEMT when transmitter is not busy */
790 static unsigned int lpuart_tx_empty(struct uart_port *port)
792 struct lpuart_port *sport = container_of(port,
793 struct lpuart_port, port);
794 unsigned char sr1 = readb(port->membase + UARTSR1);
795 unsigned char sfifo = readb(port->membase + UARTSFIFO);
797 if (sport->dma_tx_in_progress)
800 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
806 static unsigned int lpuart32_tx_empty(struct uart_port *port)
808 struct lpuart_port *sport = container_of(port,
809 struct lpuart_port, port);
810 unsigned long stat = lpuart32_read(port, UARTSTAT);
811 unsigned long sfifo = lpuart32_read(port, UARTFIFO);
812 unsigned long ctrl = lpuart32_read(port, UARTCTRL);
814 if (sport->dma_tx_in_progress)
818 * LPUART Transmission Complete Flag may never be set while queuing a break
819 * character, so avoid checking for transmission complete when UARTCTRL_SBK
822 if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK)
828 static void lpuart_txint(struct lpuart_port *sport)
832 spin_lock_irqsave(&sport->port.lock, flags);
833 lpuart_transmit_buffer(sport);
834 spin_unlock_irqrestore(&sport->port.lock, flags);
837 static void lpuart_rxint(struct lpuart_port *sport)
839 unsigned int flg, ignored = 0, overrun = 0;
840 struct tty_port *port = &sport->port.state->port;
842 unsigned char rx, sr;
844 spin_lock_irqsave(&sport->port.lock, flags);
846 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
848 sport->port.icount.rx++;
850 * to clear the FE, OR, NF, FE, PE flags,
851 * read SR1 then read DR
853 sr = readb(sport->port.membase + UARTSR1);
854 rx = readb(sport->port.membase + UARTDR);
856 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
859 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
861 sport->port.icount.parity++;
862 else if (sr & UARTSR1_FE)
863 sport->port.icount.frame++;
868 if (sr & sport->port.ignore_status_mask) {
874 sr &= sport->port.read_status_mask;
878 else if (sr & UARTSR1_FE)
884 sport->port.sysrq = 0;
887 tty_insert_flip_char(port, rx, flg);
892 sport->port.icount.overrun += overrun;
895 * Overruns cause FIFO pointers to become missaligned.
896 * Flushing the receive FIFO reinitializes the pointers.
898 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
899 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
902 spin_unlock_irqrestore(&sport->port.lock, flags);
904 tty_flip_buffer_push(port);
907 static void lpuart32_txint(struct lpuart_port *sport)
911 spin_lock_irqsave(&sport->port.lock, flags);
912 lpuart32_transmit_buffer(sport);
913 spin_unlock_irqrestore(&sport->port.lock, flags);
916 static void lpuart32_rxint(struct lpuart_port *sport)
918 unsigned int flg, ignored = 0;
919 struct tty_port *port = &sport->port.state->port;
921 unsigned long rx, sr;
923 spin_lock_irqsave(&sport->port.lock, flags);
925 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
927 sport->port.icount.rx++;
929 * to clear the FE, OR, NF, FE, PE flags,
930 * read STAT then read DATA reg
932 sr = lpuart32_read(&sport->port, UARTSTAT);
933 rx = lpuart32_read(&sport->port, UARTDATA);
936 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
939 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
940 if (sr & UARTSTAT_PE)
941 sport->port.icount.parity++;
942 else if (sr & UARTSTAT_FE)
943 sport->port.icount.frame++;
945 if (sr & UARTSTAT_OR)
946 sport->port.icount.overrun++;
948 if (sr & sport->port.ignore_status_mask) {
954 sr &= sport->port.read_status_mask;
956 if (sr & UARTSTAT_PE)
958 else if (sr & UARTSTAT_FE)
961 if (sr & UARTSTAT_OR)
964 sport->port.sysrq = 0;
967 tty_insert_flip_char(port, rx, flg);
971 spin_unlock_irqrestore(&sport->port.lock, flags);
973 tty_flip_buffer_push(port);
976 static irqreturn_t lpuart_int(int irq, void *dev_id)
978 struct lpuart_port *sport = dev_id;
981 sts = readb(sport->port.membase + UARTSR1);
983 /* SysRq, using dma, check for linebreak by framing err. */
984 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
985 readb(sport->port.membase + UARTDR);
986 uart_handle_break(&sport->port);
987 /* linebreak produces some garbage, removing it */
988 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
992 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
995 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1001 static irqreturn_t lpuart32_int(int irq, void *dev_id)
1003 struct lpuart_port *sport = dev_id;
1004 unsigned long sts, rxcount;
1006 sts = lpuart32_read(&sport->port, UARTSTAT);
1007 rxcount = lpuart32_read(&sport->port, UARTWATER);
1008 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1010 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1011 lpuart32_rxint(sport);
1013 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1014 lpuart32_txint(sport);
1016 lpuart32_write(&sport->port, sts, UARTSTAT);
1021 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1022 unsigned char *p, int count)
1025 if (*p && uart_handle_sysrq_char(port, *p))
1031 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1033 struct circ_buf *ring = &sport->rx_ring;
1036 if (ring->head < ring->tail) {
1037 count = sport->rx_sgl.length - ring->tail;
1038 lpuart_handle_sysrq_chars(&sport->port,
1039 ring->buf + ring->tail, count);
1043 if (ring->head > ring->tail) {
1044 count = ring->head - ring->tail;
1045 lpuart_handle_sysrq_chars(&sport->port,
1046 ring->buf + ring->tail, count);
1047 ring->tail = ring->head;
1051 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1053 struct tty_port *port = &sport->port.state->port;
1054 struct dma_tx_state state;
1055 enum dma_status dmastat;
1056 struct dma_chan *chan = sport->dma_rx_chan;
1057 struct circ_buf *ring = &sport->rx_ring;
1058 unsigned long flags;
1061 if (lpuart_is_32(sport)) {
1062 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1064 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1065 /* Clear the error flags */
1066 lpuart32_write(&sport->port, sr, UARTSTAT);
1068 if (sr & UARTSTAT_PE)
1069 sport->port.icount.parity++;
1070 else if (sr & UARTSTAT_FE)
1071 sport->port.icount.frame++;
1074 unsigned char sr = readb(sport->port.membase + UARTSR1);
1076 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1079 /* Disable receiver during this operation... */
1080 cr2 = readb(sport->port.membase + UARTCR2);
1082 writeb(cr2, sport->port.membase + UARTCR2);
1084 /* Read DR to clear the error flags */
1085 readb(sport->port.membase + UARTDR);
1087 if (sr & UARTSR1_PE)
1088 sport->port.icount.parity++;
1089 else if (sr & UARTSR1_FE)
1090 sport->port.icount.frame++;
1092 * At this point parity/framing error is
1093 * cleared However, since the DMA already read
1094 * the data register and we had to read it
1095 * again after reading the status register to
1096 * properly clear the flags, the FIFO actually
1097 * underflowed... This requires a clearing of
1100 if (readb(sport->port.membase + UARTSFIFO) &
1102 writeb(UARTSFIFO_RXUF,
1103 sport->port.membase + UARTSFIFO);
1104 writeb(UARTCFIFO_RXFLUSH,
1105 sport->port.membase + UARTCFIFO);
1109 writeb(cr2, sport->port.membase + UARTCR2);
1113 async_tx_ack(sport->dma_rx_desc);
1115 spin_lock_irqsave(&sport->port.lock, flags);
1117 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1118 if (dmastat == DMA_ERROR) {
1119 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1120 spin_unlock_irqrestore(&sport->port.lock, flags);
1124 /* CPU claims ownership of RX DMA buffer */
1125 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1129 * ring->head points to the end of data already written by the DMA.
1130 * ring->tail points to the beginning of data to be read by the
1132 * The current transfer size should not be larger than the dma buffer
1135 ring->head = sport->rx_sgl.length - state.residue;
1136 BUG_ON(ring->head > sport->rx_sgl.length);
1139 * Silent handling of keys pressed in the sysrq timeframe
1141 if (sport->port.sysrq) {
1142 lpuart_handle_sysrq(sport);
1147 * At this point ring->head may point to the first byte right after the
1148 * last byte of the dma buffer:
1149 * 0 <= ring->head <= sport->rx_sgl.length
1151 * However ring->tail must always points inside the dma buffer:
1152 * 0 <= ring->tail <= sport->rx_sgl.length - 1
1154 * Since we use a ring buffer, we have to handle the case
1155 * where head is lower than tail. In such a case, we first read from
1156 * tail to the end of the buffer then reset tail.
1158 if (ring->head < ring->tail) {
1159 count = sport->rx_sgl.length - ring->tail;
1161 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1163 sport->port.icount.rx += count;
1166 /* Finally we read data from tail to head */
1167 if (ring->tail < ring->head) {
1168 count = ring->head - ring->tail;
1169 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1170 /* Wrap ring->head if needed */
1171 if (ring->head >= sport->rx_sgl.length)
1173 ring->tail = ring->head;
1174 sport->port.icount.rx += count;
1178 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1181 spin_unlock_irqrestore(&sport->port.lock, flags);
1183 tty_flip_buffer_push(port);
1184 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1187 static void lpuart_dma_rx_complete(void *arg)
1189 struct lpuart_port *sport = arg;
1191 lpuart_copy_rx_to_tty(sport);
1194 static void lpuart_timer_func(struct timer_list *t)
1196 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1198 lpuart_copy_rx_to_tty(sport);
1201 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1203 struct dma_slave_config dma_rx_sconfig = {};
1204 struct circ_buf *ring = &sport->rx_ring;
1207 struct tty_port *port = &sport->port.state->port;
1208 struct tty_struct *tty = port->tty;
1209 struct ktermios *termios = &tty->termios;
1210 struct dma_chan *chan = sport->dma_rx_chan;
1212 baud = tty_get_baud_rate(tty);
1214 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1215 if (termios->c_cflag & PARENB)
1219 * Calculate length of one DMA buffer size to keep latency below
1220 * 10ms at any baud rate.
1222 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1223 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
1224 if (sport->rx_dma_rng_buf_len < 16)
1225 sport->rx_dma_rng_buf_len = 16;
1227 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1231 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1232 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1236 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1240 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1241 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1242 dma_rx_sconfig.src_maxburst = 1;
1243 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1244 ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1247 dev_err(sport->port.dev,
1248 "DMA Rx slave config failed, err = %d\n", ret);
1252 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1253 sg_dma_address(&sport->rx_sgl),
1254 sport->rx_sgl.length,
1255 sport->rx_sgl.length / 2,
1257 DMA_PREP_INTERRUPT);
1258 if (!sport->dma_rx_desc) {
1259 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1263 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1264 sport->dma_rx_desc->callback_param = sport;
1265 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1266 dma_async_issue_pending(chan);
1268 if (lpuart_is_32(sport)) {
1269 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1271 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1273 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1274 sport->port.membase + UARTCR5);
1280 static void lpuart_dma_rx_free(struct uart_port *port)
1282 struct lpuart_port *sport = container_of(port,
1283 struct lpuart_port, port);
1284 struct dma_chan *chan = sport->dma_rx_chan;
1286 dmaengine_terminate_all(chan);
1287 del_timer_sync(&sport->lpuart_timer);
1288 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1289 kfree(sport->rx_ring.buf);
1290 sport->rx_ring.tail = 0;
1291 sport->rx_ring.head = 0;
1292 sport->dma_rx_desc = NULL;
1293 sport->dma_rx_cookie = -EINVAL;
1296 static int lpuart_config_rs485(struct uart_port *port,
1297 struct serial_rs485 *rs485)
1299 struct lpuart_port *sport = container_of(port,
1300 struct lpuart_port, port);
1302 u8 modem = readb(sport->port.membase + UARTMODEM) &
1303 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1304 writeb(modem, sport->port.membase + UARTMODEM);
1306 /* clear unsupported configurations */
1307 rs485->delay_rts_before_send = 0;
1308 rs485->delay_rts_after_send = 0;
1309 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1311 if (rs485->flags & SER_RS485_ENABLED) {
1312 /* Enable auto RS-485 RTS mode */
1313 modem |= UARTMODEM_TXRTSE;
1316 * RTS needs to be logic HIGH either during transfer _or_ after
1317 * transfer, other variants are not supported by the hardware.
1320 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1321 SER_RS485_RTS_AFTER_SEND)))
1322 rs485->flags |= SER_RS485_RTS_ON_SEND;
1324 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1325 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1326 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1329 * The hardware defaults to RTS logic HIGH while transfer.
1330 * Switch polarity in case RTS shall be logic HIGH
1332 * Note: UART is assumed to be active high.
1334 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1335 modem &= ~UARTMODEM_TXRTSPOL;
1336 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1337 modem |= UARTMODEM_TXRTSPOL;
1340 /* Store the new configuration */
1341 sport->port.rs485 = *rs485;
1343 writeb(modem, sport->port.membase + UARTMODEM);
1347 static int lpuart32_config_rs485(struct uart_port *port,
1348 struct serial_rs485 *rs485)
1350 struct lpuart_port *sport = container_of(port,
1351 struct lpuart_port, port);
1353 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1354 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1355 lpuart32_write(&sport->port, modem, UARTMODIR);
1357 /* clear unsupported configurations */
1358 rs485->delay_rts_before_send = 0;
1359 rs485->delay_rts_after_send = 0;
1360 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1362 if (rs485->flags & SER_RS485_ENABLED) {
1363 /* Enable auto RS-485 RTS mode */
1364 modem |= UARTMODEM_TXRTSE;
1367 * RTS needs to be logic HIGH either during transfer _or_ after
1368 * transfer, other variants are not supported by the hardware.
1371 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1372 SER_RS485_RTS_AFTER_SEND)))
1373 rs485->flags |= SER_RS485_RTS_ON_SEND;
1375 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1376 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1377 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1380 * The hardware defaults to RTS logic HIGH while transfer.
1381 * Switch polarity in case RTS shall be logic HIGH
1383 * Note: UART is assumed to be active high.
1385 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1386 modem |= UARTMODEM_TXRTSPOL;
1387 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1388 modem &= ~UARTMODEM_TXRTSPOL;
1391 /* Store the new configuration */
1392 sport->port.rs485 = *rs485;
1394 lpuart32_write(&sport->port, modem, UARTMODIR);
1398 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1400 unsigned int temp = 0;
1403 reg = readb(port->membase + UARTMODEM);
1404 if (reg & UARTMODEM_TXCTSE)
1407 if (reg & UARTMODEM_RXRTSE)
1413 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1418 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1421 struct lpuart_port *sport = container_of(port,
1422 struct lpuart_port, port);
1424 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1425 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1426 temp = readb(sport->port.membase + UARTMODEM) &
1427 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1429 if (mctrl & TIOCM_RTS)
1430 temp |= UARTMODEM_RXRTSE;
1432 if (mctrl & TIOCM_CTS)
1433 temp |= UARTMODEM_TXCTSE;
1435 writeb(temp, port->membase + UARTMODEM);
1439 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1444 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1448 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1450 if (break_state != 0)
1451 temp |= UARTCR2_SBK;
1453 writeb(temp, port->membase + UARTCR2);
1456 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1460 temp = lpuart32_read(port, UARTCTRL);
1463 * LPUART IP now has two known bugs, one is CTS has higher priority than the
1464 * break signal, which causes the break signal sending through UARTCTRL_SBK
1465 * may impacted by the CTS input if the HW flow control is enabled. It
1466 * exists on all platforms we support in this driver.
1467 * Another bug is i.MX8QM LPUART may have an additional break character
1468 * being sent after SBK was cleared.
1469 * To avoid above two bugs, we use Transmit Data Inversion function to send
1470 * the break signal instead of UARTCTRL_SBK.
1472 if (break_state != 0) {
1474 * Disable the transmitter to prevent any data from being sent out
1475 * during break, then invert the TX line to send break.
1477 temp &= ~UARTCTRL_TE;
1478 lpuart32_write(port, temp, UARTCTRL);
1479 temp |= UARTCTRL_TXINV;
1480 lpuart32_write(port, temp, UARTCTRL);
1482 /* Disable the TXINV to turn off break and re-enable transmitter. */
1483 temp &= ~UARTCTRL_TXINV;
1484 lpuart32_write(port, temp, UARTCTRL);
1485 temp |= UARTCTRL_TE;
1486 lpuart32_write(port, temp, UARTCTRL);
1490 static void lpuart_setup_watermark(struct lpuart_port *sport)
1492 unsigned char val, cr2;
1493 unsigned char cr2_saved;
1495 cr2 = readb(sport->port.membase + UARTCR2);
1497 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1498 UARTCR2_RIE | UARTCR2_RE);
1499 writeb(cr2, sport->port.membase + UARTCR2);
1501 val = readb(sport->port.membase + UARTPFIFO);
1502 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1503 sport->port.membase + UARTPFIFO);
1505 /* flush Tx and Rx FIFO */
1506 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1507 sport->port.membase + UARTCFIFO);
1509 /* explicitly clear RDRF */
1510 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1511 readb(sport->port.membase + UARTDR);
1512 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1515 writeb(0, sport->port.membase + UARTTWFIFO);
1516 writeb(1, sport->port.membase + UARTRWFIFO);
1519 writeb(cr2_saved, sport->port.membase + UARTCR2);
1522 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1526 lpuart_setup_watermark(sport);
1528 cr2 = readb(sport->port.membase + UARTCR2);
1529 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1530 writeb(cr2, sport->port.membase + UARTCR2);
1533 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1535 unsigned long val, ctrl;
1536 unsigned long ctrl_saved;
1538 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1540 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1541 UARTCTRL_RIE | UARTCTRL_RE);
1542 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1544 /* enable FIFO mode */
1545 val = lpuart32_read(&sport->port, UARTFIFO);
1546 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1547 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1548 lpuart32_write(&sport->port, val, UARTFIFO);
1550 /* set the watermark */
1551 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1552 lpuart32_write(&sport->port, val, UARTWATER);
1555 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1558 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1562 lpuart32_setup_watermark(sport);
1564 temp = lpuart32_read(&sport->port, UARTCTRL);
1565 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1566 lpuart32_write(&sport->port, temp, UARTCTRL);
1569 static void rx_dma_timer_init(struct lpuart_port *sport)
1571 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1572 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1573 add_timer(&sport->lpuart_timer);
1576 static void lpuart_request_dma(struct lpuart_port *sport)
1578 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1579 if (IS_ERR(sport->dma_tx_chan)) {
1580 dev_dbg_once(sport->port.dev,
1581 "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1582 PTR_ERR(sport->dma_tx_chan));
1583 sport->dma_tx_chan = NULL;
1586 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1587 if (IS_ERR(sport->dma_rx_chan)) {
1588 dev_dbg_once(sport->port.dev,
1589 "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1590 PTR_ERR(sport->dma_rx_chan));
1591 sport->dma_rx_chan = NULL;
1595 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1600 if (uart_console(&sport->port))
1603 if (!sport->dma_tx_chan)
1606 ret = lpuart_dma_tx_request(&sport->port);
1610 init_waitqueue_head(&sport->dma_wait);
1611 sport->lpuart_dma_tx_use = true;
1612 if (lpuart_is_32(sport)) {
1613 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1614 lpuart32_write(&sport->port,
1615 uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1617 writeb(readb(sport->port.membase + UARTCR5) |
1618 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1624 sport->lpuart_dma_tx_use = false;
1627 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1632 if (uart_console(&sport->port))
1635 if (!sport->dma_rx_chan)
1638 ret = lpuart_start_rx_dma(sport);
1642 /* set Rx DMA timeout */
1643 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1644 if (!sport->dma_rx_timeout)
1645 sport->dma_rx_timeout = 1;
1647 sport->lpuart_dma_rx_use = true;
1648 rx_dma_timer_init(sport);
1650 if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1651 cr3 = readb(sport->port.membase + UARTCR3);
1652 cr3 |= UARTCR3_FEIE;
1653 writeb(cr3, sport->port.membase + UARTCR3);
1659 sport->lpuart_dma_rx_use = false;
1662 static int lpuart_startup(struct uart_port *port)
1664 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1665 unsigned long flags;
1668 /* determine FIFO size and enable FIFO mode */
1669 temp = readb(sport->port.membase + UARTPFIFO);
1671 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1672 UARTPFIFO_FIFOSIZE_MASK);
1673 sport->port.fifosize = sport->txfifo_size;
1675 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1676 UARTPFIFO_FIFOSIZE_MASK);
1678 lpuart_request_dma(sport);
1680 spin_lock_irqsave(&sport->port.lock, flags);
1682 lpuart_setup_watermark_enable(sport);
1684 lpuart_rx_dma_startup(sport);
1685 lpuart_tx_dma_startup(sport);
1687 spin_unlock_irqrestore(&sport->port.lock, flags);
1692 static void lpuart32_configure(struct lpuart_port *sport)
1696 if (sport->lpuart_dma_rx_use) {
1697 /* RXWATER must be 0 */
1698 temp = lpuart32_read(&sport->port, UARTWATER);
1699 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1700 lpuart32_write(&sport->port, temp, UARTWATER);
1702 temp = lpuart32_read(&sport->port, UARTCTRL);
1703 if (!sport->lpuart_dma_rx_use)
1704 temp |= UARTCTRL_RIE;
1705 if (!sport->lpuart_dma_tx_use)
1706 temp |= UARTCTRL_TIE;
1707 lpuart32_write(&sport->port, temp, UARTCTRL);
1710 static int lpuart32_startup(struct uart_port *port)
1712 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1713 unsigned long flags;
1716 /* determine FIFO size */
1717 temp = lpuart32_read(&sport->port, UARTFIFO);
1719 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1720 UARTFIFO_FIFOSIZE_MASK);
1721 sport->port.fifosize = sport->txfifo_size;
1723 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1724 UARTFIFO_FIFOSIZE_MASK);
1727 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1728 * Although they support the RX/TXSIZE fields, their encoding is
1729 * different. Eg the reference manual states 0b101 is 16 words.
1731 if (is_layerscape_lpuart(sport)) {
1732 sport->rxfifo_size = 16;
1733 sport->txfifo_size = 16;
1734 sport->port.fifosize = sport->txfifo_size;
1737 lpuart_request_dma(sport);
1739 spin_lock_irqsave(&sport->port.lock, flags);
1741 lpuart32_setup_watermark_enable(sport);
1743 lpuart_rx_dma_startup(sport);
1744 lpuart_tx_dma_startup(sport);
1746 lpuart32_configure(sport);
1748 spin_unlock_irqrestore(&sport->port.lock, flags);
1752 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1754 if (sport->lpuart_dma_rx_use) {
1755 lpuart_dma_rx_free(&sport->port);
1756 sport->lpuart_dma_rx_use = false;
1759 if (sport->lpuart_dma_tx_use) {
1760 if (wait_event_interruptible(sport->dma_wait,
1761 !sport->dma_tx_in_progress) != false) {
1762 sport->dma_tx_in_progress = false;
1763 dmaengine_terminate_all(sport->dma_tx_chan);
1765 sport->lpuart_dma_tx_use = false;
1768 if (sport->dma_tx_chan)
1769 dma_release_channel(sport->dma_tx_chan);
1770 if (sport->dma_rx_chan)
1771 dma_release_channel(sport->dma_rx_chan);
1774 static void lpuart_shutdown(struct uart_port *port)
1776 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1778 unsigned long flags;
1780 spin_lock_irqsave(&port->lock, flags);
1782 /* disable Rx/Tx and interrupts */
1783 temp = readb(port->membase + UARTCR2);
1784 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1785 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1786 writeb(temp, port->membase + UARTCR2);
1788 spin_unlock_irqrestore(&port->lock, flags);
1790 lpuart_dma_shutdown(sport);
1793 static void lpuart32_shutdown(struct uart_port *port)
1795 struct lpuart_port *sport =
1796 container_of(port, struct lpuart_port, port);
1798 unsigned long flags;
1800 spin_lock_irqsave(&port->lock, flags);
1802 /* disable Rx/Tx and interrupts */
1803 temp = lpuart32_read(port, UARTCTRL);
1804 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1805 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1806 lpuart32_write(port, temp, UARTCTRL);
1808 spin_unlock_irqrestore(&port->lock, flags);
1810 lpuart_dma_shutdown(sport);
1814 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1815 struct ktermios *old)
1817 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1818 unsigned long flags;
1819 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1821 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1822 unsigned int sbr, brfa;
1824 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1825 old_cr2 = readb(sport->port.membase + UARTCR2);
1826 cr3 = readb(sport->port.membase + UARTCR3);
1827 cr4 = readb(sport->port.membase + UARTCR4);
1828 bdh = readb(sport->port.membase + UARTBDH);
1829 modem = readb(sport->port.membase + UARTMODEM);
1831 * only support CS8 and CS7, and for CS7 must enable PE.
1838 while ((termios->c_cflag & CSIZE) != CS8 &&
1839 (termios->c_cflag & CSIZE) != CS7) {
1840 termios->c_cflag &= ~CSIZE;
1841 termios->c_cflag |= old_csize;
1845 if ((termios->c_cflag & CSIZE) == CS8 ||
1846 (termios->c_cflag & CSIZE) == CS7)
1847 cr1 = old_cr1 & ~UARTCR1_M;
1849 if (termios->c_cflag & CMSPAR) {
1850 if ((termios->c_cflag & CSIZE) != CS8) {
1851 termios->c_cflag &= ~CSIZE;
1852 termios->c_cflag |= CS8;
1858 * When auto RS-485 RTS mode is enabled,
1859 * hardware flow control need to be disabled.
1861 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1862 termios->c_cflag &= ~CRTSCTS;
1864 if (termios->c_cflag & CRTSCTS)
1865 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1867 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1869 termios->c_cflag &= ~CSTOPB;
1871 /* parity must be enabled when CS7 to match 8-bits format */
1872 if ((termios->c_cflag & CSIZE) == CS7)
1873 termios->c_cflag |= PARENB;
1875 if (termios->c_cflag & PARENB) {
1876 if (termios->c_cflag & CMSPAR) {
1878 if (termios->c_cflag & PARODD)
1884 if ((termios->c_cflag & CSIZE) == CS8)
1886 if (termios->c_cflag & PARODD)
1895 /* ask the core to calculate the divisor */
1896 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1899 * Need to update the Ring buffer length according to the selected
1900 * baud rate and restart Rx DMA path.
1902 * Since timer function acqures sport->port.lock, need to stop before
1903 * acquring same lock because otherwise del_timer_sync() can deadlock.
1905 if (old && sport->lpuart_dma_rx_use)
1906 lpuart_dma_rx_free(&sport->port);
1908 spin_lock_irqsave(&sport->port.lock, flags);
1910 sport->port.read_status_mask = 0;
1911 if (termios->c_iflag & INPCK)
1912 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1913 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1914 sport->port.read_status_mask |= UARTSR1_FE;
1916 /* characters to ignore */
1917 sport->port.ignore_status_mask = 0;
1918 if (termios->c_iflag & IGNPAR)
1919 sport->port.ignore_status_mask |= UARTSR1_PE;
1920 if (termios->c_iflag & IGNBRK) {
1921 sport->port.ignore_status_mask |= UARTSR1_FE;
1923 * if we're ignoring parity and break indicators,
1924 * ignore overruns too (for real raw support).
1926 if (termios->c_iflag & IGNPAR)
1927 sport->port.ignore_status_mask |= UARTSR1_OR;
1930 /* update the per-port timeout */
1931 uart_update_timeout(port, termios->c_cflag, baud);
1933 /* wait transmit engin complete */
1934 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1936 /* disable transmit and receive */
1937 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1938 sport->port.membase + UARTCR2);
1940 sbr = sport->port.uartclk / (16 * baud);
1941 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1942 bdh &= ~UARTBDH_SBR_MASK;
1943 bdh |= (sbr >> 8) & 0x1F;
1944 cr4 &= ~UARTCR4_BRFA_MASK;
1945 brfa &= UARTCR4_BRFA_MASK;
1946 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1947 writeb(bdh, sport->port.membase + UARTBDH);
1948 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1949 writeb(cr3, sport->port.membase + UARTCR3);
1950 writeb(cr1, sport->port.membase + UARTCR1);
1951 writeb(modem, sport->port.membase + UARTMODEM);
1953 /* restore control register */
1954 writeb(old_cr2, sport->port.membase + UARTCR2);
1956 if (old && sport->lpuart_dma_rx_use) {
1957 if (!lpuart_start_rx_dma(sport))
1958 rx_dma_timer_init(sport);
1960 sport->lpuart_dma_rx_use = false;
1963 spin_unlock_irqrestore(&sport->port.lock, flags);
1966 static void __lpuart32_serial_setbrg(struct uart_port *port,
1967 unsigned int baudrate, bool use_rx_dma,
1970 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1971 u32 clk = port->uartclk;
1974 * The idea is to use the best OSR (over-sampling rate) possible.
1975 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1976 * Loop to find the best OSR value possible, one that generates minimum
1977 * baud_diff iterate through the rest of the supported values of OSR.
1979 * Calculation Formula:
1980 * Baud Rate = baud clock / ((OSR+1) × SBR)
1982 baud_diff = baudrate;
1986 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1987 /* calculate the temporary sbr value */
1988 tmp_sbr = (clk / (baudrate * tmp_osr));
1993 * calculate the baud rate difference based on the temporary
1994 * osr and sbr values
1996 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1998 /* select best values between sbr and sbr+1 */
1999 tmp = clk / (tmp_osr * (tmp_sbr + 1));
2000 if (tmp_diff > (baudrate - tmp)) {
2001 tmp_diff = baudrate - tmp;
2005 if (tmp_sbr > UARTBAUD_SBR_MASK)
2008 if (tmp_diff <= baud_diff) {
2009 baud_diff = tmp_diff;
2018 /* handle buadrate outside acceptable rate */
2019 if (baud_diff > ((baudrate / 100) * 3))
2021 "unacceptable baud rate difference of more than 3%%\n");
2023 tmp = lpuart32_read(port, UARTBAUD);
2025 if ((osr > 3) && (osr < 8))
2026 tmp |= UARTBAUD_BOTHEDGE;
2028 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2029 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2031 tmp &= ~UARTBAUD_SBR_MASK;
2032 tmp |= sbr & UARTBAUD_SBR_MASK;
2035 tmp &= ~UARTBAUD_RDMAE;
2037 tmp &= ~UARTBAUD_TDMAE;
2039 lpuart32_write(port, tmp, UARTBAUD);
2042 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2043 unsigned int baudrate)
2045 __lpuart32_serial_setbrg(&sport->port, baudrate,
2046 sport->lpuart_dma_rx_use,
2047 sport->lpuart_dma_tx_use);
2052 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2053 struct ktermios *old)
2055 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2056 unsigned long flags;
2057 unsigned long ctrl, old_ctrl, modem;
2059 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2061 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2062 modem = lpuart32_read(&sport->port, UARTMODIR);
2064 * only support CS8 and CS7, and for CS7 must enable PE.
2071 while ((termios->c_cflag & CSIZE) != CS8 &&
2072 (termios->c_cflag & CSIZE) != CS7) {
2073 termios->c_cflag &= ~CSIZE;
2074 termios->c_cflag |= old_csize;
2078 if ((termios->c_cflag & CSIZE) == CS8 ||
2079 (termios->c_cflag & CSIZE) == CS7)
2080 ctrl = old_ctrl & ~UARTCTRL_M;
2082 if (termios->c_cflag & CMSPAR) {
2083 if ((termios->c_cflag & CSIZE) != CS8) {
2084 termios->c_cflag &= ~CSIZE;
2085 termios->c_cflag |= CS8;
2091 * When auto RS-485 RTS mode is enabled,
2092 * hardware flow control need to be disabled.
2094 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2095 termios->c_cflag &= ~CRTSCTS;
2097 if (termios->c_cflag & CRTSCTS) {
2098 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2100 termios->c_cflag &= ~CRTSCTS;
2101 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2104 if (termios->c_cflag & CSTOPB)
2105 termios->c_cflag &= ~CSTOPB;
2107 /* parity must be enabled when CS7 to match 8-bits format */
2108 if ((termios->c_cflag & CSIZE) == CS7)
2109 termios->c_cflag |= PARENB;
2111 if ((termios->c_cflag & PARENB)) {
2112 if (termios->c_cflag & CMSPAR) {
2113 ctrl &= ~UARTCTRL_PE;
2116 ctrl |= UARTCTRL_PE;
2117 if ((termios->c_cflag & CSIZE) == CS8)
2119 if (termios->c_cflag & PARODD)
2120 ctrl |= UARTCTRL_PT;
2122 ctrl &= ~UARTCTRL_PT;
2125 ctrl &= ~UARTCTRL_PE;
2128 /* ask the core to calculate the divisor */
2129 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2132 * Need to update the Ring buffer length according to the selected
2133 * baud rate and restart Rx DMA path.
2135 * Since timer function acqures sport->port.lock, need to stop before
2136 * acquring same lock because otherwise del_timer_sync() can deadlock.
2138 if (old && sport->lpuart_dma_rx_use)
2139 lpuart_dma_rx_free(&sport->port);
2141 spin_lock_irqsave(&sport->port.lock, flags);
2143 sport->port.read_status_mask = 0;
2144 if (termios->c_iflag & INPCK)
2145 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2146 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2147 sport->port.read_status_mask |= UARTSTAT_FE;
2149 /* characters to ignore */
2150 sport->port.ignore_status_mask = 0;
2151 if (termios->c_iflag & IGNPAR)
2152 sport->port.ignore_status_mask |= UARTSTAT_PE;
2153 if (termios->c_iflag & IGNBRK) {
2154 sport->port.ignore_status_mask |= UARTSTAT_FE;
2156 * if we're ignoring parity and break indicators,
2157 * ignore overruns too (for real raw support).
2159 if (termios->c_iflag & IGNPAR)
2160 sport->port.ignore_status_mask |= UARTSTAT_OR;
2163 /* update the per-port timeout */
2164 uart_update_timeout(port, termios->c_cflag, baud);
2167 * LPUART Transmission Complete Flag may never be set while queuing a break
2168 * character, so skip waiting for transmission complete when UARTCTRL_SBK is
2171 if (!(old_ctrl & UARTCTRL_SBK)) {
2172 lpuart32_write(&sport->port, 0, UARTMODIR);
2173 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2176 /* disable transmit and receive */
2177 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2180 lpuart32_serial_setbrg(sport, baud);
2181 /* disable CTS before enabling UARTCTRL_TE to avoid pending idle preamble */
2182 lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);
2183 /* restore control register */
2184 lpuart32_write(&sport->port, ctrl, UARTCTRL);
2185 /* re-enable the CTS if needed */
2186 lpuart32_write(&sport->port, modem, UARTMODIR);
2188 if (old && sport->lpuart_dma_rx_use) {
2189 if (!lpuart_start_rx_dma(sport))
2190 rx_dma_timer_init(sport);
2192 sport->lpuart_dma_rx_use = false;
2195 spin_unlock_irqrestore(&sport->port.lock, flags);
2198 static const char *lpuart_type(struct uart_port *port)
2200 return "FSL_LPUART";
2203 static void lpuart_release_port(struct uart_port *port)
2208 static int lpuart_request_port(struct uart_port *port)
2213 /* configure/autoconfigure the port */
2214 static void lpuart_config_port(struct uart_port *port, int flags)
2216 if (flags & UART_CONFIG_TYPE)
2217 port->type = PORT_LPUART;
2220 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2224 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2226 if (port->irq != ser->irq)
2228 if (ser->io_type != UPIO_MEM)
2230 if (port->uartclk / 16 != ser->baud_base)
2232 if (port->iobase != ser->port)
2239 static const struct uart_ops lpuart_pops = {
2240 .tx_empty = lpuart_tx_empty,
2241 .set_mctrl = lpuart_set_mctrl,
2242 .get_mctrl = lpuart_get_mctrl,
2243 .stop_tx = lpuart_stop_tx,
2244 .start_tx = lpuart_start_tx,
2245 .stop_rx = lpuart_stop_rx,
2246 .break_ctl = lpuart_break_ctl,
2247 .startup = lpuart_startup,
2248 .shutdown = lpuart_shutdown,
2249 .set_termios = lpuart_set_termios,
2250 .type = lpuart_type,
2251 .request_port = lpuart_request_port,
2252 .release_port = lpuart_release_port,
2253 .config_port = lpuart_config_port,
2254 .verify_port = lpuart_verify_port,
2255 .flush_buffer = lpuart_flush_buffer,
2256 #if defined(CONFIG_CONSOLE_POLL)
2257 .poll_init = lpuart_poll_init,
2258 .poll_get_char = lpuart_poll_get_char,
2259 .poll_put_char = lpuart_poll_put_char,
2263 static const struct uart_ops lpuart32_pops = {
2264 .tx_empty = lpuart32_tx_empty,
2265 .set_mctrl = lpuart32_set_mctrl,
2266 .get_mctrl = lpuart32_get_mctrl,
2267 .stop_tx = lpuart32_stop_tx,
2268 .start_tx = lpuart32_start_tx,
2269 .stop_rx = lpuart32_stop_rx,
2270 .break_ctl = lpuart32_break_ctl,
2271 .startup = lpuart32_startup,
2272 .shutdown = lpuart32_shutdown,
2273 .set_termios = lpuart32_set_termios,
2274 .type = lpuart_type,
2275 .request_port = lpuart_request_port,
2276 .release_port = lpuart_release_port,
2277 .config_port = lpuart_config_port,
2278 .verify_port = lpuart_verify_port,
2279 .flush_buffer = lpuart_flush_buffer,
2280 #if defined(CONFIG_CONSOLE_POLL)
2281 .poll_init = lpuart32_poll_init,
2282 .poll_get_char = lpuart32_poll_get_char,
2283 .poll_put_char = lpuart32_poll_put_char,
2287 static struct lpuart_port *lpuart_ports[UART_NR];
2289 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2290 static void lpuart_console_putchar(struct uart_port *port, int ch)
2292 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2293 writeb(ch, port->membase + UARTDR);
2296 static void lpuart32_console_putchar(struct uart_port *port, int ch)
2298 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2299 lpuart32_write(port, ch, UARTDATA);
2303 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2305 struct lpuart_port *sport = lpuart_ports[co->index];
2306 unsigned char old_cr2, cr2;
2307 unsigned long flags;
2310 if (sport->port.sysrq || oops_in_progress)
2311 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2313 spin_lock_irqsave(&sport->port.lock, flags);
2315 /* first save CR2 and then disable interrupts */
2316 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2317 cr2 |= UARTCR2_TE | UARTCR2_RE;
2318 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2319 writeb(cr2, sport->port.membase + UARTCR2);
2321 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2323 /* wait for transmitter finish complete and restore CR2 */
2324 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2326 writeb(old_cr2, sport->port.membase + UARTCR2);
2329 spin_unlock_irqrestore(&sport->port.lock, flags);
2333 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2335 struct lpuart_port *sport = lpuart_ports[co->index];
2336 unsigned long old_cr, cr;
2337 unsigned long flags;
2340 if (sport->port.sysrq || oops_in_progress)
2341 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2343 spin_lock_irqsave(&sport->port.lock, flags);
2345 /* first save CR2 and then disable interrupts */
2346 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2347 cr |= UARTCTRL_TE | UARTCTRL_RE;
2348 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2349 lpuart32_write(&sport->port, cr, UARTCTRL);
2351 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2353 /* wait for transmitter finish complete and restore CR2 */
2354 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2356 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2359 spin_unlock_irqrestore(&sport->port.lock, flags);
2363 * if the port was already initialised (eg, by a boot loader),
2364 * try to determine the current setup.
2367 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2368 int *parity, int *bits)
2370 unsigned char cr, bdh, bdl, brfa;
2371 unsigned int sbr, uartclk, baud_raw;
2373 cr = readb(sport->port.membase + UARTCR2);
2374 cr &= UARTCR2_TE | UARTCR2_RE;
2378 /* ok, the port was enabled */
2380 cr = readb(sport->port.membase + UARTCR1);
2383 if (cr & UARTCR1_PE) {
2384 if (cr & UARTCR1_PT)
2395 bdh = readb(sport->port.membase + UARTBDH);
2396 bdh &= UARTBDH_SBR_MASK;
2397 bdl = readb(sport->port.membase + UARTBDL);
2401 brfa = readb(sport->port.membase + UARTCR4);
2402 brfa &= UARTCR4_BRFA_MASK;
2404 uartclk = lpuart_get_baud_clk_rate(sport);
2406 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2408 baud_raw = uartclk / (16 * (sbr + brfa / 32));
2410 if (*baud != baud_raw)
2411 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2412 "from %d to %d\n", baud_raw, *baud);
2416 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2417 int *parity, int *bits)
2419 unsigned long cr, bd;
2420 unsigned int sbr, uartclk, baud_raw;
2422 cr = lpuart32_read(&sport->port, UARTCTRL);
2423 cr &= UARTCTRL_TE | UARTCTRL_RE;
2427 /* ok, the port was enabled */
2429 cr = lpuart32_read(&sport->port, UARTCTRL);
2432 if (cr & UARTCTRL_PE) {
2433 if (cr & UARTCTRL_PT)
2439 if (cr & UARTCTRL_M)
2444 bd = lpuart32_read(&sport->port, UARTBAUD);
2445 bd &= UARTBAUD_SBR_MASK;
2450 uartclk = lpuart_get_baud_clk_rate(sport);
2452 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2454 baud_raw = uartclk / (16 * sbr);
2456 if (*baud != baud_raw)
2457 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2458 "from %d to %d\n", baud_raw, *baud);
2461 static int __init lpuart_console_setup(struct console *co, char *options)
2463 struct lpuart_port *sport;
2470 * check whether an invalid uart number has been specified, and
2471 * if so, search for the first available port that does have
2474 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2477 sport = lpuart_ports[co->index];
2482 uart_parse_options(options, &baud, &parity, &bits, &flow);
2484 if (lpuart_is_32(sport))
2485 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2487 lpuart_console_get_options(sport, &baud, &parity, &bits);
2489 if (lpuart_is_32(sport))
2490 lpuart32_setup_watermark(sport);
2492 lpuart_setup_watermark(sport);
2494 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2497 static struct uart_driver lpuart_reg;
2498 static struct console lpuart_console = {
2500 .write = lpuart_console_write,
2501 .device = uart_console_device,
2502 .setup = lpuart_console_setup,
2503 .flags = CON_PRINTBUFFER,
2505 .data = &lpuart_reg,
2508 static struct console lpuart32_console = {
2510 .write = lpuart32_console_write,
2511 .device = uart_console_device,
2512 .setup = lpuart_console_setup,
2513 .flags = CON_PRINTBUFFER,
2515 .data = &lpuart_reg,
2518 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2520 struct earlycon_device *dev = con->data;
2522 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2525 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2527 struct earlycon_device *dev = con->data;
2529 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2532 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2535 if (!device->port.membase)
2538 device->con->write = lpuart_early_write;
2542 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2545 if (!device->port.membase)
2548 if (device->port.iotype != UPIO_MEM32)
2549 device->port.iotype = UPIO_MEM32BE;
2551 device->con->write = lpuart32_early_write;
2555 static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2560 if (!device->port.membase)
2563 device->port.iotype = UPIO_MEM32;
2564 device->con->write = lpuart32_early_write;
2566 /* set the baudrate */
2567 if (device->port.uartclk && device->baud)
2568 __lpuart32_serial_setbrg(&device->port, device->baud,
2571 /* enable transmitter */
2572 cr = lpuart32_read(&device->port, UARTCTRL);
2574 lpuart32_write(&device->port, cr, UARTCTRL);
2579 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2582 if (!device->port.membase)
2585 device->port.iotype = UPIO_MEM32;
2586 device->port.membase += IMX_REG_OFF;
2587 device->con->write = lpuart32_early_write;
2591 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2592 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2593 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2594 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2595 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
2596 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2597 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2598 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2600 #define LPUART_CONSOLE (&lpuart_console)
2601 #define LPUART32_CONSOLE (&lpuart32_console)
2603 #define LPUART_CONSOLE NULL
2604 #define LPUART32_CONSOLE NULL
2607 static struct uart_driver lpuart_reg = {
2608 .owner = THIS_MODULE,
2609 .driver_name = DRIVER_NAME,
2610 .dev_name = DEV_NAME,
2611 .nr = ARRAY_SIZE(lpuart_ports),
2612 .cons = LPUART_CONSOLE,
2615 static int lpuart_probe(struct platform_device *pdev)
2617 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2619 const struct lpuart_soc_data *sdata = of_id->data;
2620 struct device_node *np = pdev->dev.of_node;
2621 struct lpuart_port *sport;
2622 struct resource *res;
2623 irq_handler_t handler;
2626 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2630 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2631 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2632 if (IS_ERR(sport->port.membase))
2633 return PTR_ERR(sport->port.membase);
2635 sport->port.membase += sdata->reg_off;
2636 sport->port.mapbase = res->start + sdata->reg_off;
2637 sport->port.dev = &pdev->dev;
2638 sport->port.type = PORT_LPUART;
2639 sport->devtype = sdata->devtype;
2640 ret = platform_get_irq(pdev, 0);
2643 sport->port.irq = ret;
2644 sport->port.iotype = sdata->iotype;
2645 if (lpuart_is_32(sport))
2646 sport->port.ops = &lpuart32_pops;
2648 sport->port.ops = &lpuart_pops;
2649 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2650 sport->port.flags = UPF_BOOT_AUTOCONF;
2652 if (lpuart_is_32(sport))
2653 sport->port.rs485_config = lpuart32_config_rs485;
2655 sport->port.rs485_config = lpuart_config_rs485;
2657 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2658 if (IS_ERR(sport->ipg_clk)) {
2659 ret = PTR_ERR(sport->ipg_clk);
2660 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2664 sport->baud_clk = NULL;
2665 if (is_imx8qxp_lpuart(sport)) {
2666 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2667 if (IS_ERR(sport->baud_clk)) {
2668 ret = PTR_ERR(sport->baud_clk);
2669 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2674 ret = of_alias_get_id(np, "serial");
2676 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2679 if (ret >= ARRAY_SIZE(lpuart_ports)) {
2680 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2683 sport->port.line = ret;
2685 ret = lpuart_enable_clks(sport);
2688 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2690 lpuart_ports[sport->port.line] = sport;
2692 platform_set_drvdata(pdev, &sport->port);
2694 if (lpuart_is_32(sport)) {
2695 lpuart_reg.cons = LPUART32_CONSOLE;
2696 handler = lpuart32_int;
2698 lpuart_reg.cons = LPUART_CONSOLE;
2699 handler = lpuart_int;
2702 ret = uart_get_rs485_mode(&sport->port);
2704 goto failed_get_rs485;
2706 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2707 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2709 if (sport->port.rs485.delay_rts_before_send ||
2710 sport->port.rs485.delay_rts_after_send)
2711 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2713 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2715 goto failed_attach_port;
2717 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2718 DRIVER_NAME, sport);
2720 goto failed_irq_request;
2725 uart_remove_one_port(&lpuart_reg, &sport->port);
2728 lpuart_disable_clks(sport);
2732 static int lpuart_remove(struct platform_device *pdev)
2734 struct lpuart_port *sport = platform_get_drvdata(pdev);
2736 uart_remove_one_port(&lpuart_reg, &sport->port);
2738 lpuart_disable_clks(sport);
2740 if (sport->dma_tx_chan)
2741 dma_release_channel(sport->dma_tx_chan);
2743 if (sport->dma_rx_chan)
2744 dma_release_channel(sport->dma_rx_chan);
2749 static int __maybe_unused lpuart_suspend(struct device *dev)
2751 struct lpuart_port *sport = dev_get_drvdata(dev);
2755 if (lpuart_is_32(sport)) {
2756 /* disable Rx/Tx and interrupts */
2757 temp = lpuart32_read(&sport->port, UARTCTRL);
2758 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2759 lpuart32_write(&sport->port, temp, UARTCTRL);
2761 /* disable Rx/Tx and interrupts */
2762 temp = readb(sport->port.membase + UARTCR2);
2763 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2764 writeb(temp, sport->port.membase + UARTCR2);
2767 uart_suspend_port(&lpuart_reg, &sport->port);
2769 /* uart_suspend_port() might set wakeup flag */
2770 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2772 if (sport->lpuart_dma_rx_use) {
2774 * EDMA driver during suspend will forcefully release any
2775 * non-idle DMA channels. If port wakeup is enabled or if port
2776 * is console port or 'no_console_suspend' is set the Rx DMA
2777 * cannot resume as expected, hence gracefully release the
2778 * Rx DMA path before suspend and start Rx DMA path on resume.
2781 lpuart_dma_rx_free(&sport->port);
2784 /* Disable Rx DMA to use UART port as wakeup source */
2785 if (lpuart_is_32(sport)) {
2786 temp = lpuart32_read(&sport->port, UARTBAUD);
2787 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2790 writeb(readb(sport->port.membase + UARTCR5) &
2791 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2795 if (sport->lpuart_dma_tx_use) {
2796 sport->dma_tx_in_progress = false;
2797 dmaengine_terminate_all(sport->dma_tx_chan);
2800 if (sport->port.suspended && !irq_wake)
2801 lpuart_disable_clks(sport);
2806 static int __maybe_unused lpuart_resume(struct device *dev)
2808 struct lpuart_port *sport = dev_get_drvdata(dev);
2809 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2811 if (sport->port.suspended && !irq_wake)
2812 lpuart_enable_clks(sport);
2814 if (lpuart_is_32(sport))
2815 lpuart32_setup_watermark_enable(sport);
2817 lpuart_setup_watermark_enable(sport);
2819 if (sport->lpuart_dma_rx_use) {
2821 if (!lpuart_start_rx_dma(sport))
2822 rx_dma_timer_init(sport);
2824 sport->lpuart_dma_rx_use = false;
2828 lpuart_tx_dma_startup(sport);
2830 if (lpuart_is_32(sport))
2831 lpuart32_configure(sport);
2833 uart_resume_port(&lpuart_reg, &sport->port);
2838 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2840 static struct platform_driver lpuart_driver = {
2841 .probe = lpuart_probe,
2842 .remove = lpuart_remove,
2844 .name = "fsl-lpuart",
2845 .of_match_table = lpuart_dt_ids,
2846 .pm = &lpuart_pm_ops,
2850 static int __init lpuart_serial_init(void)
2852 int ret = uart_register_driver(&lpuart_reg);
2857 ret = platform_driver_register(&lpuart_driver);
2859 uart_unregister_driver(&lpuart_reg);
2864 static void __exit lpuart_serial_exit(void)
2866 platform_driver_unregister(&lpuart_driver);
2867 uart_unregister_driver(&lpuart_reg);
2870 module_init(lpuart_serial_init);
2871 module_exit(lpuart_serial_exit);
2873 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2874 MODULE_LICENSE("GPL v2");