drivers/tty/serial/fsl_lpuart.c

   1 /*
   2  *  Freescale lpuart serial port driver
   3  *
   4  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15
  16 #include <linux/clk.h>
  17 #include <linux/console.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_dma.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/slab.h>
  29 #include <linux/tty_flip.h>
  30
  31 /* All registers are 8-bit width */
  32 #define UARTBDH                 0x00
  33 #define UARTBDL                 0x01
  34 #define UARTCR1                 0x02
  35 #define UARTCR2                 0x03
  36 #define UARTSR1                 0x04
  37 #define UARTCR3                 0x06
  38 #define UARTDR                  0x07
  39 #define UARTCR4                 0x0a
  40 #define UARTCR5                 0x0b
  41 #define UARTMODEM               0x0d
  42 #define UARTPFIFO               0x10
  43 #define UARTCFIFO               0x11
  44 #define UARTSFIFO               0x12
  45 #define UARTTWFIFO              0x13
  46 #define UARTTCFIFO              0x14
  47 #define UARTRWFIFO              0x15
  48
  49 #define UARTBDH_LBKDIE          0x80
  50 #define UARTBDH_RXEDGIE         0x40
  51 #define UARTBDH_SBR_MASK        0x1f
  52
  53 #define UARTCR1_LOOPS           0x80
  54 #define UARTCR1_RSRC            0x20
  55 #define UARTCR1_M               0x10
  56 #define UARTCR1_WAKE            0x08
  57 #define UARTCR1_ILT             0x04
  58 #define UARTCR1_PE              0x02
  59 #define UARTCR1_PT              0x01
  60
  61 #define UARTCR2_TIE             0x80
  62 #define UARTCR2_TCIE            0x40
  63 #define UARTCR2_RIE             0x20
  64 #define UARTCR2_ILIE            0x10
  65 #define UARTCR2_TE              0x08
  66 #define UARTCR2_RE              0x04
  67 #define UARTCR2_RWU             0x02
  68 #define UARTCR2_SBK             0x01
  69
  70 #define UARTSR1_TDRE            0x80
  71 #define UARTSR1_TC              0x40
  72 #define UARTSR1_RDRF            0x20
  73 #define UARTSR1_IDLE            0x10
  74 #define UARTSR1_OR              0x08
  75 #define UARTSR1_NF              0x04
  76 #define UARTSR1_FE              0x02
  77 #define UARTSR1_PE              0x01
  78
  79 #define UARTCR3_R8              0x80
  80 #define UARTCR3_T8              0x40
  81 #define UARTCR3_TXDIR           0x20
  82 #define UARTCR3_TXINV           0x10
  83 #define UARTCR3_ORIE            0x08
  84 #define UARTCR3_NEIE            0x04
  85 #define UARTCR3_FEIE            0x02
  86 #define UARTCR3_PEIE            0x01
  87
  88 #define UARTCR4_MAEN1           0x80
  89 #define UARTCR4_MAEN2           0x40
  90 #define UARTCR4_M10             0x20
  91 #define UARTCR4_BRFA_MASK       0x1f
  92 #define UARTCR4_BRFA_OFF        0
  93
  94 #define UARTCR5_TDMAS           0x80
  95 #define UARTCR5_RDMAS           0x20
  96
  97 #define UARTMODEM_RXRTSE        0x08
  98 #define UARTMODEM_TXRTSPOL      0x04
  99 #define UARTMODEM_TXRTSE        0x02
 100 #define UARTMODEM_TXCTSE        0x01
 101
 102 #define UARTPFIFO_TXFE          0x80
 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 104 #define UARTPFIFO_TXSIZE_OFF    4
 105 #define UARTPFIFO_RXFE          0x08
 106 #define UARTPFIFO_RXSIZE_OFF    0
 107
 108 #define UARTCFIFO_TXFLUSH       0x80
 109 #define UARTCFIFO_RXFLUSH       0x40
 110 #define UARTCFIFO_RXOFE         0x04
 111 #define UARTCFIFO_TXOFE         0x02
 112 #define UARTCFIFO_RXUFE         0x01
 113
 114 #define UARTSFIFO_TXEMPT        0x80
 115 #define UARTSFIFO_RXEMPT        0x40
 116 #define UARTSFIFO_RXOF          0x04
 117 #define UARTSFIFO_TXOF          0x02
 118 #define UARTSFIFO_RXUF          0x01
 119
 120 /* 32-bit register defination */
 121 #define UARTBAUD                0x00
 122 #define UARTSTAT                0x04
 123 #define UARTCTRL                0x08
 124 #define UARTDATA                0x0C
 125 #define UARTMATCH               0x10
 126 #define UARTMODIR               0x14
 127 #define UARTFIFO                0x18
 128 #define UARTWATER               0x1c
 129
 130 #define UARTBAUD_MAEN1          0x80000000
 131 #define UARTBAUD_MAEN2          0x40000000
 132 #define UARTBAUD_M10            0x20000000
 133 #define UARTBAUD_TDMAE          0x00800000
 134 #define UARTBAUD_RDMAE          0x00200000
 135 #define UARTBAUD_MATCFG         0x00400000
 136 #define UARTBAUD_BOTHEDGE       0x00020000
 137 #define UARTBAUD_RESYNCDIS      0x00010000
 138 #define UARTBAUD_LBKDIE         0x00008000
 139 #define UARTBAUD_RXEDGIE        0x00004000
 140 #define UARTBAUD_SBNS           0x00002000
 141 #define UARTBAUD_SBR            0x00000000
 142 #define UARTBAUD_SBR_MASK       0x1fff
 143
 144 #define UARTSTAT_LBKDIF         0x80000000
 145 #define UARTSTAT_RXEDGIF        0x40000000
 146 #define UARTSTAT_MSBF           0x20000000
 147 #define UARTSTAT_RXINV          0x10000000
 148 #define UARTSTAT_RWUID          0x08000000
 149 #define UARTSTAT_BRK13          0x04000000
 150 #define UARTSTAT_LBKDE          0x02000000
 151 #define UARTSTAT_RAF            0x01000000
 152 #define UARTSTAT_TDRE           0x00800000
 153 #define UARTSTAT_TC             0x00400000
 154 #define UARTSTAT_RDRF           0x00200000
 155 #define UARTSTAT_IDLE           0x00100000
 156 #define UARTSTAT_OR             0x00080000
 157 #define UARTSTAT_NF             0x00040000
 158 #define UARTSTAT_FE             0x00020000
 159 #define UARTSTAT_PE             0x00010000
 160 #define UARTSTAT_MA1F           0x00008000
 161 #define UARTSTAT_M21F           0x00004000
 162
 163 #define UARTCTRL_R8T9           0x80000000
 164 #define UARTCTRL_R9T8           0x40000000
 165 #define UARTCTRL_TXDIR          0x20000000
 166 #define UARTCTRL_TXINV          0x10000000
 167 #define UARTCTRL_ORIE           0x08000000
 168 #define UARTCTRL_NEIE           0x04000000
 169 #define UARTCTRL_FEIE           0x02000000
 170 #define UARTCTRL_PEIE           0x01000000
 171 #define UARTCTRL_TIE            0x00800000
 172 #define UARTCTRL_TCIE           0x00400000
 173 #define UARTCTRL_RIE            0x00200000
 174 #define UARTCTRL_ILIE           0x00100000
 175 #define UARTCTRL_TE             0x00080000
 176 #define UARTCTRL_RE             0x00040000
 177 #define UARTCTRL_RWU            0x00020000
 178 #define UARTCTRL_SBK            0x00010000
 179 #define UARTCTRL_MA1IE          0x00008000
 180 #define UARTCTRL_MA2IE          0x00004000
 181 #define UARTCTRL_IDLECFG        0x00000100
 182 #define UARTCTRL_LOOPS          0x00000080
 183 #define UARTCTRL_DOZEEN         0x00000040
 184 #define UARTCTRL_RSRC           0x00000020
 185 #define UARTCTRL_M              0x00000010
 186 #define UARTCTRL_WAKE           0x00000008
 187 #define UARTCTRL_ILT            0x00000004
 188 #define UARTCTRL_PE             0x00000002
 189 #define UARTCTRL_PT             0x00000001
 190
 191 #define UARTDATA_NOISY          0x00008000
 192 #define UARTDATA_PARITYE        0x00004000
 193 #define UARTDATA_FRETSC         0x00002000
 194 #define UARTDATA_RXEMPT         0x00001000
 195 #define UARTDATA_IDLINE         0x00000800
 196 #define UARTDATA_MASK           0x3ff
 197
 198 #define UARTMODIR_IREN          0x00020000
 199 #define UARTMODIR_TXCTSSRC      0x00000020
 200 #define UARTMODIR_TXCTSC        0x00000010
 201 #define UARTMODIR_RXRTSE        0x00000008
 202 #define UARTMODIR_TXRTSPOL      0x00000004
 203 #define UARTMODIR_TXRTSE        0x00000002
 204 #define UARTMODIR_TXCTSE        0x00000001
 205
 206 #define UARTFIFO_TXEMPT         0x00800000
 207 #define UARTFIFO_RXEMPT         0x00400000
 208 #define UARTFIFO_TXOF           0x00020000
 209 #define UARTFIFO_RXUF           0x00010000
 210 #define UARTFIFO_TXFLUSH        0x00008000
 211 #define UARTFIFO_RXFLUSH        0x00004000
 212 #define UARTFIFO_TXOFE          0x00000200
 213 #define UARTFIFO_RXUFE          0x00000100
 214 #define UARTFIFO_TXFE           0x00000080
 215 #define UARTFIFO_FIFOSIZE_MASK  0x7
 216 #define UARTFIFO_TXSIZE_OFF     4
 217 #define UARTFIFO_RXFE           0x00000008
 218 #define UARTFIFO_RXSIZE_OFF     0
 219
 220 #define UARTWATER_COUNT_MASK    0xff
 221 #define UARTWATER_TXCNT_OFF     8
 222 #define UARTWATER_RXCNT_OFF     24
 223 #define UARTWATER_WATER_MASK    0xff
 224 #define UARTWATER_TXWATER_OFF   0
 225 #define UARTWATER_RXWATER_OFF   16
 226
 227 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 228 #define DMA_RX_TIMEOUT          (10)
 229
 230 #define DRIVER_NAME     "fsl-lpuart"
 231 #define DEV_NAME        "ttyLP"
 232 #define UART_NR         6
 233
 234 struct lpuart_port {
 235         struct uart_port        port;
 236         struct clk              *clk;
 237         unsigned int            txfifo_size;
 238         unsigned int            rxfifo_size;
 239         bool                    lpuart32;
 240
 241         bool                    lpuart_dma_tx_use;
 242         bool                    lpuart_dma_rx_use;
 243         struct dma_chan         *dma_tx_chan;
 244         struct dma_chan         *dma_rx_chan;
 245         struct dma_async_tx_descriptor  *dma_tx_desc;
 246         struct dma_async_tx_descriptor  *dma_rx_desc;
 247         dma_cookie_t            dma_tx_cookie;
 248         dma_cookie_t            dma_rx_cookie;
 249         unsigned int            dma_tx_bytes;
 250         unsigned int            dma_rx_bytes;
 251         bool                    dma_tx_in_progress;
 252         unsigned int            dma_rx_timeout;
 253         struct timer_list       lpuart_timer;
 254         struct scatterlist      rx_sgl, tx_sgl[2];
 255         struct circ_buf         rx_ring;
 256         int                     rx_dma_rng_buf_len;
 257         unsigned int            dma_tx_nents;
 258         wait_queue_head_t       dma_wait;
 259 };
 260
 261 static const struct of_device_id lpuart_dt_ids[] = {
 262         {
 263                 .compatible = "fsl,vf610-lpuart",
 264         },
 265         {
 266                 .compatible = "fsl,ls1021a-lpuart",
 267         },
 268         { /* sentinel */ }
 269 };
 270 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 271
 272 /* Forward declare this for the dma callbacks*/
 273 static void lpuart_dma_tx_complete(void *arg);
 274
 275 static u32 lpuart32_read(void __iomem *addr)
 276 {
 277         return ioread32be(addr);
 278 }
 279
 280 static void lpuart32_write(u32 val, void __iomem *addr)
 281 {
 282         iowrite32be(val, addr);
 283 }
 284
 285 static void lpuart_stop_tx(struct uart_port *port)
 286 {
 287         unsigned char temp;
 288
 289         temp = readb(port->membase + UARTCR2);
 290         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 291         writeb(temp, port->membase + UARTCR2);
 292 }
 293
 294 static void lpuart32_stop_tx(struct uart_port *port)
 295 {
 296         unsigned long temp;
 297
 298         temp = lpuart32_read(port->membase + UARTCTRL);
 299         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 300         lpuart32_write(temp, port->membase + UARTCTRL);
 301 }
 302
 303 static void lpuart_stop_rx(struct uart_port *port)
 304 {
 305         unsigned char temp;
 306
 307         temp = readb(port->membase + UARTCR2);
 308         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 309 }
 310
 311 static void lpuart32_stop_rx(struct uart_port *port)
 312 {
 313         unsigned long temp;
 314
 315         temp = lpuart32_read(port->membase + UARTCTRL);
 316         lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
 317 }
 318
 319 static void lpuart_dma_tx(struct lpuart_port *sport)
 320 {
 321         struct circ_buf *xmit = &sport->port.state->xmit;
 322         struct scatterlist *sgl = sport->tx_sgl;
 323         struct device *dev = sport->port.dev;
 324         int ret;
 325
 326         if (sport->dma_tx_in_progress)
 327                 return;
 328
 329         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 330
 331         if (xmit->tail < xmit->head || xmit->head == 0) {
 332                 sport->dma_tx_nents = 1;
 333                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 334         } else {
 335                 sport->dma_tx_nents = 2;
 336                 sg_init_table(sgl, 2);
 337                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 338                                 UART_XMIT_SIZE - xmit->tail);
 339                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 340         }
 341
 342         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 343         if (!ret) {
 344                 dev_err(dev, "DMA mapping error for TX.\n");
 345                 return;
 346         }
 347
 348         sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
 349                                         ret, DMA_MEM_TO_DEV,
 350                                         DMA_PREP_INTERRUPT);
 351         if (!sport->dma_tx_desc) {
 352                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 353                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 354                 return;
 355         }
 356
 357         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 358         sport->dma_tx_desc->callback_param = sport;
 359         sport->dma_tx_in_progress = true;
 360         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 361         dma_async_issue_pending(sport->dma_tx_chan);
 362 }
 363
 364 static void lpuart_dma_tx_complete(void *arg)
 365 {
 366         struct lpuart_port *sport = arg;
 367         struct scatterlist *sgl = &sport->tx_sgl[0];
 368         struct circ_buf *xmit = &sport->port.state->xmit;
 369         unsigned long flags;
 370
 371         spin_lock_irqsave(&sport->port.lock, flags);
 372
 373         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 374
 375         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 376
 377         sport->port.icount.tx += sport->dma_tx_bytes;
 378         sport->dma_tx_in_progress = false;
 379         spin_unlock_irqrestore(&sport->port.lock, flags);
 380
 381         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 382                 uart_write_wakeup(&sport->port);
 383
 384         if (waitqueue_active(&sport->dma_wait)) {
 385                 wake_up(&sport->dma_wait);
 386                 return;
 387         }
 388
 389         spin_lock_irqsave(&sport->port.lock, flags);
 390
 391         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 392                 lpuart_dma_tx(sport);
 393
 394         spin_unlock_irqrestore(&sport->port.lock, flags);
 395 }
 396
 397 static int lpuart_dma_tx_request(struct uart_port *port)
 398 {
 399         struct lpuart_port *sport = container_of(port,
 400                                         struct lpuart_port, port);
 401         struct dma_slave_config dma_tx_sconfig = {};
 402         int ret;
 403
 404         dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
 405         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 406         dma_tx_sconfig.dst_maxburst = 1;
 407         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 408         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 409
 410         if (ret) {
 411                 dev_err(sport->port.dev,
 412                                 "DMA slave config failed, err = %d\n", ret);
 413                 return ret;
 414         }
 415
 416         return 0;
 417 }
 418
 419 static void lpuart_flush_buffer(struct uart_port *port)
 420 {
 421         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 422
 423         if (sport->lpuart_dma_tx_use) {
 424                 if (sport->dma_tx_in_progress) {
 425                         dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
 426                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 427                         sport->dma_tx_in_progress = false;
 428                 }
 429                 dmaengine_terminate_all(sport->dma_tx_chan);
 430         }
 431 }
 432
 433 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 434 {
 435         struct circ_buf *xmit = &sport->port.state->xmit;
 436
 437         while (!uart_circ_empty(xmit) &&
 438                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 439                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 440                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 441                 sport->port.icount.tx++;
 442         }
 443
 444         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 445                 uart_write_wakeup(&sport->port);
 446
 447         if (uart_circ_empty(xmit))
 448                 lpuart_stop_tx(&sport->port);
 449 }
 450
 451 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 452 {
 453         struct circ_buf *xmit = &sport->port.state->xmit;
 454         unsigned long txcnt;
 455
 456         txcnt = lpuart32_read(sport->port.membase + UARTWATER);
 457         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 458         txcnt &= UARTWATER_COUNT_MASK;
 459         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 460                 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
 461                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 462                 sport->port.icount.tx++;
 463                 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
 464                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 465                 txcnt &= UARTWATER_COUNT_MASK;
 466         }
 467
 468         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 469                 uart_write_wakeup(&sport->port);
 470
 471         if (uart_circ_empty(xmit))
 472                 lpuart32_stop_tx(&sport->port);
 473 }
 474
 475 static void lpuart_start_tx(struct uart_port *port)
 476 {
 477         struct lpuart_port *sport = container_of(port,
 478                         struct lpuart_port, port);
 479         struct circ_buf *xmit = &sport->port.state->xmit;
 480         unsigned char temp;
 481
 482         temp = readb(port->membase + UARTCR2);
 483         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 484
 485         if (sport->lpuart_dma_tx_use) {
 486                 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
 487                         lpuart_dma_tx(sport);
 488         } else {
 489                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 490                         lpuart_transmit_buffer(sport);
 491         }
 492 }
 493
 494 static void lpuart32_start_tx(struct uart_port *port)
 495 {
 496         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 497         unsigned long temp;
 498
 499         temp = lpuart32_read(port->membase + UARTCTRL);
 500         lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
 501
 502         if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
 503                 lpuart32_transmit_buffer(sport);
 504 }
 505
 506 /* return TIOCSER_TEMT when transmitter is not busy */
 507 static unsigned int lpuart_tx_empty(struct uart_port *port)
 508 {
 509         struct lpuart_port *sport = container_of(port,
 510                         struct lpuart_port, port);
 511         unsigned char sr1 = readb(port->membase + UARTSR1);
 512         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 513
 514         if (sport->dma_tx_in_progress)
 515                 return 0;
 516
 517         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 518                 return TIOCSER_TEMT;
 519
 520         return 0;
 521 }
 522
 523 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 524 {
 525         return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
 526                 TIOCSER_TEMT : 0;
 527 }
 528
 529 static irqreturn_t lpuart_txint(int irq, void *dev_id)
 530 {
 531         struct lpuart_port *sport = dev_id;
 532         struct circ_buf *xmit = &sport->port.state->xmit;
 533         unsigned long flags;
 534
 535         spin_lock_irqsave(&sport->port.lock, flags);
 536         if (sport->port.x_char) {
 537                 if (sport->lpuart32)
 538                         lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
 539                 else
 540                         writeb(sport->port.x_char, sport->port.membase + UARTDR);
 541                 goto out;
 542         }
 543
 544         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 545                 if (sport->lpuart32)
 546                         lpuart32_stop_tx(&sport->port);
 547                 else
 548                         lpuart_stop_tx(&sport->port);
 549                 goto out;
 550         }
 551
 552         if (sport->lpuart32)
 553                 lpuart32_transmit_buffer(sport);
 554         else
 555                 lpuart_transmit_buffer(sport);
 556
 557         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 558                 uart_write_wakeup(&sport->port);
 559
 560 out:
 561         spin_unlock_irqrestore(&sport->port.lock, flags);
 562         return IRQ_HANDLED;
 563 }
 564
 565 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
 566 {
 567         struct lpuart_port *sport = dev_id;
 568         unsigned int flg, ignored = 0;
 569         struct tty_port *port = &sport->port.state->port;
 570         unsigned long flags;
 571         unsigned char rx, sr;
 572
 573         spin_lock_irqsave(&sport->port.lock, flags);
 574
 575         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 576                 flg = TTY_NORMAL;
 577                 sport->port.icount.rx++;
 578                 /*
 579                  * to clear the FE, OR, NF, FE, PE flags,
 580                  * read SR1 then read DR
 581                  */
 582                 sr = readb(sport->port.membase + UARTSR1);
 583                 rx = readb(sport->port.membase + UARTDR);
 584
 585                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 586                         continue;
 587
 588                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 589                         if (sr & UARTSR1_PE)
 590                                 sport->port.icount.parity++;
 591                         else if (sr & UARTSR1_FE)
 592                                 sport->port.icount.frame++;
 593
 594                         if (sr & UARTSR1_OR)
 595                                 sport->port.icount.overrun++;
 596
 597                         if (sr & sport->port.ignore_status_mask) {
 598                                 if (++ignored > 100)
 599                                         goto out;
 600                                 continue;
 601                         }
 602
 603                         sr &= sport->port.read_status_mask;
 604
 605                         if (sr & UARTSR1_PE)
 606                                 flg = TTY_PARITY;
 607                         else if (sr & UARTSR1_FE)
 608                                 flg = TTY_FRAME;
 609
 610                         if (sr & UARTSR1_OR)
 611                                 flg = TTY_OVERRUN;
 612
 613 #ifdef SUPPORT_SYSRQ
 614                         sport->port.sysrq = 0;
 615 #endif
 616                 }
 617
 618                 tty_insert_flip_char(port, rx, flg);
 619         }
 620
 621 out:
 622         spin_unlock_irqrestore(&sport->port.lock, flags);
 623
 624         tty_flip_buffer_push(port);
 625         return IRQ_HANDLED;
 626 }
 627
 628 static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
 629 {
 630         struct lpuart_port *sport = dev_id;
 631         unsigned int flg, ignored = 0;
 632         struct tty_port *port = &sport->port.state->port;
 633         unsigned long flags;
 634         unsigned long rx, sr;
 635
 636         spin_lock_irqsave(&sport->port.lock, flags);
 637
 638         while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
 639                 flg = TTY_NORMAL;
 640                 sport->port.icount.rx++;
 641                 /*
 642                  * to clear the FE, OR, NF, FE, PE flags,
 643                  * read STAT then read DATA reg
 644                  */
 645                 sr = lpuart32_read(sport->port.membase + UARTSTAT);
 646                 rx = lpuart32_read(sport->port.membase + UARTDATA);
 647                 rx &= 0x3ff;
 648
 649                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 650                         continue;
 651
 652                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 653                         if (sr & UARTSTAT_PE)
 654                                 sport->port.icount.parity++;
 655                         else if (sr & UARTSTAT_FE)
 656                                 sport->port.icount.frame++;
 657
 658                         if (sr & UARTSTAT_OR)
 659                                 sport->port.icount.overrun++;
 660
 661                         if (sr & sport->port.ignore_status_mask) {
 662                                 if (++ignored > 100)
 663                                         goto out;
 664                                 continue;
 665                         }
 666
 667                         sr &= sport->port.read_status_mask;
 668
 669                         if (sr & UARTSTAT_PE)
 670                                 flg = TTY_PARITY;
 671                         else if (sr & UARTSTAT_FE)
 672                                 flg = TTY_FRAME;
 673
 674                         if (sr & UARTSTAT_OR)
 675                                 flg = TTY_OVERRUN;
 676
 677 #ifdef SUPPORT_SYSRQ
 678                         sport->port.sysrq = 0;
 679 #endif
 680                 }
 681
 682                 tty_insert_flip_char(port, rx, flg);
 683         }
 684
 685 out:
 686         spin_unlock_irqrestore(&sport->port.lock, flags);
 687
 688         tty_flip_buffer_push(port);
 689         return IRQ_HANDLED;
 690 }
 691
 692 static irqreturn_t lpuart_int(int irq, void *dev_id)
 693 {
 694         struct lpuart_port *sport = dev_id;
 695         unsigned char sts;
 696
 697         sts = readb(sport->port.membase + UARTSR1);
 698
 699         if (sts & UARTSR1_RDRF)
 700                 lpuart_rxint(irq, dev_id);
 701
 702         if (sts & UARTSR1_TDRE)
 703                 lpuart_txint(irq, dev_id);
 704
 705         return IRQ_HANDLED;
 706 }
 707
 708 static irqreturn_t lpuart32_int(int irq, void *dev_id)
 709 {
 710         struct lpuart_port *sport = dev_id;
 711         unsigned long sts, rxcount;
 712
 713         sts = lpuart32_read(sport->port.membase + UARTSTAT);
 714         rxcount = lpuart32_read(sport->port.membase + UARTWATER);
 715         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
 716
 717         if (sts & UARTSTAT_RDRF || rxcount > 0)
 718                 lpuart32_rxint(irq, dev_id);
 719
 720         if ((sts & UARTSTAT_TDRE) &&
 721                 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
 722                 lpuart_txint(irq, dev_id);
 723
 724         lpuart32_write(sts, sport->port.membase + UARTSTAT);
 725         return IRQ_HANDLED;
 726 }
 727
 728 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
 729 {
 730         struct tty_port *port = &sport->port.state->port;
 731         struct dma_tx_state state;
 732         enum dma_status dmastat;
 733         struct circ_buf *ring = &sport->rx_ring;
 734         unsigned long flags;
 735         int count = 0;
 736         unsigned char sr;
 737
 738         sr = readb(sport->port.membase + UARTSR1);
 739
 740         if (sr & (UARTSR1_PE | UARTSR1_FE)) {
 741                 /* Read DR to clear the error flags */
 742                 readb(sport->port.membase + UARTDR);
 743
 744                 if (sr & UARTSR1_PE)
 745                     sport->port.icount.parity++;
 746                 else if (sr & UARTSR1_FE)
 747                     sport->port.icount.frame++;
 748         }
 749
 750         async_tx_ack(sport->dma_rx_desc);
 751
 752         spin_lock_irqsave(&sport->port.lock, flags);
 753
 754         dmastat = dmaengine_tx_status(sport->dma_rx_chan,
 755                                 sport->dma_rx_cookie,
 756                                 &state);
 757
 758         if (dmastat == DMA_ERROR) {
 759                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
 760                 spin_unlock_irqrestore(&sport->port.lock, flags);
 761                 return;
 762         }
 763
 764         /* CPU claims ownership of RX DMA buffer */
 765         dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
 766
 767         /*
 768          * ring->head points to the end of data already written by the DMA.
 769          * ring->tail points to the beginning of data to be read by the
 770          * framework.
 771          * The current transfer size should not be larger than the dma buffer
 772          * length.
 773          */
 774         ring->head = sport->rx_sgl.length - state.residue;
 775         BUG_ON(ring->head > sport->rx_sgl.length);
 776         /*
 777          * At this point ring->head may point to the first byte right after the
 778          * last byte of the dma buffer:
 779          * 0 <= ring->head <= sport->rx_sgl.length
 780          *
 781          * However ring->tail must always points inside the dma buffer:
 782          * 0 <= ring->tail <= sport->rx_sgl.length - 1
 783          *
 784          * Since we use a ring buffer, we have to handle the case
 785          * where head is lower than tail. In such a case, we first read from
 786          * tail to the end of the buffer then reset tail.
 787          */
 788         if (ring->head < ring->tail) {
 789                 count = sport->rx_sgl.length - ring->tail;
 790
 791                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
 792                 ring->tail = 0;
 793                 sport->port.icount.rx += count;
 794         }
 795
 796         /* Finally we read data from tail to head */
 797         if (ring->tail < ring->head) {
 798                 count = ring->head - ring->tail;
 799                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
 800                 /* Wrap ring->head if needed */
 801                 if (ring->head >= sport->rx_sgl.length)
 802                         ring->head = 0;
 803                 ring->tail = ring->head;
 804                 sport->port.icount.rx += count;
 805         }
 806
 807         dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
 808                                DMA_FROM_DEVICE);
 809
 810         spin_unlock_irqrestore(&sport->port.lock, flags);
 811
 812         tty_flip_buffer_push(port);
 813         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
 814 }
 815
 816 static void lpuart_dma_rx_complete(void *arg)
 817 {
 818         struct lpuart_port *sport = arg;
 819
 820         lpuart_copy_rx_to_tty(sport);
 821 }
 822
 823 static void lpuart_timer_func(unsigned long data)
 824 {
 825         struct lpuart_port *sport = (struct lpuart_port *)data;
 826
 827         lpuart_copy_rx_to_tty(sport);
 828 }
 829
 830 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
 831 {
 832         struct dma_slave_config dma_rx_sconfig = {};
 833         struct circ_buf *ring = &sport->rx_ring;
 834         int ret, nent;
 835         int bits, baud;
 836         struct tty_port *port = &sport->port.state->port;
 837         struct tty_struct *tty = port->tty;
 838         struct ktermios *termios = &tty->termios;
 839
 840         baud = tty_get_baud_rate(tty);
 841
 842         bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
 843         if (termios->c_cflag & PARENB)
 844                 bits++;
 845
 846         /*
 847          * Calculate length of one DMA buffer size to keep latency below
 848          * 10ms at any baud rate.
 849          */
 850         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
 851         sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
 852         if (sport->rx_dma_rng_buf_len < 16)
 853                 sport->rx_dma_rng_buf_len = 16;
 854
 855         ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
 856         if (!ring->buf) {
 857                 dev_err(sport->port.dev, "Ring buf alloc failed\n");
 858                 return -ENOMEM;
 859         }
 860
 861         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
 862         sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
 863         nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
 864
 865         if (!nent) {
 866                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
 867                 return -EINVAL;
 868         }
 869
 870         dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
 871         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 872         dma_rx_sconfig.src_maxburst = 1;
 873         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
 874         ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
 875
 876         if (ret < 0) {
 877                 dev_err(sport->port.dev,
 878                                 "DMA Rx slave config failed, err = %d\n", ret);
 879                 return ret;
 880         }
 881
 882         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
 883                                  sg_dma_address(&sport->rx_sgl),
 884                                  sport->rx_sgl.length,
 885                                  sport->rx_sgl.length / 2,
 886                                  DMA_DEV_TO_MEM,
 887                                  DMA_PREP_INTERRUPT);
 888         if (!sport->dma_rx_desc) {
 889                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
 890                 return -EFAULT;
 891         }
 892
 893         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
 894         sport->dma_rx_desc->callback_param = sport;
 895         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
 896         dma_async_issue_pending(sport->dma_rx_chan);
 897
 898         writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
 899                                 sport->port.membase + UARTCR5);
 900
 901         return 0;
 902 }
 903
 904 static void lpuart_dma_rx_free(struct uart_port *port)
 905 {
 906         struct lpuart_port *sport = container_of(port,
 907                                         struct lpuart_port, port);
 908
 909         if (sport->dma_rx_chan)
 910                 dmaengine_terminate_all(sport->dma_rx_chan);
 911
 912         dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
 913         kfree(sport->rx_ring.buf);
 914         sport->rx_ring.tail = 0;
 915         sport->rx_ring.head = 0;
 916         sport->dma_rx_desc = NULL;
 917         sport->dma_rx_cookie = -EINVAL;
 918 }
 919
 920 static int lpuart_config_rs485(struct uart_port *port,
 921                         struct serial_rs485 *rs485)
 922 {
 923         struct lpuart_port *sport = container_of(port,
 924                         struct lpuart_port, port);
 925
 926         u8 modem = readb(sport->port.membase + UARTMODEM) &
 927                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
 928         writeb(modem, sport->port.membase + UARTMODEM);
 929
 930         if (rs485->flags & SER_RS485_ENABLED) {
 931                 /* Enable auto RS-485 RTS mode */
 932                 modem |= UARTMODEM_TXRTSE;
 933
 934                 /*
 935                  * RTS needs to be logic HIGH either during transer _or_ after
 936                  * transfer, other variants are not supported by the hardware.
 937                  */
 938
 939                 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
 940                                 SER_RS485_RTS_AFTER_SEND)))
 941                         rs485->flags |= SER_RS485_RTS_ON_SEND;
 942
 943                 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
 944                                 rs485->flags & SER_RS485_RTS_AFTER_SEND)
 945                         rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
 946
 947                 /*
 948                  * The hardware defaults to RTS logic HIGH while transfer.
 949                  * Switch polarity in case RTS shall be logic HIGH
 950                  * after transfer.
 951                  * Note: UART is assumed to be active high.
 952                  */
 953                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
 954                         modem &= ~UARTMODEM_TXRTSPOL;
 955                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
 956                         modem |= UARTMODEM_TXRTSPOL;
 957         }
 958
 959         /* Store the new configuration */
 960         sport->port.rs485 = *rs485;
 961
 962         writeb(modem, sport->port.membase + UARTMODEM);
 963         return 0;
 964 }
 965
 966 static unsigned int lpuart_get_mctrl(struct uart_port *port)
 967 {
 968         unsigned int temp = 0;
 969         unsigned char reg;
 970
 971         reg = readb(port->membase + UARTMODEM);
 972         if (reg & UARTMODEM_TXCTSE)
 973                 temp |= TIOCM_CTS;
 974
 975         if (reg & UARTMODEM_RXRTSE)
 976                 temp |= TIOCM_RTS;
 977
 978         return temp;
 979 }
 980
 981 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
 982 {
 983         unsigned int temp = 0;
 984         unsigned long reg;
 985
 986         reg = lpuart32_read(port->membase + UARTMODIR);
 987         if (reg & UARTMODIR_TXCTSE)
 988                 temp |= TIOCM_CTS;
 989
 990         if (reg & UARTMODIR_RXRTSE)
 991                 temp |= TIOCM_RTS;
 992
 993         return temp;
 994 }
 995
 996 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 997 {
 998         unsigned char temp;
 999         struct lpuart_port *sport = container_of(port,
1000                                 struct lpuart_port, port);
1001
1002         /* Make sure RXRTSE bit is not set when RS485 is enabled */
1003         if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1004                 temp = readb(sport->port.membase + UARTMODEM) &
1005                         ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1006
1007                 if (mctrl & TIOCM_RTS)
1008                         temp |= UARTMODEM_RXRTSE;
1009
1010                 if (mctrl & TIOCM_CTS)
1011                         temp |= UARTMODEM_TXCTSE;
1012
1013                 writeb(temp, port->membase + UARTMODEM);
1014         }
1015 }
1016
1017 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1018 {
1019         unsigned long temp;
1020
1021         temp = lpuart32_read(port->membase + UARTMODIR) &
1022                         ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1023
1024         if (mctrl & TIOCM_RTS)
1025                 temp |= UARTMODIR_RXRTSE;
1026
1027         if (mctrl & TIOCM_CTS)
1028                 temp |= UARTMODIR_TXCTSE;
1029
1030         lpuart32_write(temp, port->membase + UARTMODIR);
1031 }
1032
1033 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1034 {
1035         unsigned char temp;
1036
1037         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1038
1039         if (break_state != 0)
1040                 temp |= UARTCR2_SBK;
1041
1042         writeb(temp, port->membase + UARTCR2);
1043 }
1044
1045 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1046 {
1047         unsigned long temp;
1048
1049         temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
1050
1051         if (break_state != 0)
1052                 temp |= UARTCTRL_SBK;
1053
1054         lpuart32_write(temp, port->membase + UARTCTRL);
1055 }
1056
1057 static void lpuart_setup_watermark(struct lpuart_port *sport)
1058 {
1059         unsigned char val, cr2;
1060         unsigned char cr2_saved;
1061
1062         cr2 = readb(sport->port.membase + UARTCR2);
1063         cr2_saved = cr2;
1064         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1065                         UARTCR2_RIE | UARTCR2_RE);
1066         writeb(cr2, sport->port.membase + UARTCR2);
1067
1068         val = readb(sport->port.membase + UARTPFIFO);
1069         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1070                         sport->port.membase + UARTPFIFO);
1071
1072         /* flush Tx and Rx FIFO */
1073         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1074                         sport->port.membase + UARTCFIFO);
1075
1076         /* explicitly clear RDRF */
1077         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1078                 readb(sport->port.membase + UARTDR);
1079                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1080         }
1081
1082         writeb(0, sport->port.membase + UARTTWFIFO);
1083         writeb(1, sport->port.membase + UARTRWFIFO);
1084
1085         /* Restore cr2 */
1086         writeb(cr2_saved, sport->port.membase + UARTCR2);
1087 }
1088
1089 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1090 {
1091         unsigned long val, ctrl;
1092         unsigned long ctrl_saved;
1093
1094         ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1095         ctrl_saved = ctrl;
1096         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1097                         UARTCTRL_RIE | UARTCTRL_RE);
1098         lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1099
1100         /* enable FIFO mode */
1101         val = lpuart32_read(sport->port.membase + UARTFIFO);
1102         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1103         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1104         lpuart32_write(val, sport->port.membase + UARTFIFO);
1105
1106         /* set the watermark */
1107         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1108         lpuart32_write(val, sport->port.membase + UARTWATER);
1109
1110         /* Restore cr2 */
1111         lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
1112 }
1113
1114 static void rx_dma_timer_init(struct lpuart_port *sport)
1115 {
1116                 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1117                                 (unsigned long)sport);
1118                 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1119                 add_timer(&sport->lpuart_timer);
1120 }
1121
1122 static int lpuart_startup(struct uart_port *port)
1123 {
1124         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1125         int ret;
1126         unsigned long flags;
1127         unsigned char temp;
1128
1129         /* determine FIFO size and enable FIFO mode */
1130         temp = readb(sport->port.membase + UARTPFIFO);
1131
1132         sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1133                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1134
1135         sport->port.fifosize = sport->txfifo_size;
1136
1137         sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1138                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1139
1140         ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1141                                 DRIVER_NAME, sport);
1142         if (ret)
1143                 return ret;
1144
1145         spin_lock_irqsave(&sport->port.lock, flags);
1146
1147         lpuart_setup_watermark(sport);
1148
1149         temp = readb(sport->port.membase + UARTCR2);
1150         temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1151         writeb(temp, sport->port.membase + UARTCR2);
1152
1153         if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1154                 /* set Rx DMA timeout */
1155                 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1156                 if (!sport->dma_rx_timeout)
1157                      sport->dma_rx_timeout = 1;
1158
1159                 sport->lpuart_dma_rx_use = true;
1160                 rx_dma_timer_init(sport);
1161         } else {
1162                 sport->lpuart_dma_rx_use = false;
1163         }
1164
1165         if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1166                 init_waitqueue_head(&sport->dma_wait);
1167                 sport->lpuart_dma_tx_use = true;
1168                 temp = readb(port->membase + UARTCR5);
1169                 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1170         } else {
1171                 sport->lpuart_dma_tx_use = false;
1172         }
1173
1174         spin_unlock_irqrestore(&sport->port.lock, flags);
1175
1176         return 0;
1177 }
1178
1179 static int lpuart32_startup(struct uart_port *port)
1180 {
1181         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1182         int ret;
1183         unsigned long flags;
1184         unsigned long temp;
1185
1186         /* determine FIFO size */
1187         temp = lpuart32_read(sport->port.membase + UARTFIFO);
1188
1189         sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1190                 UARTFIFO_FIFOSIZE_MASK) - 1);
1191
1192         sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1193                 UARTFIFO_FIFOSIZE_MASK) - 1);
1194
1195         ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1196                                 DRIVER_NAME, sport);
1197         if (ret)
1198                 return ret;
1199
1200         spin_lock_irqsave(&sport->port.lock, flags);
1201
1202         lpuart32_setup_watermark(sport);
1203
1204         temp = lpuart32_read(sport->port.membase + UARTCTRL);
1205         temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1206         temp |= UARTCTRL_ILIE;
1207         lpuart32_write(temp, sport->port.membase + UARTCTRL);
1208
1209         spin_unlock_irqrestore(&sport->port.lock, flags);
1210         return 0;
1211 }
1212
1213 static void lpuart_shutdown(struct uart_port *port)
1214 {
1215         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1216         unsigned char temp;
1217         unsigned long flags;
1218
1219         spin_lock_irqsave(&port->lock, flags);
1220
1221         /* disable Rx/Tx and interrupts */
1222         temp = readb(port->membase + UARTCR2);
1223         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1224                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1225         writeb(temp, port->membase + UARTCR2);
1226
1227         spin_unlock_irqrestore(&port->lock, flags);
1228
1229         devm_free_irq(port->dev, port->irq, sport);
1230
1231         if (sport->lpuart_dma_rx_use) {
1232                 del_timer_sync(&sport->lpuart_timer);
1233                 lpuart_dma_rx_free(&sport->port);
1234         }
1235
1236         if (sport->lpuart_dma_tx_use) {
1237                 if (wait_event_interruptible(sport->dma_wait,
1238                         !sport->dma_tx_in_progress) != false) {
1239                         sport->dma_tx_in_progress = false;
1240                         dmaengine_terminate_all(sport->dma_tx_chan);
1241                 }
1242
1243                 lpuart_stop_tx(port);
1244         }
1245 }
1246
1247 static void lpuart32_shutdown(struct uart_port *port)
1248 {
1249         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1250         unsigned long temp;
1251         unsigned long flags;
1252
1253         spin_lock_irqsave(&port->lock, flags);
1254
1255         /* disable Rx/Tx and interrupts */
1256         temp = lpuart32_read(port->membase + UARTCTRL);
1257         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1258                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1259         lpuart32_write(temp, port->membase + UARTCTRL);
1260
1261         spin_unlock_irqrestore(&port->lock, flags);
1262
1263         devm_free_irq(port->dev, port->irq, sport);
1264 }
1265
1266 static void
1267 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1268                    struct ktermios *old)
1269 {
1270         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1271         unsigned long flags;
1272         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1273         unsigned int  baud;
1274         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1275         unsigned int sbr, brfa;
1276
1277         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1278         old_cr2 = readb(sport->port.membase + UARTCR2);
1279         cr3 = readb(sport->port.membase + UARTCR3);
1280         cr4 = readb(sport->port.membase + UARTCR4);
1281         bdh = readb(sport->port.membase + UARTBDH);
1282         modem = readb(sport->port.membase + UARTMODEM);
1283         /*
1284          * only support CS8 and CS7, and for CS7 must enable PE.
1285          * supported mode:
1286          *  - (7,e/o,1)
1287          *  - (8,n,1)
1288          *  - (8,m/s,1)
1289          *  - (8,e/o,1)
1290          */
1291         while ((termios->c_cflag & CSIZE) != CS8 &&
1292                 (termios->c_cflag & CSIZE) != CS7) {
1293                 termios->c_cflag &= ~CSIZE;
1294                 termios->c_cflag |= old_csize;
1295                 old_csize = CS8;
1296         }
1297
1298         if ((termios->c_cflag & CSIZE) == CS8 ||
1299                 (termios->c_cflag & CSIZE) == CS7)
1300                 cr1 = old_cr1 & ~UARTCR1_M;
1301
1302         if (termios->c_cflag & CMSPAR) {
1303                 if ((termios->c_cflag & CSIZE) != CS8) {
1304                         termios->c_cflag &= ~CSIZE;
1305                         termios->c_cflag |= CS8;
1306                 }
1307                 cr1 |= UARTCR1_M;
1308         }
1309
1310         /*
1311          * When auto RS-485 RTS mode is enabled,
1312          * hardware flow control need to be disabled.
1313          */
1314         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1315                 termios->c_cflag &= ~CRTSCTS;
1316
1317         if (termios->c_cflag & CRTSCTS) {
1318                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1319         } else {
1320                 termios->c_cflag &= ~CRTSCTS;
1321                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1322         }
1323
1324         if (termios->c_cflag & CSTOPB)
1325                 termios->c_cflag &= ~CSTOPB;
1326
1327         /* parity must be enabled when CS7 to match 8-bits format */
1328         if ((termios->c_cflag & CSIZE) == CS7)
1329                 termios->c_cflag |= PARENB;
1330
1331         if ((termios->c_cflag & PARENB)) {
1332                 if (termios->c_cflag & CMSPAR) {
1333                         cr1 &= ~UARTCR1_PE;
1334                         if (termios->c_cflag & PARODD)
1335                                 cr3 |= UARTCR3_T8;
1336                         else
1337                                 cr3 &= ~UARTCR3_T8;
1338                 } else {
1339                         cr1 |= UARTCR1_PE;
1340                         if ((termios->c_cflag & CSIZE) == CS8)
1341                                 cr1 |= UARTCR1_M;
1342                         if (termios->c_cflag & PARODD)
1343                                 cr1 |= UARTCR1_PT;
1344                         else
1345                                 cr1 &= ~UARTCR1_PT;
1346                 }
1347         } else {
1348                 cr1 &= ~UARTCR1_PE;
1349         }
1350
1351         /* ask the core to calculate the divisor */
1352         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1353
1354         spin_lock_irqsave(&sport->port.lock, flags);
1355
1356         sport->port.read_status_mask = 0;
1357         if (termios->c_iflag & INPCK)
1358                 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
1359         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1360                 sport->port.read_status_mask |= UARTSR1_FE;
1361
1362         /* characters to ignore */
1363         sport->port.ignore_status_mask = 0;
1364         if (termios->c_iflag & IGNPAR)
1365                 sport->port.ignore_status_mask |= UARTSR1_PE;
1366         if (termios->c_iflag & IGNBRK) {
1367                 sport->port.ignore_status_mask |= UARTSR1_FE;
1368                 /*
1369                  * if we're ignoring parity and break indicators,
1370                  * ignore overruns too (for real raw support).
1371                  */
1372                 if (termios->c_iflag & IGNPAR)
1373                         sport->port.ignore_status_mask |= UARTSR1_OR;
1374         }
1375
1376         /* update the per-port timeout */
1377         uart_update_timeout(port, termios->c_cflag, baud);
1378
1379         /* wait transmit engin complete */
1380         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1381                 barrier();
1382
1383         /* disable transmit and receive */
1384         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1385                         sport->port.membase + UARTCR2);
1386
1387         sbr = sport->port.uartclk / (16 * baud);
1388         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1389         bdh &= ~UARTBDH_SBR_MASK;
1390         bdh |= (sbr >> 8) & 0x1F;
1391         cr4 &= ~UARTCR4_BRFA_MASK;
1392         brfa &= UARTCR4_BRFA_MASK;
1393         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1394         writeb(bdh, sport->port.membase + UARTBDH);
1395         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1396         writeb(cr3, sport->port.membase + UARTCR3);
1397         writeb(cr1, sport->port.membase + UARTCR1);
1398         writeb(modem, sport->port.membase + UARTMODEM);
1399
1400         /* restore control register */
1401         writeb(old_cr2, sport->port.membase + UARTCR2);
1402
1403         /*
1404          * If new baud rate is set, we will also need to update the Ring buffer
1405          * length according to the selected baud rate and restart Rx DMA path.
1406          */
1407         if (old) {
1408                 if (sport->lpuart_dma_rx_use) {
1409                         del_timer_sync(&sport->lpuart_timer);
1410                         lpuart_dma_rx_free(&sport->port);
1411                 }
1412
1413                 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1414                         sport->lpuart_dma_rx_use = true;
1415                         rx_dma_timer_init(sport);
1416                 } else {
1417                         sport->lpuart_dma_rx_use = false;
1418                 }
1419         }
1420
1421         spin_unlock_irqrestore(&sport->port.lock, flags);
1422 }
1423
1424 static void
1425 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1426                    struct ktermios *old)
1427 {
1428         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1429         unsigned long flags;
1430         unsigned long ctrl, old_ctrl, bd, modem;
1431         unsigned int  baud;
1432         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1433         unsigned int sbr;
1434
1435         ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1436         bd = lpuart32_read(sport->port.membase + UARTBAUD);
1437         modem = lpuart32_read(sport->port.membase + UARTMODIR);
1438         /*
1439          * only support CS8 and CS7, and for CS7 must enable PE.
1440          * supported mode:
1441          *  - (7,e/o,1)
1442          *  - (8,n,1)
1443          *  - (8,m/s,1)
1444          *  - (8,e/o,1)
1445          */
1446         while ((termios->c_cflag & CSIZE) != CS8 &&
1447                 (termios->c_cflag & CSIZE) != CS7) {
1448                 termios->c_cflag &= ~CSIZE;
1449                 termios->c_cflag |= old_csize;
1450                 old_csize = CS8;
1451         }
1452
1453         if ((termios->c_cflag & CSIZE) == CS8 ||
1454                 (termios->c_cflag & CSIZE) == CS7)
1455                 ctrl = old_ctrl & ~UARTCTRL_M;
1456
1457         if (termios->c_cflag & CMSPAR) {
1458                 if ((termios->c_cflag & CSIZE) != CS8) {
1459                         termios->c_cflag &= ~CSIZE;
1460                         termios->c_cflag |= CS8;
1461                 }
1462                 ctrl |= UARTCTRL_M;
1463         }
1464
1465         if (termios->c_cflag & CRTSCTS) {
1466                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1467         } else {
1468                 termios->c_cflag &= ~CRTSCTS;
1469                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1470         }
1471
1472         if (termios->c_cflag & CSTOPB)
1473                 termios->c_cflag &= ~CSTOPB;
1474
1475         /* parity must be enabled when CS7 to match 8-bits format */
1476         if ((termios->c_cflag & CSIZE) == CS7)
1477                 termios->c_cflag |= PARENB;
1478
1479         if ((termios->c_cflag & PARENB)) {
1480                 if (termios->c_cflag & CMSPAR) {
1481                         ctrl &= ~UARTCTRL_PE;
1482                         ctrl |= UARTCTRL_M;
1483                 } else {
1484                         ctrl |= UARTCR1_PE;
1485                         if ((termios->c_cflag & CSIZE) == CS8)
1486                                 ctrl |= UARTCTRL_M;
1487                         if (termios->c_cflag & PARODD)
1488                                 ctrl |= UARTCTRL_PT;
1489                         else
1490                                 ctrl &= ~UARTCTRL_PT;
1491                 }
1492         } else {
1493                 ctrl &= ~UARTCTRL_PE;
1494         }
1495
1496         /* ask the core to calculate the divisor */
1497         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
1498
1499         spin_lock_irqsave(&sport->port.lock, flags);
1500
1501         sport->port.read_status_mask = 0;
1502         if (termios->c_iflag & INPCK)
1503                 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1504         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1505                 sport->port.read_status_mask |= UARTSTAT_FE;
1506
1507         /* characters to ignore */
1508         sport->port.ignore_status_mask = 0;
1509         if (termios->c_iflag & IGNPAR)
1510                 sport->port.ignore_status_mask |= UARTSTAT_PE;
1511         if (termios->c_iflag & IGNBRK) {
1512                 sport->port.ignore_status_mask |= UARTSTAT_FE;
1513                 /*
1514                  * if we're ignoring parity and break indicators,
1515                  * ignore overruns too (for real raw support).
1516                  */
1517                 if (termios->c_iflag & IGNPAR)
1518                         sport->port.ignore_status_mask |= UARTSTAT_OR;
1519         }
1520
1521         /* update the per-port timeout */
1522         uart_update_timeout(port, termios->c_cflag, baud);
1523
1524         /* wait transmit engin complete */
1525         while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1526                 barrier();
1527
1528         /* disable transmit and receive */
1529         lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1530                         sport->port.membase + UARTCTRL);
1531
1532         sbr = sport->port.uartclk / (16 * baud);
1533         bd &= ~UARTBAUD_SBR_MASK;
1534         bd |= sbr & UARTBAUD_SBR_MASK;
1535         bd |= UARTBAUD_BOTHEDGE;
1536         bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1537         lpuart32_write(bd, sport->port.membase + UARTBAUD);
1538         lpuart32_write(modem, sport->port.membase + UARTMODIR);
1539         lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1540         /* restore control register */
1541
1542         spin_unlock_irqrestore(&sport->port.lock, flags);
1543 }
1544
1545 static const char *lpuart_type(struct uart_port *port)
1546 {
1547         return "FSL_LPUART";
1548 }
1549
1550 static void lpuart_release_port(struct uart_port *port)
1551 {
1552         /* nothing to do */
1553 }
1554
1555 static int lpuart_request_port(struct uart_port *port)
1556 {
1557         return  0;
1558 }
1559
1560 /* configure/autoconfigure the port */
1561 static void lpuart_config_port(struct uart_port *port, int flags)
1562 {
1563         if (flags & UART_CONFIG_TYPE)
1564                 port->type = PORT_LPUART;
1565 }
1566
1567 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1568 {
1569         int ret = 0;
1570
1571         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1572                 ret = -EINVAL;
1573         if (port->irq != ser->irq)
1574                 ret = -EINVAL;
1575         if (ser->io_type != UPIO_MEM)
1576                 ret = -EINVAL;
1577         if (port->uartclk / 16 != ser->baud_base)
1578                 ret = -EINVAL;
1579         if (port->iobase != ser->port)
1580                 ret = -EINVAL;
1581         if (ser->hub6 != 0)
1582                 ret = -EINVAL;
1583         return ret;
1584 }
1585
1586 static const struct uart_ops lpuart_pops = {
1587         .tx_empty       = lpuart_tx_empty,
1588         .set_mctrl      = lpuart_set_mctrl,
1589         .get_mctrl      = lpuart_get_mctrl,
1590         .stop_tx        = lpuart_stop_tx,
1591         .start_tx       = lpuart_start_tx,
1592         .stop_rx        = lpuart_stop_rx,
1593         .break_ctl      = lpuart_break_ctl,
1594         .startup        = lpuart_startup,
1595         .shutdown       = lpuart_shutdown,
1596         .set_termios    = lpuart_set_termios,
1597         .type           = lpuart_type,
1598         .request_port   = lpuart_request_port,
1599         .release_port   = lpuart_release_port,
1600         .config_port    = lpuart_config_port,
1601         .verify_port    = lpuart_verify_port,
1602         .flush_buffer   = lpuart_flush_buffer,
1603 };
1604
1605 static const struct uart_ops lpuart32_pops = {
1606         .tx_empty       = lpuart32_tx_empty,
1607         .set_mctrl      = lpuart32_set_mctrl,
1608         .get_mctrl      = lpuart32_get_mctrl,
1609         .stop_tx        = lpuart32_stop_tx,
1610         .start_tx       = lpuart32_start_tx,
1611         .stop_rx        = lpuart32_stop_rx,
1612         .break_ctl      = lpuart32_break_ctl,
1613         .startup        = lpuart32_startup,
1614         .shutdown       = lpuart32_shutdown,
1615         .set_termios    = lpuart32_set_termios,
1616         .type           = lpuart_type,
1617         .request_port   = lpuart_request_port,
1618         .release_port   = lpuart_release_port,
1619         .config_port    = lpuart_config_port,
1620         .verify_port    = lpuart_verify_port,
1621         .flush_buffer   = lpuart_flush_buffer,
1622 };
1623
1624 static struct lpuart_port *lpuart_ports[UART_NR];
1625
1626 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1627 static void lpuart_console_putchar(struct uart_port *port, int ch)
1628 {
1629         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1630                 barrier();
1631
1632         writeb(ch, port->membase + UARTDR);
1633 }
1634
1635 static void lpuart32_console_putchar(struct uart_port *port, int ch)
1636 {
1637         while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1638                 barrier();
1639
1640         lpuart32_write(ch, port->membase + UARTDATA);
1641 }
1642
1643 static void
1644 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1645 {
1646         struct lpuart_port *sport = lpuart_ports[co->index];
1647         unsigned char  old_cr2, cr2;
1648
1649         /* first save CR2 and then disable interrupts */
1650         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1651         cr2 |= (UARTCR2_TE |  UARTCR2_RE);
1652         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1653         writeb(cr2, sport->port.membase + UARTCR2);
1654
1655         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1656
1657         /* wait for transmitter finish complete and restore CR2 */
1658         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1659                 barrier();
1660
1661         writeb(old_cr2, sport->port.membase + UARTCR2);
1662 }
1663
1664 static void
1665 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1666 {
1667         struct lpuart_port *sport = lpuart_ports[co->index];
1668         unsigned long  old_cr, cr;
1669
1670         /* first save CR2 and then disable interrupts */
1671         cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1672         cr |= (UARTCTRL_TE |  UARTCTRL_RE);
1673         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1674         lpuart32_write(cr, sport->port.membase + UARTCTRL);
1675
1676         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1677
1678         /* wait for transmitter finish complete and restore CR2 */
1679         while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1680                 barrier();
1681
1682         lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1683 }
1684
1685 /*
1686  * if the port was already initialised (eg, by a boot loader),
1687  * try to determine the current setup.
1688  */
1689 static void __init
1690 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1691                            int *parity, int *bits)
1692 {
1693         unsigned char cr, bdh, bdl, brfa;
1694         unsigned int sbr, uartclk, baud_raw;
1695
1696         cr = readb(sport->port.membase + UARTCR2);
1697         cr &= UARTCR2_TE | UARTCR2_RE;
1698         if (!cr)
1699                 return;
1700
1701         /* ok, the port was enabled */
1702
1703         cr = readb(sport->port.membase + UARTCR1);
1704
1705         *parity = 'n';
1706         if (cr & UARTCR1_PE) {
1707                 if (cr & UARTCR1_PT)
1708                         *parity = 'o';
1709                 else
1710                         *parity = 'e';
1711         }
1712
1713         if (cr & UARTCR1_M)
1714                 *bits = 9;
1715         else
1716                 *bits = 8;
1717
1718         bdh = readb(sport->port.membase + UARTBDH);
1719         bdh &= UARTBDH_SBR_MASK;
1720         bdl = readb(sport->port.membase + UARTBDL);
1721         sbr = bdh;
1722         sbr <<= 8;
1723         sbr |= bdl;
1724         brfa = readb(sport->port.membase + UARTCR4);
1725         brfa &= UARTCR4_BRFA_MASK;
1726
1727         uartclk = clk_get_rate(sport->clk);
1728         /*
1729          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1730          */
1731         baud_raw = uartclk / (16 * (sbr + brfa / 32));
1732
1733         if (*baud != baud_raw)
1734                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1735                                 "from %d to %d\n", baud_raw, *baud);
1736 }
1737
1738 static void __init
1739 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1740                            int *parity, int *bits)
1741 {
1742         unsigned long cr, bd;
1743         unsigned int sbr, uartclk, baud_raw;
1744
1745         cr = lpuart32_read(sport->port.membase + UARTCTRL);
1746         cr &= UARTCTRL_TE | UARTCTRL_RE;
1747         if (!cr)
1748                 return;
1749
1750         /* ok, the port was enabled */
1751
1752         cr = lpuart32_read(sport->port.membase + UARTCTRL);
1753
1754         *parity = 'n';
1755         if (cr & UARTCTRL_PE) {
1756                 if (cr & UARTCTRL_PT)
1757                         *parity = 'o';
1758                 else
1759                         *parity = 'e';
1760         }
1761
1762         if (cr & UARTCTRL_M)
1763                 *bits = 9;
1764         else
1765                 *bits = 8;
1766
1767         bd = lpuart32_read(sport->port.membase + UARTBAUD);
1768         bd &= UARTBAUD_SBR_MASK;
1769         if (!bd)
1770                 return;
1771
1772         sbr = bd;
1773         uartclk = clk_get_rate(sport->clk);
1774         /*
1775          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1776          */
1777         baud_raw = uartclk / (16 * sbr);
1778
1779         if (*baud != baud_raw)
1780                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1781                                 "from %d to %d\n", baud_raw, *baud);
1782 }
1783
1784 static int __init lpuart_console_setup(struct console *co, char *options)
1785 {
1786         struct lpuart_port *sport;
1787         int baud = 115200;
1788         int bits = 8;
1789         int parity = 'n';
1790         int flow = 'n';
1791
1792         /*
1793          * check whether an invalid uart number has been specified, and
1794          * if so, search for the first available port that does have
1795          * console support.
1796          */
1797         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1798                 co->index = 0;
1799
1800         sport = lpuart_ports[co->index];
1801         if (sport == NULL)
1802                 return -ENODEV;
1803
1804         if (options)
1805                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1806         else
1807                 if (sport->lpuart32)
1808                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
1809                 else
1810                         lpuart_console_get_options(sport, &baud, &parity, &bits);
1811
1812         if (sport->lpuart32)
1813                 lpuart32_setup_watermark(sport);
1814         else
1815                 lpuart_setup_watermark(sport);
1816
1817         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1818 }
1819
1820 static struct uart_driver lpuart_reg;
1821 static struct console lpuart_console = {
1822         .name           = DEV_NAME,
1823         .write          = lpuart_console_write,
1824         .device         = uart_console_device,
1825         .setup          = lpuart_console_setup,
1826         .flags          = CON_PRINTBUFFER,
1827         .index          = -1,
1828         .data           = &lpuart_reg,
1829 };
1830
1831 static struct console lpuart32_console = {
1832         .name           = DEV_NAME,
1833         .write          = lpuart32_console_write,
1834         .device         = uart_console_device,
1835         .setup          = lpuart_console_setup,
1836         .flags          = CON_PRINTBUFFER,
1837         .index          = -1,
1838         .data           = &lpuart_reg,
1839 };
1840
1841 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
1842 {
1843         struct earlycon_device *dev = con->data;
1844
1845         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
1846 }
1847
1848 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
1849 {
1850         struct earlycon_device *dev = con->data;
1851
1852         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
1853 }
1854
1855 static int __init lpuart_early_console_setup(struct earlycon_device *device,
1856                                           const char *opt)
1857 {
1858         if (!device->port.membase)
1859                 return -ENODEV;
1860
1861         device->con->write = lpuart_early_write;
1862         return 0;
1863 }
1864
1865 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
1866                                           const char *opt)
1867 {
1868         if (!device->port.membase)
1869                 return -ENODEV;
1870
1871         device->con->write = lpuart32_early_write;
1872         return 0;
1873 }
1874
1875 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
1876 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
1877 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
1878 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
1879
1880 #define LPUART_CONSOLE  (&lpuart_console)
1881 #define LPUART32_CONSOLE        (&lpuart32_console)
1882 #else
1883 #define LPUART_CONSOLE  NULL
1884 #define LPUART32_CONSOLE        NULL
1885 #endif
1886
1887 static struct uart_driver lpuart_reg = {
1888         .owner          = THIS_MODULE,
1889         .driver_name    = DRIVER_NAME,
1890         .dev_name       = DEV_NAME,
1891         .nr             = ARRAY_SIZE(lpuart_ports),
1892         .cons           = LPUART_CONSOLE,
1893 };
1894
1895 static int lpuart_probe(struct platform_device *pdev)
1896 {
1897         struct device_node *np = pdev->dev.of_node;
1898         struct lpuart_port *sport;
1899         struct resource *res;
1900         int ret;
1901
1902         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1903         if (!sport)
1904                 return -ENOMEM;
1905
1906         pdev->dev.coherent_dma_mask = 0;
1907
1908         ret = of_alias_get_id(np, "serial");
1909         if (ret < 0) {
1910                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1911                 return ret;
1912         }
1913         if (ret >= ARRAY_SIZE(lpuart_ports)) {
1914                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
1915                 return -EINVAL;
1916         }
1917         sport->port.line = ret;
1918         sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
1919
1920         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1921         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1922         if (IS_ERR(sport->port.membase))
1923                 return PTR_ERR(sport->port.membase);
1924
1925         sport->port.mapbase = res->start;
1926         sport->port.dev = &pdev->dev;
1927         sport->port.type = PORT_LPUART;
1928         sport->port.iotype = UPIO_MEM;
1929         ret = platform_get_irq(pdev, 0);
1930         if (ret < 0) {
1931                 dev_err(&pdev->dev, "cannot obtain irq\n");
1932                 return ret;
1933         }
1934         sport->port.irq = ret;
1935
1936         if (sport->lpuart32)
1937                 sport->port.ops = &lpuart32_pops;
1938         else
1939                 sport->port.ops = &lpuart_pops;
1940         sport->port.flags = UPF_BOOT_AUTOCONF;
1941
1942         sport->port.rs485_config = lpuart_config_rs485;
1943
1944         sport->clk = devm_clk_get(&pdev->dev, "ipg");
1945         if (IS_ERR(sport->clk)) {
1946                 ret = PTR_ERR(sport->clk);
1947                 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1948                 return ret;
1949         }
1950
1951         ret = clk_prepare_enable(sport->clk);
1952         if (ret) {
1953                 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1954                 return ret;
1955         }
1956
1957         sport->port.uartclk = clk_get_rate(sport->clk);
1958
1959         lpuart_ports[sport->port.line] = sport;
1960
1961         platform_set_drvdata(pdev, &sport->port);
1962
1963         if (sport->lpuart32)
1964                 lpuart_reg.cons = LPUART32_CONSOLE;
1965         else
1966                 lpuart_reg.cons = LPUART_CONSOLE;
1967
1968         ret = uart_add_one_port(&lpuart_reg, &sport->port);
1969         if (ret) {
1970                 clk_disable_unprepare(sport->clk);
1971                 return ret;
1972         }
1973
1974         sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
1975         if (!sport->dma_tx_chan)
1976                 dev_info(sport->port.dev, "DMA tx channel request failed, "
1977                                 "operating without tx DMA\n");
1978
1979         sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1980         if (!sport->dma_rx_chan)
1981                 dev_info(sport->port.dev, "DMA rx channel request failed, "
1982                                 "operating without rx DMA\n");
1983
1984         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) {
1985                 sport->port.rs485.flags |= SER_RS485_ENABLED;
1986                 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND;
1987                 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM);
1988         }
1989
1990         return 0;
1991 }
1992
1993 static int lpuart_remove(struct platform_device *pdev)
1994 {
1995         struct lpuart_port *sport = platform_get_drvdata(pdev);
1996
1997         uart_remove_one_port(&lpuart_reg, &sport->port);
1998
1999         clk_disable_unprepare(sport->clk);
2000
2001         if (sport->dma_tx_chan)
2002                 dma_release_channel(sport->dma_tx_chan);
2003
2004         if (sport->dma_rx_chan)
2005                 dma_release_channel(sport->dma_rx_chan);
2006
2007         return 0;
2008 }
2009
2010 #ifdef CONFIG_PM_SLEEP
2011 static int lpuart_suspend(struct device *dev)
2012 {
2013         struct lpuart_port *sport = dev_get_drvdata(dev);
2014         unsigned long temp;
2015
2016         if (sport->lpuart32) {
2017                 /* disable Rx/Tx and interrupts */
2018                 temp = lpuart32_read(sport->port.membase + UARTCTRL);
2019                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2020                 lpuart32_write(temp, sport->port.membase + UARTCTRL);
2021         } else {
2022                 /* disable Rx/Tx and interrupts */
2023                 temp = readb(sport->port.membase + UARTCR2);
2024                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2025                 writeb(temp, sport->port.membase + UARTCR2);
2026         }
2027
2028         uart_suspend_port(&lpuart_reg, &sport->port);
2029
2030         if (sport->lpuart_dma_rx_use) {
2031                 /*
2032                  * EDMA driver during suspend will forcefully release any
2033                  * non-idle DMA channels. If port wakeup is enabled or if port
2034                  * is console port or 'no_console_suspend' is set the Rx DMA
2035                  * cannot resume as as expected, hence gracefully release the
2036                  * Rx DMA path before suspend and start Rx DMA path on resume.
2037                  */
2038                 if (sport->port.irq_wake) {
2039                         del_timer_sync(&sport->lpuart_timer);
2040                         lpuart_dma_rx_free(&sport->port);
2041                 }
2042
2043                 /* Disable Rx DMA to use UART port as wakeup source */
2044                 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
2045                                         sport->port.membase + UARTCR5);
2046         }
2047
2048         if (sport->lpuart_dma_tx_use) {
2049                 sport->dma_tx_in_progress = false;
2050                 dmaengine_terminate_all(sport->dma_tx_chan);
2051         }
2052
2053         if (sport->port.suspended && !sport->port.irq_wake)
2054                 clk_disable_unprepare(sport->clk);
2055
2056         return 0;
2057 }
2058
2059 static int lpuart_resume(struct device *dev)
2060 {
2061         struct lpuart_port *sport = dev_get_drvdata(dev);
2062         unsigned long temp;
2063
2064         if (sport->port.suspended && !sport->port.irq_wake)
2065                 clk_prepare_enable(sport->clk);
2066
2067         if (sport->lpuart32) {
2068                 lpuart32_setup_watermark(sport);
2069                 temp = lpuart32_read(sport->port.membase + UARTCTRL);
2070                 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
2071                          UARTCTRL_TE | UARTCTRL_ILIE);
2072                 lpuart32_write(temp, sport->port.membase + UARTCTRL);
2073         } else {
2074                 lpuart_setup_watermark(sport);
2075                 temp = readb(sport->port.membase + UARTCR2);
2076                 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2077                 writeb(temp, sport->port.membase + UARTCR2);
2078         }
2079
2080         if (sport->lpuart_dma_rx_use) {
2081                 if (sport->port.irq_wake) {
2082                         if (!lpuart_start_rx_dma(sport)) {
2083                                 sport->lpuart_dma_rx_use = true;
2084                                 rx_dma_timer_init(sport);
2085                         } else {
2086                                 sport->lpuart_dma_rx_use = false;
2087                         }
2088                 }
2089         }
2090
2091         if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2092                         init_waitqueue_head(&sport->dma_wait);
2093                         sport->lpuart_dma_tx_use = true;
2094                         writeb(readb(sport->port.membase + UARTCR5) |
2095                                 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2096         } else {
2097                 sport->lpuart_dma_tx_use = false;
2098         }
2099
2100         uart_resume_port(&lpuart_reg, &sport->port);
2101
2102         return 0;
2103 }
2104 #endif
2105
2106 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2107
2108 static struct platform_driver lpuart_driver = {
2109         .probe          = lpuart_probe,
2110         .remove         = lpuart_remove,
2111         .driver         = {
2112                 .name   = "fsl-lpuart",
2113                 .of_match_table = lpuart_dt_ids,
2114                 .pm     = &lpuart_pm_ops,
2115         },
2116 };
2117
2118 static int __init lpuart_serial_init(void)
2119 {
2120         int ret = uart_register_driver(&lpuart_reg);
2121
2122         if (ret)
2123                 return ret;
2124
2125         ret = platform_driver_register(&lpuart_driver);
2126         if (ret)
2127                 uart_unregister_driver(&lpuart_reg);
2128
2129         return ret;
2130 }
2131
2132 static void __exit lpuart_serial_exit(void)
2133 {
2134         platform_driver_unregister(&lpuart_driver);
2135         uart_unregister_driver(&lpuart_reg);
2136 }
2137
2138 module_init(lpuart_serial_init);
2139 module_exit(lpuart_serial_exit);
2140
2141 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2142 MODULE_LICENSE("GPL v2");