drivers/tty/serial/fsl_lpuart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Freescale lpuart serial port driver
   4  *
   5  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/console.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dmapool.h>
  13 #include <linux/io.h>
  14 #include <linux/irq.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_dma.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/slab.h>
  21 #include <linux/tty_flip.h>
  22
  23 /* All registers are 8-bit width */
  24 #define UARTBDH                 0x00
  25 #define UARTBDL                 0x01
  26 #define UARTCR1                 0x02
  27 #define UARTCR2                 0x03
  28 #define UARTSR1                 0x04
  29 #define UARTCR3                 0x06
  30 #define UARTDR                  0x07
  31 #define UARTCR4                 0x0a
  32 #define UARTCR5                 0x0b
  33 #define UARTMODEM               0x0d
  34 #define UARTPFIFO               0x10
  35 #define UARTCFIFO               0x11
  36 #define UARTSFIFO               0x12
  37 #define UARTTWFIFO              0x13
  38 #define UARTTCFIFO              0x14
  39 #define UARTRWFIFO              0x15
  40
  41 #define UARTBDH_LBKDIE          0x80
  42 #define UARTBDH_RXEDGIE         0x40
  43 #define UARTBDH_SBR_MASK        0x1f
  44
  45 #define UARTCR1_LOOPS           0x80
  46 #define UARTCR1_RSRC            0x20
  47 #define UARTCR1_M               0x10
  48 #define UARTCR1_WAKE            0x08
  49 #define UARTCR1_ILT             0x04
  50 #define UARTCR1_PE              0x02
  51 #define UARTCR1_PT              0x01
  52
  53 #define UARTCR2_TIE             0x80
  54 #define UARTCR2_TCIE            0x40
  55 #define UARTCR2_RIE             0x20
  56 #define UARTCR2_ILIE            0x10
  57 #define UARTCR2_TE              0x08
  58 #define UARTCR2_RE              0x04
  59 #define UARTCR2_RWU             0x02
  60 #define UARTCR2_SBK             0x01
  61
  62 #define UARTSR1_TDRE            0x80
  63 #define UARTSR1_TC              0x40
  64 #define UARTSR1_RDRF            0x20
  65 #define UARTSR1_IDLE            0x10
  66 #define UARTSR1_OR              0x08
  67 #define UARTSR1_NF              0x04
  68 #define UARTSR1_FE              0x02
  69 #define UARTSR1_PE              0x01
  70
  71 #define UARTCR3_R8              0x80
  72 #define UARTCR3_T8              0x40
  73 #define UARTCR3_TXDIR           0x20
  74 #define UARTCR3_TXINV           0x10
  75 #define UARTCR3_ORIE            0x08
  76 #define UARTCR3_NEIE            0x04
  77 #define UARTCR3_FEIE            0x02
  78 #define UARTCR3_PEIE            0x01
  79
  80 #define UARTCR4_MAEN1           0x80
  81 #define UARTCR4_MAEN2           0x40
  82 #define UARTCR4_M10             0x20
  83 #define UARTCR4_BRFA_MASK       0x1f
  84 #define UARTCR4_BRFA_OFF        0
  85
  86 #define UARTCR5_TDMAS           0x80
  87 #define UARTCR5_RDMAS           0x20
  88
  89 #define UARTMODEM_RXRTSE        0x08
  90 #define UARTMODEM_TXRTSPOL      0x04
  91 #define UARTMODEM_TXRTSE        0x02
  92 #define UARTMODEM_TXCTSE        0x01
  93
  94 #define UARTPFIFO_TXFE          0x80
  95 #define UARTPFIFO_FIFOSIZE_MASK 0x7
  96 #define UARTPFIFO_TXSIZE_OFF    4
  97 #define UARTPFIFO_RXFE          0x08
  98 #define UARTPFIFO_RXSIZE_OFF    0
  99
 100 #define UARTCFIFO_TXFLUSH       0x80
 101 #define UARTCFIFO_RXFLUSH       0x40
 102 #define UARTCFIFO_RXOFE         0x04
 103 #define UARTCFIFO_TXOFE         0x02
 104 #define UARTCFIFO_RXUFE         0x01
 105
 106 #define UARTSFIFO_TXEMPT        0x80
 107 #define UARTSFIFO_RXEMPT        0x40
 108 #define UARTSFIFO_RXOF          0x04
 109 #define UARTSFIFO_TXOF          0x02
 110 #define UARTSFIFO_RXUF          0x01
 111
 112 /* 32-bit register definition */
 113 #define UARTBAUD                0x00
 114 #define UARTSTAT                0x04
 115 #define UARTCTRL                0x08
 116 #define UARTDATA                0x0C
 117 #define UARTMATCH               0x10
 118 #define UARTMODIR               0x14
 119 #define UARTFIFO                0x18
 120 #define UARTWATER               0x1c
 121
 122 #define UARTBAUD_MAEN1          0x80000000
 123 #define UARTBAUD_MAEN2          0x40000000
 124 #define UARTBAUD_M10            0x20000000
 125 #define UARTBAUD_TDMAE          0x00800000
 126 #define UARTBAUD_RDMAE          0x00200000
 127 #define UARTBAUD_MATCFG         0x00400000
 128 #define UARTBAUD_BOTHEDGE       0x00020000
 129 #define UARTBAUD_RESYNCDIS      0x00010000
 130 #define UARTBAUD_LBKDIE         0x00008000
 131 #define UARTBAUD_RXEDGIE        0x00004000
 132 #define UARTBAUD_SBNS           0x00002000
 133 #define UARTBAUD_SBR            0x00000000
 134 #define UARTBAUD_SBR_MASK       0x1fff
 135 #define UARTBAUD_OSR_MASK       0x1f
 136 #define UARTBAUD_OSR_SHIFT      24
 137
 138 #define UARTSTAT_LBKDIF         0x80000000
 139 #define UARTSTAT_RXEDGIF        0x40000000
 140 #define UARTSTAT_MSBF           0x20000000
 141 #define UARTSTAT_RXINV          0x10000000
 142 #define UARTSTAT_RWUID          0x08000000
 143 #define UARTSTAT_BRK13          0x04000000
 144 #define UARTSTAT_LBKDE          0x02000000
 145 #define UARTSTAT_RAF            0x01000000
 146 #define UARTSTAT_TDRE           0x00800000
 147 #define UARTSTAT_TC             0x00400000
 148 #define UARTSTAT_RDRF           0x00200000
 149 #define UARTSTAT_IDLE           0x00100000
 150 #define UARTSTAT_OR             0x00080000
 151 #define UARTSTAT_NF             0x00040000
 152 #define UARTSTAT_FE             0x00020000
 153 #define UARTSTAT_PE             0x00010000
 154 #define UARTSTAT_MA1F           0x00008000
 155 #define UARTSTAT_M21F           0x00004000
 156
 157 #define UARTCTRL_R8T9           0x80000000
 158 #define UARTCTRL_R9T8           0x40000000
 159 #define UARTCTRL_TXDIR          0x20000000
 160 #define UARTCTRL_TXINV          0x10000000
 161 #define UARTCTRL_ORIE           0x08000000
 162 #define UARTCTRL_NEIE           0x04000000
 163 #define UARTCTRL_FEIE           0x02000000
 164 #define UARTCTRL_PEIE           0x01000000
 165 #define UARTCTRL_TIE            0x00800000
 166 #define UARTCTRL_TCIE           0x00400000
 167 #define UARTCTRL_RIE            0x00200000
 168 #define UARTCTRL_ILIE           0x00100000
 169 #define UARTCTRL_TE             0x00080000
 170 #define UARTCTRL_RE             0x00040000
 171 #define UARTCTRL_RWU            0x00020000
 172 #define UARTCTRL_SBK            0x00010000
 173 #define UARTCTRL_MA1IE          0x00008000
 174 #define UARTCTRL_MA2IE          0x00004000
 175 #define UARTCTRL_IDLECFG        0x00000100
 176 #define UARTCTRL_LOOPS          0x00000080
 177 #define UARTCTRL_DOZEEN         0x00000040
 178 #define UARTCTRL_RSRC           0x00000020
 179 #define UARTCTRL_M              0x00000010
 180 #define UARTCTRL_WAKE           0x00000008
 181 #define UARTCTRL_ILT            0x00000004
 182 #define UARTCTRL_PE             0x00000002
 183 #define UARTCTRL_PT             0x00000001
 184
 185 #define UARTDATA_NOISY          0x00008000
 186 #define UARTDATA_PARITYE        0x00004000
 187 #define UARTDATA_FRETSC         0x00002000
 188 #define UARTDATA_RXEMPT         0x00001000
 189 #define UARTDATA_IDLINE         0x00000800
 190 #define UARTDATA_MASK           0x3ff
 191
 192 #define UARTMODIR_IREN          0x00020000
 193 #define UARTMODIR_TXCTSSRC      0x00000020
 194 #define UARTMODIR_TXCTSC        0x00000010
 195 #define UARTMODIR_RXRTSE        0x00000008
 196 #define UARTMODIR_TXRTSPOL      0x00000004
 197 #define UARTMODIR_TXRTSE        0x00000002
 198 #define UARTMODIR_TXCTSE        0x00000001
 199
 200 #define UARTFIFO_TXEMPT         0x00800000
 201 #define UARTFIFO_RXEMPT         0x00400000
 202 #define UARTFIFO_TXOF           0x00020000
 203 #define UARTFIFO_RXUF           0x00010000
 204 #define UARTFIFO_TXFLUSH        0x00008000
 205 #define UARTFIFO_RXFLUSH        0x00004000
 206 #define UARTFIFO_TXOFE          0x00000200
 207 #define UARTFIFO_RXUFE          0x00000100
 208 #define UARTFIFO_TXFE           0x00000080
 209 #define UARTFIFO_FIFOSIZE_MASK  0x7
 210 #define UARTFIFO_TXSIZE_OFF     4
 211 #define UARTFIFO_RXFE           0x00000008
 212 #define UARTFIFO_RXSIZE_OFF     0
 213 #define UARTFIFO_DEPTH(x)       (0x1 << ((x) ? ((x) + 1) : 0))
 214
 215 #define UARTWATER_COUNT_MASK    0xff
 216 #define UARTWATER_TXCNT_OFF     8
 217 #define UARTWATER_RXCNT_OFF     24
 218 #define UARTWATER_WATER_MASK    0xff
 219 #define UARTWATER_TXWATER_OFF   0
 220 #define UARTWATER_RXWATER_OFF   16
 221
 222 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 223 #define DMA_RX_TIMEOUT          (10)
 224
 225 #define DRIVER_NAME     "fsl-lpuart"
 226 #define DEV_NAME        "ttyLP"
 227 #define UART_NR         6
 228
 229 /* IMX lpuart has four extra unused regs located at the beginning */
 230 #define IMX_REG_OFF     0x10
 231
 232 enum lpuart_type {
 233         VF610_LPUART,
 234         LS1021A_LPUART,
 235         LS1028A_LPUART,
 236         IMX7ULP_LPUART,
 237         IMX8QXP_LPUART,
 238 };
 239
 240 struct lpuart_port {
 241         struct uart_port        port;
 242         enum lpuart_type        devtype;
 243         struct clk              *ipg_clk;
 244         struct clk              *baud_clk;
 245         unsigned int            txfifo_size;
 246         unsigned int            rxfifo_size;
 247
 248         bool                    lpuart_dma_tx_use;
 249         bool                    lpuart_dma_rx_use;
 250         struct dma_chan         *dma_tx_chan;
 251         struct dma_chan         *dma_rx_chan;
 252         struct dma_async_tx_descriptor  *dma_tx_desc;
 253         struct dma_async_tx_descriptor  *dma_rx_desc;
 254         dma_cookie_t            dma_tx_cookie;
 255         dma_cookie_t            dma_rx_cookie;
 256         unsigned int            dma_tx_bytes;
 257         unsigned int            dma_rx_bytes;
 258         bool                    dma_tx_in_progress;
 259         unsigned int            dma_rx_timeout;
 260         struct timer_list       lpuart_timer;
 261         struct scatterlist      rx_sgl, tx_sgl[2];
 262         struct circ_buf         rx_ring;
 263         int                     rx_dma_rng_buf_len;
 264         unsigned int            dma_tx_nents;
 265         wait_queue_head_t       dma_wait;
 266 };
 267
 268 struct lpuart_soc_data {
 269         enum lpuart_type devtype;
 270         char iotype;
 271         u8 reg_off;
 272 };
 273
 274 static const struct lpuart_soc_data vf_data = {
 275         .devtype = VF610_LPUART,
 276         .iotype = UPIO_MEM,
 277 };
 278
 279 static const struct lpuart_soc_data ls1021a_data = {
 280         .devtype = LS1021A_LPUART,
 281         .iotype = UPIO_MEM32BE,
 282 };
 283
 284 static const struct lpuart_soc_data ls1028a_data = {
 285         .devtype = LS1028A_LPUART,
 286         .iotype = UPIO_MEM32,
 287 };
 288
 289 static struct lpuart_soc_data imx7ulp_data = {
 290         .devtype = IMX7ULP_LPUART,
 291         .iotype = UPIO_MEM32,
 292         .reg_off = IMX_REG_OFF,
 293 };
 294
 295 static struct lpuart_soc_data imx8qxp_data = {
 296         .devtype = IMX8QXP_LPUART,
 297         .iotype = UPIO_MEM32,
 298         .reg_off = IMX_REG_OFF,
 299 };
 300
 301 static const struct of_device_id lpuart_dt_ids[] = {
 302         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 303         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls1021a_data, },
 304         { .compatible = "fsl,ls1028a-lpuart",   .data = &ls1028a_data, },
 305         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx7ulp_data, },
 306         { .compatible = "fsl,imx8qxp-lpuart",   .data = &imx8qxp_data, },
 307         { /* sentinel */ }
 308 };
 309 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 310
 311 /* Forward declare this for the dma callbacks*/
 312 static void lpuart_dma_tx_complete(void *arg);
 313
 314 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
 315 {
 316         return (sport->devtype == LS1021A_LPUART ||
 317                 sport->devtype == LS1028A_LPUART);
 318 }
 319
 320 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
 321 {
 322         return sport->devtype == IMX8QXP_LPUART;
 323 }
 324
 325 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 326 {
 327         switch (port->iotype) {
 328         case UPIO_MEM32:
 329                 return readl(port->membase + off);
 330         case UPIO_MEM32BE:
 331                 return ioread32be(port->membase + off);
 332         default:
 333                 return 0;
 334         }
 335 }
 336
 337 static inline void lpuart32_write(struct uart_port *port, u32 val,
 338                                   u32 off)
 339 {
 340         switch (port->iotype) {
 341         case UPIO_MEM32:
 342                 writel(val, port->membase + off);
 343                 break;
 344         case UPIO_MEM32BE:
 345                 iowrite32be(val, port->membase + off);
 346                 break;
 347         }
 348 }
 349
 350 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
 351 {
 352         int ret = 0;
 353
 354         if (is_en) {
 355                 ret = clk_prepare_enable(sport->ipg_clk);
 356                 if (ret)
 357                         return ret;
 358
 359                 ret = clk_prepare_enable(sport->baud_clk);
 360                 if (ret) {
 361                         clk_disable_unprepare(sport->ipg_clk);
 362                         return ret;
 363                 }
 364         } else {
 365                 clk_disable_unprepare(sport->baud_clk);
 366                 clk_disable_unprepare(sport->ipg_clk);
 367         }
 368
 369         return 0;
 370 }
 371
 372 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
 373 {
 374         if (is_imx8qxp_lpuart(sport))
 375                 return clk_get_rate(sport->baud_clk);
 376
 377         return clk_get_rate(sport->ipg_clk);
 378 }
 379
 380 #define lpuart_enable_clks(x)   __lpuart_enable_clks(x, true)
 381 #define lpuart_disable_clks(x)  __lpuart_enable_clks(x, false)
 382
 383 static void lpuart_stop_tx(struct uart_port *port)
 384 {
 385         unsigned char temp;
 386
 387         temp = readb(port->membase + UARTCR2);
 388         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 389         writeb(temp, port->membase + UARTCR2);
 390 }
 391
 392 static void lpuart32_stop_tx(struct uart_port *port)
 393 {
 394         unsigned long temp;
 395
 396         temp = lpuart32_read(port, UARTCTRL);
 397         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 398         lpuart32_write(port, temp, UARTCTRL);
 399 }
 400
 401 static void lpuart_stop_rx(struct uart_port *port)
 402 {
 403         unsigned char temp;
 404
 405         temp = readb(port->membase + UARTCR2);
 406         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 407 }
 408
 409 static void lpuart32_stop_rx(struct uart_port *port)
 410 {
 411         unsigned long temp;
 412
 413         temp = lpuart32_read(port, UARTCTRL);
 414         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 415 }
 416
 417 static void lpuart_dma_tx(struct lpuart_port *sport)
 418 {
 419         struct circ_buf *xmit = &sport->port.state->xmit;
 420         struct scatterlist *sgl = sport->tx_sgl;
 421         struct device *dev = sport->port.dev;
 422         struct dma_chan *chan = sport->dma_tx_chan;
 423         int ret;
 424
 425         if (sport->dma_tx_in_progress)
 426                 return;
 427
 428         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 429
 430         if (xmit->tail < xmit->head || xmit->head == 0) {
 431                 sport->dma_tx_nents = 1;
 432                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 433         } else {
 434                 sport->dma_tx_nents = 2;
 435                 sg_init_table(sgl, 2);
 436                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 437                                 UART_XMIT_SIZE - xmit->tail);
 438                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 439         }
 440
 441         ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 442                          DMA_TO_DEVICE);
 443         if (!ret) {
 444                 dev_err(dev, "DMA mapping error for TX.\n");
 445                 return;
 446         }
 447
 448         sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
 449                                         ret, DMA_MEM_TO_DEV,
 450                                         DMA_PREP_INTERRUPT);
 451         if (!sport->dma_tx_desc) {
 452                 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 453                               DMA_TO_DEVICE);
 454                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 455                 return;
 456         }
 457
 458         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 459         sport->dma_tx_desc->callback_param = sport;
 460         sport->dma_tx_in_progress = true;
 461         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 462         dma_async_issue_pending(chan);
 463 }
 464
 465 static bool lpuart_stopped_or_empty(struct uart_port *port)
 466 {
 467         return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
 468 }
 469
 470 static void lpuart_dma_tx_complete(void *arg)
 471 {
 472         struct lpuart_port *sport = arg;
 473         struct scatterlist *sgl = &sport->tx_sgl[0];
 474         struct circ_buf *xmit = &sport->port.state->xmit;
 475         struct dma_chan *chan = sport->dma_tx_chan;
 476         unsigned long flags;
 477
 478         spin_lock_irqsave(&sport->port.lock, flags);
 479
 480         dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 481                      DMA_TO_DEVICE);
 482
 483         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 484
 485         sport->port.icount.tx += sport->dma_tx_bytes;
 486         sport->dma_tx_in_progress = false;
 487         spin_unlock_irqrestore(&sport->port.lock, flags);
 488
 489         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 490                 uart_write_wakeup(&sport->port);
 491
 492         if (waitqueue_active(&sport->dma_wait)) {
 493                 wake_up(&sport->dma_wait);
 494                 return;
 495         }
 496
 497         spin_lock_irqsave(&sport->port.lock, flags);
 498
 499         if (!lpuart_stopped_or_empty(&sport->port))
 500                 lpuart_dma_tx(sport);
 501
 502         spin_unlock_irqrestore(&sport->port.lock, flags);
 503 }
 504
 505 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
 506 {
 507         switch (sport->port.iotype) {
 508         case UPIO_MEM32:
 509                 return sport->port.mapbase + UARTDATA;
 510         case UPIO_MEM32BE:
 511                 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
 512         }
 513         return sport->port.mapbase + UARTDR;
 514 }
 515
 516 static int lpuart_dma_tx_request(struct uart_port *port)
 517 {
 518         struct lpuart_port *sport = container_of(port,
 519                                         struct lpuart_port, port);
 520         struct dma_slave_config dma_tx_sconfig = {};
 521         int ret;
 522
 523         dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
 524         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 525         dma_tx_sconfig.dst_maxburst = 1;
 526         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 527         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 528
 529         if (ret) {
 530                 dev_err(sport->port.dev,
 531                                 "DMA slave config failed, err = %d\n", ret);
 532                 return ret;
 533         }
 534
 535         return 0;
 536 }
 537
 538 static bool lpuart_is_32(struct lpuart_port *sport)
 539 {
 540         return sport->port.iotype == UPIO_MEM32 ||
 541                sport->port.iotype ==  UPIO_MEM32BE;
 542 }
 543
 544 static void lpuart_flush_buffer(struct uart_port *port)
 545 {
 546         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 547         struct dma_chan *chan = sport->dma_tx_chan;
 548         u32 val;
 549
 550         if (sport->lpuart_dma_tx_use) {
 551                 if (sport->dma_tx_in_progress) {
 552                         dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
 553                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 554                         sport->dma_tx_in_progress = false;
 555                 }
 556                 dmaengine_terminate_all(chan);
 557         }
 558
 559         if (lpuart_is_32(sport)) {
 560                 val = lpuart32_read(&sport->port, UARTFIFO);
 561                 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
 562                 lpuart32_write(&sport->port, val, UARTFIFO);
 563         } else {
 564                 val = readb(sport->port.membase + UARTCFIFO);
 565                 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
 566                 writeb(val, sport->port.membase + UARTCFIFO);
 567         }
 568 }
 569
 570 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
 571                                 u8 bit)
 572 {
 573         while (!(readb(port->membase + offset) & bit))
 574                 cpu_relax();
 575 }
 576
 577 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
 578                                   u32 bit)
 579 {
 580         while (!(lpuart32_read(port, offset) & bit))
 581                 cpu_relax();
 582 }
 583
 584 #if defined(CONFIG_CONSOLE_POLL)
 585
 586 static int lpuart_poll_init(struct uart_port *port)
 587 {
 588         struct lpuart_port *sport = container_of(port,
 589                                         struct lpuart_port, port);
 590         unsigned long flags;
 591         unsigned char temp;
 592
 593         sport->port.fifosize = 0;
 594
 595         spin_lock_irqsave(&sport->port.lock, flags);
 596         /* Disable Rx & Tx */
 597         writeb(0, sport->port.membase + UARTCR2);
 598
 599         temp = readb(sport->port.membase + UARTPFIFO);
 600         /* Enable Rx and Tx FIFO */
 601         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 602                         sport->port.membase + UARTPFIFO);
 603
 604         /* flush Tx and Rx FIFO */
 605         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 606                         sport->port.membase + UARTCFIFO);
 607
 608         /* explicitly clear RDRF */
 609         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 610                 readb(sport->port.membase + UARTDR);
 611                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 612         }
 613
 614         writeb(0, sport->port.membase + UARTTWFIFO);
 615         writeb(1, sport->port.membase + UARTRWFIFO);
 616
 617         /* Enable Rx and Tx */
 618         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 619         spin_unlock_irqrestore(&sport->port.lock, flags);
 620
 621         return 0;
 622 }
 623
 624 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 625 {
 626         /* drain */
 627         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
 628         writeb(c, port->membase + UARTDR);
 629 }
 630
 631 static int lpuart_poll_get_char(struct uart_port *port)
 632 {
 633         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 634                 return NO_POLL_CHAR;
 635
 636         return readb(port->membase + UARTDR);
 637 }
 638
 639 static int lpuart32_poll_init(struct uart_port *port)
 640 {
 641         unsigned long flags;
 642         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 643         u32 temp;
 644
 645         sport->port.fifosize = 0;
 646
 647         spin_lock_irqsave(&sport->port.lock, flags);
 648
 649         /* Disable Rx & Tx */
 650         lpuart32_write(&sport->port, 0, UARTCTRL);
 651
 652         temp = lpuart32_read(&sport->port, UARTFIFO);
 653
 654         /* Enable Rx and Tx FIFO */
 655         lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
 656
 657         /* flush Tx and Rx FIFO */
 658         lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
 659
 660         /* explicitly clear RDRF */
 661         if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
 662                 lpuart32_read(&sport->port, UARTDATA);
 663                 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
 664         }
 665
 666         /* Enable Rx and Tx */
 667         lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
 668         spin_unlock_irqrestore(&sport->port.lock, flags);
 669
 670         return 0;
 671 }
 672
 673 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
 674 {
 675         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
 676         lpuart32_write(port, c, UARTDATA);
 677 }
 678
 679 static int lpuart32_poll_get_char(struct uart_port *port)
 680 {
 681         if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
 682                 return NO_POLL_CHAR;
 683
 684         return lpuart32_read(port, UARTDATA);
 685 }
 686 #endif
 687
 688 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 689 {
 690         struct circ_buf *xmit = &sport->port.state->xmit;
 691
 692         if (sport->port.x_char) {
 693                 writeb(sport->port.x_char, sport->port.membase + UARTDR);
 694                 sport->port.icount.tx++;
 695                 sport->port.x_char = 0;
 696                 return;
 697         }
 698
 699         if (lpuart_stopped_or_empty(&sport->port)) {
 700                 lpuart_stop_tx(&sport->port);
 701                 return;
 702         }
 703
 704         while (!uart_circ_empty(xmit) &&
 705                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 706                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 707                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 708                 sport->port.icount.tx++;
 709         }
 710
 711         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 712                 uart_write_wakeup(&sport->port);
 713
 714         if (uart_circ_empty(xmit))
 715                 lpuart_stop_tx(&sport->port);
 716 }
 717
 718 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 719 {
 720         struct circ_buf *xmit = &sport->port.state->xmit;
 721         unsigned long txcnt;
 722
 723         if (sport->port.x_char) {
 724                 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 725                 sport->port.icount.tx++;
 726                 sport->port.x_char = 0;
 727                 return;
 728         }
 729
 730         if (lpuart_stopped_or_empty(&sport->port)) {
 731                 lpuart32_stop_tx(&sport->port);
 732                 return;
 733         }
 734
 735         txcnt = lpuart32_read(&sport->port, UARTWATER);
 736         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 737         txcnt &= UARTWATER_COUNT_MASK;
 738         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 739                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 740                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 741                 sport->port.icount.tx++;
 742                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 743                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 744                 txcnt &= UARTWATER_COUNT_MASK;
 745         }
 746
 747         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 748                 uart_write_wakeup(&sport->port);
 749
 750         if (uart_circ_empty(xmit))
 751                 lpuart32_stop_tx(&sport->port);
 752 }
 753
 754 static void lpuart_start_tx(struct uart_port *port)
 755 {
 756         struct lpuart_port *sport = container_of(port,
 757                         struct lpuart_port, port);
 758         unsigned char temp;
 759
 760         temp = readb(port->membase + UARTCR2);
 761         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 762
 763         if (sport->lpuart_dma_tx_use) {
 764                 if (!lpuart_stopped_or_empty(port))
 765                         lpuart_dma_tx(sport);
 766         } else {
 767                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 768                         lpuart_transmit_buffer(sport);
 769         }
 770 }
 771
 772 static void lpuart32_start_tx(struct uart_port *port)
 773 {
 774         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 775         unsigned long temp;
 776
 777         if (sport->lpuart_dma_tx_use) {
 778                 if (!lpuart_stopped_or_empty(port))
 779                         lpuart_dma_tx(sport);
 780         } else {
 781                 temp = lpuart32_read(port, UARTCTRL);
 782                 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 783
 784                 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 785                         lpuart32_transmit_buffer(sport);
 786         }
 787 }
 788
 789 /* return TIOCSER_TEMT when transmitter is not busy */
 790 static unsigned int lpuart_tx_empty(struct uart_port *port)
 791 {
 792         struct lpuart_port *sport = container_of(port,
 793                         struct lpuart_port, port);
 794         unsigned char sr1 = readb(port->membase + UARTSR1);
 795         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 796
 797         if (sport->dma_tx_in_progress)
 798                 return 0;
 799
 800         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 801                 return TIOCSER_TEMT;
 802
 803         return 0;
 804 }
 805
 806 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 807 {
 808         struct lpuart_port *sport = container_of(port,
 809                         struct lpuart_port, port);
 810         unsigned long stat = lpuart32_read(port, UARTSTAT);
 811         unsigned long sfifo = lpuart32_read(port, UARTFIFO);
 812
 813         if (sport->dma_tx_in_progress)
 814                 return 0;
 815
 816         if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
 817                 return TIOCSER_TEMT;
 818
 819         return 0;
 820 }
 821
 822 static void lpuart_txint(struct lpuart_port *sport)
 823 {
 824         unsigned long flags;
 825
 826         spin_lock_irqsave(&sport->port.lock, flags);
 827         lpuart_transmit_buffer(sport);
 828         spin_unlock_irqrestore(&sport->port.lock, flags);
 829 }
 830
 831 static void lpuart_rxint(struct lpuart_port *sport)
 832 {
 833         unsigned int flg, ignored = 0, overrun = 0;
 834         struct tty_port *port = &sport->port.state->port;
 835         unsigned long flags;
 836         unsigned char rx, sr;
 837
 838         spin_lock_irqsave(&sport->port.lock, flags);
 839
 840         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 841                 flg = TTY_NORMAL;
 842                 sport->port.icount.rx++;
 843                 /*
 844                  * to clear the FE, OR, NF, FE, PE flags,
 845                  * read SR1 then read DR
 846                  */
 847                 sr = readb(sport->port.membase + UARTSR1);
 848                 rx = readb(sport->port.membase + UARTDR);
 849
 850                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 851                         continue;
 852
 853                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 854                         if (sr & UARTSR1_PE)
 855                                 sport->port.icount.parity++;
 856                         else if (sr & UARTSR1_FE)
 857                                 sport->port.icount.frame++;
 858
 859                         if (sr & UARTSR1_OR)
 860                                 overrun++;
 861
 862                         if (sr & sport->port.ignore_status_mask) {
 863                                 if (++ignored > 100)
 864                                         goto out;
 865                                 continue;
 866                         }
 867
 868                         sr &= sport->port.read_status_mask;
 869
 870                         if (sr & UARTSR1_PE)
 871                                 flg = TTY_PARITY;
 872                         else if (sr & UARTSR1_FE)
 873                                 flg = TTY_FRAME;
 874
 875                         if (sr & UARTSR1_OR)
 876                                 flg = TTY_OVERRUN;
 877
 878                         sport->port.sysrq = 0;
 879                 }
 880
 881                 tty_insert_flip_char(port, rx, flg);
 882         }
 883
 884 out:
 885         if (overrun) {
 886                 sport->port.icount.overrun += overrun;
 887
 888                 /*
 889                  * Overruns cause FIFO pointers to become missaligned.
 890                  * Flushing the receive FIFO reinitializes the pointers.
 891                  */
 892                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
 893                 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
 894         }
 895
 896         spin_unlock_irqrestore(&sport->port.lock, flags);
 897
 898         tty_flip_buffer_push(port);
 899 }
 900
 901 static void lpuart32_txint(struct lpuart_port *sport)
 902 {
 903         unsigned long flags;
 904
 905         spin_lock_irqsave(&sport->port.lock, flags);
 906         lpuart32_transmit_buffer(sport);
 907         spin_unlock_irqrestore(&sport->port.lock, flags);
 908 }
 909
 910 static void lpuart32_rxint(struct lpuart_port *sport)
 911 {
 912         unsigned int flg, ignored = 0;
 913         struct tty_port *port = &sport->port.state->port;
 914         unsigned long flags;
 915         unsigned long rx, sr;
 916
 917         spin_lock_irqsave(&sport->port.lock, flags);
 918
 919         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 920                 flg = TTY_NORMAL;
 921                 sport->port.icount.rx++;
 922                 /*
 923                  * to clear the FE, OR, NF, FE, PE flags,
 924                  * read STAT then read DATA reg
 925                  */
 926                 sr = lpuart32_read(&sport->port, UARTSTAT);
 927                 rx = lpuart32_read(&sport->port, UARTDATA);
 928                 rx &= 0x3ff;
 929
 930                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 931                         continue;
 932
 933                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 934                         if (sr & UARTSTAT_PE)
 935                                 sport->port.icount.parity++;
 936                         else if (sr & UARTSTAT_FE)
 937                                 sport->port.icount.frame++;
 938
 939                         if (sr & UARTSTAT_OR)
 940                                 sport->port.icount.overrun++;
 941
 942                         if (sr & sport->port.ignore_status_mask) {
 943                                 if (++ignored > 100)
 944                                         goto out;
 945                                 continue;
 946                         }
 947
 948                         sr &= sport->port.read_status_mask;
 949
 950                         if (sr & UARTSTAT_PE)
 951                                 flg = TTY_PARITY;
 952                         else if (sr & UARTSTAT_FE)
 953                                 flg = TTY_FRAME;
 954
 955                         if (sr & UARTSTAT_OR)
 956                                 flg = TTY_OVERRUN;
 957
 958                         sport->port.sysrq = 0;
 959                 }
 960
 961                 tty_insert_flip_char(port, rx, flg);
 962         }
 963
 964 out:
 965         spin_unlock_irqrestore(&sport->port.lock, flags);
 966
 967         tty_flip_buffer_push(port);
 968 }
 969
 970 static irqreturn_t lpuart_int(int irq, void *dev_id)
 971 {
 972         struct lpuart_port *sport = dev_id;
 973         unsigned char sts;
 974
 975         sts = readb(sport->port.membase + UARTSR1);
 976
 977         /* SysRq, using dma, check for linebreak by framing err. */
 978         if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
 979                 readb(sport->port.membase + UARTDR);
 980                 uart_handle_break(&sport->port);
 981                 /* linebreak produces some garbage, removing it */
 982                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
 983                 return IRQ_HANDLED;
 984         }
 985
 986         if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
 987                 lpuart_rxint(sport);
 988
 989         if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
 990                 lpuart_txint(sport);
 991
 992         return IRQ_HANDLED;
 993 }
 994
 995 static irqreturn_t lpuart32_int(int irq, void *dev_id)
 996 {
 997         struct lpuart_port *sport = dev_id;
 998         unsigned long sts, rxcount;
 999
1000         sts = lpuart32_read(&sport->port, UARTSTAT);
1001         rxcount = lpuart32_read(&sport->port, UARTWATER);
1002         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1003
1004         if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1005                 lpuart32_rxint(sport);
1006
1007         if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1008                 lpuart32_txint(sport);
1009
1010         lpuart32_write(&sport->port, sts, UARTSTAT);
1011         return IRQ_HANDLED;
1012 }
1013
1014
1015 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1016                                              unsigned char *p, int count)
1017 {
1018         while (count--) {
1019                 if (*p && uart_handle_sysrq_char(port, *p))
1020                         return;
1021                 p++;
1022         }
1023 }
1024
1025 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1026 {
1027         struct circ_buf *ring = &sport->rx_ring;
1028         int count;
1029
1030         if (ring->head < ring->tail) {
1031                 count = sport->rx_sgl.length - ring->tail;
1032                 lpuart_handle_sysrq_chars(&sport->port,
1033                                           ring->buf + ring->tail, count);
1034                 ring->tail = 0;
1035         }
1036
1037         if (ring->head > ring->tail) {
1038                 count = ring->head - ring->tail;
1039                 lpuart_handle_sysrq_chars(&sport->port,
1040                                           ring->buf + ring->tail, count);
1041                 ring->tail = ring->head;
1042         }
1043 }
1044
1045 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1046 {
1047         struct tty_port *port = &sport->port.state->port;
1048         struct dma_tx_state state;
1049         enum dma_status dmastat;
1050         struct dma_chan *chan = sport->dma_rx_chan;
1051         struct circ_buf *ring = &sport->rx_ring;
1052         unsigned long flags;
1053         int count = 0;
1054
1055         if (lpuart_is_32(sport)) {
1056                 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1057
1058                 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1059                         /* Read DR to clear the error flags */
1060                         lpuart32_read(&sport->port, UARTDATA);
1061
1062                         if (sr & UARTSTAT_PE)
1063                                 sport->port.icount.parity++;
1064                         else if (sr & UARTSTAT_FE)
1065                                 sport->port.icount.frame++;
1066                 }
1067         } else {
1068                 unsigned char sr = readb(sport->port.membase + UARTSR1);
1069
1070                 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1071                         unsigned char cr2;
1072
1073                         /* Disable receiver during this operation... */
1074                         cr2 = readb(sport->port.membase + UARTCR2);
1075                         cr2 &= ~UARTCR2_RE;
1076                         writeb(cr2, sport->port.membase + UARTCR2);
1077
1078                         /* Read DR to clear the error flags */
1079                         readb(sport->port.membase + UARTDR);
1080
1081                         if (sr & UARTSR1_PE)
1082                                 sport->port.icount.parity++;
1083                         else if (sr & UARTSR1_FE)
1084                                 sport->port.icount.frame++;
1085                         /*
1086                          * At this point parity/framing error is
1087                          * cleared However, since the DMA already read
1088                          * the data register and we had to read it
1089                          * again after reading the status register to
1090                          * properly clear the flags, the FIFO actually
1091                          * underflowed... This requires a clearing of
1092                          * the FIFO...
1093                          */
1094                         if (readb(sport->port.membase + UARTSFIFO) &
1095                             UARTSFIFO_RXUF) {
1096                                 writeb(UARTSFIFO_RXUF,
1097                                        sport->port.membase + UARTSFIFO);
1098                                 writeb(UARTCFIFO_RXFLUSH,
1099                                        sport->port.membase + UARTCFIFO);
1100                         }
1101
1102                         cr2 |= UARTCR2_RE;
1103                         writeb(cr2, sport->port.membase + UARTCR2);
1104                 }
1105         }
1106
1107         async_tx_ack(sport->dma_rx_desc);
1108
1109         spin_lock_irqsave(&sport->port.lock, flags);
1110
1111         dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1112         if (dmastat == DMA_ERROR) {
1113                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1114                 spin_unlock_irqrestore(&sport->port.lock, flags);
1115                 return;
1116         }
1117
1118         /* CPU claims ownership of RX DMA buffer */
1119         dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1120                             DMA_FROM_DEVICE);
1121
1122         /*
1123          * ring->head points to the end of data already written by the DMA.
1124          * ring->tail points to the beginning of data to be read by the
1125          * framework.
1126          * The current transfer size should not be larger than the dma buffer
1127          * length.
1128          */
1129         ring->head = sport->rx_sgl.length - state.residue;
1130         BUG_ON(ring->head > sport->rx_sgl.length);
1131
1132         /*
1133          * Silent handling of keys pressed in the sysrq timeframe
1134          */
1135         if (sport->port.sysrq) {
1136                 lpuart_handle_sysrq(sport);
1137                 goto exit;
1138         }
1139
1140         /*
1141          * At this point ring->head may point to the first byte right after the
1142          * last byte of the dma buffer:
1143          * 0 <= ring->head <= sport->rx_sgl.length
1144          *
1145          * However ring->tail must always points inside the dma buffer:
1146          * 0 <= ring->tail <= sport->rx_sgl.length - 1
1147          *
1148          * Since we use a ring buffer, we have to handle the case
1149          * where head is lower than tail. In such a case, we first read from
1150          * tail to the end of the buffer then reset tail.
1151          */
1152         if (ring->head < ring->tail) {
1153                 count = sport->rx_sgl.length - ring->tail;
1154
1155                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1156                 ring->tail = 0;
1157                 sport->port.icount.rx += count;
1158         }
1159
1160         /* Finally we read data from tail to head */
1161         if (ring->tail < ring->head) {
1162                 count = ring->head - ring->tail;
1163                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1164                 /* Wrap ring->head if needed */
1165                 if (ring->head >= sport->rx_sgl.length)
1166                         ring->head = 0;
1167                 ring->tail = ring->head;
1168                 sport->port.icount.rx += count;
1169         }
1170
1171 exit:
1172         dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1173                                DMA_FROM_DEVICE);
1174
1175         spin_unlock_irqrestore(&sport->port.lock, flags);
1176
1177         tty_flip_buffer_push(port);
1178         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1179 }
1180
1181 static void lpuart_dma_rx_complete(void *arg)
1182 {
1183         struct lpuart_port *sport = arg;
1184
1185         lpuart_copy_rx_to_tty(sport);
1186 }
1187
1188 static void lpuart_timer_func(struct timer_list *t)
1189 {
1190         struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1191
1192         lpuart_copy_rx_to_tty(sport);
1193 }
1194
1195 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1196 {
1197         struct dma_slave_config dma_rx_sconfig = {};
1198         struct circ_buf *ring = &sport->rx_ring;
1199         int ret, nent;
1200         int bits, baud;
1201         struct tty_port *port = &sport->port.state->port;
1202         struct tty_struct *tty = port->tty;
1203         struct ktermios *termios = &tty->termios;
1204         struct dma_chan *chan = sport->dma_rx_chan;
1205
1206         baud = tty_get_baud_rate(tty);
1207
1208         bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1209         if (termios->c_cflag & PARENB)
1210                 bits++;
1211
1212         /*
1213          * Calculate length of one DMA buffer size to keep latency below
1214          * 10ms at any baud rate.
1215          */
1216         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1217         sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1218         if (sport->rx_dma_rng_buf_len < 16)
1219                 sport->rx_dma_rng_buf_len = 16;
1220
1221         ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1222         if (!ring->buf)
1223                 return -ENOMEM;
1224
1225         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1226         nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1227                           DMA_FROM_DEVICE);
1228
1229         if (!nent) {
1230                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1231                 return -EINVAL;
1232         }
1233
1234         dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1235         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1236         dma_rx_sconfig.src_maxburst = 1;
1237         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1238         ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1239
1240         if (ret < 0) {
1241                 dev_err(sport->port.dev,
1242                                 "DMA Rx slave config failed, err = %d\n", ret);
1243                 return ret;
1244         }
1245
1246         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1247                                  sg_dma_address(&sport->rx_sgl),
1248                                  sport->rx_sgl.length,
1249                                  sport->rx_sgl.length / 2,
1250                                  DMA_DEV_TO_MEM,
1251                                  DMA_PREP_INTERRUPT);
1252         if (!sport->dma_rx_desc) {
1253                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1254                 return -EFAULT;
1255         }
1256
1257         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1258         sport->dma_rx_desc->callback_param = sport;
1259         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1260         dma_async_issue_pending(chan);
1261
1262         if (lpuart_is_32(sport)) {
1263                 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1264
1265                 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1266         } else {
1267                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1268                        sport->port.membase + UARTCR5);
1269         }
1270
1271         return 0;
1272 }
1273
1274 static void lpuart_dma_rx_free(struct uart_port *port)
1275 {
1276         struct lpuart_port *sport = container_of(port,
1277                                         struct lpuart_port, port);
1278         struct dma_chan *chan = sport->dma_rx_chan;
1279
1280         dmaengine_terminate_all(chan);
1281         dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1282         kfree(sport->rx_ring.buf);
1283         sport->rx_ring.tail = 0;
1284         sport->rx_ring.head = 0;
1285         sport->dma_rx_desc = NULL;
1286         sport->dma_rx_cookie = -EINVAL;
1287 }
1288
1289 static int lpuart_config_rs485(struct uart_port *port,
1290                         struct serial_rs485 *rs485)
1291 {
1292         struct lpuart_port *sport = container_of(port,
1293                         struct lpuart_port, port);
1294
1295         u8 modem = readb(sport->port.membase + UARTMODEM) &
1296                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1297         writeb(modem, sport->port.membase + UARTMODEM);
1298
1299         /* clear unsupported configurations */
1300         rs485->delay_rts_before_send = 0;
1301         rs485->delay_rts_after_send = 0;
1302         rs485->flags &= ~SER_RS485_RX_DURING_TX;
1303
1304         if (rs485->flags & SER_RS485_ENABLED) {
1305                 /* Enable auto RS-485 RTS mode */
1306                 modem |= UARTMODEM_TXRTSE;
1307
1308                 /*
1309                  * RTS needs to be logic HIGH either during transfer _or_ after
1310                  * transfer, other variants are not supported by the hardware.
1311                  */
1312
1313                 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1314                                 SER_RS485_RTS_AFTER_SEND)))
1315                         rs485->flags |= SER_RS485_RTS_ON_SEND;
1316
1317                 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1318                                 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1319                         rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1320
1321                 /*
1322                  * The hardware defaults to RTS logic HIGH while transfer.
1323                  * Switch polarity in case RTS shall be logic HIGH
1324                  * after transfer.
1325                  * Note: UART is assumed to be active high.
1326                  */
1327                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1328                         modem &= ~UARTMODEM_TXRTSPOL;
1329                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1330                         modem |= UARTMODEM_TXRTSPOL;
1331         }
1332
1333         /* Store the new configuration */
1334         sport->port.rs485 = *rs485;
1335
1336         writeb(modem, sport->port.membase + UARTMODEM);
1337         return 0;
1338 }
1339
1340 static int lpuart32_config_rs485(struct uart_port *port,
1341                         struct serial_rs485 *rs485)
1342 {
1343         struct lpuart_port *sport = container_of(port,
1344                         struct lpuart_port, port);
1345
1346         unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1347                                 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1348         lpuart32_write(&sport->port, modem, UARTMODIR);
1349
1350         /* clear unsupported configurations */
1351         rs485->delay_rts_before_send = 0;
1352         rs485->delay_rts_after_send = 0;
1353         rs485->flags &= ~SER_RS485_RX_DURING_TX;
1354
1355         if (rs485->flags & SER_RS485_ENABLED) {
1356                 /* Enable auto RS-485 RTS mode */
1357                 modem |= UARTMODEM_TXRTSE;
1358
1359                 /*
1360                  * RTS needs to be logic HIGH either during transfer _or_ after
1361                  * transfer, other variants are not supported by the hardware.
1362                  */
1363
1364                 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1365                                 SER_RS485_RTS_AFTER_SEND)))
1366                         rs485->flags |= SER_RS485_RTS_ON_SEND;
1367
1368                 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1369                                 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1370                         rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1371
1372                 /*
1373                  * The hardware defaults to RTS logic HIGH while transfer.
1374                  * Switch polarity in case RTS shall be logic HIGH
1375                  * after transfer.
1376                  * Note: UART is assumed to be active high.
1377                  */
1378                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1379                         modem |= UARTMODEM_TXRTSPOL;
1380                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1381                         modem &= ~UARTMODEM_TXRTSPOL;
1382         }
1383
1384         /* Store the new configuration */
1385         sport->port.rs485 = *rs485;
1386
1387         lpuart32_write(&sport->port, modem, UARTMODIR);
1388         return 0;
1389 }
1390
1391 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1392 {
1393         unsigned int temp = 0;
1394         unsigned char reg;
1395
1396         reg = readb(port->membase + UARTMODEM);
1397         if (reg & UARTMODEM_TXCTSE)
1398                 temp |= TIOCM_CTS;
1399
1400         if (reg & UARTMODEM_RXRTSE)
1401                 temp |= TIOCM_RTS;
1402
1403         return temp;
1404 }
1405
1406 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1407 {
1408         return 0;
1409 }
1410
1411 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1412 {
1413         unsigned char temp;
1414         struct lpuart_port *sport = container_of(port,
1415                                 struct lpuart_port, port);
1416
1417         /* Make sure RXRTSE bit is not set when RS485 is enabled */
1418         if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1419                 temp = readb(sport->port.membase + UARTMODEM) &
1420                         ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1421
1422                 if (mctrl & TIOCM_RTS)
1423                         temp |= UARTMODEM_RXRTSE;
1424
1425                 if (mctrl & TIOCM_CTS)
1426                         temp |= UARTMODEM_TXCTSE;
1427
1428                 writeb(temp, port->membase + UARTMODEM);
1429         }
1430 }
1431
1432 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1433 {
1434
1435 }
1436
1437 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1438 {
1439         unsigned char temp;
1440
1441         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1442
1443         if (break_state != 0)
1444                 temp |= UARTCR2_SBK;
1445
1446         writeb(temp, port->membase + UARTCR2);
1447 }
1448
1449 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1450 {
1451         unsigned long temp;
1452
1453         temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1454
1455         if (break_state != 0)
1456                 temp |= UARTCTRL_SBK;
1457
1458         lpuart32_write(port, temp, UARTCTRL);
1459 }
1460
1461 static void lpuart_setup_watermark(struct lpuart_port *sport)
1462 {
1463         unsigned char val, cr2;
1464         unsigned char cr2_saved;
1465
1466         cr2 = readb(sport->port.membase + UARTCR2);
1467         cr2_saved = cr2;
1468         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1469                         UARTCR2_RIE | UARTCR2_RE);
1470         writeb(cr2, sport->port.membase + UARTCR2);
1471
1472         val = readb(sport->port.membase + UARTPFIFO);
1473         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1474                         sport->port.membase + UARTPFIFO);
1475
1476         /* flush Tx and Rx FIFO */
1477         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1478                         sport->port.membase + UARTCFIFO);
1479
1480         /* explicitly clear RDRF */
1481         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1482                 readb(sport->port.membase + UARTDR);
1483                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1484         }
1485
1486         writeb(0, sport->port.membase + UARTTWFIFO);
1487         writeb(1, sport->port.membase + UARTRWFIFO);
1488
1489         /* Restore cr2 */
1490         writeb(cr2_saved, sport->port.membase + UARTCR2);
1491 }
1492
1493 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1494 {
1495         unsigned char cr2;
1496
1497         lpuart_setup_watermark(sport);
1498
1499         cr2 = readb(sport->port.membase + UARTCR2);
1500         cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1501         writeb(cr2, sport->port.membase + UARTCR2);
1502 }
1503
1504 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1505 {
1506         unsigned long val, ctrl;
1507         unsigned long ctrl_saved;
1508
1509         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1510         ctrl_saved = ctrl;
1511         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1512                         UARTCTRL_RIE | UARTCTRL_RE);
1513         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1514
1515         /* enable FIFO mode */
1516         val = lpuart32_read(&sport->port, UARTFIFO);
1517         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1518         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1519         lpuart32_write(&sport->port, val, UARTFIFO);
1520
1521         /* set the watermark */
1522         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1523         lpuart32_write(&sport->port, val, UARTWATER);
1524
1525         /* Restore cr2 */
1526         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1527 }
1528
1529 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1530 {
1531         u32 temp;
1532
1533         lpuart32_setup_watermark(sport);
1534
1535         temp = lpuart32_read(&sport->port, UARTCTRL);
1536         temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1537         lpuart32_write(&sport->port, temp, UARTCTRL);
1538 }
1539
1540 static void rx_dma_timer_init(struct lpuart_port *sport)
1541 {
1542         timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1543         sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1544         add_timer(&sport->lpuart_timer);
1545 }
1546
1547 static void lpuart_request_dma(struct lpuart_port *sport)
1548 {
1549         sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1550         if (IS_ERR(sport->dma_tx_chan)) {
1551                 dev_dbg_once(sport->port.dev,
1552                              "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1553                              PTR_ERR(sport->dma_tx_chan));
1554                 sport->dma_tx_chan = NULL;
1555         }
1556
1557         sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1558         if (IS_ERR(sport->dma_rx_chan)) {
1559                 dev_dbg_once(sport->port.dev,
1560                              "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1561                              PTR_ERR(sport->dma_rx_chan));
1562                 sport->dma_rx_chan = NULL;
1563         }
1564 }
1565
1566 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1567 {
1568         u32 uartbaud;
1569         int ret;
1570
1571         if (uart_console(&sport->port))
1572                 goto err;
1573
1574         if (!sport->dma_tx_chan)
1575                 goto err;
1576
1577         ret = lpuart_dma_tx_request(&sport->port);
1578         if (ret)
1579                 goto err;
1580
1581         init_waitqueue_head(&sport->dma_wait);
1582         sport->lpuart_dma_tx_use = true;
1583         if (lpuart_is_32(sport)) {
1584                 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1585                 lpuart32_write(&sport->port,
1586                                uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1587         } else {
1588                 writeb(readb(sport->port.membase + UARTCR5) |
1589                        UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1590         }
1591
1592         return;
1593
1594 err:
1595         sport->lpuart_dma_tx_use = false;
1596 }
1597
1598 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1599 {
1600         int ret;
1601         unsigned char cr3;
1602
1603         if (uart_console(&sport->port))
1604                 goto err;
1605
1606         if (!sport->dma_rx_chan)
1607                 goto err;
1608
1609         ret = lpuart_start_rx_dma(sport);
1610         if (ret)
1611                 goto err;
1612
1613         /* set Rx DMA timeout */
1614         sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1615         if (!sport->dma_rx_timeout)
1616                 sport->dma_rx_timeout = 1;
1617
1618         sport->lpuart_dma_rx_use = true;
1619         rx_dma_timer_init(sport);
1620
1621         if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1622                 cr3 = readb(sport->port.membase + UARTCR3);
1623                 cr3 |= UARTCR3_FEIE;
1624                 writeb(cr3, sport->port.membase + UARTCR3);
1625         }
1626
1627         return;
1628
1629 err:
1630         sport->lpuart_dma_rx_use = false;
1631 }
1632
1633 static int lpuart_startup(struct uart_port *port)
1634 {
1635         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1636         unsigned long flags;
1637         unsigned char temp;
1638
1639         /* determine FIFO size and enable FIFO mode */
1640         temp = readb(sport->port.membase + UARTPFIFO);
1641
1642         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1643                                             UARTPFIFO_FIFOSIZE_MASK);
1644         sport->port.fifosize = sport->txfifo_size;
1645
1646         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1647                                             UARTPFIFO_FIFOSIZE_MASK);
1648
1649         lpuart_request_dma(sport);
1650
1651         spin_lock_irqsave(&sport->port.lock, flags);
1652
1653         lpuart_setup_watermark_enable(sport);
1654
1655         lpuart_rx_dma_startup(sport);
1656         lpuart_tx_dma_startup(sport);
1657
1658         spin_unlock_irqrestore(&sport->port.lock, flags);
1659
1660         return 0;
1661 }
1662
1663 static void lpuart32_configure(struct lpuart_port *sport)
1664 {
1665         unsigned long temp;
1666
1667         if (sport->lpuart_dma_rx_use) {
1668                 /* RXWATER must be 0 */
1669                 temp = lpuart32_read(&sport->port, UARTWATER);
1670                 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1671                 lpuart32_write(&sport->port, temp, UARTWATER);
1672         }
1673         temp = lpuart32_read(&sport->port, UARTCTRL);
1674         if (!sport->lpuart_dma_rx_use)
1675                 temp |= UARTCTRL_RIE;
1676         if (!sport->lpuart_dma_tx_use)
1677                 temp |= UARTCTRL_TIE;
1678         lpuart32_write(&sport->port, temp, UARTCTRL);
1679 }
1680
1681 static int lpuart32_startup(struct uart_port *port)
1682 {
1683         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1684         unsigned long flags;
1685         unsigned long temp;
1686
1687         /* determine FIFO size */
1688         temp = lpuart32_read(&sport->port, UARTFIFO);
1689
1690         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1691                                             UARTFIFO_FIFOSIZE_MASK);
1692         sport->port.fifosize = sport->txfifo_size;
1693
1694         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1695                                             UARTFIFO_FIFOSIZE_MASK);
1696
1697         /*
1698          * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1699          * Although they support the RX/TXSIZE fields, their encoding is
1700          * different. Eg the reference manual states 0b101 is 16 words.
1701          */
1702         if (is_layerscape_lpuart(sport)) {
1703                 sport->rxfifo_size = 16;
1704                 sport->txfifo_size = 16;
1705                 sport->port.fifosize = sport->txfifo_size;
1706         }
1707
1708         lpuart_request_dma(sport);
1709
1710         spin_lock_irqsave(&sport->port.lock, flags);
1711
1712         lpuart32_setup_watermark_enable(sport);
1713
1714         lpuart_rx_dma_startup(sport);
1715         lpuart_tx_dma_startup(sport);
1716
1717         lpuart32_configure(sport);
1718
1719         spin_unlock_irqrestore(&sport->port.lock, flags);
1720         return 0;
1721 }
1722
1723 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1724 {
1725         if (sport->lpuart_dma_rx_use) {
1726                 del_timer_sync(&sport->lpuart_timer);
1727                 lpuart_dma_rx_free(&sport->port);
1728                 sport->lpuart_dma_rx_use = false;
1729         }
1730
1731         if (sport->lpuart_dma_tx_use) {
1732                 if (wait_event_interruptible(sport->dma_wait,
1733                         !sport->dma_tx_in_progress) != false) {
1734                         sport->dma_tx_in_progress = false;
1735                         dmaengine_terminate_all(sport->dma_tx_chan);
1736                 }
1737                 sport->lpuart_dma_tx_use = false;
1738         }
1739
1740         if (sport->dma_tx_chan)
1741                 dma_release_channel(sport->dma_tx_chan);
1742         if (sport->dma_rx_chan)
1743                 dma_release_channel(sport->dma_rx_chan);
1744 }
1745
1746 static void lpuart_shutdown(struct uart_port *port)
1747 {
1748         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1749         unsigned char temp;
1750         unsigned long flags;
1751
1752         spin_lock_irqsave(&port->lock, flags);
1753
1754         /* disable Rx/Tx and interrupts */
1755         temp = readb(port->membase + UARTCR2);
1756         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1757                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1758         writeb(temp, port->membase + UARTCR2);
1759
1760         spin_unlock_irqrestore(&port->lock, flags);
1761
1762         lpuart_dma_shutdown(sport);
1763 }
1764
1765 static void lpuart32_shutdown(struct uart_port *port)
1766 {
1767         struct lpuart_port *sport =
1768                 container_of(port, struct lpuart_port, port);
1769         unsigned long temp;
1770         unsigned long flags;
1771
1772         spin_lock_irqsave(&port->lock, flags);
1773
1774         /* disable Rx/Tx and interrupts */
1775         temp = lpuart32_read(port, UARTCTRL);
1776         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1777                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1778         lpuart32_write(port, temp, UARTCTRL);
1779
1780         spin_unlock_irqrestore(&port->lock, flags);
1781
1782         lpuart_dma_shutdown(sport);
1783 }
1784
1785 static void
1786 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1787                    struct ktermios *old)
1788 {
1789         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1790         unsigned long flags;
1791         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1792         unsigned int  baud;
1793         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1794         unsigned int sbr, brfa;
1795
1796         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1797         old_cr2 = readb(sport->port.membase + UARTCR2);
1798         cr3 = readb(sport->port.membase + UARTCR3);
1799         cr4 = readb(sport->port.membase + UARTCR4);
1800         bdh = readb(sport->port.membase + UARTBDH);
1801         modem = readb(sport->port.membase + UARTMODEM);
1802         /*
1803          * only support CS8 and CS7, and for CS7 must enable PE.
1804          * supported mode:
1805          *  - (7,e/o,1)
1806          *  - (8,n,1)
1807          *  - (8,m/s,1)
1808          *  - (8,e/o,1)
1809          */
1810         while ((termios->c_cflag & CSIZE) != CS8 &&
1811                 (termios->c_cflag & CSIZE) != CS7) {
1812                 termios->c_cflag &= ~CSIZE;
1813                 termios->c_cflag |= old_csize;
1814                 old_csize = CS8;
1815         }
1816
1817         if ((termios->c_cflag & CSIZE) == CS8 ||
1818                 (termios->c_cflag & CSIZE) == CS7)
1819                 cr1 = old_cr1 & ~UARTCR1_M;
1820
1821         if (termios->c_cflag & CMSPAR) {
1822                 if ((termios->c_cflag & CSIZE) != CS8) {
1823                         termios->c_cflag &= ~CSIZE;
1824                         termios->c_cflag |= CS8;
1825                 }
1826                 cr1 |= UARTCR1_M;
1827         }
1828
1829         /*
1830          * When auto RS-485 RTS mode is enabled,
1831          * hardware flow control need to be disabled.
1832          */
1833         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1834                 termios->c_cflag &= ~CRTSCTS;
1835
1836         if (termios->c_cflag & CRTSCTS)
1837                 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1838         else
1839                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1840
1841         termios->c_cflag &= ~CSTOPB;
1842
1843         /* parity must be enabled when CS7 to match 8-bits format */
1844         if ((termios->c_cflag & CSIZE) == CS7)
1845                 termios->c_cflag |= PARENB;
1846
1847         if (termios->c_cflag & PARENB) {
1848                 if (termios->c_cflag & CMSPAR) {
1849                         cr1 &= ~UARTCR1_PE;
1850                         if (termios->c_cflag & PARODD)
1851                                 cr3 |= UARTCR3_T8;
1852                         else
1853                                 cr3 &= ~UARTCR3_T8;
1854                 } else {
1855                         cr1 |= UARTCR1_PE;
1856                         if ((termios->c_cflag & CSIZE) == CS8)
1857                                 cr1 |= UARTCR1_M;
1858                         if (termios->c_cflag & PARODD)
1859                                 cr1 |= UARTCR1_PT;
1860                         else
1861                                 cr1 &= ~UARTCR1_PT;
1862                 }
1863         } else {
1864                 cr1 &= ~UARTCR1_PE;
1865         }
1866
1867         /* ask the core to calculate the divisor */
1868         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1869
1870         /*
1871          * Need to update the Ring buffer length according to the selected
1872          * baud rate and restart Rx DMA path.
1873          *
1874          * Since timer function acqures sport->port.lock, need to stop before
1875          * acquring same lock because otherwise del_timer_sync() can deadlock.
1876          */
1877         if (old && sport->lpuart_dma_rx_use) {
1878                 del_timer_sync(&sport->lpuart_timer);
1879                 lpuart_dma_rx_free(&sport->port);
1880         }
1881
1882         spin_lock_irqsave(&sport->port.lock, flags);
1883
1884         sport->port.read_status_mask = 0;
1885         if (termios->c_iflag & INPCK)
1886                 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1887         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1888                 sport->port.read_status_mask |= UARTSR1_FE;
1889
1890         /* characters to ignore */
1891         sport->port.ignore_status_mask = 0;
1892         if (termios->c_iflag & IGNPAR)
1893                 sport->port.ignore_status_mask |= UARTSR1_PE;
1894         if (termios->c_iflag & IGNBRK) {
1895                 sport->port.ignore_status_mask |= UARTSR1_FE;
1896                 /*
1897                  * if we're ignoring parity and break indicators,
1898                  * ignore overruns too (for real raw support).
1899                  */
1900                 if (termios->c_iflag & IGNPAR)
1901                         sport->port.ignore_status_mask |= UARTSR1_OR;
1902         }
1903
1904         /* update the per-port timeout */
1905         uart_update_timeout(port, termios->c_cflag, baud);
1906
1907         /* wait transmit engin complete */
1908         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1909
1910         /* disable transmit and receive */
1911         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1912                         sport->port.membase + UARTCR2);
1913
1914         sbr = sport->port.uartclk / (16 * baud);
1915         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1916         bdh &= ~UARTBDH_SBR_MASK;
1917         bdh |= (sbr >> 8) & 0x1F;
1918         cr4 &= ~UARTCR4_BRFA_MASK;
1919         brfa &= UARTCR4_BRFA_MASK;
1920         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1921         writeb(bdh, sport->port.membase + UARTBDH);
1922         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1923         writeb(cr3, sport->port.membase + UARTCR3);
1924         writeb(cr1, sport->port.membase + UARTCR1);
1925         writeb(modem, sport->port.membase + UARTMODEM);
1926
1927         /* restore control register */
1928         writeb(old_cr2, sport->port.membase + UARTCR2);
1929
1930         if (old && sport->lpuart_dma_rx_use) {
1931                 if (!lpuart_start_rx_dma(sport))
1932                         rx_dma_timer_init(sport);
1933                 else
1934                         sport->lpuart_dma_rx_use = false;
1935         }
1936
1937         spin_unlock_irqrestore(&sport->port.lock, flags);
1938 }
1939
1940 static void __lpuart32_serial_setbrg(struct uart_port *port,
1941                                      unsigned int baudrate, bool use_rx_dma,
1942                                      bool use_tx_dma)
1943 {
1944         u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1945         u32 clk = port->uartclk;
1946
1947         /*
1948          * The idea is to use the best OSR (over-sampling rate) possible.
1949          * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1950          * Loop to find the best OSR value possible, one that generates minimum
1951          * baud_diff iterate through the rest of the supported values of OSR.
1952          *
1953          * Calculation Formula:
1954          *  Baud Rate = baud clock / ((OSR+1) × SBR)
1955          */
1956         baud_diff = baudrate;
1957         osr = 0;
1958         sbr = 0;
1959
1960         for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1961                 /* calculate the temporary sbr value  */
1962                 tmp_sbr = (clk / (baudrate * tmp_osr));
1963                 if (tmp_sbr == 0)
1964                         tmp_sbr = 1;
1965
1966                 /*
1967                  * calculate the baud rate difference based on the temporary
1968                  * osr and sbr values
1969                  */
1970                 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1971
1972                 /* select best values between sbr and sbr+1 */
1973                 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1974                 if (tmp_diff > (baudrate - tmp)) {
1975                         tmp_diff = baudrate - tmp;
1976                         tmp_sbr++;
1977                 }
1978
1979                 if (tmp_sbr > UARTBAUD_SBR_MASK)
1980                         continue;
1981
1982                 if (tmp_diff <= baud_diff) {
1983                         baud_diff = tmp_diff;
1984                         osr = tmp_osr;
1985                         sbr = tmp_sbr;
1986
1987                         if (!baud_diff)
1988                                 break;
1989                 }
1990         }
1991
1992         /* handle buadrate outside acceptable rate */
1993         if (baud_diff > ((baudrate / 100) * 3))
1994                 dev_warn(port->dev,
1995                          "unacceptable baud rate difference of more than 3%%\n");
1996
1997         tmp = lpuart32_read(port, UARTBAUD);
1998
1999         if ((osr > 3) && (osr < 8))
2000                 tmp |= UARTBAUD_BOTHEDGE;
2001
2002         tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2003         tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2004
2005         tmp &= ~UARTBAUD_SBR_MASK;
2006         tmp |= sbr & UARTBAUD_SBR_MASK;
2007
2008         if (!use_rx_dma)
2009                 tmp &= ~UARTBAUD_RDMAE;
2010         if (!use_tx_dma)
2011                 tmp &= ~UARTBAUD_TDMAE;
2012
2013         lpuart32_write(port, tmp, UARTBAUD);
2014 }
2015
2016 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2017                                    unsigned int baudrate)
2018 {
2019         __lpuart32_serial_setbrg(&sport->port, baudrate,
2020                                  sport->lpuart_dma_rx_use,
2021                                  sport->lpuart_dma_tx_use);
2022 }
2023
2024
2025 static void
2026 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2027                    struct ktermios *old)
2028 {
2029         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2030         unsigned long flags;
2031         unsigned long ctrl, old_ctrl, modem;
2032         unsigned int  baud;
2033         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2034
2035         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2036         modem = lpuart32_read(&sport->port, UARTMODIR);
2037         /*
2038          * only support CS8 and CS7, and for CS7 must enable PE.
2039          * supported mode:
2040          *  - (7,e/o,1)
2041          *  - (8,n,1)
2042          *  - (8,m/s,1)
2043          *  - (8,e/o,1)
2044          */
2045         while ((termios->c_cflag & CSIZE) != CS8 &&
2046                 (termios->c_cflag & CSIZE) != CS7) {
2047                 termios->c_cflag &= ~CSIZE;
2048                 termios->c_cflag |= old_csize;
2049                 old_csize = CS8;
2050         }
2051
2052         if ((termios->c_cflag & CSIZE) == CS8 ||
2053                 (termios->c_cflag & CSIZE) == CS7)
2054                 ctrl = old_ctrl & ~UARTCTRL_M;
2055
2056         if (termios->c_cflag & CMSPAR) {
2057                 if ((termios->c_cflag & CSIZE) != CS8) {
2058                         termios->c_cflag &= ~CSIZE;
2059                         termios->c_cflag |= CS8;
2060                 }
2061                 ctrl |= UARTCTRL_M;
2062         }
2063
2064         /*
2065          * When auto RS-485 RTS mode is enabled,
2066          * hardware flow control need to be disabled.
2067          */
2068         if (sport->port.rs485.flags & SER_RS485_ENABLED)
2069                 termios->c_cflag &= ~CRTSCTS;
2070
2071         if (termios->c_cflag & CRTSCTS) {
2072                 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2073         } else {
2074                 termios->c_cflag &= ~CRTSCTS;
2075                 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2076         }
2077
2078         if (termios->c_cflag & CSTOPB)
2079                 termios->c_cflag &= ~CSTOPB;
2080
2081         /* parity must be enabled when CS7 to match 8-bits format */
2082         if ((termios->c_cflag & CSIZE) == CS7)
2083                 termios->c_cflag |= PARENB;
2084
2085         if ((termios->c_cflag & PARENB)) {
2086                 if (termios->c_cflag & CMSPAR) {
2087                         ctrl &= ~UARTCTRL_PE;
2088                         ctrl |= UARTCTRL_M;
2089                 } else {
2090                         ctrl |= UARTCTRL_PE;
2091                         if ((termios->c_cflag & CSIZE) == CS8)
2092                                 ctrl |= UARTCTRL_M;
2093                         if (termios->c_cflag & PARODD)
2094                                 ctrl |= UARTCTRL_PT;
2095                         else
2096                                 ctrl &= ~UARTCTRL_PT;
2097                 }
2098         } else {
2099                 ctrl &= ~UARTCTRL_PE;
2100         }
2101
2102         /* ask the core to calculate the divisor */
2103         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2104
2105         /*
2106          * Need to update the Ring buffer length according to the selected
2107          * baud rate and restart Rx DMA path.
2108          *
2109          * Since timer function acqures sport->port.lock, need to stop before
2110          * acquring same lock because otherwise del_timer_sync() can deadlock.
2111          */
2112         if (old && sport->lpuart_dma_rx_use) {
2113                 del_timer_sync(&sport->lpuart_timer);
2114                 lpuart_dma_rx_free(&sport->port);
2115         }
2116
2117         spin_lock_irqsave(&sport->port.lock, flags);
2118
2119         sport->port.read_status_mask = 0;
2120         if (termios->c_iflag & INPCK)
2121                 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2122         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2123                 sport->port.read_status_mask |= UARTSTAT_FE;
2124
2125         /* characters to ignore */
2126         sport->port.ignore_status_mask = 0;
2127         if (termios->c_iflag & IGNPAR)
2128                 sport->port.ignore_status_mask |= UARTSTAT_PE;
2129         if (termios->c_iflag & IGNBRK) {
2130                 sport->port.ignore_status_mask |= UARTSTAT_FE;
2131                 /*
2132                  * if we're ignoring parity and break indicators,
2133                  * ignore overruns too (for real raw support).
2134                  */
2135                 if (termios->c_iflag & IGNPAR)
2136                         sport->port.ignore_status_mask |= UARTSTAT_OR;
2137         }
2138
2139         /* update the per-port timeout */
2140         uart_update_timeout(port, termios->c_cflag, baud);
2141
2142         /* wait transmit engin complete */
2143         lpuart32_write(&sport->port, 0, UARTMODIR);
2144         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2145
2146         /* disable transmit and receive */
2147         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2148                        UARTCTRL);
2149
2150         lpuart32_serial_setbrg(sport, baud);
2151         lpuart32_write(&sport->port, modem, UARTMODIR);
2152         lpuart32_write(&sport->port, ctrl, UARTCTRL);
2153         /* restore control register */
2154
2155         if (old && sport->lpuart_dma_rx_use) {
2156                 if (!lpuart_start_rx_dma(sport))
2157                         rx_dma_timer_init(sport);
2158                 else
2159                         sport->lpuart_dma_rx_use = false;
2160         }
2161
2162         spin_unlock_irqrestore(&sport->port.lock, flags);
2163 }
2164
2165 static const char *lpuart_type(struct uart_port *port)
2166 {
2167         return "FSL_LPUART";
2168 }
2169
2170 static void lpuart_release_port(struct uart_port *port)
2171 {
2172         /* nothing to do */
2173 }
2174
2175 static int lpuart_request_port(struct uart_port *port)
2176 {
2177         return  0;
2178 }
2179
2180 /* configure/autoconfigure the port */
2181 static void lpuart_config_port(struct uart_port *port, int flags)
2182 {
2183         if (flags & UART_CONFIG_TYPE)
2184                 port->type = PORT_LPUART;
2185 }
2186
2187 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2188 {
2189         int ret = 0;
2190
2191         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2192                 ret = -EINVAL;
2193         if (port->irq != ser->irq)
2194                 ret = -EINVAL;
2195         if (ser->io_type != UPIO_MEM)
2196                 ret = -EINVAL;
2197         if (port->uartclk / 16 != ser->baud_base)
2198                 ret = -EINVAL;
2199         if (port->iobase != ser->port)
2200                 ret = -EINVAL;
2201         if (ser->hub6 != 0)
2202                 ret = -EINVAL;
2203         return ret;
2204 }
2205
2206 static const struct uart_ops lpuart_pops = {
2207         .tx_empty       = lpuart_tx_empty,
2208         .set_mctrl      = lpuart_set_mctrl,
2209         .get_mctrl      = lpuart_get_mctrl,
2210         .stop_tx        = lpuart_stop_tx,
2211         .start_tx       = lpuart_start_tx,
2212         .stop_rx        = lpuart_stop_rx,
2213         .break_ctl      = lpuart_break_ctl,
2214         .startup        = lpuart_startup,
2215         .shutdown       = lpuart_shutdown,
2216         .set_termios    = lpuart_set_termios,
2217         .type           = lpuart_type,
2218         .request_port   = lpuart_request_port,
2219         .release_port   = lpuart_release_port,
2220         .config_port    = lpuart_config_port,
2221         .verify_port    = lpuart_verify_port,
2222         .flush_buffer   = lpuart_flush_buffer,
2223 #if defined(CONFIG_CONSOLE_POLL)
2224         .poll_init      = lpuart_poll_init,
2225         .poll_get_char  = lpuart_poll_get_char,
2226         .poll_put_char  = lpuart_poll_put_char,
2227 #endif
2228 };
2229
2230 static const struct uart_ops lpuart32_pops = {
2231         .tx_empty       = lpuart32_tx_empty,
2232         .set_mctrl      = lpuart32_set_mctrl,
2233         .get_mctrl      = lpuart32_get_mctrl,
2234         .stop_tx        = lpuart32_stop_tx,
2235         .start_tx       = lpuart32_start_tx,
2236         .stop_rx        = lpuart32_stop_rx,
2237         .break_ctl      = lpuart32_break_ctl,
2238         .startup        = lpuart32_startup,
2239         .shutdown       = lpuart32_shutdown,
2240         .set_termios    = lpuart32_set_termios,
2241         .type           = lpuart_type,
2242         .request_port   = lpuart_request_port,
2243         .release_port   = lpuart_release_port,
2244         .config_port    = lpuart_config_port,
2245         .verify_port    = lpuart_verify_port,
2246         .flush_buffer   = lpuart_flush_buffer,
2247 #if defined(CONFIG_CONSOLE_POLL)
2248         .poll_init      = lpuart32_poll_init,
2249         .poll_get_char  = lpuart32_poll_get_char,
2250         .poll_put_char  = lpuart32_poll_put_char,
2251 #endif
2252 };
2253
2254 static struct lpuart_port *lpuart_ports[UART_NR];
2255
2256 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2257 static void lpuart_console_putchar(struct uart_port *port, int ch)
2258 {
2259         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2260         writeb(ch, port->membase + UARTDR);
2261 }
2262
2263 static void lpuart32_console_putchar(struct uart_port *port, int ch)
2264 {
2265         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2266         lpuart32_write(port, ch, UARTDATA);
2267 }
2268
2269 static void
2270 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2271 {
2272         struct lpuart_port *sport = lpuart_ports[co->index];
2273         unsigned char  old_cr2, cr2;
2274         unsigned long flags;
2275         int locked = 1;
2276
2277         if (sport->port.sysrq || oops_in_progress)
2278                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2279         else
2280                 spin_lock_irqsave(&sport->port.lock, flags);
2281
2282         /* first save CR2 and then disable interrupts */
2283         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2284         cr2 |= UARTCR2_TE | UARTCR2_RE;
2285         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2286         writeb(cr2, sport->port.membase + UARTCR2);
2287
2288         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2289
2290         /* wait for transmitter finish complete and restore CR2 */
2291         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2292
2293         writeb(old_cr2, sport->port.membase + UARTCR2);
2294
2295         if (locked)
2296                 spin_unlock_irqrestore(&sport->port.lock, flags);
2297 }
2298
2299 static void
2300 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2301 {
2302         struct lpuart_port *sport = lpuart_ports[co->index];
2303         unsigned long  old_cr, cr;
2304         unsigned long flags;
2305         int locked = 1;
2306
2307         if (sport->port.sysrq || oops_in_progress)
2308                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2309         else
2310                 spin_lock_irqsave(&sport->port.lock, flags);
2311
2312         /* first save CR2 and then disable interrupts */
2313         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2314         cr |= UARTCTRL_TE | UARTCTRL_RE;
2315         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2316         lpuart32_write(&sport->port, cr, UARTCTRL);
2317
2318         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2319
2320         /* wait for transmitter finish complete and restore CR2 */
2321         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2322
2323         lpuart32_write(&sport->port, old_cr, UARTCTRL);
2324
2325         if (locked)
2326                 spin_unlock_irqrestore(&sport->port.lock, flags);
2327 }
2328
2329 /*
2330  * if the port was already initialised (eg, by a boot loader),
2331  * try to determine the current setup.
2332  */
2333 static void __init
2334 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2335                            int *parity, int *bits)
2336 {
2337         unsigned char cr, bdh, bdl, brfa;
2338         unsigned int sbr, uartclk, baud_raw;
2339
2340         cr = readb(sport->port.membase + UARTCR2);
2341         cr &= UARTCR2_TE | UARTCR2_RE;
2342         if (!cr)
2343                 return;
2344
2345         /* ok, the port was enabled */
2346
2347         cr = readb(sport->port.membase + UARTCR1);
2348
2349         *parity = 'n';
2350         if (cr & UARTCR1_PE) {
2351                 if (cr & UARTCR1_PT)
2352                         *parity = 'o';
2353                 else
2354                         *parity = 'e';
2355         }
2356
2357         if (cr & UARTCR1_M)
2358                 *bits = 9;
2359         else
2360                 *bits = 8;
2361
2362         bdh = readb(sport->port.membase + UARTBDH);
2363         bdh &= UARTBDH_SBR_MASK;
2364         bdl = readb(sport->port.membase + UARTBDL);
2365         sbr = bdh;
2366         sbr <<= 8;
2367         sbr |= bdl;
2368         brfa = readb(sport->port.membase + UARTCR4);
2369         brfa &= UARTCR4_BRFA_MASK;
2370
2371         uartclk = lpuart_get_baud_clk_rate(sport);
2372         /*
2373          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2374          */
2375         baud_raw = uartclk / (16 * (sbr + brfa / 32));
2376
2377         if (*baud != baud_raw)
2378                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2379                                 "from %d to %d\n", baud_raw, *baud);
2380 }
2381
2382 static void __init
2383 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2384                            int *parity, int *bits)
2385 {
2386         unsigned long cr, bd;
2387         unsigned int sbr, uartclk, baud_raw;
2388
2389         cr = lpuart32_read(&sport->port, UARTCTRL);
2390         cr &= UARTCTRL_TE | UARTCTRL_RE;
2391         if (!cr)
2392                 return;
2393
2394         /* ok, the port was enabled */
2395
2396         cr = lpuart32_read(&sport->port, UARTCTRL);
2397
2398         *parity = 'n';
2399         if (cr & UARTCTRL_PE) {
2400                 if (cr & UARTCTRL_PT)
2401                         *parity = 'o';
2402                 else
2403                         *parity = 'e';
2404         }
2405
2406         if (cr & UARTCTRL_M)
2407                 *bits = 9;
2408         else
2409                 *bits = 8;
2410
2411         bd = lpuart32_read(&sport->port, UARTBAUD);
2412         bd &= UARTBAUD_SBR_MASK;
2413         if (!bd)
2414                 return;
2415
2416         sbr = bd;
2417         uartclk = lpuart_get_baud_clk_rate(sport);
2418         /*
2419          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2420          */
2421         baud_raw = uartclk / (16 * sbr);
2422
2423         if (*baud != baud_raw)
2424                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2425                                 "from %d to %d\n", baud_raw, *baud);
2426 }
2427
2428 static int __init lpuart_console_setup(struct console *co, char *options)
2429 {
2430         struct lpuart_port *sport;
2431         int baud = 115200;
2432         int bits = 8;
2433         int parity = 'n';
2434         int flow = 'n';
2435
2436         /*
2437          * check whether an invalid uart number has been specified, and
2438          * if so, search for the first available port that does have
2439          * console support.
2440          */
2441         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2442                 co->index = 0;
2443
2444         sport = lpuart_ports[co->index];
2445         if (sport == NULL)
2446                 return -ENODEV;
2447
2448         if (options)
2449                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2450         else
2451                 if (lpuart_is_32(sport))
2452                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
2453                 else
2454                         lpuart_console_get_options(sport, &baud, &parity, &bits);
2455
2456         if (lpuart_is_32(sport))
2457                 lpuart32_setup_watermark(sport);
2458         else
2459                 lpuart_setup_watermark(sport);
2460
2461         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2462 }
2463
2464 static struct uart_driver lpuart_reg;
2465 static struct console lpuart_console = {
2466         .name           = DEV_NAME,
2467         .write          = lpuart_console_write,
2468         .device         = uart_console_device,
2469         .setup          = lpuart_console_setup,
2470         .flags          = CON_PRINTBUFFER,
2471         .index          = -1,
2472         .data           = &lpuart_reg,
2473 };
2474
2475 static struct console lpuart32_console = {
2476         .name           = DEV_NAME,
2477         .write          = lpuart32_console_write,
2478         .device         = uart_console_device,
2479         .setup          = lpuart_console_setup,
2480         .flags          = CON_PRINTBUFFER,
2481         .index          = -1,
2482         .data           = &lpuart_reg,
2483 };
2484
2485 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2486 {
2487         struct earlycon_device *dev = con->data;
2488
2489         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2490 }
2491
2492 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2493 {
2494         struct earlycon_device *dev = con->data;
2495
2496         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2497 }
2498
2499 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2500                                           const char *opt)
2501 {
2502         if (!device->port.membase)
2503                 return -ENODEV;
2504
2505         device->con->write = lpuart_early_write;
2506         return 0;
2507 }
2508
2509 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2510                                           const char *opt)
2511 {
2512         if (!device->port.membase)
2513                 return -ENODEV;
2514
2515         if (device->port.iotype != UPIO_MEM32)
2516                 device->port.iotype = UPIO_MEM32BE;
2517
2518         device->con->write = lpuart32_early_write;
2519         return 0;
2520 }
2521
2522 static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2523                                               const char *opt)
2524 {
2525         u32 cr;
2526
2527         if (!device->port.membase)
2528                 return -ENODEV;
2529
2530         device->port.iotype = UPIO_MEM32;
2531         device->con->write = lpuart32_early_write;
2532
2533         /* set the baudrate */
2534         if (device->port.uartclk && device->baud)
2535                 __lpuart32_serial_setbrg(&device->port, device->baud,
2536                                          false, false);
2537
2538         /* enable transmitter */
2539         cr = lpuart32_read(&device->port, UARTCTRL);
2540         cr |= UARTCTRL_TE;
2541         lpuart32_write(&device->port, cr, UARTCTRL);
2542
2543         return 0;
2544 }
2545
2546 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2547                                                    const char *opt)
2548 {
2549         if (!device->port.membase)
2550                 return -ENODEV;
2551
2552         device->port.iotype = UPIO_MEM32;
2553         device->port.membase += IMX_REG_OFF;
2554         device->con->write = lpuart32_early_write;
2555
2556         return 0;
2557 }
2558 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2559 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2560 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2561 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2562 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2563 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2564 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2565
2566 #define LPUART_CONSOLE  (&lpuart_console)
2567 #define LPUART32_CONSOLE        (&lpuart32_console)
2568 #else
2569 #define LPUART_CONSOLE  NULL
2570 #define LPUART32_CONSOLE        NULL
2571 #endif
2572
2573 static struct uart_driver lpuart_reg = {
2574         .owner          = THIS_MODULE,
2575         .driver_name    = DRIVER_NAME,
2576         .dev_name       = DEV_NAME,
2577         .nr             = ARRAY_SIZE(lpuart_ports),
2578         .cons           = LPUART_CONSOLE,
2579 };
2580
2581 static int lpuart_probe(struct platform_device *pdev)
2582 {
2583         const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2584                                                            &pdev->dev);
2585         const struct lpuart_soc_data *sdata = of_id->data;
2586         struct device_node *np = pdev->dev.of_node;
2587         struct lpuart_port *sport;
2588         struct resource *res;
2589         int ret;
2590
2591         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2592         if (!sport)
2593                 return -ENOMEM;
2594
2595         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2596         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2597         if (IS_ERR(sport->port.membase))
2598                 return PTR_ERR(sport->port.membase);
2599
2600         sport->port.membase += sdata->reg_off;
2601         sport->port.mapbase = res->start + sdata->reg_off;
2602         sport->port.dev = &pdev->dev;
2603         sport->port.type = PORT_LPUART;
2604         sport->devtype = sdata->devtype;
2605         ret = platform_get_irq(pdev, 0);
2606         if (ret < 0)
2607                 return ret;
2608         sport->port.irq = ret;
2609         sport->port.iotype = sdata->iotype;
2610         if (lpuart_is_32(sport))
2611                 sport->port.ops = &lpuart32_pops;
2612         else
2613                 sport->port.ops = &lpuart_pops;
2614         sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2615         sport->port.flags = UPF_BOOT_AUTOCONF;
2616
2617         if (lpuart_is_32(sport))
2618                 sport->port.rs485_config = lpuart32_config_rs485;
2619         else
2620                 sport->port.rs485_config = lpuart_config_rs485;
2621
2622         sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2623         if (IS_ERR(sport->ipg_clk)) {
2624                 ret = PTR_ERR(sport->ipg_clk);
2625                 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2626                 return ret;
2627         }
2628
2629         sport->baud_clk = NULL;
2630         if (is_imx8qxp_lpuart(sport)) {
2631                 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2632                 if (IS_ERR(sport->baud_clk)) {
2633                         ret = PTR_ERR(sport->baud_clk);
2634                         dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2635                         return ret;
2636                 }
2637         }
2638
2639         ret = of_alias_get_id(np, "serial");
2640         if (ret < 0) {
2641                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2642                 return ret;
2643         }
2644         if (ret >= ARRAY_SIZE(lpuart_ports)) {
2645                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2646                 return -EINVAL;
2647         }
2648         sport->port.line = ret;
2649
2650         ret = lpuart_enable_clks(sport);
2651         if (ret)
2652                 return ret;
2653         sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2654
2655         lpuart_ports[sport->port.line] = sport;
2656
2657         platform_set_drvdata(pdev, &sport->port);
2658
2659         if (lpuart_is_32(sport)) {
2660                 lpuart_reg.cons = LPUART32_CONSOLE;
2661                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2662                                         DRIVER_NAME, sport);
2663         } else {
2664                 lpuart_reg.cons = LPUART_CONSOLE;
2665                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2666                                         DRIVER_NAME, sport);
2667         }
2668
2669         if (ret)
2670                 goto failed_irq_request;
2671
2672         ret = uart_get_rs485_mode(&sport->port);
2673         if (ret)
2674                 goto failed_get_rs485;
2675
2676         if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2677                 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2678
2679         if (sport->port.rs485.delay_rts_before_send ||
2680             sport->port.rs485.delay_rts_after_send)
2681                 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2682
2683         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2684         if (ret)
2685                 goto failed_attach_port;
2686
2687         return 0;
2688
2689 failed_get_rs485:
2690 failed_attach_port:
2691 failed_irq_request:
2692         lpuart_disable_clks(sport);
2693         return ret;
2694 }
2695
2696 static int lpuart_remove(struct platform_device *pdev)
2697 {
2698         struct lpuart_port *sport = platform_get_drvdata(pdev);
2699
2700         uart_remove_one_port(&lpuart_reg, &sport->port);
2701
2702         lpuart_disable_clks(sport);
2703
2704         if (sport->dma_tx_chan)
2705                 dma_release_channel(sport->dma_tx_chan);
2706
2707         if (sport->dma_rx_chan)
2708                 dma_release_channel(sport->dma_rx_chan);
2709
2710         return 0;
2711 }
2712
2713 static int __maybe_unused lpuart_suspend(struct device *dev)
2714 {
2715         struct lpuart_port *sport = dev_get_drvdata(dev);
2716         unsigned long temp;
2717         bool irq_wake;
2718
2719         if (lpuart_is_32(sport)) {
2720                 /* disable Rx/Tx and interrupts */
2721                 temp = lpuart32_read(&sport->port, UARTCTRL);
2722                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2723                 lpuart32_write(&sport->port, temp, UARTCTRL);
2724         } else {
2725                 /* disable Rx/Tx and interrupts */
2726                 temp = readb(sport->port.membase + UARTCR2);
2727                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2728                 writeb(temp, sport->port.membase + UARTCR2);
2729         }
2730
2731         uart_suspend_port(&lpuart_reg, &sport->port);
2732
2733         /* uart_suspend_port() might set wakeup flag */
2734         irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2735
2736         if (sport->lpuart_dma_rx_use) {
2737                 /*
2738                  * EDMA driver during suspend will forcefully release any
2739                  * non-idle DMA channels. If port wakeup is enabled or if port
2740                  * is console port or 'no_console_suspend' is set the Rx DMA
2741                  * cannot resume as as expected, hence gracefully release the
2742                  * Rx DMA path before suspend and start Rx DMA path on resume.
2743                  */
2744                 if (irq_wake) {
2745                         del_timer_sync(&sport->lpuart_timer);
2746                         lpuart_dma_rx_free(&sport->port);
2747                 }
2748
2749                 /* Disable Rx DMA to use UART port as wakeup source */
2750                 if (lpuart_is_32(sport)) {
2751                         temp = lpuart32_read(&sport->port, UARTBAUD);
2752                         lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2753                                        UARTBAUD);
2754                 } else {
2755                         writeb(readb(sport->port.membase + UARTCR5) &
2756                                ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2757                 }
2758         }
2759
2760         if (sport->lpuart_dma_tx_use) {
2761                 sport->dma_tx_in_progress = false;
2762                 dmaengine_terminate_all(sport->dma_tx_chan);
2763         }
2764
2765         if (sport->port.suspended && !irq_wake)
2766                 lpuart_disable_clks(sport);
2767
2768         return 0;
2769 }
2770
2771 static int __maybe_unused lpuart_resume(struct device *dev)
2772 {
2773         struct lpuart_port *sport = dev_get_drvdata(dev);
2774         bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2775
2776         if (sport->port.suspended && !irq_wake)
2777                 lpuart_enable_clks(sport);
2778
2779         if (lpuart_is_32(sport))
2780                 lpuart32_setup_watermark_enable(sport);
2781         else
2782                 lpuart_setup_watermark_enable(sport);
2783
2784         if (sport->lpuart_dma_rx_use) {
2785                 if (irq_wake) {
2786                         if (!lpuart_start_rx_dma(sport))
2787                                 rx_dma_timer_init(sport);
2788                         else
2789                                 sport->lpuart_dma_rx_use = false;
2790                 }
2791         }
2792
2793         lpuart_tx_dma_startup(sport);
2794
2795         if (lpuart_is_32(sport))
2796                 lpuart32_configure(sport);
2797
2798         uart_resume_port(&lpuart_reg, &sport->port);
2799
2800         return 0;
2801 }
2802
2803 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2804
2805 static struct platform_driver lpuart_driver = {
2806         .probe          = lpuart_probe,
2807         .remove         = lpuart_remove,
2808         .driver         = {
2809                 .name   = "fsl-lpuart",
2810                 .of_match_table = lpuart_dt_ids,
2811                 .pm     = &lpuart_pm_ops,
2812         },
2813 };
2814
2815 static int __init lpuart_serial_init(void)
2816 {
2817         int ret = uart_register_driver(&lpuart_reg);
2818
2819         if (ret)
2820                 return ret;
2821
2822         ret = platform_driver_register(&lpuart_driver);
2823         if (ret)
2824                 uart_unregister_driver(&lpuart_reg);
2825
2826         return ret;
2827 }
2828
2829 static void __exit lpuart_serial_exit(void)
2830 {
2831         platform_driver_unregister(&lpuart_driver);
2832         uart_unregister_driver(&lpuart_reg);
2833 }
2834
2835 module_init(lpuart_serial_init);
2836 module_exit(lpuart_serial_exit);
2837
2838 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2839 MODULE_LICENSE("GPL v2");