drivers/tty/serial/fsl_lpuart.c

   1 /*
   2  *  Freescale lpuart serial port driver
   3  *
   4  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15
  16 #include <linux/clk.h>
  17 #include <linux/console.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_dma.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/slab.h>
  29 #include <linux/tty_flip.h>
  30
  31 /* All registers are 8-bit width */
  32 #define UARTBDH                 0x00
  33 #define UARTBDL                 0x01
  34 #define UARTCR1                 0x02
  35 #define UARTCR2                 0x03
  36 #define UARTSR1                 0x04
  37 #define UARTCR3                 0x06
  38 #define UARTDR                  0x07
  39 #define UARTCR4                 0x0a
  40 #define UARTCR5                 0x0b
  41 #define UARTMODEM               0x0d
  42 #define UARTPFIFO               0x10
  43 #define UARTCFIFO               0x11
  44 #define UARTSFIFO               0x12
  45 #define UARTTWFIFO              0x13
  46 #define UARTTCFIFO              0x14
  47 #define UARTRWFIFO              0x15
  48
  49 #define UARTBDH_LBKDIE          0x80
  50 #define UARTBDH_RXEDGIE         0x40
  51 #define UARTBDH_SBR_MASK        0x1f
  52
  53 #define UARTCR1_LOOPS           0x80
  54 #define UARTCR1_RSRC            0x20
  55 #define UARTCR1_M               0x10
  56 #define UARTCR1_WAKE            0x08
  57 #define UARTCR1_ILT             0x04
  58 #define UARTCR1_PE              0x02
  59 #define UARTCR1_PT              0x01
  60
  61 #define UARTCR2_TIE             0x80
  62 #define UARTCR2_TCIE            0x40
  63 #define UARTCR2_RIE             0x20
  64 #define UARTCR2_ILIE            0x10
  65 #define UARTCR2_TE              0x08
  66 #define UARTCR2_RE              0x04
  67 #define UARTCR2_RWU             0x02
  68 #define UARTCR2_SBK             0x01
  69
  70 #define UARTSR1_TDRE            0x80
  71 #define UARTSR1_TC              0x40
  72 #define UARTSR1_RDRF            0x20
  73 #define UARTSR1_IDLE            0x10
  74 #define UARTSR1_OR              0x08
  75 #define UARTSR1_NF              0x04
  76 #define UARTSR1_FE              0x02
  77 #define UARTSR1_PE              0x01
  78
  79 #define UARTCR3_R8              0x80
  80 #define UARTCR3_T8              0x40
  81 #define UARTCR3_TXDIR           0x20
  82 #define UARTCR3_TXINV           0x10
  83 #define UARTCR3_ORIE            0x08
  84 #define UARTCR3_NEIE            0x04
  85 #define UARTCR3_FEIE            0x02
  86 #define UARTCR3_PEIE            0x01
  87
  88 #define UARTCR4_MAEN1           0x80
  89 #define UARTCR4_MAEN2           0x40
  90 #define UARTCR4_M10             0x20
  91 #define UARTCR4_BRFA_MASK       0x1f
  92 #define UARTCR4_BRFA_OFF        0
  93
  94 #define UARTCR5_TDMAS           0x80
  95 #define UARTCR5_RDMAS           0x20
  96
  97 #define UARTMODEM_RXRTSE        0x08
  98 #define UARTMODEM_TXRTSPOL      0x04
  99 #define UARTMODEM_TXRTSE        0x02
 100 #define UARTMODEM_TXCTSE        0x01
 101
 102 #define UARTPFIFO_TXFE          0x80
 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 104 #define UARTPFIFO_TXSIZE_OFF    4
 105 #define UARTPFIFO_RXFE          0x08
 106 #define UARTPFIFO_RXSIZE_OFF    0
 107
 108 #define UARTCFIFO_TXFLUSH       0x80
 109 #define UARTCFIFO_RXFLUSH       0x40
 110 #define UARTCFIFO_RXOFE         0x04
 111 #define UARTCFIFO_TXOFE         0x02
 112 #define UARTCFIFO_RXUFE         0x01
 113
 114 #define UARTSFIFO_TXEMPT        0x80
 115 #define UARTSFIFO_RXEMPT        0x40
 116 #define UARTSFIFO_RXOF          0x04
 117 #define UARTSFIFO_TXOF          0x02
 118 #define UARTSFIFO_RXUF          0x01
 119
 120 /* 32-bit register definition */
 121 #define UARTBAUD                0x00
 122 #define UARTSTAT                0x04
 123 #define UARTCTRL                0x08
 124 #define UARTDATA                0x0C
 125 #define UARTMATCH               0x10
 126 #define UARTMODIR               0x14
 127 #define UARTFIFO                0x18
 128 #define UARTWATER               0x1c
 129
 130 #define UARTBAUD_MAEN1          0x80000000
 131 #define UARTBAUD_MAEN2          0x40000000
 132 #define UARTBAUD_M10            0x20000000
 133 #define UARTBAUD_TDMAE          0x00800000
 134 #define UARTBAUD_RDMAE          0x00200000
 135 #define UARTBAUD_MATCFG         0x00400000
 136 #define UARTBAUD_BOTHEDGE       0x00020000
 137 #define UARTBAUD_RESYNCDIS      0x00010000
 138 #define UARTBAUD_LBKDIE         0x00008000
 139 #define UARTBAUD_RXEDGIE        0x00004000
 140 #define UARTBAUD_SBNS           0x00002000
 141 #define UARTBAUD_SBR            0x00000000
 142 #define UARTBAUD_SBR_MASK       0x1fff
 143 #define UARTBAUD_OSR_MASK       0x1f
 144 #define UARTBAUD_OSR_SHIFT      24
 145
 146 #define UARTSTAT_LBKDIF         0x80000000
 147 #define UARTSTAT_RXEDGIF        0x40000000
 148 #define UARTSTAT_MSBF           0x20000000
 149 #define UARTSTAT_RXINV          0x10000000
 150 #define UARTSTAT_RWUID          0x08000000
 151 #define UARTSTAT_BRK13          0x04000000
 152 #define UARTSTAT_LBKDE          0x02000000
 153 #define UARTSTAT_RAF            0x01000000
 154 #define UARTSTAT_TDRE           0x00800000
 155 #define UARTSTAT_TC             0x00400000
 156 #define UARTSTAT_RDRF           0x00200000
 157 #define UARTSTAT_IDLE           0x00100000
 158 #define UARTSTAT_OR             0x00080000
 159 #define UARTSTAT_NF             0x00040000
 160 #define UARTSTAT_FE             0x00020000
 161 #define UARTSTAT_PE             0x00010000
 162 #define UARTSTAT_MA1F           0x00008000
 163 #define UARTSTAT_M21F           0x00004000
 164
 165 #define UARTCTRL_R8T9           0x80000000
 166 #define UARTCTRL_R9T8           0x40000000
 167 #define UARTCTRL_TXDIR          0x20000000
 168 #define UARTCTRL_TXINV          0x10000000
 169 #define UARTCTRL_ORIE           0x08000000
 170 #define UARTCTRL_NEIE           0x04000000
 171 #define UARTCTRL_FEIE           0x02000000
 172 #define UARTCTRL_PEIE           0x01000000
 173 #define UARTCTRL_TIE            0x00800000
 174 #define UARTCTRL_TCIE           0x00400000
 175 #define UARTCTRL_RIE            0x00200000
 176 #define UARTCTRL_ILIE           0x00100000
 177 #define UARTCTRL_TE             0x00080000
 178 #define UARTCTRL_RE             0x00040000
 179 #define UARTCTRL_RWU            0x00020000
 180 #define UARTCTRL_SBK            0x00010000
 181 #define UARTCTRL_MA1IE          0x00008000
 182 #define UARTCTRL_MA2IE          0x00004000
 183 #define UARTCTRL_IDLECFG        0x00000100
 184 #define UARTCTRL_LOOPS          0x00000080
 185 #define UARTCTRL_DOZEEN         0x00000040
 186 #define UARTCTRL_RSRC           0x00000020
 187 #define UARTCTRL_M              0x00000010
 188 #define UARTCTRL_WAKE           0x00000008
 189 #define UARTCTRL_ILT            0x00000004
 190 #define UARTCTRL_PE             0x00000002
 191 #define UARTCTRL_PT             0x00000001
 192
 193 #define UARTDATA_NOISY          0x00008000
 194 #define UARTDATA_PARITYE        0x00004000
 195 #define UARTDATA_FRETSC         0x00002000
 196 #define UARTDATA_RXEMPT         0x00001000
 197 #define UARTDATA_IDLINE         0x00000800
 198 #define UARTDATA_MASK           0x3ff
 199
 200 #define UARTMODIR_IREN          0x00020000
 201 #define UARTMODIR_TXCTSSRC      0x00000020
 202 #define UARTMODIR_TXCTSC        0x00000010
 203 #define UARTMODIR_RXRTSE        0x00000008
 204 #define UARTMODIR_TXRTSPOL      0x00000004
 205 #define UARTMODIR_TXRTSE        0x00000002
 206 #define UARTMODIR_TXCTSE        0x00000001
 207
 208 #define UARTFIFO_TXEMPT         0x00800000
 209 #define UARTFIFO_RXEMPT         0x00400000
 210 #define UARTFIFO_TXOF           0x00020000
 211 #define UARTFIFO_RXUF           0x00010000
 212 #define UARTFIFO_TXFLUSH        0x00008000
 213 #define UARTFIFO_RXFLUSH        0x00004000
 214 #define UARTFIFO_TXOFE          0x00000200
 215 #define UARTFIFO_RXUFE          0x00000100
 216 #define UARTFIFO_TXFE           0x00000080
 217 #define UARTFIFO_FIFOSIZE_MASK  0x7
 218 #define UARTFIFO_TXSIZE_OFF     4
 219 #define UARTFIFO_RXFE           0x00000008
 220 #define UARTFIFO_RXSIZE_OFF     0
 221
 222 #define UARTWATER_COUNT_MASK    0xff
 223 #define UARTWATER_TXCNT_OFF     8
 224 #define UARTWATER_RXCNT_OFF     24
 225 #define UARTWATER_WATER_MASK    0xff
 226 #define UARTWATER_TXWATER_OFF   0
 227 #define UARTWATER_RXWATER_OFF   16
 228
 229 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 230 #define DMA_RX_TIMEOUT          (10)
 231
 232 #define DRIVER_NAME     "fsl-lpuart"
 233 #define DEV_NAME        "ttyLP"
 234 #define UART_NR         6
 235
 236 /* IMX lpuart has four extra unused regs located at the beginning */
 237 #define IMX_REG_OFF     0x10
 238
 239 struct lpuart_port {
 240         struct uart_port        port;
 241         struct clk              *clk;
 242         unsigned int            txfifo_size;
 243         unsigned int            rxfifo_size;
 244
 245         bool                    lpuart_dma_tx_use;
 246         bool                    lpuart_dma_rx_use;
 247         struct dma_chan         *dma_tx_chan;
 248         struct dma_chan         *dma_rx_chan;
 249         struct dma_async_tx_descriptor  *dma_tx_desc;
 250         struct dma_async_tx_descriptor  *dma_rx_desc;
 251         dma_cookie_t            dma_tx_cookie;
 252         dma_cookie_t            dma_rx_cookie;
 253         unsigned int            dma_tx_bytes;
 254         unsigned int            dma_rx_bytes;
 255         bool                    dma_tx_in_progress;
 256         unsigned int            dma_rx_timeout;
 257         struct timer_list       lpuart_timer;
 258         struct scatterlist      rx_sgl, tx_sgl[2];
 259         struct circ_buf         rx_ring;
 260         int                     rx_dma_rng_buf_len;
 261         unsigned int            dma_tx_nents;
 262         wait_queue_head_t       dma_wait;
 263 };
 264
 265 struct lpuart_soc_data {
 266         char    iotype;
 267         u8      reg_off;
 268 };
 269
 270 static const struct lpuart_soc_data vf_data = {
 271         .iotype = UPIO_MEM,
 272 };
 273
 274 static const struct lpuart_soc_data ls_data = {
 275         .iotype = UPIO_MEM32BE,
 276 };
 277
 278 static struct lpuart_soc_data imx_data = {
 279         .iotype = UPIO_MEM32,
 280         .reg_off = IMX_REG_OFF,
 281 };
 282
 283 static const struct of_device_id lpuart_dt_ids[] = {
 284         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 285         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls_data, },
 286         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx_data, },
 287         { /* sentinel */ }
 288 };
 289 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 290
 291 /* Forward declare this for the dma callbacks*/
 292 static void lpuart_dma_tx_complete(void *arg);
 293
 294 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 295 {
 296         switch (port->iotype) {
 297         case UPIO_MEM32:
 298                 return readl(port->membase + off);
 299         case UPIO_MEM32BE:
 300                 return ioread32be(port->membase + off);
 301         default:
 302                 return 0;
 303         }
 304 }
 305
 306 static inline void lpuart32_write(struct uart_port *port, u32 val,
 307                                   u32 off)
 308 {
 309         switch (port->iotype) {
 310         case UPIO_MEM32:
 311                 writel(val, port->membase + off);
 312                 break;
 313         case UPIO_MEM32BE:
 314                 iowrite32be(val, port->membase + off);
 315                 break;
 316         }
 317 }
 318
 319 static void lpuart_stop_tx(struct uart_port *port)
 320 {
 321         unsigned char temp;
 322
 323         temp = readb(port->membase + UARTCR2);
 324         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 325         writeb(temp, port->membase + UARTCR2);
 326 }
 327
 328 static void lpuart32_stop_tx(struct uart_port *port)
 329 {
 330         unsigned long temp;
 331
 332         temp = lpuart32_read(port, UARTCTRL);
 333         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 334         lpuart32_write(port, temp, UARTCTRL);
 335 }
 336
 337 static void lpuart_stop_rx(struct uart_port *port)
 338 {
 339         unsigned char temp;
 340
 341         temp = readb(port->membase + UARTCR2);
 342         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 343 }
 344
 345 static void lpuart32_stop_rx(struct uart_port *port)
 346 {
 347         unsigned long temp;
 348
 349         temp = lpuart32_read(port, UARTCTRL);
 350         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 351 }
 352
 353 static void lpuart_dma_tx(struct lpuart_port *sport)
 354 {
 355         struct circ_buf *xmit = &sport->port.state->xmit;
 356         struct scatterlist *sgl = sport->tx_sgl;
 357         struct device *dev = sport->port.dev;
 358         int ret;
 359
 360         if (sport->dma_tx_in_progress)
 361                 return;
 362
 363         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 364
 365         if (xmit->tail < xmit->head || xmit->head == 0) {
 366                 sport->dma_tx_nents = 1;
 367                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 368         } else {
 369                 sport->dma_tx_nents = 2;
 370                 sg_init_table(sgl, 2);
 371                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 372                                 UART_XMIT_SIZE - xmit->tail);
 373                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 374         }
 375
 376         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 377         if (!ret) {
 378                 dev_err(dev, "DMA mapping error for TX.\n");
 379                 return;
 380         }
 381
 382         sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
 383                                         ret, DMA_MEM_TO_DEV,
 384                                         DMA_PREP_INTERRUPT);
 385         if (!sport->dma_tx_desc) {
 386                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 387                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 388                 return;
 389         }
 390
 391         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 392         sport->dma_tx_desc->callback_param = sport;
 393         sport->dma_tx_in_progress = true;
 394         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 395         dma_async_issue_pending(sport->dma_tx_chan);
 396 }
 397
 398 static void lpuart_dma_tx_complete(void *arg)
 399 {
 400         struct lpuart_port *sport = arg;
 401         struct scatterlist *sgl = &sport->tx_sgl[0];
 402         struct circ_buf *xmit = &sport->port.state->xmit;
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&sport->port.lock, flags);
 406
 407         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 408
 409         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 410
 411         sport->port.icount.tx += sport->dma_tx_bytes;
 412         sport->dma_tx_in_progress = false;
 413         spin_unlock_irqrestore(&sport->port.lock, flags);
 414
 415         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 416                 uart_write_wakeup(&sport->port);
 417
 418         if (waitqueue_active(&sport->dma_wait)) {
 419                 wake_up(&sport->dma_wait);
 420                 return;
 421         }
 422
 423         spin_lock_irqsave(&sport->port.lock, flags);
 424
 425         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 426                 lpuart_dma_tx(sport);
 427
 428         spin_unlock_irqrestore(&sport->port.lock, flags);
 429 }
 430
 431 static int lpuart_dma_tx_request(struct uart_port *port)
 432 {
 433         struct lpuart_port *sport = container_of(port,
 434                                         struct lpuart_port, port);
 435         struct dma_slave_config dma_tx_sconfig = {};
 436         int ret;
 437
 438         dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
 439         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 440         dma_tx_sconfig.dst_maxburst = 1;
 441         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 442         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 443
 444         if (ret) {
 445                 dev_err(sport->port.dev,
 446                                 "DMA slave config failed, err = %d\n", ret);
 447                 return ret;
 448         }
 449
 450         return 0;
 451 }
 452
 453 static void lpuart_flush_buffer(struct uart_port *port)
 454 {
 455         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 456
 457         if (sport->lpuart_dma_tx_use) {
 458                 if (sport->dma_tx_in_progress) {
 459                         dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
 460                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 461                         sport->dma_tx_in_progress = false;
 462                 }
 463                 dmaengine_terminate_all(sport->dma_tx_chan);
 464         }
 465 }
 466
 467 #if defined(CONFIG_CONSOLE_POLL)
 468
 469 static int lpuart_poll_init(struct uart_port *port)
 470 {
 471         struct lpuart_port *sport = container_of(port,
 472                                         struct lpuart_port, port);
 473         unsigned long flags;
 474         unsigned char temp;
 475
 476         sport->port.fifosize = 0;
 477
 478         spin_lock_irqsave(&sport->port.lock, flags);
 479         /* Disable Rx & Tx */
 480         writeb(0, sport->port.membase + UARTCR2);
 481
 482         temp = readb(sport->port.membase + UARTPFIFO);
 483         /* Enable Rx and Tx FIFO */
 484         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 485                         sport->port.membase + UARTPFIFO);
 486
 487         /* flush Tx and Rx FIFO */
 488         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 489                         sport->port.membase + UARTCFIFO);
 490
 491         /* explicitly clear RDRF */
 492         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 493                 readb(sport->port.membase + UARTDR);
 494                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 495         }
 496
 497         writeb(0, sport->port.membase + UARTTWFIFO);
 498         writeb(1, sport->port.membase + UARTRWFIFO);
 499
 500         /* Enable Rx and Tx */
 501         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 502         spin_unlock_irqrestore(&sport->port.lock, flags);
 503
 504         return 0;
 505 }
 506
 507 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 508 {
 509         /* drain */
 510         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
 511                 barrier();
 512
 513         writeb(c, port->membase + UARTDR);
 514 }
 515
 516 static int lpuart_poll_get_char(struct uart_port *port)
 517 {
 518         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 519                 return NO_POLL_CHAR;
 520
 521         return readb(port->membase + UARTDR);
 522 }
 523
 524 static int lpuart32_poll_init(struct uart_port *port)
 525 {
 526         unsigned long flags;
 527         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 528         u32 temp;
 529
 530         sport->port.fifosize = 0;
 531
 532         spin_lock_irqsave(&sport->port.lock, flags);
 533
 534         /* Disable Rx & Tx */
 535         lpuart32_write(&sport->port, UARTCTRL, 0);
 536
 537         temp = lpuart32_read(&sport->port, UARTFIFO);
 538
 539         /* Enable Rx and Tx FIFO */
 540         lpuart32_write(&sport->port, UARTFIFO,
 541                        temp | UARTFIFO_RXFE | UARTFIFO_TXFE);
 542
 543         /* flush Tx and Rx FIFO */
 544         lpuart32_write(&sport->port, UARTFIFO,
 545                        UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH);
 546
 547         /* explicitly clear RDRF */
 548         if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
 549                 lpuart32_read(&sport->port, UARTDATA);
 550                 lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF);
 551         }
 552
 553         /* Enable Rx and Tx */
 554         lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE | UARTCTRL_TE);
 555         spin_unlock_irqrestore(&sport->port.lock, flags);
 556
 557         return 0;
 558 }
 559
 560 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
 561 {
 562         while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
 563                 barrier();
 564
 565         lpuart32_write(port, UARTDATA, c);
 566 }
 567
 568 static int lpuart32_poll_get_char(struct uart_port *port)
 569 {
 570         if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
 571                 return NO_POLL_CHAR;
 572
 573         return lpuart32_read(port, UARTDATA);
 574 }
 575 #endif
 576
 577 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 578 {
 579         struct circ_buf *xmit = &sport->port.state->xmit;
 580
 581         while (!uart_circ_empty(xmit) &&
 582                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 583                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 584                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 585                 sport->port.icount.tx++;
 586         }
 587
 588         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 589                 uart_write_wakeup(&sport->port);
 590
 591         if (uart_circ_empty(xmit))
 592                 lpuart_stop_tx(&sport->port);
 593 }
 594
 595 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 596 {
 597         struct circ_buf *xmit = &sport->port.state->xmit;
 598         unsigned long txcnt;
 599
 600         txcnt = lpuart32_read(&sport->port, UARTWATER);
 601         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 602         txcnt &= UARTWATER_COUNT_MASK;
 603         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 604                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 605                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 606                 sport->port.icount.tx++;
 607                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 608                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 609                 txcnt &= UARTWATER_COUNT_MASK;
 610         }
 611
 612         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 613                 uart_write_wakeup(&sport->port);
 614
 615         if (uart_circ_empty(xmit))
 616                 lpuart32_stop_tx(&sport->port);
 617 }
 618
 619 static void lpuart_start_tx(struct uart_port *port)
 620 {
 621         struct lpuart_port *sport = container_of(port,
 622                         struct lpuart_port, port);
 623         struct circ_buf *xmit = &sport->port.state->xmit;
 624         unsigned char temp;
 625
 626         temp = readb(port->membase + UARTCR2);
 627         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 628
 629         if (sport->lpuart_dma_tx_use) {
 630                 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
 631                         lpuart_dma_tx(sport);
 632         } else {
 633                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 634                         lpuart_transmit_buffer(sport);
 635         }
 636 }
 637
 638 static void lpuart32_start_tx(struct uart_port *port)
 639 {
 640         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 641         unsigned long temp;
 642
 643         temp = lpuart32_read(port, UARTCTRL);
 644         lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 645
 646         if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 647                 lpuart32_transmit_buffer(sport);
 648 }
 649
 650 /* return TIOCSER_TEMT when transmitter is not busy */
 651 static unsigned int lpuart_tx_empty(struct uart_port *port)
 652 {
 653         struct lpuart_port *sport = container_of(port,
 654                         struct lpuart_port, port);
 655         unsigned char sr1 = readb(port->membase + UARTSR1);
 656         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 657
 658         if (sport->dma_tx_in_progress)
 659                 return 0;
 660
 661         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 662                 return TIOCSER_TEMT;
 663
 664         return 0;
 665 }
 666
 667 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 668 {
 669         return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ?
 670                 TIOCSER_TEMT : 0;
 671 }
 672
 673 static bool lpuart_is_32(struct lpuart_port *sport)
 674 {
 675         return sport->port.iotype == UPIO_MEM32 ||
 676                sport->port.iotype ==  UPIO_MEM32BE;
 677 }
 678
 679 static irqreturn_t lpuart_txint(int irq, void *dev_id)
 680 {
 681         struct lpuart_port *sport = dev_id;
 682         struct circ_buf *xmit = &sport->port.state->xmit;
 683         unsigned long flags;
 684
 685         spin_lock_irqsave(&sport->port.lock, flags);
 686         if (sport->port.x_char) {
 687                 if (lpuart_is_32(sport))
 688                         lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 689                 else
 690                         writeb(sport->port.x_char, sport->port.membase + UARTDR);
 691                 goto out;
 692         }
 693
 694         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 695                 if (lpuart_is_32(sport))
 696                         lpuart32_stop_tx(&sport->port);
 697                 else
 698                         lpuart_stop_tx(&sport->port);
 699                 goto out;
 700         }
 701
 702         if (lpuart_is_32(sport))
 703                 lpuart32_transmit_buffer(sport);
 704         else
 705                 lpuart_transmit_buffer(sport);
 706
 707         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 708                 uart_write_wakeup(&sport->port);
 709
 710 out:
 711         spin_unlock_irqrestore(&sport->port.lock, flags);
 712         return IRQ_HANDLED;
 713 }
 714
 715 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
 716 {
 717         struct lpuart_port *sport = dev_id;
 718         unsigned int flg, ignored = 0;
 719         struct tty_port *port = &sport->port.state->port;
 720         unsigned long flags;
 721         unsigned char rx, sr;
 722
 723         spin_lock_irqsave(&sport->port.lock, flags);
 724
 725         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 726                 flg = TTY_NORMAL;
 727                 sport->port.icount.rx++;
 728                 /*
 729                  * to clear the FE, OR, NF, FE, PE flags,
 730                  * read SR1 then read DR
 731                  */
 732                 sr = readb(sport->port.membase + UARTSR1);
 733                 rx = readb(sport->port.membase + UARTDR);
 734
 735                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 736                         continue;
 737
 738                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 739                         if (sr & UARTSR1_PE)
 740                                 sport->port.icount.parity++;
 741                         else if (sr & UARTSR1_FE)
 742                                 sport->port.icount.frame++;
 743
 744                         if (sr & UARTSR1_OR)
 745                                 sport->port.icount.overrun++;
 746
 747                         if (sr & sport->port.ignore_status_mask) {
 748                                 if (++ignored > 100)
 749                                         goto out;
 750                                 continue;
 751                         }
 752
 753                         sr &= sport->port.read_status_mask;
 754
 755                         if (sr & UARTSR1_PE)
 756                                 flg = TTY_PARITY;
 757                         else if (sr & UARTSR1_FE)
 758                                 flg = TTY_FRAME;
 759
 760                         if (sr & UARTSR1_OR)
 761                                 flg = TTY_OVERRUN;
 762
 763 #ifdef SUPPORT_SYSRQ
 764                         sport->port.sysrq = 0;
 765 #endif
 766                 }
 767
 768                 tty_insert_flip_char(port, rx, flg);
 769         }
 770
 771 out:
 772         spin_unlock_irqrestore(&sport->port.lock, flags);
 773
 774         tty_flip_buffer_push(port);
 775         return IRQ_HANDLED;
 776 }
 777
 778 static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
 779 {
 780         struct lpuart_port *sport = dev_id;
 781         unsigned int flg, ignored = 0;
 782         struct tty_port *port = &sport->port.state->port;
 783         unsigned long flags;
 784         unsigned long rx, sr;
 785
 786         spin_lock_irqsave(&sport->port.lock, flags);
 787
 788         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 789                 flg = TTY_NORMAL;
 790                 sport->port.icount.rx++;
 791                 /*
 792                  * to clear the FE, OR, NF, FE, PE flags,
 793                  * read STAT then read DATA reg
 794                  */
 795                 sr = lpuart32_read(&sport->port, UARTSTAT);
 796                 rx = lpuart32_read(&sport->port, UARTDATA);
 797                 rx &= 0x3ff;
 798
 799                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 800                         continue;
 801
 802                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 803                         if (sr & UARTSTAT_PE)
 804                                 sport->port.icount.parity++;
 805                         else if (sr & UARTSTAT_FE)
 806                                 sport->port.icount.frame++;
 807
 808                         if (sr & UARTSTAT_OR)
 809                                 sport->port.icount.overrun++;
 810
 811                         if (sr & sport->port.ignore_status_mask) {
 812                                 if (++ignored > 100)
 813                                         goto out;
 814                                 continue;
 815                         }
 816
 817                         sr &= sport->port.read_status_mask;
 818
 819                         if (sr & UARTSTAT_PE)
 820                                 flg = TTY_PARITY;
 821                         else if (sr & UARTSTAT_FE)
 822                                 flg = TTY_FRAME;
 823
 824                         if (sr & UARTSTAT_OR)
 825                                 flg = TTY_OVERRUN;
 826
 827 #ifdef SUPPORT_SYSRQ
 828                         sport->port.sysrq = 0;
 829 #endif
 830                 }
 831
 832                 tty_insert_flip_char(port, rx, flg);
 833         }
 834
 835 out:
 836         spin_unlock_irqrestore(&sport->port.lock, flags);
 837
 838         tty_flip_buffer_push(port);
 839         return IRQ_HANDLED;
 840 }
 841
 842 static irqreturn_t lpuart_int(int irq, void *dev_id)
 843 {
 844         struct lpuart_port *sport = dev_id;
 845         unsigned char sts;
 846
 847         sts = readb(sport->port.membase + UARTSR1);
 848
 849         if (sts & UARTSR1_RDRF)
 850                 lpuart_rxint(irq, dev_id);
 851
 852         if (sts & UARTSR1_TDRE)
 853                 lpuart_txint(irq, dev_id);
 854
 855         return IRQ_HANDLED;
 856 }
 857
 858 static irqreturn_t lpuart32_int(int irq, void *dev_id)
 859 {
 860         struct lpuart_port *sport = dev_id;
 861         unsigned long sts, rxcount;
 862
 863         sts = lpuart32_read(&sport->port, UARTSTAT);
 864         rxcount = lpuart32_read(&sport->port, UARTWATER);
 865         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
 866
 867         if (sts & UARTSTAT_RDRF || rxcount > 0)
 868                 lpuart32_rxint(irq, dev_id);
 869
 870         if ((sts & UARTSTAT_TDRE) &&
 871                 !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE))
 872                 lpuart_txint(irq, dev_id);
 873
 874         lpuart32_write(&sport->port, sts, UARTSTAT);
 875         return IRQ_HANDLED;
 876 }
 877
 878 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
 879 {
 880         struct tty_port *port = &sport->port.state->port;
 881         struct dma_tx_state state;
 882         enum dma_status dmastat;
 883         struct circ_buf *ring = &sport->rx_ring;
 884         unsigned long flags;
 885         int count = 0;
 886         unsigned char sr;
 887
 888         sr = readb(sport->port.membase + UARTSR1);
 889
 890         if (sr & (UARTSR1_PE | UARTSR1_FE)) {
 891                 /* Read DR to clear the error flags */
 892                 readb(sport->port.membase + UARTDR);
 893
 894                 if (sr & UARTSR1_PE)
 895                     sport->port.icount.parity++;
 896                 else if (sr & UARTSR1_FE)
 897                     sport->port.icount.frame++;
 898         }
 899
 900         async_tx_ack(sport->dma_rx_desc);
 901
 902         spin_lock_irqsave(&sport->port.lock, flags);
 903
 904         dmastat = dmaengine_tx_status(sport->dma_rx_chan,
 905                                 sport->dma_rx_cookie,
 906                                 &state);
 907
 908         if (dmastat == DMA_ERROR) {
 909                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
 910                 spin_unlock_irqrestore(&sport->port.lock, flags);
 911                 return;
 912         }
 913
 914         /* CPU claims ownership of RX DMA buffer */
 915         dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
 916
 917         /*
 918          * ring->head points to the end of data already written by the DMA.
 919          * ring->tail points to the beginning of data to be read by the
 920          * framework.
 921          * The current transfer size should not be larger than the dma buffer
 922          * length.
 923          */
 924         ring->head = sport->rx_sgl.length - state.residue;
 925         BUG_ON(ring->head > sport->rx_sgl.length);
 926         /*
 927          * At this point ring->head may point to the first byte right after the
 928          * last byte of the dma buffer:
 929          * 0 <= ring->head <= sport->rx_sgl.length
 930          *
 931          * However ring->tail must always points inside the dma buffer:
 932          * 0 <= ring->tail <= sport->rx_sgl.length - 1
 933          *
 934          * Since we use a ring buffer, we have to handle the case
 935          * where head is lower than tail. In such a case, we first read from
 936          * tail to the end of the buffer then reset tail.
 937          */
 938         if (ring->head < ring->tail) {
 939                 count = sport->rx_sgl.length - ring->tail;
 940
 941                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
 942                 ring->tail = 0;
 943                 sport->port.icount.rx += count;
 944         }
 945
 946         /* Finally we read data from tail to head */
 947         if (ring->tail < ring->head) {
 948                 count = ring->head - ring->tail;
 949                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
 950                 /* Wrap ring->head if needed */
 951                 if (ring->head >= sport->rx_sgl.length)
 952                         ring->head = 0;
 953                 ring->tail = ring->head;
 954                 sport->port.icount.rx += count;
 955         }
 956
 957         dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
 958                                DMA_FROM_DEVICE);
 959
 960         spin_unlock_irqrestore(&sport->port.lock, flags);
 961
 962         tty_flip_buffer_push(port);
 963         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
 964 }
 965
 966 static void lpuart_dma_rx_complete(void *arg)
 967 {
 968         struct lpuart_port *sport = arg;
 969
 970         lpuart_copy_rx_to_tty(sport);
 971 }
 972
 973 static void lpuart_timer_func(unsigned long data)
 974 {
 975         struct lpuart_port *sport = (struct lpuart_port *)data;
 976
 977         lpuart_copy_rx_to_tty(sport);
 978 }
 979
 980 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
 981 {
 982         struct dma_slave_config dma_rx_sconfig = {};
 983         struct circ_buf *ring = &sport->rx_ring;
 984         int ret, nent;
 985         int bits, baud;
 986         struct tty_port *port = &sport->port.state->port;
 987         struct tty_struct *tty = port->tty;
 988         struct ktermios *termios = &tty->termios;
 989
 990         baud = tty_get_baud_rate(tty);
 991
 992         bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
 993         if (termios->c_cflag & PARENB)
 994                 bits++;
 995
 996         /*
 997          * Calculate length of one DMA buffer size to keep latency below
 998          * 10ms at any baud rate.
 999          */
1000         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1001         sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
1002         if (sport->rx_dma_rng_buf_len < 16)
1003                 sport->rx_dma_rng_buf_len = 16;
1004
1005         ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1006         if (!ring->buf) {
1007                 dev_err(sport->port.dev, "Ring buf alloc failed\n");
1008                 return -ENOMEM;
1009         }
1010
1011         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1012         sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1013         nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1014
1015         if (!nent) {
1016                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1017                 return -EINVAL;
1018         }
1019
1020         dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1021         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1022         dma_rx_sconfig.src_maxburst = 1;
1023         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1024         ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
1025
1026         if (ret < 0) {
1027                 dev_err(sport->port.dev,
1028                                 "DMA Rx slave config failed, err = %d\n", ret);
1029                 return ret;
1030         }
1031
1032         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
1033                                  sg_dma_address(&sport->rx_sgl),
1034                                  sport->rx_sgl.length,
1035                                  sport->rx_sgl.length / 2,
1036                                  DMA_DEV_TO_MEM,
1037                                  DMA_PREP_INTERRUPT);
1038         if (!sport->dma_rx_desc) {
1039                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1040                 return -EFAULT;
1041         }
1042
1043         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1044         sport->dma_rx_desc->callback_param = sport;
1045         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1046         dma_async_issue_pending(sport->dma_rx_chan);
1047
1048         writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1049                                 sport->port.membase + UARTCR5);
1050
1051         return 0;
1052 }
1053
1054 static void lpuart_dma_rx_free(struct uart_port *port)
1055 {
1056         struct lpuart_port *sport = container_of(port,
1057                                         struct lpuart_port, port);
1058
1059         if (sport->dma_rx_chan)
1060                 dmaengine_terminate_all(sport->dma_rx_chan);
1061
1062         dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1063         kfree(sport->rx_ring.buf);
1064         sport->rx_ring.tail = 0;
1065         sport->rx_ring.head = 0;
1066         sport->dma_rx_desc = NULL;
1067         sport->dma_rx_cookie = -EINVAL;
1068 }
1069
1070 static int lpuart_config_rs485(struct uart_port *port,
1071                         struct serial_rs485 *rs485)
1072 {
1073         struct lpuart_port *sport = container_of(port,
1074                         struct lpuart_port, port);
1075
1076         u8 modem = readb(sport->port.membase + UARTMODEM) &
1077                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1078         writeb(modem, sport->port.membase + UARTMODEM);
1079
1080         /* clear unsupported configurations */
1081         rs485->delay_rts_before_send = 0;
1082         rs485->delay_rts_after_send = 0;
1083         rs485->flags &= ~SER_RS485_RX_DURING_TX;
1084
1085         if (rs485->flags & SER_RS485_ENABLED) {
1086                 /* Enable auto RS-485 RTS mode */
1087                 modem |= UARTMODEM_TXRTSE;
1088
1089                 /*
1090                  * RTS needs to be logic HIGH either during transer _or_ after
1091                  * transfer, other variants are not supported by the hardware.
1092                  */
1093
1094                 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1095                                 SER_RS485_RTS_AFTER_SEND)))
1096                         rs485->flags |= SER_RS485_RTS_ON_SEND;
1097
1098                 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1099                                 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1100                         rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1101
1102                 /*
1103                  * The hardware defaults to RTS logic HIGH while transfer.
1104                  * Switch polarity in case RTS shall be logic HIGH
1105                  * after transfer.
1106                  * Note: UART is assumed to be active high.
1107                  */
1108                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1109                         modem |= UARTMODEM_TXRTSPOL;
1110                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1111                         modem &= ~UARTMODEM_TXRTSPOL;
1112         }
1113
1114         /* Store the new configuration */
1115         sport->port.rs485 = *rs485;
1116
1117         writeb(modem, sport->port.membase + UARTMODEM);
1118         return 0;
1119 }
1120
1121 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1122 {
1123         unsigned int temp = 0;
1124         unsigned char reg;
1125
1126         reg = readb(port->membase + UARTMODEM);
1127         if (reg & UARTMODEM_TXCTSE)
1128                 temp |= TIOCM_CTS;
1129
1130         if (reg & UARTMODEM_RXRTSE)
1131                 temp |= TIOCM_RTS;
1132
1133         return temp;
1134 }
1135
1136 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1137 {
1138         unsigned int temp = 0;
1139         unsigned long reg;
1140
1141         reg = lpuart32_read(port, UARTMODIR);
1142         if (reg & UARTMODIR_TXCTSE)
1143                 temp |= TIOCM_CTS;
1144
1145         if (reg & UARTMODIR_RXRTSE)
1146                 temp |= TIOCM_RTS;
1147
1148         return temp;
1149 }
1150
1151 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1152 {
1153         unsigned char temp;
1154         struct lpuart_port *sport = container_of(port,
1155                                 struct lpuart_port, port);
1156
1157         /* Make sure RXRTSE bit is not set when RS485 is enabled */
1158         if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1159                 temp = readb(sport->port.membase + UARTMODEM) &
1160                         ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1161
1162                 if (mctrl & TIOCM_RTS)
1163                         temp |= UARTMODEM_RXRTSE;
1164
1165                 if (mctrl & TIOCM_CTS)
1166                         temp |= UARTMODEM_TXCTSE;
1167
1168                 writeb(temp, port->membase + UARTMODEM);
1169         }
1170 }
1171
1172 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1173 {
1174         unsigned long temp;
1175
1176         temp = lpuart32_read(port, UARTMODIR) &
1177                         ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1178
1179         if (mctrl & TIOCM_RTS)
1180                 temp |= UARTMODIR_RXRTSE;
1181
1182         if (mctrl & TIOCM_CTS)
1183                 temp |= UARTMODIR_TXCTSE;
1184
1185         lpuart32_write(port, temp, UARTMODIR);
1186 }
1187
1188 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1189 {
1190         unsigned char temp;
1191
1192         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1193
1194         if (break_state != 0)
1195                 temp |= UARTCR2_SBK;
1196
1197         writeb(temp, port->membase + UARTCR2);
1198 }
1199
1200 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1201 {
1202         unsigned long temp;
1203
1204         temp = lpuart32_read(port, UARTCTRL);
1205
1206         /*
1207          * LPUART IP now has two known bugs, one is CTS has higher priority than the
1208          * break signal, which causes the break signal sending through UARTCTRL_SBK
1209          * may impacted by the CTS input if the HW flow control is enabled. It
1210          * exists on all platforms we support in this driver.
1211          * Another bug is i.MX8QM LPUART may have an additional break character
1212          * being sent after SBK was cleared.
1213          * To avoid above two bugs, we use Transmit Data Inversion function to send
1214          * the break signal instead of UARTCTRL_SBK.
1215          */
1216         if (break_state != 0) {
1217                 /*
1218                  * Disable the transmitter to prevent any data from being sent out
1219                  * during break, then invert the TX line to send break.
1220                  */
1221                 temp &= ~UARTCTRL_TE;
1222                 lpuart32_write(port, temp, UARTCTRL);
1223                 temp |= UARTCTRL_TXINV;
1224                 lpuart32_write(port, temp, UARTCTRL);
1225         } else {
1226                 /* Disable the TXINV to turn off break and re-enable transmitter. */
1227                 temp &= ~UARTCTRL_TXINV;
1228                 lpuart32_write(port, temp, UARTCTRL);
1229                 temp |= UARTCTRL_TE;
1230                 lpuart32_write(port, temp, UARTCTRL);
1231         }
1232 }
1233
1234 static void lpuart_setup_watermark(struct lpuart_port *sport)
1235 {
1236         unsigned char val, cr2;
1237         unsigned char cr2_saved;
1238
1239         cr2 = readb(sport->port.membase + UARTCR2);
1240         cr2_saved = cr2;
1241         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1242                         UARTCR2_RIE | UARTCR2_RE);
1243         writeb(cr2, sport->port.membase + UARTCR2);
1244
1245         val = readb(sport->port.membase + UARTPFIFO);
1246         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1247                         sport->port.membase + UARTPFIFO);
1248
1249         /* flush Tx and Rx FIFO */
1250         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1251                         sport->port.membase + UARTCFIFO);
1252
1253         /* explicitly clear RDRF */
1254         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1255                 readb(sport->port.membase + UARTDR);
1256                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1257         }
1258
1259         writeb(0, sport->port.membase + UARTTWFIFO);
1260         writeb(1, sport->port.membase + UARTRWFIFO);
1261
1262         /* Restore cr2 */
1263         writeb(cr2_saved, sport->port.membase + UARTCR2);
1264 }
1265
1266 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1267 {
1268         unsigned long val, ctrl;
1269         unsigned long ctrl_saved;
1270
1271         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1272         ctrl_saved = ctrl;
1273         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1274                         UARTCTRL_RIE | UARTCTRL_RE);
1275         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1276
1277         /* enable FIFO mode */
1278         val = lpuart32_read(&sport->port, UARTFIFO);
1279         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1280         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1281         lpuart32_write(&sport->port, val, UARTFIFO);
1282
1283         /* set the watermark */
1284         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1285         lpuart32_write(&sport->port, val, UARTWATER);
1286
1287         /* Restore cr2 */
1288         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1289 }
1290
1291 static void rx_dma_timer_init(struct lpuart_port *sport)
1292 {
1293                 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1294                                 (unsigned long)sport);
1295                 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1296                 add_timer(&sport->lpuart_timer);
1297 }
1298
1299 static int lpuart_startup(struct uart_port *port)
1300 {
1301         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1302         unsigned long flags;
1303         unsigned char temp;
1304
1305         /* determine FIFO size and enable FIFO mode */
1306         temp = readb(sport->port.membase + UARTPFIFO);
1307
1308         sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1309                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1310
1311         sport->port.fifosize = sport->txfifo_size;
1312
1313         sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1314                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1315
1316         spin_lock_irqsave(&sport->port.lock, flags);
1317
1318         lpuart_setup_watermark(sport);
1319
1320         temp = readb(sport->port.membase + UARTCR2);
1321         temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1322         writeb(temp, sport->port.membase + UARTCR2);
1323
1324         if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1325                 /* set Rx DMA timeout */
1326                 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1327                 if (!sport->dma_rx_timeout)
1328                      sport->dma_rx_timeout = 1;
1329
1330                 sport->lpuart_dma_rx_use = true;
1331                 rx_dma_timer_init(sport);
1332         } else {
1333                 sport->lpuart_dma_rx_use = false;
1334         }
1335
1336         if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1337                 init_waitqueue_head(&sport->dma_wait);
1338                 sport->lpuart_dma_tx_use = true;
1339                 temp = readb(port->membase + UARTCR5);
1340                 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1341         } else {
1342                 sport->lpuart_dma_tx_use = false;
1343         }
1344
1345         spin_unlock_irqrestore(&sport->port.lock, flags);
1346
1347         return 0;
1348 }
1349
1350 static int lpuart32_startup(struct uart_port *port)
1351 {
1352         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1353         unsigned long flags;
1354         unsigned long temp;
1355
1356         /* determine FIFO size */
1357         temp = lpuart32_read(&sport->port, UARTFIFO);
1358
1359         sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1360                 UARTFIFO_FIFOSIZE_MASK) - 1);
1361
1362         sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1363                 UARTFIFO_FIFOSIZE_MASK) - 1);
1364
1365         spin_lock_irqsave(&sport->port.lock, flags);
1366
1367         lpuart32_setup_watermark(sport);
1368
1369         temp = lpuart32_read(&sport->port, UARTCTRL);
1370         temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1371         temp |= UARTCTRL_ILIE;
1372         lpuart32_write(&sport->port, temp, UARTCTRL);
1373
1374         spin_unlock_irqrestore(&sport->port.lock, flags);
1375         return 0;
1376 }
1377
1378 static void lpuart_shutdown(struct uart_port *port)
1379 {
1380         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1381         unsigned char temp;
1382         unsigned long flags;
1383
1384         spin_lock_irqsave(&port->lock, flags);
1385
1386         /* disable Rx/Tx and interrupts */
1387         temp = readb(port->membase + UARTCR2);
1388         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1389                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1390         writeb(temp, port->membase + UARTCR2);
1391
1392         spin_unlock_irqrestore(&port->lock, flags);
1393
1394         if (sport->lpuart_dma_rx_use) {
1395                 del_timer_sync(&sport->lpuart_timer);
1396                 lpuart_dma_rx_free(&sport->port);
1397         }
1398
1399         if (sport->lpuart_dma_tx_use) {
1400                 if (wait_event_interruptible(sport->dma_wait,
1401                         !sport->dma_tx_in_progress) != false) {
1402                         sport->dma_tx_in_progress = false;
1403                         dmaengine_terminate_all(sport->dma_tx_chan);
1404                 }
1405
1406                 lpuart_stop_tx(port);
1407         }
1408 }
1409
1410 static void lpuart32_shutdown(struct uart_port *port)
1411 {
1412         unsigned long temp;
1413         unsigned long flags;
1414
1415         spin_lock_irqsave(&port->lock, flags);
1416
1417         /* disable Rx/Tx and interrupts */
1418         temp = lpuart32_read(port, UARTCTRL);
1419         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1420                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1421         lpuart32_write(port, temp, UARTCTRL);
1422
1423         spin_unlock_irqrestore(&port->lock, flags);
1424 }
1425
1426 static void
1427 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1428                    struct ktermios *old)
1429 {
1430         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1431         unsigned long flags;
1432         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1433         unsigned int  baud;
1434         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1435         unsigned int sbr, brfa;
1436
1437         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1438         old_cr2 = readb(sport->port.membase + UARTCR2);
1439         cr3 = readb(sport->port.membase + UARTCR3);
1440         cr4 = readb(sport->port.membase + UARTCR4);
1441         bdh = readb(sport->port.membase + UARTBDH);
1442         modem = readb(sport->port.membase + UARTMODEM);
1443         /*
1444          * only support CS8 and CS7, and for CS7 must enable PE.
1445          * supported mode:
1446          *  - (7,e/o,1)
1447          *  - (8,n,1)
1448          *  - (8,m/s,1)
1449          *  - (8,e/o,1)
1450          */
1451         while ((termios->c_cflag & CSIZE) != CS8 &&
1452                 (termios->c_cflag & CSIZE) != CS7) {
1453                 termios->c_cflag &= ~CSIZE;
1454                 termios->c_cflag |= old_csize;
1455                 old_csize = CS8;
1456         }
1457
1458         if ((termios->c_cflag & CSIZE) == CS8 ||
1459                 (termios->c_cflag & CSIZE) == CS7)
1460                 cr1 = old_cr1 & ~UARTCR1_M;
1461
1462         if (termios->c_cflag & CMSPAR) {
1463                 if ((termios->c_cflag & CSIZE) != CS8) {
1464                         termios->c_cflag &= ~CSIZE;
1465                         termios->c_cflag |= CS8;
1466                 }
1467                 cr1 |= UARTCR1_M;
1468         }
1469
1470         /*
1471          * When auto RS-485 RTS mode is enabled,
1472          * hardware flow control need to be disabled.
1473          */
1474         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1475                 termios->c_cflag &= ~CRTSCTS;
1476
1477         if (termios->c_cflag & CRTSCTS) {
1478                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1479         } else {
1480                 termios->c_cflag &= ~CRTSCTS;
1481                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1482         }
1483
1484         if (termios->c_cflag & CSTOPB)
1485                 termios->c_cflag &= ~CSTOPB;
1486
1487         /* parity must be enabled when CS7 to match 8-bits format */
1488         if ((termios->c_cflag & CSIZE) == CS7)
1489                 termios->c_cflag |= PARENB;
1490
1491         if ((termios->c_cflag & PARENB)) {
1492                 if (termios->c_cflag & CMSPAR) {
1493                         cr1 &= ~UARTCR1_PE;
1494                         if (termios->c_cflag & PARODD)
1495                                 cr3 |= UARTCR3_T8;
1496                         else
1497                                 cr3 &= ~UARTCR3_T8;
1498                 } else {
1499                         cr1 |= UARTCR1_PE;
1500                         if ((termios->c_cflag & CSIZE) == CS8)
1501                                 cr1 |= UARTCR1_M;
1502                         if (termios->c_cflag & PARODD)
1503                                 cr1 |= UARTCR1_PT;
1504                         else
1505                                 cr1 &= ~UARTCR1_PT;
1506                 }
1507         } else {
1508                 cr1 &= ~UARTCR1_PE;
1509         }
1510
1511         /* ask the core to calculate the divisor */
1512         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1513
1514         /*
1515          * Need to update the Ring buffer length according to the selected
1516          * baud rate and restart Rx DMA path.
1517          *
1518          * Since timer function acqures sport->port.lock, need to stop before
1519          * acquring same lock because otherwise del_timer_sync() can deadlock.
1520          */
1521         if (old && sport->lpuart_dma_rx_use) {
1522                 del_timer_sync(&sport->lpuart_timer);
1523                 lpuart_dma_rx_free(&sport->port);
1524         }
1525
1526         spin_lock_irqsave(&sport->port.lock, flags);
1527
1528         sport->port.read_status_mask = 0;
1529         if (termios->c_iflag & INPCK)
1530                 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
1531         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1532                 sport->port.read_status_mask |= UARTSR1_FE;
1533
1534         /* characters to ignore */
1535         sport->port.ignore_status_mask = 0;
1536         if (termios->c_iflag & IGNPAR)
1537                 sport->port.ignore_status_mask |= UARTSR1_PE;
1538         if (termios->c_iflag & IGNBRK) {
1539                 sport->port.ignore_status_mask |= UARTSR1_FE;
1540                 /*
1541                  * if we're ignoring parity and break indicators,
1542                  * ignore overruns too (for real raw support).
1543                  */
1544                 if (termios->c_iflag & IGNPAR)
1545                         sport->port.ignore_status_mask |= UARTSR1_OR;
1546         }
1547
1548         /* update the per-port timeout */
1549         uart_update_timeout(port, termios->c_cflag, baud);
1550
1551         /* wait transmit engin complete */
1552         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1553                 barrier();
1554
1555         /* disable transmit and receive */
1556         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1557                         sport->port.membase + UARTCR2);
1558
1559         sbr = sport->port.uartclk / (16 * baud);
1560         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1561         bdh &= ~UARTBDH_SBR_MASK;
1562         bdh |= (sbr >> 8) & 0x1F;
1563         cr4 &= ~UARTCR4_BRFA_MASK;
1564         brfa &= UARTCR4_BRFA_MASK;
1565         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1566         writeb(bdh, sport->port.membase + UARTBDH);
1567         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1568         writeb(cr3, sport->port.membase + UARTCR3);
1569         writeb(cr1, sport->port.membase + UARTCR1);
1570         writeb(modem, sport->port.membase + UARTMODEM);
1571
1572         /* restore control register */
1573         writeb(old_cr2, sport->port.membase + UARTCR2);
1574
1575         if (old && sport->lpuart_dma_rx_use) {
1576                 if (!lpuart_start_rx_dma(sport))
1577                         rx_dma_timer_init(sport);
1578                 else
1579                         sport->lpuart_dma_rx_use = false;
1580         }
1581
1582         spin_unlock_irqrestore(&sport->port.lock, flags);
1583 }
1584
1585 static void
1586 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
1587 {
1588         u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1589         u32 clk = sport->port.uartclk;
1590
1591         /*
1592          * The idea is to use the best OSR (over-sampling rate) possible.
1593          * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1594          * Loop to find the best OSR value possible, one that generates minimum
1595          * baud_diff iterate through the rest of the supported values of OSR.
1596          *
1597          * Calculation Formula:
1598          *  Baud Rate = baud clock / ((OSR+1) × SBR)
1599          */
1600         baud_diff = baudrate;
1601         osr = 0;
1602         sbr = 0;
1603
1604         for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1605                 /* calculate the temporary sbr value  */
1606                 tmp_sbr = (clk / (baudrate * tmp_osr));
1607                 if (tmp_sbr == 0)
1608                         tmp_sbr = 1;
1609
1610                 /*
1611                  * calculate the baud rate difference based on the temporary
1612                  * osr and sbr values
1613                  */
1614                 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1615
1616                 /* select best values between sbr and sbr+1 */
1617                 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1618                 if (tmp_diff > (baudrate - tmp)) {
1619                         tmp_diff = baudrate - tmp;
1620                         tmp_sbr++;
1621                 }
1622
1623                 if (tmp_diff <= baud_diff) {
1624                         baud_diff = tmp_diff;
1625                         osr = tmp_osr;
1626                         sbr = tmp_sbr;
1627
1628                         if (!baud_diff)
1629                                 break;
1630                 }
1631         }
1632
1633         /* handle buadrate outside acceptable rate */
1634         if (baud_diff > ((baudrate / 100) * 3))
1635                 dev_warn(sport->port.dev,
1636                          "unacceptable baud rate difference of more than 3%%\n");
1637
1638         tmp = lpuart32_read(&sport->port, UARTBAUD);
1639
1640         if ((osr > 3) && (osr < 8))
1641                 tmp |= UARTBAUD_BOTHEDGE;
1642
1643         tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1644         tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT);
1645
1646         tmp &= ~UARTBAUD_SBR_MASK;
1647         tmp |= sbr & UARTBAUD_SBR_MASK;
1648
1649         tmp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1650
1651         lpuart32_write(&sport->port, tmp, UARTBAUD);
1652 }
1653
1654 static void
1655 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1656                    struct ktermios *old)
1657 {
1658         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1659         unsigned long flags;
1660         unsigned long ctrl, old_ctrl, bd, modem;
1661         unsigned int  baud;
1662         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1663
1664         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1665         bd = lpuart32_read(&sport->port, UARTBAUD);
1666         modem = lpuart32_read(&sport->port, UARTMODIR);
1667         /*
1668          * only support CS8 and CS7, and for CS7 must enable PE.
1669          * supported mode:
1670          *  - (7,e/o,1)
1671          *  - (8,n,1)
1672          *  - (8,m/s,1)
1673          *  - (8,e/o,1)
1674          */
1675         while ((termios->c_cflag & CSIZE) != CS8 &&
1676                 (termios->c_cflag & CSIZE) != CS7) {
1677                 termios->c_cflag &= ~CSIZE;
1678                 termios->c_cflag |= old_csize;
1679                 old_csize = CS8;
1680         }
1681
1682         if ((termios->c_cflag & CSIZE) == CS8 ||
1683                 (termios->c_cflag & CSIZE) == CS7)
1684                 ctrl = old_ctrl & ~UARTCTRL_M;
1685
1686         if (termios->c_cflag & CMSPAR) {
1687                 if ((termios->c_cflag & CSIZE) != CS8) {
1688                         termios->c_cflag &= ~CSIZE;
1689                         termios->c_cflag |= CS8;
1690                 }
1691                 ctrl |= UARTCTRL_M;
1692         }
1693
1694         if (termios->c_cflag & CRTSCTS) {
1695                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1696         } else {
1697                 termios->c_cflag &= ~CRTSCTS;
1698                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1699         }
1700
1701         if (termios->c_cflag & CSTOPB)
1702                 termios->c_cflag &= ~CSTOPB;
1703
1704         /* parity must be enabled when CS7 to match 8-bits format */
1705         if ((termios->c_cflag & CSIZE) == CS7)
1706                 termios->c_cflag |= PARENB;
1707
1708         if ((termios->c_cflag & PARENB)) {
1709                 if (termios->c_cflag & CMSPAR) {
1710                         ctrl &= ~UARTCTRL_PE;
1711                         ctrl |= UARTCTRL_M;
1712                 } else {
1713                         ctrl |= UARTCR1_PE;
1714                         if ((termios->c_cflag & CSIZE) == CS8)
1715                                 ctrl |= UARTCTRL_M;
1716                         if (termios->c_cflag & PARODD)
1717                                 ctrl |= UARTCTRL_PT;
1718                         else
1719                                 ctrl &= ~UARTCTRL_PT;
1720                 }
1721         } else {
1722                 ctrl &= ~UARTCTRL_PE;
1723         }
1724
1725         /* ask the core to calculate the divisor */
1726         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
1727
1728         spin_lock_irqsave(&sport->port.lock, flags);
1729
1730         sport->port.read_status_mask = 0;
1731         if (termios->c_iflag & INPCK)
1732                 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1733         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1734                 sport->port.read_status_mask |= UARTSTAT_FE;
1735
1736         /* characters to ignore */
1737         sport->port.ignore_status_mask = 0;
1738         if (termios->c_iflag & IGNPAR)
1739                 sport->port.ignore_status_mask |= UARTSTAT_PE;
1740         if (termios->c_iflag & IGNBRK) {
1741                 sport->port.ignore_status_mask |= UARTSTAT_FE;
1742                 /*
1743                  * if we're ignoring parity and break indicators,
1744                  * ignore overruns too (for real raw support).
1745                  */
1746                 if (termios->c_iflag & IGNPAR)
1747                         sport->port.ignore_status_mask |= UARTSTAT_OR;
1748         }
1749
1750         /* update the per-port timeout */
1751         uart_update_timeout(port, termios->c_cflag, baud);
1752
1753         /* wait transmit engin complete */
1754         while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1755                 barrier();
1756
1757         /* disable transmit and receive */
1758         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1759                        UARTCTRL);
1760
1761         lpuart32_serial_setbrg(sport, baud);
1762         lpuart32_write(&sport->port, modem, UARTMODIR);
1763         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1764         /* restore control register */
1765
1766         spin_unlock_irqrestore(&sport->port.lock, flags);
1767 }
1768
1769 static const char *lpuart_type(struct uart_port *port)
1770 {
1771         return "FSL_LPUART";
1772 }
1773
1774 static void lpuart_release_port(struct uart_port *port)
1775 {
1776         /* nothing to do */
1777 }
1778
1779 static int lpuart_request_port(struct uart_port *port)
1780 {
1781         return  0;
1782 }
1783
1784 /* configure/autoconfigure the port */
1785 static void lpuart_config_port(struct uart_port *port, int flags)
1786 {
1787         if (flags & UART_CONFIG_TYPE)
1788                 port->type = PORT_LPUART;
1789 }
1790
1791 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1792 {
1793         int ret = 0;
1794
1795         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1796                 ret = -EINVAL;
1797         if (port->irq != ser->irq)
1798                 ret = -EINVAL;
1799         if (ser->io_type != UPIO_MEM)
1800                 ret = -EINVAL;
1801         if (port->uartclk / 16 != ser->baud_base)
1802                 ret = -EINVAL;
1803         if (port->iobase != ser->port)
1804                 ret = -EINVAL;
1805         if (ser->hub6 != 0)
1806                 ret = -EINVAL;
1807         return ret;
1808 }
1809
1810 static const struct uart_ops lpuart_pops = {
1811         .tx_empty       = lpuart_tx_empty,
1812         .set_mctrl      = lpuart_set_mctrl,
1813         .get_mctrl      = lpuart_get_mctrl,
1814         .stop_tx        = lpuart_stop_tx,
1815         .start_tx       = lpuart_start_tx,
1816         .stop_rx        = lpuart_stop_rx,
1817         .break_ctl      = lpuart_break_ctl,
1818         .startup        = lpuart_startup,
1819         .shutdown       = lpuart_shutdown,
1820         .set_termios    = lpuart_set_termios,
1821         .type           = lpuart_type,
1822         .request_port   = lpuart_request_port,
1823         .release_port   = lpuart_release_port,
1824         .config_port    = lpuart_config_port,
1825         .verify_port    = lpuart_verify_port,
1826         .flush_buffer   = lpuart_flush_buffer,
1827 #if defined(CONFIG_CONSOLE_POLL)
1828         .poll_init      = lpuart_poll_init,
1829         .poll_get_char  = lpuart_poll_get_char,
1830         .poll_put_char  = lpuart_poll_put_char,
1831 #endif
1832 };
1833
1834 static const struct uart_ops lpuart32_pops = {
1835         .tx_empty       = lpuart32_tx_empty,
1836         .set_mctrl      = lpuart32_set_mctrl,
1837         .get_mctrl      = lpuart32_get_mctrl,
1838         .stop_tx        = lpuart32_stop_tx,
1839         .start_tx       = lpuart32_start_tx,
1840         .stop_rx        = lpuart32_stop_rx,
1841         .break_ctl      = lpuart32_break_ctl,
1842         .startup        = lpuart32_startup,
1843         .shutdown       = lpuart32_shutdown,
1844         .set_termios    = lpuart32_set_termios,
1845         .type           = lpuart_type,
1846         .request_port   = lpuart_request_port,
1847         .release_port   = lpuart_release_port,
1848         .config_port    = lpuart_config_port,
1849         .verify_port    = lpuart_verify_port,
1850         .flush_buffer   = lpuart_flush_buffer,
1851 #if defined(CONFIG_CONSOLE_POLL)
1852         .poll_init      = lpuart32_poll_init,
1853         .poll_get_char  = lpuart32_poll_get_char,
1854         .poll_put_char  = lpuart32_poll_put_char,
1855 #endif
1856 };
1857
1858 static struct lpuart_port *lpuart_ports[UART_NR];
1859
1860 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1861 static void lpuart_console_putchar(struct uart_port *port, int ch)
1862 {
1863         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1864                 barrier();
1865
1866         writeb(ch, port->membase + UARTDR);
1867 }
1868
1869 static void lpuart32_console_putchar(struct uart_port *port, int ch)
1870 {
1871         while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
1872                 barrier();
1873
1874         lpuart32_write(port, ch, UARTDATA);
1875 }
1876
1877 static void
1878 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1879 {
1880         struct lpuart_port *sport = lpuart_ports[co->index];
1881         unsigned char  old_cr2, cr2;
1882         unsigned long flags;
1883         int locked = 1;
1884
1885         if (sport->port.sysrq || oops_in_progress)
1886                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1887         else
1888                 spin_lock_irqsave(&sport->port.lock, flags);
1889
1890         /* first save CR2 and then disable interrupts */
1891         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1892         cr2 |= (UARTCR2_TE |  UARTCR2_RE);
1893         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1894         writeb(cr2, sport->port.membase + UARTCR2);
1895
1896         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1897
1898         /* wait for transmitter finish complete and restore CR2 */
1899         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1900                 barrier();
1901
1902         writeb(old_cr2, sport->port.membase + UARTCR2);
1903
1904         if (locked)
1905                 spin_unlock_irqrestore(&sport->port.lock, flags);
1906 }
1907
1908 static void
1909 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1910 {
1911         struct lpuart_port *sport = lpuart_ports[co->index];
1912         unsigned long  old_cr, cr;
1913         unsigned long flags;
1914         int locked = 1;
1915
1916         if (sport->port.sysrq || oops_in_progress)
1917                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1918         else
1919                 spin_lock_irqsave(&sport->port.lock, flags);
1920
1921         /* first save CR2 and then disable interrupts */
1922         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
1923         cr |= (UARTCTRL_TE |  UARTCTRL_RE);
1924         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1925         lpuart32_write(&sport->port, cr, UARTCTRL);
1926
1927         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1928
1929         /* wait for transmitter finish complete and restore CR2 */
1930         while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1931                 barrier();
1932
1933         lpuart32_write(&sport->port, old_cr, UARTCTRL);
1934
1935         if (locked)
1936                 spin_unlock_irqrestore(&sport->port.lock, flags);
1937 }
1938
1939 /*
1940  * if the port was already initialised (eg, by a boot loader),
1941  * try to determine the current setup.
1942  */
1943 static void __init
1944 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1945                            int *parity, int *bits)
1946 {
1947         unsigned char cr, bdh, bdl, brfa;
1948         unsigned int sbr, uartclk, baud_raw;
1949
1950         cr = readb(sport->port.membase + UARTCR2);
1951         cr &= UARTCR2_TE | UARTCR2_RE;
1952         if (!cr)
1953                 return;
1954
1955         /* ok, the port was enabled */
1956
1957         cr = readb(sport->port.membase + UARTCR1);
1958
1959         *parity = 'n';
1960         if (cr & UARTCR1_PE) {
1961                 if (cr & UARTCR1_PT)
1962                         *parity = 'o';
1963                 else
1964                         *parity = 'e';
1965         }
1966
1967         if (cr & UARTCR1_M)
1968                 *bits = 9;
1969         else
1970                 *bits = 8;
1971
1972         bdh = readb(sport->port.membase + UARTBDH);
1973         bdh &= UARTBDH_SBR_MASK;
1974         bdl = readb(sport->port.membase + UARTBDL);
1975         sbr = bdh;
1976         sbr <<= 8;
1977         sbr |= bdl;
1978         brfa = readb(sport->port.membase + UARTCR4);
1979         brfa &= UARTCR4_BRFA_MASK;
1980
1981         uartclk = clk_get_rate(sport->clk);
1982         /*
1983          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1984          */
1985         baud_raw = uartclk / (16 * (sbr + brfa / 32));
1986
1987         if (*baud != baud_raw)
1988                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1989                                 "from %d to %d\n", baud_raw, *baud);
1990 }
1991
1992 static void __init
1993 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1994                            int *parity, int *bits)
1995 {
1996         unsigned long cr, bd;
1997         unsigned int sbr, uartclk, baud_raw;
1998
1999         cr = lpuart32_read(&sport->port, UARTCTRL);
2000         cr &= UARTCTRL_TE | UARTCTRL_RE;
2001         if (!cr)
2002                 return;
2003
2004         /* ok, the port was enabled */
2005
2006         cr = lpuart32_read(&sport->port, UARTCTRL);
2007
2008         *parity = 'n';
2009         if (cr & UARTCTRL_PE) {
2010                 if (cr & UARTCTRL_PT)
2011                         *parity = 'o';
2012                 else
2013                         *parity = 'e';
2014         }
2015
2016         if (cr & UARTCTRL_M)
2017                 *bits = 9;
2018         else
2019                 *bits = 8;
2020
2021         bd = lpuart32_read(&sport->port, UARTBAUD);
2022         bd &= UARTBAUD_SBR_MASK;
2023         if (!bd)
2024                 return;
2025
2026         sbr = bd;
2027         uartclk = clk_get_rate(sport->clk);
2028         /*
2029          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2030          */
2031         baud_raw = uartclk / (16 * sbr);
2032
2033         if (*baud != baud_raw)
2034                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
2035                                 "from %d to %d\n", baud_raw, *baud);
2036 }
2037
2038 static int __init lpuart_console_setup(struct console *co, char *options)
2039 {
2040         struct lpuart_port *sport;
2041         int baud = 115200;
2042         int bits = 8;
2043         int parity = 'n';
2044         int flow = 'n';
2045
2046         /*
2047          * check whether an invalid uart number has been specified, and
2048          * if so, search for the first available port that does have
2049          * console support.
2050          */
2051         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2052                 co->index = 0;
2053
2054         sport = lpuart_ports[co->index];
2055         if (sport == NULL)
2056                 return -ENODEV;
2057
2058         if (options)
2059                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2060         else
2061                 if (lpuart_is_32(sport))
2062                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
2063                 else
2064                         lpuart_console_get_options(sport, &baud, &parity, &bits);
2065
2066         if (lpuart_is_32(sport))
2067                 lpuart32_setup_watermark(sport);
2068         else
2069                 lpuart_setup_watermark(sport);
2070
2071         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2072 }
2073
2074 static struct uart_driver lpuart_reg;
2075 static struct console lpuart_console = {
2076         .name           = DEV_NAME,
2077         .write          = lpuart_console_write,
2078         .device         = uart_console_device,
2079         .setup          = lpuart_console_setup,
2080         .flags          = CON_PRINTBUFFER,
2081         .index          = -1,
2082         .data           = &lpuart_reg,
2083 };
2084
2085 static struct console lpuart32_console = {
2086         .name           = DEV_NAME,
2087         .write          = lpuart32_console_write,
2088         .device         = uart_console_device,
2089         .setup          = lpuart_console_setup,
2090         .flags          = CON_PRINTBUFFER,
2091         .index          = -1,
2092         .data           = &lpuart_reg,
2093 };
2094
2095 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2096 {
2097         struct earlycon_device *dev = con->data;
2098
2099         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2100 }
2101
2102 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2103 {
2104         struct earlycon_device *dev = con->data;
2105
2106         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2107 }
2108
2109 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2110                                           const char *opt)
2111 {
2112         if (!device->port.membase)
2113                 return -ENODEV;
2114
2115         device->con->write = lpuart_early_write;
2116         return 0;
2117 }
2118
2119 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2120                                           const char *opt)
2121 {
2122         if (!device->port.membase)
2123                 return -ENODEV;
2124
2125         device->port.iotype = UPIO_MEM32BE;
2126         device->con->write = lpuart32_early_write;
2127         return 0;
2128 }
2129
2130 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2131                                                    const char *opt)
2132 {
2133         if (!device->port.membase)
2134                 return -ENODEV;
2135
2136         device->port.iotype = UPIO_MEM32;
2137         device->port.membase += IMX_REG_OFF;
2138         device->con->write = lpuart32_early_write;
2139
2140         return 0;
2141 }
2142 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2143 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2144 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2145 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2146 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2147
2148 #define LPUART_CONSOLE  (&lpuart_console)
2149 #define LPUART32_CONSOLE        (&lpuart32_console)
2150 #else
2151 #define LPUART_CONSOLE  NULL
2152 #define LPUART32_CONSOLE        NULL
2153 #endif
2154
2155 static struct uart_driver lpuart_reg = {
2156         .owner          = THIS_MODULE,
2157         .driver_name    = DRIVER_NAME,
2158         .dev_name       = DEV_NAME,
2159         .nr             = ARRAY_SIZE(lpuart_ports),
2160         .cons           = LPUART_CONSOLE,
2161 };
2162
2163 static int lpuart_probe(struct platform_device *pdev)
2164 {
2165         const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2166                                                            &pdev->dev);
2167         const struct lpuart_soc_data *sdata = of_id->data;
2168         struct device_node *np = pdev->dev.of_node;
2169         struct lpuart_port *sport;
2170         struct resource *res;
2171         int ret;
2172
2173         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2174         if (!sport)
2175                 return -ENOMEM;
2176
2177         pdev->dev.coherent_dma_mask = 0;
2178
2179         ret = of_alias_get_id(np, "serial");
2180         if (ret < 0) {
2181                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2182                 return ret;
2183         }
2184         if (ret >= ARRAY_SIZE(lpuart_ports)) {
2185                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2186                 return -EINVAL;
2187         }
2188         sport->port.line = ret;
2189         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2190         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2191         if (IS_ERR(sport->port.membase))
2192                 return PTR_ERR(sport->port.membase);
2193
2194         sport->port.membase += sdata->reg_off;
2195         sport->port.mapbase = res->start + sdata->reg_off;
2196         sport->port.dev = &pdev->dev;
2197         sport->port.type = PORT_LPUART;
2198         ret = platform_get_irq(pdev, 0);
2199         if (ret < 0) {
2200                 dev_err(&pdev->dev, "cannot obtain irq\n");
2201                 return ret;
2202         }
2203         sport->port.irq = ret;
2204         sport->port.iotype = sdata->iotype;
2205         if (lpuart_is_32(sport))
2206                 sport->port.ops = &lpuart32_pops;
2207         else
2208                 sport->port.ops = &lpuart_pops;
2209         sport->port.flags = UPF_BOOT_AUTOCONF;
2210
2211         sport->port.rs485_config = lpuart_config_rs485;
2212
2213         sport->clk = devm_clk_get(&pdev->dev, "ipg");
2214         if (IS_ERR(sport->clk)) {
2215                 ret = PTR_ERR(sport->clk);
2216                 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
2217                 return ret;
2218         }
2219
2220         ret = clk_prepare_enable(sport->clk);
2221         if (ret) {
2222                 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
2223                 return ret;
2224         }
2225
2226         sport->port.uartclk = clk_get_rate(sport->clk);
2227
2228         lpuart_ports[sport->port.line] = sport;
2229
2230         platform_set_drvdata(pdev, &sport->port);
2231
2232         if (lpuart_is_32(sport)) {
2233                 lpuart_reg.cons = LPUART32_CONSOLE;
2234                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2235                                         DRIVER_NAME, sport);
2236         } else {
2237                 lpuart_reg.cons = LPUART_CONSOLE;
2238                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2239                                         DRIVER_NAME, sport);
2240         }
2241
2242         if (ret)
2243                 goto failed_irq_request;
2244
2245         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2246         if (ret)
2247                 goto failed_attach_port;
2248
2249         sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2250         if (!sport->dma_tx_chan)
2251                 dev_info(sport->port.dev, "DMA tx channel request failed, "
2252                                 "operating without tx DMA\n");
2253
2254         sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2255         if (!sport->dma_rx_chan)
2256                 dev_info(sport->port.dev, "DMA rx channel request failed, "
2257                                 "operating without rx DMA\n");
2258
2259         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) {
2260                 sport->port.rs485.flags |= SER_RS485_ENABLED;
2261                 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND;
2262                 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM);
2263         }
2264
2265         return 0;
2266
2267 failed_attach_port:
2268 failed_irq_request:
2269         clk_disable_unprepare(sport->clk);
2270         return ret;
2271 }
2272
2273 static int lpuart_remove(struct platform_device *pdev)
2274 {
2275         struct lpuart_port *sport = platform_get_drvdata(pdev);
2276
2277         uart_remove_one_port(&lpuart_reg, &sport->port);
2278
2279         clk_disable_unprepare(sport->clk);
2280
2281         if (sport->dma_tx_chan)
2282                 dma_release_channel(sport->dma_tx_chan);
2283
2284         if (sport->dma_rx_chan)
2285                 dma_release_channel(sport->dma_rx_chan);
2286
2287         return 0;
2288 }
2289
2290 #ifdef CONFIG_PM_SLEEP
2291 static int lpuart_suspend(struct device *dev)
2292 {
2293         struct lpuart_port *sport = dev_get_drvdata(dev);
2294         unsigned long temp;
2295         bool irq_wake;
2296
2297         if (lpuart_is_32(sport)) {
2298                 /* disable Rx/Tx and interrupts */
2299                 temp = lpuart32_read(&sport->port, UARTCTRL);
2300                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2301                 lpuart32_write(&sport->port, temp, UARTCTRL);
2302         } else {
2303                 /* disable Rx/Tx and interrupts */
2304                 temp = readb(sport->port.membase + UARTCR2);
2305                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2306                 writeb(temp, sport->port.membase + UARTCR2);
2307         }
2308
2309         uart_suspend_port(&lpuart_reg, &sport->port);
2310
2311         /* uart_suspend_port() might set wakeup flag */
2312         irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2313
2314         if (sport->lpuart_dma_rx_use) {
2315                 /*
2316                  * EDMA driver during suspend will forcefully release any
2317                  * non-idle DMA channels. If port wakeup is enabled or if port
2318                  * is console port or 'no_console_suspend' is set the Rx DMA
2319                  * cannot resume as as expected, hence gracefully release the
2320                  * Rx DMA path before suspend and start Rx DMA path on resume.
2321                  */
2322                 if (irq_wake) {
2323                         del_timer_sync(&sport->lpuart_timer);
2324                         lpuart_dma_rx_free(&sport->port);
2325                 }
2326
2327                 /* Disable Rx DMA to use UART port as wakeup source */
2328                 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
2329                                         sport->port.membase + UARTCR5);
2330         }
2331
2332         if (sport->lpuart_dma_tx_use) {
2333                 sport->dma_tx_in_progress = false;
2334                 dmaengine_terminate_all(sport->dma_tx_chan);
2335         }
2336
2337         if (sport->port.suspended && !irq_wake)
2338                 clk_disable_unprepare(sport->clk);
2339
2340         return 0;
2341 }
2342
2343 static int lpuart_resume(struct device *dev)
2344 {
2345         struct lpuart_port *sport = dev_get_drvdata(dev);
2346         bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2347         unsigned long temp;
2348
2349         if (sport->port.suspended && !irq_wake)
2350                 clk_prepare_enable(sport->clk);
2351
2352         if (lpuart_is_32(sport)) {
2353                 lpuart32_setup_watermark(sport);
2354                 temp = lpuart32_read(&sport->port, UARTCTRL);
2355                 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
2356                          UARTCTRL_TE | UARTCTRL_ILIE);
2357                 lpuart32_write(&sport->port, temp, UARTCTRL);
2358         } else {
2359                 lpuart_setup_watermark(sport);
2360                 temp = readb(sport->port.membase + UARTCR2);
2361                 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2362                 writeb(temp, sport->port.membase + UARTCR2);
2363         }
2364
2365         if (sport->lpuart_dma_rx_use) {
2366                 if (irq_wake) {
2367                         if (!lpuart_start_rx_dma(sport))
2368                                 rx_dma_timer_init(sport);
2369                         else
2370                                 sport->lpuart_dma_rx_use = false;
2371                 }
2372         }
2373
2374         if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2375                         init_waitqueue_head(&sport->dma_wait);
2376                         sport->lpuart_dma_tx_use = true;
2377                         writeb(readb(sport->port.membase + UARTCR5) |
2378                                 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2379         } else {
2380                 sport->lpuart_dma_tx_use = false;
2381         }
2382
2383         uart_resume_port(&lpuart_reg, &sport->port);
2384
2385         return 0;
2386 }
2387 #endif
2388
2389 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2390
2391 static struct platform_driver lpuart_driver = {
2392         .probe          = lpuart_probe,
2393         .remove         = lpuart_remove,
2394         .driver         = {
2395                 .name   = "fsl-lpuart",
2396                 .of_match_table = lpuart_dt_ids,
2397                 .pm     = &lpuart_pm_ops,
2398         },
2399 };
2400
2401 static int __init lpuart_serial_init(void)
2402 {
2403         int ret = uart_register_driver(&lpuart_reg);
2404
2405         if (ret)
2406                 return ret;
2407
2408         ret = platform_driver_register(&lpuart_driver);
2409         if (ret)
2410                 uart_unregister_driver(&lpuart_reg);
2411
2412         return ret;
2413 }
2414
2415 static void __exit lpuart_serial_exit(void)
2416 {
2417         platform_driver_unregister(&lpuart_driver);
2418         uart_unregister_driver(&lpuart_reg);
2419 }
2420
2421 module_init(lpuart_serial_init);
2422 module_exit(lpuart_serial_exit);
2423
2424 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2425 MODULE_LICENSE("GPL v2");