1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 * DMA support added by Chip Coldwell.
11 #include <linux/tty.h>
12 #include <linux/ioport.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/serial.h>
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/sysrq.h>
19 #include <linux/tty_flip.h>
20 #include <linux/platform_device.h>
22 #include <linux/of_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmaengine.h>
25 #include <linux/atmel_pdc.h>
26 #include <linux/uaccess.h>
27 #include <linux/platform_data/atmel.h>
28 #include <linux/timer.h>
29 #include <linux/err.h>
30 #include <linux/irq.h>
31 #include <linux/suspend.h>
34 #include <asm/div64.h>
36 #include <asm/ioctls.h>
38 #define PDC_BUFFER_SIZE 512
39 /* Revisit: We should calculate this based on the actual port settings */
40 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
42 /* The minium number of data FIFOs should be able to contain */
43 #define ATMEL_MIN_FIFO_SIZE 8
45 * These two offsets are substracted from the RX FIFO size to define the RTS
46 * high and low thresholds
48 #define ATMEL_RTS_HIGH_OFFSET 16
49 #define ATMEL_RTS_LOW_OFFSET 20
51 #include <linux/serial_core.h>
53 #include "serial_mctrl_gpio.h"
54 #include "atmel_serial.h"
56 static void atmel_start_rx(struct uart_port *port);
57 static void atmel_stop_rx(struct uart_port *port);
59 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
61 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
62 * should coexist with the 8250 driver, such as if we have an external 16C550
64 #define SERIAL_ATMEL_MAJOR 204
65 #define MINOR_START 154
66 #define ATMEL_DEVICENAME "ttyAT"
70 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
71 * name, but it is legally reserved for the 8250 driver. */
72 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
73 #define MINOR_START 64
74 #define ATMEL_DEVICENAME "ttyS"
78 #define ATMEL_ISR_PASS_LIMIT 256
80 struct atmel_dma_buffer {
83 unsigned int dma_size;
87 struct atmel_uart_char {
93 * Be careful, the real size of the ring buffer is
94 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
95 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
98 #define ATMEL_SERIAL_RINGSIZE 1024
101 * at91: 6 USARTs and one DBGU port (SAM9260)
102 * samx7: 3 USARTs and 5 UARTs
104 #define ATMEL_MAX_UART 8
107 * We wrap our port structure around the generic uart_port.
109 struct atmel_uart_port {
110 struct uart_port uart; /* uart */
111 struct clk *clk; /* uart clock */
112 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
113 u32 backup_imr; /* IMR saved during suspend */
114 int break_active; /* break being received */
116 bool use_dma_rx; /* enable DMA receiver */
117 bool use_pdc_rx; /* enable PDC receiver */
118 short pdc_rx_idx; /* current PDC RX buffer */
119 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
121 bool use_dma_tx; /* enable DMA transmitter */
122 bool use_pdc_tx; /* enable PDC transmitter */
123 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
125 spinlock_t lock_tx; /* port lock */
126 spinlock_t lock_rx; /* port lock */
127 struct dma_chan *chan_tx;
128 struct dma_chan *chan_rx;
129 struct dma_async_tx_descriptor *desc_tx;
130 struct dma_async_tx_descriptor *desc_rx;
131 dma_cookie_t cookie_tx;
132 dma_cookie_t cookie_rx;
133 struct scatterlist sg_tx;
134 struct scatterlist sg_rx;
135 struct tasklet_struct tasklet_rx;
136 struct tasklet_struct tasklet_tx;
137 atomic_t tasklet_shutdown;
138 unsigned int irq_status_prev;
141 struct circ_buf rx_ring;
143 struct mctrl_gpios *gpios;
144 u32 backup_mode; /* MR saved during iso7816 operations */
145 u32 backup_brgr; /* BRGR saved during iso7816 operations */
146 unsigned int tx_done_mask;
151 u32 rtor; /* address of receiver timeout register if it exists */
152 bool has_frac_baudrate;
154 struct timer_list uart_timer;
158 unsigned int pending;
159 unsigned int pending_status;
160 spinlock_t lock_suspended;
162 bool hd_start_rx; /* can start RX during half-duplex operation */
165 unsigned int fidi_min;
166 unsigned int fidi_max;
181 int (*prepare_rx)(struct uart_port *port);
182 int (*prepare_tx)(struct uart_port *port);
183 void (*schedule_rx)(struct uart_port *port);
184 void (*schedule_tx)(struct uart_port *port);
185 void (*release_rx)(struct uart_port *port);
186 void (*release_tx)(struct uart_port *port);
189 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
190 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
192 #if defined(CONFIG_OF)
193 static const struct of_device_id atmel_serial_dt_ids[] = {
194 { .compatible = "atmel,at91rm9200-usart-serial" },
199 static inline struct atmel_uart_port *
200 to_atmel_uart_port(struct uart_port *uart)
202 return container_of(uart, struct atmel_uart_port, uart);
205 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
207 return __raw_readl(port->membase + reg);
210 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
212 __raw_writel(value, port->membase + reg);
215 static inline u8 atmel_uart_read_char(struct uart_port *port)
217 return __raw_readb(port->membase + ATMEL_US_RHR);
220 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
222 __raw_writeb(value, port->membase + ATMEL_US_THR);
225 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
227 return ((port->rs485.flags & SER_RS485_ENABLED) &&
228 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
229 (port->iso7816.flags & SER_ISO7816_ENABLED);
232 #ifdef CONFIG_SERIAL_ATMEL_PDC
233 static bool atmel_use_pdc_rx(struct uart_port *port)
235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
237 return atmel_port->use_pdc_rx;
240 static bool atmel_use_pdc_tx(struct uart_port *port)
242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
244 return atmel_port->use_pdc_tx;
247 static bool atmel_use_pdc_rx(struct uart_port *port)
252 static bool atmel_use_pdc_tx(struct uart_port *port)
258 static bool atmel_use_dma_tx(struct uart_port *port)
260 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
262 return atmel_port->use_dma_tx;
265 static bool atmel_use_dma_rx(struct uart_port *port)
267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
269 return atmel_port->use_dma_rx;
272 static bool atmel_use_fifo(struct uart_port *port)
274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
276 return atmel_port->fifo_size;
279 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
280 struct tasklet_struct *t)
282 if (!atomic_read(&atmel_port->tasklet_shutdown))
286 /* Enable or disable the rs485 support */
287 static int atmel_config_rs485(struct uart_port *port,
288 struct serial_rs485 *rs485conf)
290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
293 /* Disable interrupts */
294 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
296 mode = atmel_uart_readl(port, ATMEL_US_MR);
298 if (rs485conf->flags & SER_RS485_ENABLED) {
299 dev_dbg(port->dev, "Setting UART to RS485\n");
300 if (rs485conf->flags & SER_RS485_RX_DURING_TX)
301 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
303 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
305 atmel_uart_writel(port, ATMEL_US_TTGR,
306 rs485conf->delay_rts_after_send);
307 mode &= ~ATMEL_US_USMODE;
308 mode |= ATMEL_US_USMODE_RS485;
310 dev_dbg(port->dev, "Setting UART to RS232\n");
311 if (atmel_use_pdc_tx(port))
312 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
315 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
317 atmel_uart_writel(port, ATMEL_US_MR, mode);
319 /* Enable interrupts */
320 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
325 static unsigned int atmel_calc_cd(struct uart_port *port,
326 struct serial_iso7816 *iso7816conf)
328 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
332 mck_rate = (u64)clk_get_rate(atmel_port->clk);
333 do_div(mck_rate, iso7816conf->clk);
338 static unsigned int atmel_calc_fidi(struct uart_port *port,
339 struct serial_iso7816 *iso7816conf)
343 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
344 fidi = (u64)iso7816conf->sc_fi;
345 do_div(fidi, iso7816conf->sc_di);
350 /* Enable or disable the iso7816 support */
351 /* Called with interrupts disabled */
352 static int atmel_config_iso7816(struct uart_port *port,
353 struct serial_iso7816 *iso7816conf)
355 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
357 unsigned int cd, fidi;
360 /* Disable interrupts */
361 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
363 mode = atmel_uart_readl(port, ATMEL_US_MR);
365 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
366 mode &= ~ATMEL_US_USMODE;
368 if (iso7816conf->tg > 255) {
369 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
370 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
375 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
376 == SER_ISO7816_T(0)) {
377 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
378 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
379 == SER_ISO7816_T(1)) {
380 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
382 dev_err(port->dev, "ISO7816: Type not supported\n");
383 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
388 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
390 /* select mck clock, and output */
391 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
392 /* set parity for normal/inverse mode + max iterations */
393 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
395 cd = atmel_calc_cd(port, iso7816conf);
396 fidi = atmel_calc_fidi(port, iso7816conf);
398 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
399 } else if (fidi < atmel_port->fidi_min
400 || fidi > atmel_port->fidi_max) {
401 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
402 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
407 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
408 /* port not yet in iso7816 mode: store configuration */
409 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
410 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
413 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
414 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
415 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
417 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
418 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
420 dev_dbg(port->dev, "Setting UART back to RS232\n");
421 /* back to last RS232 settings */
422 mode = atmel_port->backup_mode;
423 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
424 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
425 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
426 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
428 if (atmel_use_pdc_tx(port))
429 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
432 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
435 port->iso7816 = *iso7816conf;
437 atmel_uart_writel(port, ATMEL_US_MR, mode);
440 /* Enable interrupts */
441 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
447 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
449 static u_int atmel_tx_empty(struct uart_port *port)
451 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
453 if (atmel_port->tx_stopped)
455 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
461 * Set state of the modem control output lines
463 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
465 unsigned int control = 0;
466 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
467 unsigned int rts_paused, rts_ready;
468 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
470 /* override mode to RS485 if needed, otherwise keep the current mode */
471 if (port->rs485.flags & SER_RS485_ENABLED) {
472 atmel_uart_writel(port, ATMEL_US_TTGR,
473 port->rs485.delay_rts_after_send);
474 mode &= ~ATMEL_US_USMODE;
475 mode |= ATMEL_US_USMODE_RS485;
478 /* set the RTS line state according to the mode */
479 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
480 /* force RTS line to high level */
481 rts_paused = ATMEL_US_RTSEN;
483 /* give the control of the RTS line back to the hardware */
484 rts_ready = ATMEL_US_RTSDIS;
486 /* force RTS line to high level */
487 rts_paused = ATMEL_US_RTSDIS;
489 /* force RTS line to low level */
490 rts_ready = ATMEL_US_RTSEN;
493 if (mctrl & TIOCM_RTS)
494 control |= rts_ready;
496 control |= rts_paused;
498 if (mctrl & TIOCM_DTR)
499 control |= ATMEL_US_DTREN;
501 control |= ATMEL_US_DTRDIS;
503 atmel_uart_writel(port, ATMEL_US_CR, control);
505 mctrl_gpio_set(atmel_port->gpios, mctrl);
507 /* Local loopback mode? */
508 mode &= ~ATMEL_US_CHMODE;
509 if (mctrl & TIOCM_LOOP)
510 mode |= ATMEL_US_CHMODE_LOC_LOOP;
512 mode |= ATMEL_US_CHMODE_NORMAL;
514 atmel_uart_writel(port, ATMEL_US_MR, mode);
518 * Get state of the modem control input lines
520 static u_int atmel_get_mctrl(struct uart_port *port)
522 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
523 unsigned int ret = 0, status;
525 status = atmel_uart_readl(port, ATMEL_US_CSR);
528 * The control signals are active low.
530 if (!(status & ATMEL_US_DCD))
532 if (!(status & ATMEL_US_CTS))
534 if (!(status & ATMEL_US_DSR))
536 if (!(status & ATMEL_US_RI))
539 return mctrl_gpio_get(atmel_port->gpios, &ret);
545 static void atmel_stop_tx(struct uart_port *port)
547 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
549 if (atmel_use_pdc_tx(port)) {
550 /* disable PDC transmit */
551 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
555 * Disable the transmitter.
556 * This is mandatory when DMA is used, otherwise the DMA buffer
557 * is fully transmitted.
559 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
560 atmel_port->tx_stopped = true;
562 /* Disable interrupts */
563 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
565 if (atmel_uart_is_half_duplex(port))
566 if (!atomic_read(&atmel_port->tasklet_shutdown))
567 atmel_start_rx(port);
572 * Start transmitting.
574 static void atmel_start_tx(struct uart_port *port)
576 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
578 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
580 /* The transmitter is already running. Yes, we
584 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
585 if (atmel_uart_is_half_duplex(port))
588 if (atmel_use_pdc_tx(port))
589 /* re-enable PDC transmit */
590 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
592 /* Enable interrupts */
593 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
595 /* re-enable the transmitter */
596 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
597 atmel_port->tx_stopped = false;
601 * start receiving - port is in process of being opened.
603 static void atmel_start_rx(struct uart_port *port)
605 /* reset status and receiver */
606 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
608 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
610 if (atmel_use_pdc_rx(port)) {
611 /* enable PDC controller */
612 atmel_uart_writel(port, ATMEL_US_IER,
613 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
614 port->read_status_mask);
615 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
617 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
622 * Stop receiving - port is in process of being closed.
624 static void atmel_stop_rx(struct uart_port *port)
626 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
628 if (atmel_use_pdc_rx(port)) {
629 /* disable PDC receive */
630 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
631 atmel_uart_writel(port, ATMEL_US_IDR,
632 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
633 port->read_status_mask);
635 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
640 * Enable modem status interrupts
642 static void atmel_enable_ms(struct uart_port *port)
644 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
648 * Interrupt should not be enabled twice
650 if (atmel_port->ms_irq_enabled)
653 atmel_port->ms_irq_enabled = true;
655 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
656 ier |= ATMEL_US_CTSIC;
658 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
659 ier |= ATMEL_US_DSRIC;
661 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
662 ier |= ATMEL_US_RIIC;
664 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
665 ier |= ATMEL_US_DCDIC;
667 atmel_uart_writel(port, ATMEL_US_IER, ier);
669 mctrl_gpio_enable_ms(atmel_port->gpios);
673 * Disable modem status interrupts
675 static void atmel_disable_ms(struct uart_port *port)
677 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
681 * Interrupt should not be disabled twice
683 if (!atmel_port->ms_irq_enabled)
686 atmel_port->ms_irq_enabled = false;
688 mctrl_gpio_disable_ms(atmel_port->gpios);
690 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
691 idr |= ATMEL_US_CTSIC;
693 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
694 idr |= ATMEL_US_DSRIC;
696 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
697 idr |= ATMEL_US_RIIC;
699 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
700 idr |= ATMEL_US_DCDIC;
702 atmel_uart_writel(port, ATMEL_US_IDR, idr);
706 * Control the transmission of a break signal
708 static void atmel_break_ctl(struct uart_port *port, int break_state)
710 if (break_state != 0)
712 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
715 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
719 * Stores the incoming character in the ring buffer
722 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
725 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
726 struct circ_buf *ring = &atmel_port->rx_ring;
727 struct atmel_uart_char *c;
729 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
730 /* Buffer overflow, ignore char */
733 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
737 /* Make sure the character is stored before we update head. */
740 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
744 * Deal with parity, framing and overrun errors.
746 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
749 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
751 if (status & ATMEL_US_RXBRK) {
752 /* ignore side-effect */
753 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
756 if (status & ATMEL_US_PARE)
757 port->icount.parity++;
758 if (status & ATMEL_US_FRAME)
759 port->icount.frame++;
760 if (status & ATMEL_US_OVRE)
761 port->icount.overrun++;
765 * Characters received (called from interrupt handler)
767 static void atmel_rx_chars(struct uart_port *port)
769 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
770 unsigned int status, ch;
772 status = atmel_uart_readl(port, ATMEL_US_CSR);
773 while (status & ATMEL_US_RXRDY) {
774 ch = atmel_uart_read_char(port);
777 * note that the error handling code is
778 * out of the main execution path
780 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
781 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
782 || atmel_port->break_active)) {
785 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
787 if (status & ATMEL_US_RXBRK
788 && !atmel_port->break_active) {
789 atmel_port->break_active = 1;
790 atmel_uart_writel(port, ATMEL_US_IER,
794 * This is either the end-of-break
795 * condition or we've received at
796 * least one character without RXBRK
797 * being set. In both cases, the next
798 * RXBRK will indicate start-of-break.
800 atmel_uart_writel(port, ATMEL_US_IDR,
802 status &= ~ATMEL_US_RXBRK;
803 atmel_port->break_active = 0;
807 atmel_buffer_rx_char(port, status, ch);
808 status = atmel_uart_readl(port, ATMEL_US_CSR);
811 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
815 * Transmit characters (called from tasklet with TXRDY interrupt
818 static void atmel_tx_chars(struct uart_port *port)
820 struct circ_buf *xmit = &port->state->xmit;
821 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
824 (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) {
825 atmel_uart_write_char(port, port->x_char);
829 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
832 while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) {
833 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
834 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
836 if (uart_circ_empty(xmit))
840 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
841 uart_write_wakeup(port);
843 if (!uart_circ_empty(xmit)) {
844 /* we still have characters to transmit, so we should continue
845 * transmitting them when TX is ready, regardless of
848 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
850 /* Enable interrupts */
851 atmel_uart_writel(port, ATMEL_US_IER,
852 atmel_port->tx_done_mask);
854 if (atmel_uart_is_half_duplex(port))
855 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
859 static void atmel_complete_tx_dma(void *arg)
861 struct atmel_uart_port *atmel_port = arg;
862 struct uart_port *port = &atmel_port->uart;
863 struct circ_buf *xmit = &port->state->xmit;
864 struct dma_chan *chan = atmel_port->chan_tx;
867 spin_lock_irqsave(&port->lock, flags);
870 dmaengine_terminate_all(chan);
871 xmit->tail += atmel_port->tx_len;
872 xmit->tail &= UART_XMIT_SIZE - 1;
874 port->icount.tx += atmel_port->tx_len;
876 spin_lock_irq(&atmel_port->lock_tx);
877 async_tx_ack(atmel_port->desc_tx);
878 atmel_port->cookie_tx = -EINVAL;
879 atmel_port->desc_tx = NULL;
880 spin_unlock_irq(&atmel_port->lock_tx);
882 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
883 uart_write_wakeup(port);
886 * xmit is a circular buffer so, if we have just send data from
887 * xmit->tail to the end of xmit->buf, now we have to transmit the
888 * remaining data from the beginning of xmit->buf to xmit->head.
890 if (!uart_circ_empty(xmit))
891 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
892 else if (atmel_uart_is_half_duplex(port)) {
894 * DMA done, re-enable TXEMPTY and signal that we can stop
895 * TX and start RX for RS485
897 atmel_port->hd_start_rx = true;
898 atmel_uart_writel(port, ATMEL_US_IER,
899 atmel_port->tx_done_mask);
902 spin_unlock_irqrestore(&port->lock, flags);
905 static void atmel_release_tx_dma(struct uart_port *port)
907 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
908 struct dma_chan *chan = atmel_port->chan_tx;
911 dmaengine_terminate_all(chan);
912 dma_release_channel(chan);
913 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
917 atmel_port->desc_tx = NULL;
918 atmel_port->chan_tx = NULL;
919 atmel_port->cookie_tx = -EINVAL;
923 * Called from tasklet with TXRDY interrupt is disabled.
925 static void atmel_tx_dma(struct uart_port *port)
927 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
928 struct circ_buf *xmit = &port->state->xmit;
929 struct dma_chan *chan = atmel_port->chan_tx;
930 struct dma_async_tx_descriptor *desc;
931 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
932 unsigned int tx_len, part1_len, part2_len, sg_len;
933 dma_addr_t phys_addr;
935 /* Make sure we have an idle channel */
936 if (atmel_port->desc_tx != NULL)
939 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
942 * Port xmit buffer is already mapped,
943 * and it is one page... Just adjust
944 * offsets and lengths. Since it is a circular buffer,
945 * we have to transmit till the end, and then the rest.
946 * Take the port lock to get a
947 * consistent xmit buffer state.
949 tx_len = CIRC_CNT_TO_END(xmit->head,
953 if (atmel_port->fifo_size) {
954 /* multi data mode */
955 part1_len = (tx_len & ~0x3); /* DWORD access */
956 part2_len = (tx_len & 0x3); /* BYTE access */
958 /* single data (legacy) mode */
960 part2_len = tx_len; /* BYTE access only */
963 sg_init_table(sgl, 2);
965 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
968 sg_dma_address(sg) = phys_addr;
969 sg_dma_len(sg) = part1_len;
971 phys_addr += part1_len;
976 sg_dma_address(sg) = phys_addr;
977 sg_dma_len(sg) = part2_len;
981 * save tx_len so atmel_complete_tx_dma() will increase
982 * xmit->tail correctly
984 atmel_port->tx_len = tx_len;
986 desc = dmaengine_prep_slave_sg(chan,
993 dev_err(port->dev, "Failed to send via dma!\n");
997 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
999 atmel_port->desc_tx = desc;
1000 desc->callback = atmel_complete_tx_dma;
1001 desc->callback_param = atmel_port;
1002 atmel_port->cookie_tx = dmaengine_submit(desc);
1003 if (dma_submit_error(atmel_port->cookie_tx)) {
1004 dev_err(port->dev, "dma_submit_error %d\n",
1005 atmel_port->cookie_tx);
1009 dma_async_issue_pending(chan);
1012 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1013 uart_write_wakeup(port);
1016 static int atmel_prepare_tx_dma(struct uart_port *port)
1018 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1019 struct device *mfd_dev = port->dev->parent;
1020 dma_cap_mask_t mask;
1021 struct dma_slave_config config;
1025 dma_cap_set(DMA_SLAVE, mask);
1027 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1028 if (atmel_port->chan_tx == NULL)
1030 dev_info(port->dev, "using %s for tx DMA transfers\n",
1031 dma_chan_name(atmel_port->chan_tx));
1033 spin_lock_init(&atmel_port->lock_tx);
1034 sg_init_table(&atmel_port->sg_tx, 1);
1035 /* UART circular tx buffer is an aligned page. */
1036 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1037 sg_set_page(&atmel_port->sg_tx,
1038 virt_to_page(port->state->xmit.buf),
1040 offset_in_page(port->state->xmit.buf));
1041 nent = dma_map_sg(port->dev,
1047 dev_dbg(port->dev, "need to release resource of dma\n");
1050 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1051 sg_dma_len(&atmel_port->sg_tx),
1052 port->state->xmit.buf,
1053 &sg_dma_address(&atmel_port->sg_tx));
1056 /* Configure the slave DMA */
1057 memset(&config, 0, sizeof(config));
1058 config.direction = DMA_MEM_TO_DEV;
1059 config.dst_addr_width = (atmel_port->fifo_size) ?
1060 DMA_SLAVE_BUSWIDTH_4_BYTES :
1061 DMA_SLAVE_BUSWIDTH_1_BYTE;
1062 config.dst_addr = port->mapbase + ATMEL_US_THR;
1063 config.dst_maxburst = 1;
1065 ret = dmaengine_slave_config(atmel_port->chan_tx,
1068 dev_err(port->dev, "DMA tx slave configuration failed\n");
1075 dev_err(port->dev, "TX channel not available, switch to pio\n");
1076 atmel_port->use_dma_tx = false;
1077 if (atmel_port->chan_tx)
1078 atmel_release_tx_dma(port);
1082 static void atmel_complete_rx_dma(void *arg)
1084 struct uart_port *port = arg;
1085 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1087 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1090 static void atmel_release_rx_dma(struct uart_port *port)
1092 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1093 struct dma_chan *chan = atmel_port->chan_rx;
1096 dmaengine_terminate_all(chan);
1097 dma_release_channel(chan);
1098 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1102 atmel_port->desc_rx = NULL;
1103 atmel_port->chan_rx = NULL;
1104 atmel_port->cookie_rx = -EINVAL;
1107 static void atmel_rx_from_dma(struct uart_port *port)
1109 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1110 struct tty_port *tport = &port->state->port;
1111 struct circ_buf *ring = &atmel_port->rx_ring;
1112 struct dma_chan *chan = atmel_port->chan_rx;
1113 struct dma_tx_state state;
1114 enum dma_status dmastat;
1118 /* Reset the UART timeout early so that we don't miss one */
1119 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1120 dmastat = dmaengine_tx_status(chan,
1121 atmel_port->cookie_rx,
1123 /* Restart a new tasklet if DMA status is error */
1124 if (dmastat == DMA_ERROR) {
1125 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1126 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1127 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1131 /* CPU claims ownership of RX DMA buffer */
1132 dma_sync_sg_for_cpu(port->dev,
1138 * ring->head points to the end of data already written by the DMA.
1139 * ring->tail points to the beginning of data to be read by the
1141 * The current transfer size should not be larger than the dma buffer
1144 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1145 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1147 * At this point ring->head may point to the first byte right after the
1148 * last byte of the dma buffer:
1149 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1151 * However ring->tail must always points inside the dma buffer:
1152 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1154 * Since we use a ring buffer, we have to handle the case
1155 * where head is lower than tail. In such a case, we first read from
1156 * tail to the end of the buffer then reset tail.
1158 if (ring->head < ring->tail) {
1159 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1161 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1163 port->icount.rx += count;
1166 /* Finally we read data from tail to head */
1167 if (ring->tail < ring->head) {
1168 count = ring->head - ring->tail;
1170 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1171 /* Wrap ring->head if needed */
1172 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1174 ring->tail = ring->head;
1175 port->icount.rx += count;
1178 /* USART retreives ownership of RX DMA buffer */
1179 dma_sync_sg_for_device(port->dev,
1185 * Drop the lock here since it might end up calling
1186 * uart_start(), which takes the lock.
1188 spin_unlock(&port->lock);
1189 tty_flip_buffer_push(tport);
1190 spin_lock(&port->lock);
1192 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1195 static int atmel_prepare_rx_dma(struct uart_port *port)
1197 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1198 struct device *mfd_dev = port->dev->parent;
1199 struct dma_async_tx_descriptor *desc;
1200 dma_cap_mask_t mask;
1201 struct dma_slave_config config;
1202 struct circ_buf *ring;
1205 ring = &atmel_port->rx_ring;
1208 dma_cap_set(DMA_CYCLIC, mask);
1210 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1211 if (atmel_port->chan_rx == NULL)
1213 dev_info(port->dev, "using %s for rx DMA transfers\n",
1214 dma_chan_name(atmel_port->chan_rx));
1216 spin_lock_init(&atmel_port->lock_rx);
1217 sg_init_table(&atmel_port->sg_rx, 1);
1218 /* UART circular rx buffer is an aligned page. */
1219 BUG_ON(!PAGE_ALIGNED(ring->buf));
1220 sg_set_page(&atmel_port->sg_rx,
1221 virt_to_page(ring->buf),
1222 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1223 offset_in_page(ring->buf));
1224 nent = dma_map_sg(port->dev,
1230 dev_dbg(port->dev, "need to release resource of dma\n");
1233 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1234 sg_dma_len(&atmel_port->sg_rx),
1236 &sg_dma_address(&atmel_port->sg_rx));
1239 /* Configure the slave DMA */
1240 memset(&config, 0, sizeof(config));
1241 config.direction = DMA_DEV_TO_MEM;
1242 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1243 config.src_addr = port->mapbase + ATMEL_US_RHR;
1244 config.src_maxburst = 1;
1246 ret = dmaengine_slave_config(atmel_port->chan_rx,
1249 dev_err(port->dev, "DMA rx slave configuration failed\n");
1253 * Prepare a cyclic dma transfer, assign 2 descriptors,
1254 * each one is half ring buffer size
1256 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1257 sg_dma_address(&atmel_port->sg_rx),
1258 sg_dma_len(&atmel_port->sg_rx),
1259 sg_dma_len(&atmel_port->sg_rx)/2,
1261 DMA_PREP_INTERRUPT);
1263 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1266 desc->callback = atmel_complete_rx_dma;
1267 desc->callback_param = port;
1268 atmel_port->desc_rx = desc;
1269 atmel_port->cookie_rx = dmaengine_submit(desc);
1270 if (dma_submit_error(atmel_port->cookie_rx)) {
1271 dev_err(port->dev, "dma_submit_error %d\n",
1272 atmel_port->cookie_rx);
1276 dma_async_issue_pending(atmel_port->chan_rx);
1281 dev_err(port->dev, "RX channel not available, switch to pio\n");
1282 atmel_port->use_dma_rx = false;
1283 if (atmel_port->chan_rx)
1284 atmel_release_rx_dma(port);
1288 static void atmel_uart_timer_callback(struct timer_list *t)
1290 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1292 struct uart_port *port = &atmel_port->uart;
1294 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1295 tasklet_schedule(&atmel_port->tasklet_rx);
1296 mod_timer(&atmel_port->uart_timer,
1297 jiffies + uart_poll_timeout(port));
1302 * receive interrupt handler.
1305 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1307 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1309 if (atmel_use_pdc_rx(port)) {
1311 * PDC receive. Just schedule the tasklet and let it
1312 * figure out the details.
1314 * TODO: We're not handling error flags correctly at
1317 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1318 atmel_uart_writel(port, ATMEL_US_IDR,
1319 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1320 atmel_tasklet_schedule(atmel_port,
1321 &atmel_port->tasklet_rx);
1324 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1325 ATMEL_US_FRAME | ATMEL_US_PARE))
1326 atmel_pdc_rxerr(port, pending);
1329 if (atmel_use_dma_rx(port)) {
1330 if (pending & ATMEL_US_TIMEOUT) {
1331 atmel_uart_writel(port, ATMEL_US_IDR,
1333 atmel_tasklet_schedule(atmel_port,
1334 &atmel_port->tasklet_rx);
1338 /* Interrupt receive */
1339 if (pending & ATMEL_US_RXRDY)
1340 atmel_rx_chars(port);
1341 else if (pending & ATMEL_US_RXBRK) {
1343 * End of break detected. If it came along with a
1344 * character, atmel_rx_chars will handle it.
1346 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1347 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1348 atmel_port->break_active = 0;
1353 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1356 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1358 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1360 if (pending & atmel_port->tx_done_mask) {
1361 atmel_uart_writel(port, ATMEL_US_IDR,
1362 atmel_port->tx_done_mask);
1364 /* Start RX if flag was set and FIFO is empty */
1365 if (atmel_port->hd_start_rx) {
1366 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1367 & ATMEL_US_TXEMPTY))
1368 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1370 atmel_port->hd_start_rx = false;
1371 atmel_start_rx(port);
1374 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1379 * status flags interrupt handler.
1382 atmel_handle_status(struct uart_port *port, unsigned int pending,
1383 unsigned int status)
1385 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1386 unsigned int status_change;
1388 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1389 | ATMEL_US_CTSIC)) {
1390 status_change = status ^ atmel_port->irq_status_prev;
1391 atmel_port->irq_status_prev = status;
1393 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1394 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1395 /* TODO: All reads to CSR will clear these interrupts! */
1396 if (status_change & ATMEL_US_RI)
1398 if (status_change & ATMEL_US_DSR)
1400 if (status_change & ATMEL_US_DCD)
1401 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1402 if (status_change & ATMEL_US_CTS)
1403 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1405 wake_up_interruptible(&port->state->port.delta_msr_wait);
1409 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1410 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1416 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1418 struct uart_port *port = dev_id;
1419 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1420 unsigned int status, pending, mask, pass_counter = 0;
1422 spin_lock(&atmel_port->lock_suspended);
1425 status = atmel_uart_readl(port, ATMEL_US_CSR);
1426 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1427 pending = status & mask;
1431 if (atmel_port->suspended) {
1432 atmel_port->pending |= pending;
1433 atmel_port->pending_status = status;
1434 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1439 atmel_handle_receive(port, pending);
1440 atmel_handle_status(port, pending, status);
1441 atmel_handle_transmit(port, pending);
1442 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1444 spin_unlock(&atmel_port->lock_suspended);
1446 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1449 static void atmel_release_tx_pdc(struct uart_port *port)
1451 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1452 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1454 dma_unmap_single(port->dev,
1461 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1463 static void atmel_tx_pdc(struct uart_port *port)
1465 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1466 struct circ_buf *xmit = &port->state->xmit;
1467 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1470 /* nothing left to transmit? */
1471 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1474 xmit->tail += pdc->ofs;
1475 xmit->tail &= UART_XMIT_SIZE - 1;
1477 port->icount.tx += pdc->ofs;
1480 /* more to transmit - setup next transfer */
1482 /* disable PDC transmit */
1483 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1485 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1486 dma_sync_single_for_device(port->dev,
1491 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1494 atmel_uart_writel(port, ATMEL_PDC_TPR,
1495 pdc->dma_addr + xmit->tail);
1496 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1497 /* re-enable PDC transmit */
1498 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1499 /* Enable interrupts */
1500 atmel_uart_writel(port, ATMEL_US_IER,
1501 atmel_port->tx_done_mask);
1503 if (atmel_uart_is_half_duplex(port)) {
1504 /* DMA done, stop TX, start RX for RS485 */
1505 atmel_start_rx(port);
1509 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1510 uart_write_wakeup(port);
1513 static int atmel_prepare_tx_pdc(struct uart_port *port)
1515 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1516 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1517 struct circ_buf *xmit = &port->state->xmit;
1519 pdc->buf = xmit->buf;
1520 pdc->dma_addr = dma_map_single(port->dev,
1524 pdc->dma_size = UART_XMIT_SIZE;
1530 static void atmel_rx_from_ring(struct uart_port *port)
1532 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1533 struct circ_buf *ring = &atmel_port->rx_ring;
1535 unsigned int status;
1537 while (ring->head != ring->tail) {
1538 struct atmel_uart_char c;
1540 /* Make sure c is loaded after head. */
1543 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1545 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1552 * note that the error handling code is
1553 * out of the main execution path
1555 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1556 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1557 if (status & ATMEL_US_RXBRK) {
1558 /* ignore side-effect */
1559 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1562 if (uart_handle_break(port))
1565 if (status & ATMEL_US_PARE)
1566 port->icount.parity++;
1567 if (status & ATMEL_US_FRAME)
1568 port->icount.frame++;
1569 if (status & ATMEL_US_OVRE)
1570 port->icount.overrun++;
1572 status &= port->read_status_mask;
1574 if (status & ATMEL_US_RXBRK)
1576 else if (status & ATMEL_US_PARE)
1578 else if (status & ATMEL_US_FRAME)
1583 if (uart_handle_sysrq_char(port, c.ch))
1586 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1590 * Drop the lock here since it might end up calling
1591 * uart_start(), which takes the lock.
1593 spin_unlock(&port->lock);
1594 tty_flip_buffer_push(&port->state->port);
1595 spin_lock(&port->lock);
1598 static void atmel_release_rx_pdc(struct uart_port *port)
1600 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1603 for (i = 0; i < 2; i++) {
1604 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1606 dma_unmap_single(port->dev,
1614 static void atmel_rx_from_pdc(struct uart_port *port)
1616 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1617 struct tty_port *tport = &port->state->port;
1618 struct atmel_dma_buffer *pdc;
1619 int rx_idx = atmel_port->pdc_rx_idx;
1625 /* Reset the UART timeout early so that we don't miss one */
1626 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1628 pdc = &atmel_port->pdc_rx[rx_idx];
1629 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1632 /* If the PDC has switched buffers, RPR won't contain
1633 * any address within the current buffer. Since head
1634 * is unsigned, we just need a one-way comparison to
1637 * In this case, we just need to consume the entire
1638 * buffer and resubmit it for DMA. This will clear the
1639 * ENDRX bit as well, so that we can safely re-enable
1640 * all interrupts below.
1642 head = min(head, pdc->dma_size);
1644 if (likely(head != tail)) {
1645 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1646 pdc->dma_size, DMA_FROM_DEVICE);
1649 * head will only wrap around when we recycle
1650 * the DMA buffer, and when that happens, we
1651 * explicitly set tail to 0. So head will
1652 * always be greater than tail.
1654 count = head - tail;
1656 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1659 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1660 pdc->dma_size, DMA_FROM_DEVICE);
1662 port->icount.rx += count;
1667 * If the current buffer is full, we need to check if
1668 * the next one contains any additional data.
1670 if (head >= pdc->dma_size) {
1672 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1673 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1676 atmel_port->pdc_rx_idx = rx_idx;
1678 } while (head >= pdc->dma_size);
1681 * Drop the lock here since it might end up calling
1682 * uart_start(), which takes the lock.
1684 spin_unlock(&port->lock);
1685 tty_flip_buffer_push(tport);
1686 spin_lock(&port->lock);
1688 atmel_uart_writel(port, ATMEL_US_IER,
1689 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1692 static int atmel_prepare_rx_pdc(struct uart_port *port)
1694 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1697 for (i = 0; i < 2; i++) {
1698 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1700 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1701 if (pdc->buf == NULL) {
1703 dma_unmap_single(port->dev,
1704 atmel_port->pdc_rx[0].dma_addr,
1707 kfree(atmel_port->pdc_rx[0].buf);
1709 atmel_port->use_pdc_rx = false;
1712 pdc->dma_addr = dma_map_single(port->dev,
1716 pdc->dma_size = PDC_BUFFER_SIZE;
1720 atmel_port->pdc_rx_idx = 0;
1722 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1723 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1725 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1726 atmel_port->pdc_rx[1].dma_addr);
1727 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1733 * tasklet handling tty stuff outside the interrupt handler.
1735 static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1737 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1739 struct uart_port *port = &atmel_port->uart;
1741 /* The interrupt handler does not take the lock */
1742 spin_lock(&port->lock);
1743 atmel_port->schedule_rx(port);
1744 spin_unlock(&port->lock);
1747 static void atmel_tasklet_tx_func(struct tasklet_struct *t)
1749 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1751 struct uart_port *port = &atmel_port->uart;
1753 /* The interrupt handler does not take the lock */
1754 spin_lock(&port->lock);
1755 atmel_port->schedule_tx(port);
1756 spin_unlock(&port->lock);
1759 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1760 struct platform_device *pdev)
1762 struct device_node *np = pdev->dev.of_node;
1764 /* DMA/PDC usage specification */
1765 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1766 if (of_property_read_bool(np, "dmas")) {
1767 atmel_port->use_dma_rx = true;
1768 atmel_port->use_pdc_rx = false;
1770 atmel_port->use_dma_rx = false;
1771 atmel_port->use_pdc_rx = true;
1774 atmel_port->use_dma_rx = false;
1775 atmel_port->use_pdc_rx = false;
1778 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1779 if (of_property_read_bool(np, "dmas")) {
1780 atmel_port->use_dma_tx = true;
1781 atmel_port->use_pdc_tx = false;
1783 atmel_port->use_dma_tx = false;
1784 atmel_port->use_pdc_tx = true;
1787 atmel_port->use_dma_tx = false;
1788 atmel_port->use_pdc_tx = false;
1792 static void atmel_set_ops(struct uart_port *port)
1794 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1796 if (atmel_use_dma_rx(port)) {
1797 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1798 atmel_port->schedule_rx = &atmel_rx_from_dma;
1799 atmel_port->release_rx = &atmel_release_rx_dma;
1800 } else if (atmel_use_pdc_rx(port)) {
1801 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1802 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1803 atmel_port->release_rx = &atmel_release_rx_pdc;
1805 atmel_port->prepare_rx = NULL;
1806 atmel_port->schedule_rx = &atmel_rx_from_ring;
1807 atmel_port->release_rx = NULL;
1810 if (atmel_use_dma_tx(port)) {
1811 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1812 atmel_port->schedule_tx = &atmel_tx_dma;
1813 atmel_port->release_tx = &atmel_release_tx_dma;
1814 } else if (atmel_use_pdc_tx(port)) {
1815 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1816 atmel_port->schedule_tx = &atmel_tx_pdc;
1817 atmel_port->release_tx = &atmel_release_tx_pdc;
1819 atmel_port->prepare_tx = NULL;
1820 atmel_port->schedule_tx = &atmel_tx_chars;
1821 atmel_port->release_tx = NULL;
1826 * Get ip name usart or uart
1828 static void atmel_get_ip_name(struct uart_port *port)
1830 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1831 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1833 u32 usart, dbgu_uart, new_uart;
1834 /* ASCII decoding for IP version */
1835 usart = 0x55534152; /* USAR(T) */
1836 dbgu_uart = 0x44424755; /* DBGU */
1837 new_uart = 0x55415254; /* UART */
1840 * Only USART devices from at91sam9260 SOC implement fractional
1841 * baudrate. It is available for all asynchronous modes, with the
1842 * following restriction: the sampling clock's duty cycle is not
1845 atmel_port->has_frac_baudrate = false;
1846 atmel_port->has_hw_timer = false;
1848 if (name == new_uart) {
1849 dev_dbg(port->dev, "Uart with hw timer");
1850 atmel_port->has_hw_timer = true;
1851 atmel_port->rtor = ATMEL_UA_RTOR;
1852 } else if (name == usart) {
1853 dev_dbg(port->dev, "Usart\n");
1854 atmel_port->has_frac_baudrate = true;
1855 atmel_port->has_hw_timer = true;
1856 atmel_port->rtor = ATMEL_US_RTOR;
1857 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1859 case 0x814: /* sama5d2 */
1861 case 0x701: /* sama5d4 */
1862 atmel_port->fidi_min = 3;
1863 atmel_port->fidi_max = 65535;
1865 case 0x502: /* sam9x5, sama5d3 */
1866 atmel_port->fidi_min = 3;
1867 atmel_port->fidi_max = 2047;
1870 atmel_port->fidi_min = 1;
1871 atmel_port->fidi_max = 2047;
1873 } else if (name == dbgu_uart) {
1874 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1876 /* fallback for older SoCs: use version field */
1877 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1882 dev_dbg(port->dev, "This version is usart\n");
1883 atmel_port->has_frac_baudrate = true;
1884 atmel_port->has_hw_timer = true;
1885 atmel_port->rtor = ATMEL_US_RTOR;
1889 dev_dbg(port->dev, "This version is uart\n");
1892 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1898 * Perform initialization and enable port for reception
1900 static int atmel_startup(struct uart_port *port)
1902 struct platform_device *pdev = to_platform_device(port->dev);
1903 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1907 * Ensure that no interrupts are enabled otherwise when
1908 * request_irq() is called we could get stuck trying to
1909 * handle an unexpected interrupt
1911 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1912 atmel_port->ms_irq_enabled = false;
1917 retval = request_irq(port->irq, atmel_interrupt,
1918 IRQF_SHARED | IRQF_COND_SUSPEND,
1919 dev_name(&pdev->dev), port);
1921 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1925 atomic_set(&atmel_port->tasklet_shutdown, 0);
1926 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1927 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1930 * Initialize DMA (if necessary)
1932 atmel_init_property(atmel_port, pdev);
1933 atmel_set_ops(port);
1935 if (atmel_port->prepare_rx) {
1936 retval = atmel_port->prepare_rx(port);
1938 atmel_set_ops(port);
1941 if (atmel_port->prepare_tx) {
1942 retval = atmel_port->prepare_tx(port);
1944 atmel_set_ops(port);
1948 * Enable FIFO when available
1950 if (atmel_port->fifo_size) {
1951 unsigned int txrdym = ATMEL_US_ONE_DATA;
1952 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1955 atmel_uart_writel(port, ATMEL_US_CR,
1960 if (atmel_use_dma_tx(port))
1961 txrdym = ATMEL_US_FOUR_DATA;
1963 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1964 if (atmel_port->rts_high &&
1965 atmel_port->rts_low)
1966 fmr |= ATMEL_US_FRTSC |
1967 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1968 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1970 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1973 /* Save current CSR for comparison in atmel_tasklet_func() */
1974 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1977 * Finally, enable the serial port
1979 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1980 /* enable xmit & rcvr */
1981 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1982 atmel_port->tx_stopped = false;
1984 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1986 if (atmel_use_pdc_rx(port)) {
1987 /* set UART timeout */
1988 if (!atmel_port->has_hw_timer) {
1989 mod_timer(&atmel_port->uart_timer,
1990 jiffies + uart_poll_timeout(port));
1991 /* set USART timeout */
1993 atmel_uart_writel(port, atmel_port->rtor,
1995 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1997 atmel_uart_writel(port, ATMEL_US_IER,
1998 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2000 /* enable PDC controller */
2001 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
2002 } else if (atmel_use_dma_rx(port)) {
2003 /* set UART timeout */
2004 if (!atmel_port->has_hw_timer) {
2005 mod_timer(&atmel_port->uart_timer,
2006 jiffies + uart_poll_timeout(port));
2007 /* set USART timeout */
2009 atmel_uart_writel(port, atmel_port->rtor,
2011 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
2013 atmel_uart_writel(port, ATMEL_US_IER,
2017 /* enable receive only */
2018 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2025 * Flush any TX data submitted for DMA. Called when the TX circular
2028 static void atmel_flush_buffer(struct uart_port *port)
2030 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2032 if (atmel_use_pdc_tx(port)) {
2033 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2034 atmel_port->pdc_tx.ofs = 0;
2037 * in uart_flush_buffer(), the xmit circular buffer has just
2038 * been cleared, so we have to reset tx_len accordingly.
2040 atmel_port->tx_len = 0;
2046 static void atmel_shutdown(struct uart_port *port)
2048 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2050 /* Disable modem control lines interrupts */
2051 atmel_disable_ms(port);
2053 /* Disable interrupts at device level */
2054 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2056 /* Prevent spurious interrupts from scheduling the tasklet */
2057 atomic_inc(&atmel_port->tasklet_shutdown);
2060 * Prevent any tasklets being scheduled during
2063 del_timer_sync(&atmel_port->uart_timer);
2065 /* Make sure that no interrupt is on the fly */
2066 synchronize_irq(port->irq);
2069 * Clear out any scheduled tasklets before
2070 * we destroy the buffers
2072 tasklet_kill(&atmel_port->tasklet_rx);
2073 tasklet_kill(&atmel_port->tasklet_tx);
2076 * Ensure everything is stopped and
2077 * disable port and break condition.
2079 atmel_stop_rx(port);
2080 atmel_stop_tx(port);
2082 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2085 * Shut-down the DMA.
2087 if (atmel_port->release_rx)
2088 atmel_port->release_rx(port);
2089 if (atmel_port->release_tx)
2090 atmel_port->release_tx(port);
2093 * Reset ring buffer pointers
2095 atmel_port->rx_ring.head = 0;
2096 atmel_port->rx_ring.tail = 0;
2099 * Free the interrupts
2101 free_irq(port->irq, port);
2103 atmel_flush_buffer(port);
2107 * Power / Clock management.
2109 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2110 unsigned int oldstate)
2112 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2117 * Enable the peripheral clock for this serial port.
2118 * This is called on uart_open() or a resume event.
2120 clk_prepare_enable(atmel_port->clk);
2122 /* re-enable interrupts if we disabled some on suspend */
2123 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2126 /* Back up the interrupt mask and disable all interrupts */
2127 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2128 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2131 * Disable the peripheral clock for this serial port.
2132 * This is called on uart_close() or a suspend event.
2134 clk_disable_unprepare(atmel_port->clk);
2137 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2142 * Change the port parameters
2144 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2145 struct ktermios *old)
2147 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2148 unsigned long flags;
2149 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2151 /* save the current mode register */
2152 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2154 /* reset the mode, clock divisor, parity, stop bits and data size */
2155 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2156 ATMEL_US_PAR | ATMEL_US_USMODE);
2158 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2161 switch (termios->c_cflag & CSIZE) {
2163 mode |= ATMEL_US_CHRL_5;
2166 mode |= ATMEL_US_CHRL_6;
2169 mode |= ATMEL_US_CHRL_7;
2172 mode |= ATMEL_US_CHRL_8;
2177 if (termios->c_cflag & CSTOPB)
2178 mode |= ATMEL_US_NBSTOP_2;
2181 if (termios->c_cflag & PARENB) {
2182 /* Mark or Space parity */
2183 if (termios->c_cflag & CMSPAR) {
2184 if (termios->c_cflag & PARODD)
2185 mode |= ATMEL_US_PAR_MARK;
2187 mode |= ATMEL_US_PAR_SPACE;
2188 } else if (termios->c_cflag & PARODD)
2189 mode |= ATMEL_US_PAR_ODD;
2191 mode |= ATMEL_US_PAR_EVEN;
2193 mode |= ATMEL_US_PAR_NONE;
2195 spin_lock_irqsave(&port->lock, flags);
2197 port->read_status_mask = ATMEL_US_OVRE;
2198 if (termios->c_iflag & INPCK)
2199 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2200 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2201 port->read_status_mask |= ATMEL_US_RXBRK;
2203 if (atmel_use_pdc_rx(port))
2204 /* need to enable error interrupts */
2205 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2208 * Characters to ignore
2210 port->ignore_status_mask = 0;
2211 if (termios->c_iflag & IGNPAR)
2212 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2213 if (termios->c_iflag & IGNBRK) {
2214 port->ignore_status_mask |= ATMEL_US_RXBRK;
2216 * If we're ignoring parity and break indicators,
2217 * ignore overruns too (for real raw support).
2219 if (termios->c_iflag & IGNPAR)
2220 port->ignore_status_mask |= ATMEL_US_OVRE;
2222 /* TODO: Ignore all characters if CREAD is set.*/
2224 /* update the per-port timeout */
2225 uart_update_timeout(port, termios->c_cflag, baud);
2228 * save/disable interrupts. The tty layer will ensure that the
2229 * transmitter is empty if requested by the caller, so there's
2230 * no need to wait for it here.
2232 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2233 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2235 /* disable receiver and transmitter */
2236 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2237 atmel_port->tx_stopped = true;
2240 if (port->rs485.flags & SER_RS485_ENABLED) {
2241 atmel_uart_writel(port, ATMEL_US_TTGR,
2242 port->rs485.delay_rts_after_send);
2243 mode |= ATMEL_US_USMODE_RS485;
2244 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2245 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2246 /* select mck clock, and output */
2247 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2248 /* set max iterations */
2249 mode |= ATMEL_US_MAX_ITER(3);
2250 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2251 == SER_ISO7816_T(0))
2252 mode |= ATMEL_US_USMODE_ISO7816_T0;
2254 mode |= ATMEL_US_USMODE_ISO7816_T1;
2255 } else if (termios->c_cflag & CRTSCTS) {
2256 /* RS232 with hardware handshake (RTS/CTS) */
2257 if (atmel_use_fifo(port) &&
2258 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2260 * with ATMEL_US_USMODE_HWHS set, the controller will
2261 * be able to drive the RTS pin high/low when the RX
2262 * FIFO is above RXFTHRES/below RXFTHRES2.
2263 * It will also disable the transmitter when the CTS
2265 * This mode is not activated if CTS pin is a GPIO
2266 * because in this case, the transmitter is always
2267 * disabled (there must be an internal pull-up
2268 * responsible for this behaviour).
2269 * If the RTS pin is a GPIO, the controller won't be
2270 * able to drive it according to the FIFO thresholds,
2271 * but it will be handled by the driver.
2273 mode |= ATMEL_US_USMODE_HWHS;
2276 * For platforms without FIFO, the flow control is
2277 * handled by the driver.
2279 mode |= ATMEL_US_USMODE_NORMAL;
2282 /* RS232 without hadware handshake */
2283 mode |= ATMEL_US_USMODE_NORMAL;
2287 * Set the baud rate:
2288 * Fractional baudrate allows to setup output frequency more
2289 * accurately. This feature is enabled only when using normal mode.
2290 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2291 * Currently, OVER is always set to 0 so we get
2292 * baudrate = selected clock / (16 * (CD + FP / 8))
2294 * 8 CD + FP = selected clock / (2 * baudrate)
2296 if (atmel_port->has_frac_baudrate) {
2297 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2299 fp = div & ATMEL_US_FP_MASK;
2301 cd = uart_get_divisor(port, baud);
2304 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2306 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2308 quot = cd | fp << ATMEL_US_FP_OFFSET;
2310 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2311 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2313 /* set the mode, clock divisor, parity, stop bits and data size */
2314 atmel_uart_writel(port, ATMEL_US_MR, mode);
2317 * when switching the mode, set the RTS line state according to the
2318 * new mode, otherwise keep the former state
2320 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2321 unsigned int rts_state;
2323 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2324 /* let the hardware control the RTS line */
2325 rts_state = ATMEL_US_RTSDIS;
2327 /* force RTS line to low level */
2328 rts_state = ATMEL_US_RTSEN;
2331 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2334 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2335 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2336 atmel_port->tx_stopped = false;
2338 /* restore interrupts */
2339 atmel_uart_writel(port, ATMEL_US_IER, imr);
2341 /* CTS flow-control and modem-status interrupts */
2342 if (UART_ENABLE_MS(port, termios->c_cflag))
2343 atmel_enable_ms(port);
2345 atmel_disable_ms(port);
2347 spin_unlock_irqrestore(&port->lock, flags);
2350 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2352 if (termios->c_line == N_PPS) {
2353 port->flags |= UPF_HARDPPS_CD;
2354 spin_lock_irq(&port->lock);
2355 atmel_enable_ms(port);
2356 spin_unlock_irq(&port->lock);
2358 port->flags &= ~UPF_HARDPPS_CD;
2359 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2360 spin_lock_irq(&port->lock);
2361 atmel_disable_ms(port);
2362 spin_unlock_irq(&port->lock);
2368 * Return string describing the specified port
2370 static const char *atmel_type(struct uart_port *port)
2372 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2376 * Release the memory region(s) being used by 'port'.
2378 static void atmel_release_port(struct uart_port *port)
2380 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2381 int size = resource_size(mpdev->resource);
2383 release_mem_region(port->mapbase, size);
2385 if (port->flags & UPF_IOREMAP) {
2386 iounmap(port->membase);
2387 port->membase = NULL;
2392 * Request the memory region(s) being used by 'port'.
2394 static int atmel_request_port(struct uart_port *port)
2396 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2397 int size = resource_size(mpdev->resource);
2399 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2402 if (port->flags & UPF_IOREMAP) {
2403 port->membase = ioremap(port->mapbase, size);
2404 if (port->membase == NULL) {
2405 release_mem_region(port->mapbase, size);
2414 * Configure/autoconfigure the port.
2416 static void atmel_config_port(struct uart_port *port, int flags)
2418 if (flags & UART_CONFIG_TYPE) {
2419 port->type = PORT_ATMEL;
2420 atmel_request_port(port);
2425 * Verify the new serial_struct (for TIOCSSERIAL).
2427 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2430 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2432 if (port->irq != ser->irq)
2434 if (ser->io_type != SERIAL_IO_MEM)
2436 if (port->uartclk / 16 != ser->baud_base)
2438 if (port->mapbase != (unsigned long)ser->iomem_base)
2440 if (port->iobase != ser->port)
2447 #ifdef CONFIG_CONSOLE_POLL
2448 static int atmel_poll_get_char(struct uart_port *port)
2450 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2453 return atmel_uart_read_char(port);
2456 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2458 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2461 atmel_uart_write_char(port, ch);
2465 static const struct uart_ops atmel_pops = {
2466 .tx_empty = atmel_tx_empty,
2467 .set_mctrl = atmel_set_mctrl,
2468 .get_mctrl = atmel_get_mctrl,
2469 .stop_tx = atmel_stop_tx,
2470 .start_tx = atmel_start_tx,
2471 .stop_rx = atmel_stop_rx,
2472 .enable_ms = atmel_enable_ms,
2473 .break_ctl = atmel_break_ctl,
2474 .startup = atmel_startup,
2475 .shutdown = atmel_shutdown,
2476 .flush_buffer = atmel_flush_buffer,
2477 .set_termios = atmel_set_termios,
2478 .set_ldisc = atmel_set_ldisc,
2480 .release_port = atmel_release_port,
2481 .request_port = atmel_request_port,
2482 .config_port = atmel_config_port,
2483 .verify_port = atmel_verify_port,
2484 .pm = atmel_serial_pm,
2485 #ifdef CONFIG_CONSOLE_POLL
2486 .poll_get_char = atmel_poll_get_char,
2487 .poll_put_char = atmel_poll_put_char,
2492 * Configure the port from the platform device resource info.
2494 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2495 struct platform_device *pdev)
2498 struct uart_port *port = &atmel_port->uart;
2499 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2501 atmel_init_property(atmel_port, pdev);
2502 atmel_set_ops(port);
2504 port->iotype = UPIO_MEM;
2505 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2506 port->ops = &atmel_pops;
2508 port->dev = &pdev->dev;
2509 port->mapbase = mpdev->resource[0].start;
2510 port->irq = mpdev->resource[1].start;
2511 port->rs485_config = atmel_config_rs485;
2512 port->iso7816_config = atmel_config_iso7816;
2513 port->membase = NULL;
2515 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2517 ret = uart_get_rs485_mode(port);
2521 /* for console, the clock could already be configured */
2522 if (!atmel_port->clk) {
2523 atmel_port->clk = clk_get(&mpdev->dev, "usart");
2524 if (IS_ERR(atmel_port->clk)) {
2525 ret = PTR_ERR(atmel_port->clk);
2526 atmel_port->clk = NULL;
2529 ret = clk_prepare_enable(atmel_port->clk);
2531 clk_put(atmel_port->clk);
2532 atmel_port->clk = NULL;
2535 port->uartclk = clk_get_rate(atmel_port->clk);
2536 clk_disable_unprepare(atmel_port->clk);
2537 /* only enable clock when USART is in use */
2541 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2544 if (atmel_uart_is_half_duplex(port))
2545 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2546 else if (atmel_use_pdc_tx(port)) {
2547 port->fifosize = PDC_BUFFER_SIZE;
2548 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2550 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2556 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2557 static void atmel_console_putchar(struct uart_port *port, int ch)
2559 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2561 atmel_uart_write_char(port, ch);
2565 * Interrupts are disabled on entering
2567 static void atmel_console_write(struct console *co, const char *s, u_int count)
2569 struct uart_port *port = &atmel_ports[co->index].uart;
2570 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2571 unsigned int status, imr;
2572 unsigned int pdc_tx;
2575 * First, save IMR and then disable interrupts
2577 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2578 atmel_uart_writel(port, ATMEL_US_IDR,
2579 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2581 /* Store PDC transmit status and disable it */
2582 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2583 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2585 /* Make sure that tx path is actually able to send characters */
2586 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2587 atmel_port->tx_stopped = false;
2589 uart_console_write(port, s, count, atmel_console_putchar);
2592 * Finally, wait for transmitter to become empty
2596 status = atmel_uart_readl(port, ATMEL_US_CSR);
2597 } while (!(status & ATMEL_US_TXRDY));
2599 /* Restore PDC transmit status */
2601 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2603 /* set interrupts back the way they were */
2604 atmel_uart_writel(port, ATMEL_US_IER, imr);
2608 * If the port was already initialised (eg, by a boot loader),
2609 * try to determine the current setup.
2611 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2612 int *parity, int *bits)
2614 unsigned int mr, quot;
2617 * If the baud rate generator isn't running, the port wasn't
2618 * initialized by the boot loader.
2620 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2624 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2625 if (mr == ATMEL_US_CHRL_8)
2630 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2631 if (mr == ATMEL_US_PAR_EVEN)
2633 else if (mr == ATMEL_US_PAR_ODD)
2637 * The serial core only rounds down when matching this to a
2638 * supported baud rate. Make sure we don't end up slightly
2639 * lower than one of those, as it would make us fall through
2640 * to a much lower baud rate than we really want.
2642 *baud = port->uartclk / (16 * (quot - 1));
2645 static int __init atmel_console_setup(struct console *co, char *options)
2648 struct uart_port *port = &atmel_ports[co->index].uart;
2649 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2655 if (port->membase == NULL) {
2656 /* Port not initialized yet - delay setup */
2660 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2664 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2665 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2666 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2667 atmel_port->tx_stopped = false;
2670 uart_parse_options(options, &baud, &parity, &bits, &flow);
2672 atmel_console_get_options(port, &baud, &parity, &bits);
2674 return uart_set_options(port, co, baud, parity, bits, flow);
2677 static struct uart_driver atmel_uart;
2679 static struct console atmel_console = {
2680 .name = ATMEL_DEVICENAME,
2681 .write = atmel_console_write,
2682 .device = uart_console_device,
2683 .setup = atmel_console_setup,
2684 .flags = CON_PRINTBUFFER,
2686 .data = &atmel_uart,
2689 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2692 #define ATMEL_CONSOLE_DEVICE NULL
2695 static struct uart_driver atmel_uart = {
2696 .owner = THIS_MODULE,
2697 .driver_name = "atmel_serial",
2698 .dev_name = ATMEL_DEVICENAME,
2699 .major = SERIAL_ATMEL_MAJOR,
2700 .minor = MINOR_START,
2701 .nr = ATMEL_MAX_UART,
2702 .cons = ATMEL_CONSOLE_DEVICE,
2706 static bool atmel_serial_clk_will_stop(void)
2708 #ifdef CONFIG_ARCH_AT91
2709 return at91_suspend_entering_slow_clock();
2715 static int atmel_serial_suspend(struct platform_device *pdev,
2718 struct uart_port *port = platform_get_drvdata(pdev);
2719 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2721 if (uart_console(port) && console_suspend_enabled) {
2722 /* Drain the TX shifter */
2723 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2728 if (uart_console(port) && !console_suspend_enabled) {
2729 /* Cache register values as we won't get a full shutdown/startup
2732 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2733 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2734 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2735 atmel_port->cache.rtor = atmel_uart_readl(port,
2737 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2738 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2739 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2742 /* we can not wake up if we're running on slow clock */
2743 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2744 if (atmel_serial_clk_will_stop()) {
2745 unsigned long flags;
2747 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2748 atmel_port->suspended = true;
2749 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2750 device_set_wakeup_enable(&pdev->dev, 0);
2753 uart_suspend_port(&atmel_uart, port);
2758 static int atmel_serial_resume(struct platform_device *pdev)
2760 struct uart_port *port = platform_get_drvdata(pdev);
2761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2762 unsigned long flags;
2764 if (uart_console(port) && !console_suspend_enabled) {
2765 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2766 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2767 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2768 atmel_uart_writel(port, atmel_port->rtor,
2769 atmel_port->cache.rtor);
2770 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2772 if (atmel_port->fifo_size) {
2773 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2774 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2775 atmel_uart_writel(port, ATMEL_US_FMR,
2776 atmel_port->cache.fmr);
2777 atmel_uart_writel(port, ATMEL_US_FIER,
2778 atmel_port->cache.fimr);
2780 atmel_start_rx(port);
2783 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2784 if (atmel_port->pending) {
2785 atmel_handle_receive(port, atmel_port->pending);
2786 atmel_handle_status(port, atmel_port->pending,
2787 atmel_port->pending_status);
2788 atmel_handle_transmit(port, atmel_port->pending);
2789 atmel_port->pending = 0;
2791 atmel_port->suspended = false;
2792 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2794 uart_resume_port(&atmel_uart, port);
2795 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2800 #define atmel_serial_suspend NULL
2801 #define atmel_serial_resume NULL
2804 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2805 struct platform_device *pdev)
2807 atmel_port->fifo_size = 0;
2808 atmel_port->rts_low = 0;
2809 atmel_port->rts_high = 0;
2811 if (of_property_read_u32(pdev->dev.of_node,
2813 &atmel_port->fifo_size))
2816 if (!atmel_port->fifo_size)
2819 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2820 atmel_port->fifo_size = 0;
2821 dev_err(&pdev->dev, "Invalid FIFO size\n");
2826 * 0 <= rts_low <= rts_high <= fifo_size
2827 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2828 * to flush their internal TX FIFO, commonly up to 16 data, before
2829 * actually stopping to send new data. So we try to set the RTS High
2830 * Threshold to a reasonably high value respecting this 16 data
2831 * empirical rule when possible.
2833 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2834 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2835 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2836 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2838 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2839 atmel_port->fifo_size);
2840 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2841 atmel_port->rts_high);
2842 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2843 atmel_port->rts_low);
2846 static int atmel_serial_probe(struct platform_device *pdev)
2848 struct atmel_uart_port *atmel_port;
2849 struct device_node *np = pdev->dev.parent->of_node;
2854 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2857 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2858 * as compatible string. This driver is probed by at91-usart mfd driver
2859 * which is just a wrapper over the atmel_serial driver and
2860 * spi-at91-usart driver. All attributes needed by this driver are
2861 * found in of_node of parent.
2863 pdev->dev.of_node = np;
2865 ret = of_alias_get_id(np, "serial");
2867 /* port id not found in platform data nor device-tree aliases:
2868 * auto-enumerate it */
2869 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2871 if (ret >= ATMEL_MAX_UART) {
2876 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2877 /* port already in use */
2882 atmel_port = &atmel_ports[ret];
2883 atmel_port->backup_imr = 0;
2884 atmel_port->uart.line = ret;
2885 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2886 atmel_serial_probe_fifos(atmel_port, pdev);
2888 atomic_set(&atmel_port->tasklet_shutdown, 0);
2889 spin_lock_init(&atmel_port->lock_suspended);
2891 ret = atmel_init_port(atmel_port, pdev);
2895 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2896 if (IS_ERR(atmel_port->gpios)) {
2897 ret = PTR_ERR(atmel_port->gpios);
2901 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2903 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2904 sizeof(struct atmel_uart_char),
2907 goto err_alloc_ring;
2908 atmel_port->rx_ring.buf = data;
2911 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2913 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2917 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2918 if (uart_console(&atmel_port->uart)
2919 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2921 * The serial core enabled the clock for us, so undo
2922 * the clk_prepare_enable() in atmel_console_setup()
2924 clk_disable_unprepare(atmel_port->clk);
2928 device_init_wakeup(&pdev->dev, 1);
2929 platform_set_drvdata(pdev, atmel_port);
2932 * The peripheral clock has been disabled by atmel_init_port():
2933 * enable it before accessing I/O registers
2935 clk_prepare_enable(atmel_port->clk);
2937 if (rs485_enabled) {
2938 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2939 ATMEL_US_USMODE_NORMAL);
2940 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2945 * Get port name of usart or uart
2947 atmel_get_ip_name(&atmel_port->uart);
2950 * The peripheral clock can now safely be disabled till the port
2953 clk_disable_unprepare(atmel_port->clk);
2958 kfree(atmel_port->rx_ring.buf);
2959 atmel_port->rx_ring.buf = NULL;
2961 if (!uart_console(&atmel_port->uart)) {
2962 clk_put(atmel_port->clk);
2963 atmel_port->clk = NULL;
2966 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2972 * Even if the driver is not modular, it makes sense to be able to
2973 * unbind a device: there can be many bound devices, and there are
2974 * situations where dynamic binding and unbinding can be useful.
2976 * For example, a connected device can require a specific firmware update
2977 * protocol that needs bitbanging on IO lines, but use the regular serial
2978 * port in the normal case.
2980 static int atmel_serial_remove(struct platform_device *pdev)
2982 struct uart_port *port = platform_get_drvdata(pdev);
2983 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2986 tasklet_kill(&atmel_port->tasklet_rx);
2987 tasklet_kill(&atmel_port->tasklet_tx);
2989 device_init_wakeup(&pdev->dev, 0);
2991 ret = uart_remove_one_port(&atmel_uart, port);
2993 kfree(atmel_port->rx_ring.buf);
2995 /* "port" is allocated statically, so we shouldn't free it */
2997 clear_bit(port->line, atmel_ports_in_use);
2999 clk_put(atmel_port->clk);
3000 atmel_port->clk = NULL;
3001 pdev->dev.of_node = NULL;
3006 static struct platform_driver atmel_serial_driver = {
3007 .probe = atmel_serial_probe,
3008 .remove = atmel_serial_remove,
3009 .suspend = atmel_serial_suspend,
3010 .resume = atmel_serial_resume,
3012 .name = "atmel_usart_serial",
3013 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
3017 static int __init atmel_serial_init(void)
3021 ret = uart_register_driver(&atmel_uart);
3025 ret = platform_driver_register(&atmel_serial_driver);
3027 uart_unregister_driver(&atmel_uart);
3031 device_initcall(atmel_serial_init);