1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 * DMA support added by Chip Coldwell.
11 #include <linux/circ_buf.h>
12 #include <linux/tty.h>
13 #include <linux/ioport.h>
14 #include <linux/slab.h>
15 #include <linux/init.h>
16 #include <linux/serial.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/console.h>
20 #include <linux/sysrq.h>
21 #include <linux/tty_flip.h>
22 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/atmel_pdc.h>
27 #include <linux/uaccess.h>
28 #include <linux/platform_data/atmel.h>
29 #include <linux/timer.h>
30 #include <linux/err.h>
31 #include <linux/irq.h>
32 #include <linux/suspend.h>
36 #include <asm/div64.h>
37 #include <asm/ioctls.h>
39 #define PDC_BUFFER_SIZE 512
40 /* Revisit: We should calculate this based on the actual port settings */
41 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
43 /* The minium number of data FIFOs should be able to contain */
44 #define ATMEL_MIN_FIFO_SIZE 8
46 * These two offsets are substracted from the RX FIFO size to define the RTS
47 * high and low thresholds
49 #define ATMEL_RTS_HIGH_OFFSET 16
50 #define ATMEL_RTS_LOW_OFFSET 20
52 #include <linux/serial_core.h>
54 #include "serial_mctrl_gpio.h"
55 #include "atmel_serial.h"
57 static void atmel_start_rx(struct uart_port *port);
58 static void atmel_stop_rx(struct uart_port *port);
60 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
62 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
63 * should coexist with the 8250 driver, such as if we have an external 16C550
65 #define SERIAL_ATMEL_MAJOR 204
66 #define MINOR_START 154
67 #define ATMEL_DEVICENAME "ttyAT"
71 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
72 * name, but it is legally reserved for the 8250 driver. */
73 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
74 #define MINOR_START 64
75 #define ATMEL_DEVICENAME "ttyS"
79 #define ATMEL_ISR_PASS_LIMIT 256
81 struct atmel_dma_buffer {
84 unsigned int dma_size;
88 struct atmel_uart_char {
94 * Be careful, the real size of the ring buffer is
95 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
96 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
99 #define ATMEL_SERIAL_RINGSIZE 1024
102 * at91: 6 USARTs and one DBGU port (SAM9260)
103 * samx7: 3 USARTs and 5 UARTs
105 #define ATMEL_MAX_UART 8
108 * We wrap our port structure around the generic uart_port.
110 struct atmel_uart_port {
111 struct uart_port uart; /* uart */
112 struct clk *clk; /* uart clock */
113 struct clk *gclk; /* uart generic clock */
114 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
115 u32 backup_imr; /* IMR saved during suspend */
116 int break_active; /* break being received */
118 bool use_dma_rx; /* enable DMA receiver */
119 bool use_pdc_rx; /* enable PDC receiver */
120 short pdc_rx_idx; /* current PDC RX buffer */
121 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
123 bool use_dma_tx; /* enable DMA transmitter */
124 bool use_pdc_tx; /* enable PDC transmitter */
125 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
127 spinlock_t lock_tx; /* port lock */
128 spinlock_t lock_rx; /* port lock */
129 struct dma_chan *chan_tx;
130 struct dma_chan *chan_rx;
131 struct dma_async_tx_descriptor *desc_tx;
132 struct dma_async_tx_descriptor *desc_rx;
133 dma_cookie_t cookie_tx;
134 dma_cookie_t cookie_rx;
135 struct scatterlist sg_tx;
136 struct scatterlist sg_rx;
137 struct tasklet_struct tasklet_rx;
138 struct tasklet_struct tasklet_tx;
139 atomic_t tasklet_shutdown;
140 unsigned int irq_status_prev;
143 struct circ_buf rx_ring;
145 struct mctrl_gpios *gpios;
146 u32 backup_mode; /* MR saved during iso7816 operations */
147 u32 backup_brgr; /* BRGR saved during iso7816 operations */
148 unsigned int tx_done_mask;
153 u32 rtor; /* address of receiver timeout register if it exists */
155 bool has_frac_baudrate;
157 struct timer_list uart_timer;
161 unsigned int pending;
162 unsigned int pending_status;
163 spinlock_t lock_suspended;
165 bool hd_start_rx; /* can start RX during half-duplex operation */
168 unsigned int fidi_min;
169 unsigned int fidi_max;
182 int (*prepare_rx)(struct uart_port *port);
183 int (*prepare_tx)(struct uart_port *port);
184 void (*schedule_rx)(struct uart_port *port);
185 void (*schedule_tx)(struct uart_port *port);
186 void (*release_rx)(struct uart_port *port);
187 void (*release_tx)(struct uart_port *port);
190 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
191 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
193 #if defined(CONFIG_OF)
194 static const struct of_device_id atmel_serial_dt_ids[] = {
195 { .compatible = "atmel,at91rm9200-usart-serial" },
200 static inline struct atmel_uart_port *
201 to_atmel_uart_port(struct uart_port *uart)
203 return container_of(uart, struct atmel_uart_port, uart);
206 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
208 return __raw_readl(port->membase + reg);
211 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
213 __raw_writel(value, port->membase + reg);
216 static inline u8 atmel_uart_read_char(struct uart_port *port)
218 return __raw_readb(port->membase + ATMEL_US_RHR);
221 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
223 __raw_writeb(value, port->membase + ATMEL_US_THR);
226 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
228 return ((port->rs485.flags & SER_RS485_ENABLED) &&
229 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
230 (port->iso7816.flags & SER_ISO7816_ENABLED);
233 static inline int atmel_error_rate(int desired_value, int actual_value)
235 return 100 - (desired_value * 100) / actual_value;
238 #ifdef CONFIG_SERIAL_ATMEL_PDC
239 static bool atmel_use_pdc_rx(struct uart_port *port)
241 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
243 return atmel_port->use_pdc_rx;
246 static bool atmel_use_pdc_tx(struct uart_port *port)
248 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
250 return atmel_port->use_pdc_tx;
253 static bool atmel_use_pdc_rx(struct uart_port *port)
258 static bool atmel_use_pdc_tx(struct uart_port *port)
264 static bool atmel_use_dma_tx(struct uart_port *port)
266 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
268 return atmel_port->use_dma_tx;
271 static bool atmel_use_dma_rx(struct uart_port *port)
273 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
275 return atmel_port->use_dma_rx;
278 static bool atmel_use_fifo(struct uart_port *port)
280 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
282 return atmel_port->fifo_size;
285 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
286 struct tasklet_struct *t)
288 if (!atomic_read(&atmel_port->tasklet_shutdown))
292 /* Enable or disable the rs485 support */
293 static int atmel_config_rs485(struct uart_port *port, struct ktermios *termios,
294 struct serial_rs485 *rs485conf)
296 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
299 /* Disable interrupts */
300 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
302 mode = atmel_uart_readl(port, ATMEL_US_MR);
304 if (rs485conf->flags & SER_RS485_ENABLED) {
305 dev_dbg(port->dev, "Setting UART to RS485\n");
306 if (rs485conf->flags & SER_RS485_RX_DURING_TX)
307 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
309 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
311 atmel_uart_writel(port, ATMEL_US_TTGR,
312 rs485conf->delay_rts_after_send);
313 mode &= ~ATMEL_US_USMODE;
314 mode |= ATMEL_US_USMODE_RS485;
316 dev_dbg(port->dev, "Setting UART to RS232\n");
317 if (atmel_use_pdc_tx(port))
318 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
321 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
323 atmel_uart_writel(port, ATMEL_US_MR, mode);
325 /* Enable interrupts */
326 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
331 static unsigned int atmel_calc_cd(struct uart_port *port,
332 struct serial_iso7816 *iso7816conf)
334 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
338 mck_rate = (u64)clk_get_rate(atmel_port->clk);
339 do_div(mck_rate, iso7816conf->clk);
344 static unsigned int atmel_calc_fidi(struct uart_port *port,
345 struct serial_iso7816 *iso7816conf)
349 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
350 fidi = (u64)iso7816conf->sc_fi;
351 do_div(fidi, iso7816conf->sc_di);
356 /* Enable or disable the iso7816 support */
357 /* Called with interrupts disabled */
358 static int atmel_config_iso7816(struct uart_port *port,
359 struct serial_iso7816 *iso7816conf)
361 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
363 unsigned int cd, fidi;
366 /* Disable interrupts */
367 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
369 mode = atmel_uart_readl(port, ATMEL_US_MR);
371 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
372 mode &= ~ATMEL_US_USMODE;
374 if (iso7816conf->tg > 255) {
375 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
376 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
381 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
382 == SER_ISO7816_T(0)) {
383 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
384 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
385 == SER_ISO7816_T(1)) {
386 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
388 dev_err(port->dev, "ISO7816: Type not supported\n");
389 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
394 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
396 /* select mck clock, and output */
397 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
398 /* set parity for normal/inverse mode + max iterations */
399 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
401 cd = atmel_calc_cd(port, iso7816conf);
402 fidi = atmel_calc_fidi(port, iso7816conf);
404 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
405 } else if (fidi < atmel_port->fidi_min
406 || fidi > atmel_port->fidi_max) {
407 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
408 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
413 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
414 /* port not yet in iso7816 mode: store configuration */
415 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
416 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
419 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
420 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
421 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
423 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
424 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
426 dev_dbg(port->dev, "Setting UART back to RS232\n");
427 /* back to last RS232 settings */
428 mode = atmel_port->backup_mode;
429 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
430 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
431 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
432 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
434 if (atmel_use_pdc_tx(port))
435 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
438 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
441 port->iso7816 = *iso7816conf;
443 atmel_uart_writel(port, ATMEL_US_MR, mode);
446 /* Enable interrupts */
447 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
453 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
455 static u_int atmel_tx_empty(struct uart_port *port)
457 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
459 if (atmel_port->tx_stopped)
461 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
467 * Set state of the modem control output lines
469 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
471 unsigned int control = 0;
472 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
473 unsigned int rts_paused, rts_ready;
474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
476 /* override mode to RS485 if needed, otherwise keep the current mode */
477 if (port->rs485.flags & SER_RS485_ENABLED) {
478 atmel_uart_writel(port, ATMEL_US_TTGR,
479 port->rs485.delay_rts_after_send);
480 mode &= ~ATMEL_US_USMODE;
481 mode |= ATMEL_US_USMODE_RS485;
484 /* set the RTS line state according to the mode */
485 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
486 /* force RTS line to high level */
487 rts_paused = ATMEL_US_RTSEN;
489 /* give the control of the RTS line back to the hardware */
490 rts_ready = ATMEL_US_RTSDIS;
492 /* force RTS line to high level */
493 rts_paused = ATMEL_US_RTSDIS;
495 /* force RTS line to low level */
496 rts_ready = ATMEL_US_RTSEN;
499 if (mctrl & TIOCM_RTS)
500 control |= rts_ready;
502 control |= rts_paused;
504 if (mctrl & TIOCM_DTR)
505 control |= ATMEL_US_DTREN;
507 control |= ATMEL_US_DTRDIS;
509 atmel_uart_writel(port, ATMEL_US_CR, control);
511 mctrl_gpio_set(atmel_port->gpios, mctrl);
513 /* Local loopback mode? */
514 mode &= ~ATMEL_US_CHMODE;
515 if (mctrl & TIOCM_LOOP)
516 mode |= ATMEL_US_CHMODE_LOC_LOOP;
518 mode |= ATMEL_US_CHMODE_NORMAL;
520 atmel_uart_writel(port, ATMEL_US_MR, mode);
524 * Get state of the modem control input lines
526 static u_int atmel_get_mctrl(struct uart_port *port)
528 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
529 unsigned int ret = 0, status;
531 status = atmel_uart_readl(port, ATMEL_US_CSR);
534 * The control signals are active low.
536 if (!(status & ATMEL_US_DCD))
538 if (!(status & ATMEL_US_CTS))
540 if (!(status & ATMEL_US_DSR))
542 if (!(status & ATMEL_US_RI))
545 return mctrl_gpio_get(atmel_port->gpios, &ret);
551 static void atmel_stop_tx(struct uart_port *port)
553 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
554 bool is_pdc = atmel_use_pdc_tx(port);
555 bool is_dma = is_pdc || atmel_use_dma_tx(port);
558 /* disable PDC transmit */
559 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
564 * Disable the transmitter.
565 * This is mandatory when DMA is used, otherwise the DMA buffer
566 * is fully transmitted.
568 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
569 atmel_port->tx_stopped = true;
572 /* Disable interrupts */
573 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
575 if (atmel_uart_is_half_duplex(port))
576 if (!atomic_read(&atmel_port->tasklet_shutdown))
577 atmel_start_rx(port);
581 * Start transmitting.
583 static void atmel_start_tx(struct uart_port *port)
585 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
586 bool is_pdc = atmel_use_pdc_tx(port);
587 bool is_dma = is_pdc || atmel_use_dma_tx(port);
589 if (is_pdc && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
591 /* The transmitter is already running. Yes, we
595 if (is_dma && atmel_uart_is_half_duplex(port))
599 /* re-enable PDC transmit */
600 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
603 /* Enable interrupts */
604 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
607 /* re-enable the transmitter */
608 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
609 atmel_port->tx_stopped = false;
614 * start receiving - port is in process of being opened.
616 static void atmel_start_rx(struct uart_port *port)
618 /* reset status and receiver */
619 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
621 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
623 if (atmel_use_pdc_rx(port)) {
624 /* enable PDC controller */
625 atmel_uart_writel(port, ATMEL_US_IER,
626 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
627 port->read_status_mask);
628 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
630 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
635 * Stop receiving - port is in process of being closed.
637 static void atmel_stop_rx(struct uart_port *port)
639 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
641 if (atmel_use_pdc_rx(port)) {
642 /* disable PDC receive */
643 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
644 atmel_uart_writel(port, ATMEL_US_IDR,
645 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
646 port->read_status_mask);
648 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
653 * Enable modem status interrupts
655 static void atmel_enable_ms(struct uart_port *port)
657 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
661 * Interrupt should not be enabled twice
663 if (atmel_port->ms_irq_enabled)
666 atmel_port->ms_irq_enabled = true;
668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
669 ier |= ATMEL_US_CTSIC;
671 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
672 ier |= ATMEL_US_DSRIC;
674 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
675 ier |= ATMEL_US_RIIC;
677 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
678 ier |= ATMEL_US_DCDIC;
680 atmel_uart_writel(port, ATMEL_US_IER, ier);
682 mctrl_gpio_enable_ms(atmel_port->gpios);
686 * Disable modem status interrupts
688 static void atmel_disable_ms(struct uart_port *port)
690 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
694 * Interrupt should not be disabled twice
696 if (!atmel_port->ms_irq_enabled)
699 atmel_port->ms_irq_enabled = false;
701 mctrl_gpio_disable_ms(atmel_port->gpios);
703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
704 idr |= ATMEL_US_CTSIC;
706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
707 idr |= ATMEL_US_DSRIC;
709 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
710 idr |= ATMEL_US_RIIC;
712 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
713 idr |= ATMEL_US_DCDIC;
715 atmel_uart_writel(port, ATMEL_US_IDR, idr);
719 * Control the transmission of a break signal
721 static void atmel_break_ctl(struct uart_port *port, int break_state)
723 if (break_state != 0)
725 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
728 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
732 * Stores the incoming character in the ring buffer
735 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
738 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
739 struct circ_buf *ring = &atmel_port->rx_ring;
740 struct atmel_uart_char *c;
742 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
743 /* Buffer overflow, ignore char */
746 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
750 /* Make sure the character is stored before we update head. */
753 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
757 * Deal with parity, framing and overrun errors.
759 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
762 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
764 if (status & ATMEL_US_RXBRK) {
765 /* ignore side-effect */
766 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
769 if (status & ATMEL_US_PARE)
770 port->icount.parity++;
771 if (status & ATMEL_US_FRAME)
772 port->icount.frame++;
773 if (status & ATMEL_US_OVRE)
774 port->icount.overrun++;
778 * Characters received (called from interrupt handler)
780 static void atmel_rx_chars(struct uart_port *port)
782 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
783 unsigned int status, ch;
785 status = atmel_uart_readl(port, ATMEL_US_CSR);
786 while (status & ATMEL_US_RXRDY) {
787 ch = atmel_uart_read_char(port);
790 * note that the error handling code is
791 * out of the main execution path
793 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
794 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
795 || atmel_port->break_active)) {
798 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
800 if (status & ATMEL_US_RXBRK
801 && !atmel_port->break_active) {
802 atmel_port->break_active = 1;
803 atmel_uart_writel(port, ATMEL_US_IER,
807 * This is either the end-of-break
808 * condition or we've received at
809 * least one character without RXBRK
810 * being set. In both cases, the next
811 * RXBRK will indicate start-of-break.
813 atmel_uart_writel(port, ATMEL_US_IDR,
815 status &= ~ATMEL_US_RXBRK;
816 atmel_port->break_active = 0;
820 atmel_buffer_rx_char(port, status, ch);
821 status = atmel_uart_readl(port, ATMEL_US_CSR);
824 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
828 * Transmit characters (called from tasklet with TXRDY interrupt
831 static void atmel_tx_chars(struct uart_port *port)
833 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
837 pending = uart_port_tx(port, ch,
838 atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY,
839 atmel_uart_write_char(port, ch));
841 /* we still have characters to transmit, so we should continue
842 * transmitting them when TX is ready, regardless of
845 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
847 /* Enable interrupts */
848 atmel_uart_writel(port, ATMEL_US_IER,
849 atmel_port->tx_done_mask);
851 if (atmel_uart_is_half_duplex(port))
852 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
856 static void atmel_complete_tx_dma(void *arg)
858 struct atmel_uart_port *atmel_port = arg;
859 struct uart_port *port = &atmel_port->uart;
860 struct circ_buf *xmit = &port->state->xmit;
861 struct dma_chan *chan = atmel_port->chan_tx;
864 uart_port_lock_irqsave(port, &flags);
867 dmaengine_terminate_all(chan);
868 uart_xmit_advance(port, atmel_port->tx_len);
870 spin_lock(&atmel_port->lock_tx);
871 async_tx_ack(atmel_port->desc_tx);
872 atmel_port->cookie_tx = -EINVAL;
873 atmel_port->desc_tx = NULL;
874 spin_unlock(&atmel_port->lock_tx);
876 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
877 uart_write_wakeup(port);
880 * xmit is a circular buffer so, if we have just send data from
881 * xmit->tail to the end of xmit->buf, now we have to transmit the
882 * remaining data from the beginning of xmit->buf to xmit->head.
884 if (!uart_circ_empty(xmit))
885 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
886 else if (atmel_uart_is_half_duplex(port)) {
888 * DMA done, re-enable TXEMPTY and signal that we can stop
889 * TX and start RX for RS485
891 atmel_port->hd_start_rx = true;
892 atmel_uart_writel(port, ATMEL_US_IER,
893 atmel_port->tx_done_mask);
896 uart_port_unlock_irqrestore(port, flags);
899 static void atmel_release_tx_dma(struct uart_port *port)
901 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
902 struct dma_chan *chan = atmel_port->chan_tx;
905 dmaengine_terminate_all(chan);
906 dma_release_channel(chan);
907 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
911 atmel_port->desc_tx = NULL;
912 atmel_port->chan_tx = NULL;
913 atmel_port->cookie_tx = -EINVAL;
917 * Called from tasklet with TXRDY interrupt is disabled.
919 static void atmel_tx_dma(struct uart_port *port)
921 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
922 struct circ_buf *xmit = &port->state->xmit;
923 struct dma_chan *chan = atmel_port->chan_tx;
924 struct dma_async_tx_descriptor *desc;
925 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
926 unsigned int tx_len, part1_len, part2_len, sg_len;
927 dma_addr_t phys_addr;
929 /* Make sure we have an idle channel */
930 if (atmel_port->desc_tx != NULL)
933 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
936 * Port xmit buffer is already mapped,
937 * and it is one page... Just adjust
938 * offsets and lengths. Since it is a circular buffer,
939 * we have to transmit till the end, and then the rest.
940 * Take the port lock to get a
941 * consistent xmit buffer state.
943 tx_len = CIRC_CNT_TO_END(xmit->head,
947 if (atmel_port->fifo_size) {
948 /* multi data mode */
949 part1_len = (tx_len & ~0x3); /* DWORD access */
950 part2_len = (tx_len & 0x3); /* BYTE access */
952 /* single data (legacy) mode */
954 part2_len = tx_len; /* BYTE access only */
957 sg_init_table(sgl, 2);
959 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
962 sg_dma_address(sg) = phys_addr;
963 sg_dma_len(sg) = part1_len;
965 phys_addr += part1_len;
970 sg_dma_address(sg) = phys_addr;
971 sg_dma_len(sg) = part2_len;
975 * save tx_len so atmel_complete_tx_dma() will increase
976 * xmit->tail correctly
978 atmel_port->tx_len = tx_len;
980 desc = dmaengine_prep_slave_sg(chan,
987 dev_err(port->dev, "Failed to send via dma!\n");
991 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
993 atmel_port->desc_tx = desc;
994 desc->callback = atmel_complete_tx_dma;
995 desc->callback_param = atmel_port;
996 atmel_port->cookie_tx = dmaengine_submit(desc);
997 if (dma_submit_error(atmel_port->cookie_tx)) {
998 dev_err(port->dev, "dma_submit_error %d\n",
999 atmel_port->cookie_tx);
1003 dma_async_issue_pending(chan);
1006 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1007 uart_write_wakeup(port);
1010 static int atmel_prepare_tx_dma(struct uart_port *port)
1012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1013 struct device *mfd_dev = port->dev->parent;
1014 dma_cap_mask_t mask;
1015 struct dma_slave_config config;
1016 struct dma_chan *chan;
1020 dma_cap_set(DMA_SLAVE, mask);
1022 chan = dma_request_chan(mfd_dev, "tx");
1024 atmel_port->chan_tx = NULL;
1027 atmel_port->chan_tx = chan;
1028 dev_info(port->dev, "using %s for tx DMA transfers\n",
1029 dma_chan_name(atmel_port->chan_tx));
1031 spin_lock_init(&atmel_port->lock_tx);
1032 sg_init_table(&atmel_port->sg_tx, 1);
1033 /* UART circular tx buffer is an aligned page. */
1034 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1035 sg_set_page(&atmel_port->sg_tx,
1036 virt_to_page(port->state->xmit.buf),
1038 offset_in_page(port->state->xmit.buf));
1039 nent = dma_map_sg(port->dev,
1045 dev_dbg(port->dev, "need to release resource of dma\n");
1048 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1049 sg_dma_len(&atmel_port->sg_tx),
1050 port->state->xmit.buf,
1051 &sg_dma_address(&atmel_port->sg_tx));
1054 /* Configure the slave DMA */
1055 memset(&config, 0, sizeof(config));
1056 config.direction = DMA_MEM_TO_DEV;
1057 config.dst_addr_width = (atmel_port->fifo_size) ?
1058 DMA_SLAVE_BUSWIDTH_4_BYTES :
1059 DMA_SLAVE_BUSWIDTH_1_BYTE;
1060 config.dst_addr = port->mapbase + ATMEL_US_THR;
1061 config.dst_maxburst = 1;
1063 ret = dmaengine_slave_config(atmel_port->chan_tx,
1066 dev_err(port->dev, "DMA tx slave configuration failed\n");
1073 dev_err(port->dev, "TX channel not available, switch to pio\n");
1074 atmel_port->use_dma_tx = false;
1075 if (atmel_port->chan_tx)
1076 atmel_release_tx_dma(port);
1080 static void atmel_complete_rx_dma(void *arg)
1082 struct uart_port *port = arg;
1083 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1085 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1088 static void atmel_release_rx_dma(struct uart_port *port)
1090 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1091 struct dma_chan *chan = atmel_port->chan_rx;
1094 dmaengine_terminate_all(chan);
1095 dma_release_channel(chan);
1096 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1100 atmel_port->desc_rx = NULL;
1101 atmel_port->chan_rx = NULL;
1102 atmel_port->cookie_rx = -EINVAL;
1105 static void atmel_rx_from_dma(struct uart_port *port)
1107 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1108 struct tty_port *tport = &port->state->port;
1109 struct circ_buf *ring = &atmel_port->rx_ring;
1110 struct dma_chan *chan = atmel_port->chan_rx;
1111 struct dma_tx_state state;
1112 enum dma_status dmastat;
1116 /* Reset the UART timeout early so that we don't miss one */
1117 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1118 dmastat = dmaengine_tx_status(chan,
1119 atmel_port->cookie_rx,
1121 /* Restart a new tasklet if DMA status is error */
1122 if (dmastat == DMA_ERROR) {
1123 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1124 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1125 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1129 /* CPU claims ownership of RX DMA buffer */
1130 dma_sync_sg_for_cpu(port->dev,
1136 * ring->head points to the end of data already written by the DMA.
1137 * ring->tail points to the beginning of data to be read by the
1139 * The current transfer size should not be larger than the dma buffer
1142 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1143 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1145 * At this point ring->head may point to the first byte right after the
1146 * last byte of the dma buffer:
1147 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1149 * However ring->tail must always points inside the dma buffer:
1150 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1152 * Since we use a ring buffer, we have to handle the case
1153 * where head is lower than tail. In such a case, we first read from
1154 * tail to the end of the buffer then reset tail.
1156 if (ring->head < ring->tail) {
1157 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1159 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1161 port->icount.rx += count;
1164 /* Finally we read data from tail to head */
1165 if (ring->tail < ring->head) {
1166 count = ring->head - ring->tail;
1168 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1169 /* Wrap ring->head if needed */
1170 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1172 ring->tail = ring->head;
1173 port->icount.rx += count;
1176 /* USART retreives ownership of RX DMA buffer */
1177 dma_sync_sg_for_device(port->dev,
1182 tty_flip_buffer_push(tport);
1184 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1187 static int atmel_prepare_rx_dma(struct uart_port *port)
1189 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1190 struct device *mfd_dev = port->dev->parent;
1191 struct dma_async_tx_descriptor *desc;
1192 dma_cap_mask_t mask;
1193 struct dma_slave_config config;
1194 struct circ_buf *ring;
1195 struct dma_chan *chan;
1198 ring = &atmel_port->rx_ring;
1201 dma_cap_set(DMA_CYCLIC, mask);
1203 chan = dma_request_chan(mfd_dev, "rx");
1205 atmel_port->chan_rx = NULL;
1208 atmel_port->chan_rx = chan;
1209 dev_info(port->dev, "using %s for rx DMA transfers\n",
1210 dma_chan_name(atmel_port->chan_rx));
1212 spin_lock_init(&atmel_port->lock_rx);
1213 sg_init_table(&atmel_port->sg_rx, 1);
1214 /* UART circular rx buffer is an aligned page. */
1215 BUG_ON(!PAGE_ALIGNED(ring->buf));
1216 sg_set_page(&atmel_port->sg_rx,
1217 virt_to_page(ring->buf),
1218 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1219 offset_in_page(ring->buf));
1220 nent = dma_map_sg(port->dev,
1226 dev_dbg(port->dev, "need to release resource of dma\n");
1229 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1230 sg_dma_len(&atmel_port->sg_rx),
1232 &sg_dma_address(&atmel_port->sg_rx));
1235 /* Configure the slave DMA */
1236 memset(&config, 0, sizeof(config));
1237 config.direction = DMA_DEV_TO_MEM;
1238 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1239 config.src_addr = port->mapbase + ATMEL_US_RHR;
1240 config.src_maxburst = 1;
1242 ret = dmaengine_slave_config(atmel_port->chan_rx,
1245 dev_err(port->dev, "DMA rx slave configuration failed\n");
1249 * Prepare a cyclic dma transfer, assign 2 descriptors,
1250 * each one is half ring buffer size
1252 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1253 sg_dma_address(&atmel_port->sg_rx),
1254 sg_dma_len(&atmel_port->sg_rx),
1255 sg_dma_len(&atmel_port->sg_rx)/2,
1257 DMA_PREP_INTERRUPT);
1259 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1262 desc->callback = atmel_complete_rx_dma;
1263 desc->callback_param = port;
1264 atmel_port->desc_rx = desc;
1265 atmel_port->cookie_rx = dmaengine_submit(desc);
1266 if (dma_submit_error(atmel_port->cookie_rx)) {
1267 dev_err(port->dev, "dma_submit_error %d\n",
1268 atmel_port->cookie_rx);
1272 dma_async_issue_pending(atmel_port->chan_rx);
1277 dev_err(port->dev, "RX channel not available, switch to pio\n");
1278 atmel_port->use_dma_rx = false;
1279 if (atmel_port->chan_rx)
1280 atmel_release_rx_dma(port);
1284 static void atmel_uart_timer_callback(struct timer_list *t)
1286 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1288 struct uart_port *port = &atmel_port->uart;
1290 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1291 tasklet_schedule(&atmel_port->tasklet_rx);
1292 mod_timer(&atmel_port->uart_timer,
1293 jiffies + uart_poll_timeout(port));
1298 * receive interrupt handler.
1301 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1303 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1305 if (atmel_use_pdc_rx(port)) {
1307 * PDC receive. Just schedule the tasklet and let it
1308 * figure out the details.
1310 * TODO: We're not handling error flags correctly at
1313 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1314 atmel_uart_writel(port, ATMEL_US_IDR,
1315 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1316 atmel_tasklet_schedule(atmel_port,
1317 &atmel_port->tasklet_rx);
1320 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1321 ATMEL_US_FRAME | ATMEL_US_PARE))
1322 atmel_pdc_rxerr(port, pending);
1325 if (atmel_use_dma_rx(port)) {
1326 if (pending & ATMEL_US_TIMEOUT) {
1327 atmel_uart_writel(port, ATMEL_US_IDR,
1329 atmel_tasklet_schedule(atmel_port,
1330 &atmel_port->tasklet_rx);
1334 /* Interrupt receive */
1335 if (pending & ATMEL_US_RXRDY)
1336 atmel_rx_chars(port);
1337 else if (pending & ATMEL_US_RXBRK) {
1339 * End of break detected. If it came along with a
1340 * character, atmel_rx_chars will handle it.
1342 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1343 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1344 atmel_port->break_active = 0;
1349 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1352 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1354 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1356 if (pending & atmel_port->tx_done_mask) {
1357 atmel_uart_writel(port, ATMEL_US_IDR,
1358 atmel_port->tx_done_mask);
1360 /* Start RX if flag was set and FIFO is empty */
1361 if (atmel_port->hd_start_rx) {
1362 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1363 & ATMEL_US_TXEMPTY))
1364 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1366 atmel_port->hd_start_rx = false;
1367 atmel_start_rx(port);
1370 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1375 * status flags interrupt handler.
1378 atmel_handle_status(struct uart_port *port, unsigned int pending,
1379 unsigned int status)
1381 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1382 unsigned int status_change;
1384 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1385 | ATMEL_US_CTSIC)) {
1386 status_change = status ^ atmel_port->irq_status_prev;
1387 atmel_port->irq_status_prev = status;
1389 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1390 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1391 /* TODO: All reads to CSR will clear these interrupts! */
1392 if (status_change & ATMEL_US_RI)
1394 if (status_change & ATMEL_US_DSR)
1396 if (status_change & ATMEL_US_DCD)
1397 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1398 if (status_change & ATMEL_US_CTS)
1399 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1401 wake_up_interruptible(&port->state->port.delta_msr_wait);
1405 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1406 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1412 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1414 struct uart_port *port = dev_id;
1415 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1416 unsigned int status, pending, mask, pass_counter = 0;
1418 spin_lock(&atmel_port->lock_suspended);
1421 status = atmel_uart_readl(port, ATMEL_US_CSR);
1422 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1423 pending = status & mask;
1427 if (atmel_port->suspended) {
1428 atmel_port->pending |= pending;
1429 atmel_port->pending_status = status;
1430 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1435 atmel_handle_receive(port, pending);
1436 atmel_handle_status(port, pending, status);
1437 atmel_handle_transmit(port, pending);
1438 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1440 spin_unlock(&atmel_port->lock_suspended);
1442 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1445 static void atmel_release_tx_pdc(struct uart_port *port)
1447 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1448 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1450 dma_unmap_single(port->dev,
1457 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1459 static void atmel_tx_pdc(struct uart_port *port)
1461 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1462 struct circ_buf *xmit = &port->state->xmit;
1463 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1466 /* nothing left to transmit? */
1467 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1469 uart_xmit_advance(port, pdc->ofs);
1472 /* more to transmit - setup next transfer */
1474 /* disable PDC transmit */
1475 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1477 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1478 dma_sync_single_for_device(port->dev,
1483 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1486 atmel_uart_writel(port, ATMEL_PDC_TPR,
1487 pdc->dma_addr + xmit->tail);
1488 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1489 /* re-enable PDC transmit */
1490 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1491 /* Enable interrupts */
1492 atmel_uart_writel(port, ATMEL_US_IER,
1493 atmel_port->tx_done_mask);
1495 if (atmel_uart_is_half_duplex(port)) {
1496 /* DMA done, stop TX, start RX for RS485 */
1497 atmel_start_rx(port);
1501 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1502 uart_write_wakeup(port);
1505 static int atmel_prepare_tx_pdc(struct uart_port *port)
1507 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1508 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1509 struct circ_buf *xmit = &port->state->xmit;
1511 pdc->buf = xmit->buf;
1512 pdc->dma_addr = dma_map_single(port->dev,
1516 pdc->dma_size = UART_XMIT_SIZE;
1522 static void atmel_rx_from_ring(struct uart_port *port)
1524 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1525 struct circ_buf *ring = &atmel_port->rx_ring;
1526 unsigned int status;
1529 while (ring->head != ring->tail) {
1530 struct atmel_uart_char c;
1532 /* Make sure c is loaded after head. */
1535 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1537 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1544 * note that the error handling code is
1545 * out of the main execution path
1547 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1548 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1549 if (status & ATMEL_US_RXBRK) {
1550 /* ignore side-effect */
1551 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1554 if (uart_handle_break(port))
1557 if (status & ATMEL_US_PARE)
1558 port->icount.parity++;
1559 if (status & ATMEL_US_FRAME)
1560 port->icount.frame++;
1561 if (status & ATMEL_US_OVRE)
1562 port->icount.overrun++;
1564 status &= port->read_status_mask;
1566 if (status & ATMEL_US_RXBRK)
1568 else if (status & ATMEL_US_PARE)
1570 else if (status & ATMEL_US_FRAME)
1575 if (uart_handle_sysrq_char(port, c.ch))
1578 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1581 tty_flip_buffer_push(&port->state->port);
1584 static void atmel_release_rx_pdc(struct uart_port *port)
1586 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1589 for (i = 0; i < 2; i++) {
1590 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1592 dma_unmap_single(port->dev,
1600 static void atmel_rx_from_pdc(struct uart_port *port)
1602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1603 struct tty_port *tport = &port->state->port;
1604 struct atmel_dma_buffer *pdc;
1605 int rx_idx = atmel_port->pdc_rx_idx;
1611 /* Reset the UART timeout early so that we don't miss one */
1612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1614 pdc = &atmel_port->pdc_rx[rx_idx];
1615 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1618 /* If the PDC has switched buffers, RPR won't contain
1619 * any address within the current buffer. Since head
1620 * is unsigned, we just need a one-way comparison to
1623 * In this case, we just need to consume the entire
1624 * buffer and resubmit it for DMA. This will clear the
1625 * ENDRX bit as well, so that we can safely re-enable
1626 * all interrupts below.
1628 head = min(head, pdc->dma_size);
1630 if (likely(head != tail)) {
1631 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1632 pdc->dma_size, DMA_FROM_DEVICE);
1635 * head will only wrap around when we recycle
1636 * the DMA buffer, and when that happens, we
1637 * explicitly set tail to 0. So head will
1638 * always be greater than tail.
1640 count = head - tail;
1642 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1645 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1646 pdc->dma_size, DMA_FROM_DEVICE);
1648 port->icount.rx += count;
1653 * If the current buffer is full, we need to check if
1654 * the next one contains any additional data.
1656 if (head >= pdc->dma_size) {
1658 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1659 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1662 atmel_port->pdc_rx_idx = rx_idx;
1664 } while (head >= pdc->dma_size);
1666 tty_flip_buffer_push(tport);
1668 atmel_uart_writel(port, ATMEL_US_IER,
1669 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1672 static int atmel_prepare_rx_pdc(struct uart_port *port)
1674 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1677 for (i = 0; i < 2; i++) {
1678 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1680 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1681 if (pdc->buf == NULL) {
1683 dma_unmap_single(port->dev,
1684 atmel_port->pdc_rx[0].dma_addr,
1687 kfree(atmel_port->pdc_rx[0].buf);
1689 atmel_port->use_pdc_rx = false;
1692 pdc->dma_addr = dma_map_single(port->dev,
1696 pdc->dma_size = PDC_BUFFER_SIZE;
1700 atmel_port->pdc_rx_idx = 0;
1702 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1703 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1705 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1706 atmel_port->pdc_rx[1].dma_addr);
1707 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1713 * tasklet handling tty stuff outside the interrupt handler.
1715 static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1717 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1719 struct uart_port *port = &atmel_port->uart;
1721 /* The interrupt handler does not take the lock */
1722 uart_port_lock(port);
1723 atmel_port->schedule_rx(port);
1724 uart_port_unlock(port);
1727 static void atmel_tasklet_tx_func(struct tasklet_struct *t)
1729 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1731 struct uart_port *port = &atmel_port->uart;
1733 /* The interrupt handler does not take the lock */
1734 uart_port_lock(port);
1735 atmel_port->schedule_tx(port);
1736 uart_port_unlock(port);
1739 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1740 struct platform_device *pdev)
1742 struct device_node *np = pdev->dev.of_node;
1744 /* DMA/PDC usage specification */
1745 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1746 if (of_property_read_bool(np, "dmas")) {
1747 atmel_port->use_dma_rx = true;
1748 atmel_port->use_pdc_rx = false;
1750 atmel_port->use_dma_rx = false;
1751 atmel_port->use_pdc_rx = true;
1754 atmel_port->use_dma_rx = false;
1755 atmel_port->use_pdc_rx = false;
1758 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1759 if (of_property_read_bool(np, "dmas")) {
1760 atmel_port->use_dma_tx = true;
1761 atmel_port->use_pdc_tx = false;
1763 atmel_port->use_dma_tx = false;
1764 atmel_port->use_pdc_tx = true;
1767 atmel_port->use_dma_tx = false;
1768 atmel_port->use_pdc_tx = false;
1772 static void atmel_set_ops(struct uart_port *port)
1774 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1776 if (atmel_use_dma_rx(port)) {
1777 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1778 atmel_port->schedule_rx = &atmel_rx_from_dma;
1779 atmel_port->release_rx = &atmel_release_rx_dma;
1780 } else if (atmel_use_pdc_rx(port)) {
1781 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1782 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1783 atmel_port->release_rx = &atmel_release_rx_pdc;
1785 atmel_port->prepare_rx = NULL;
1786 atmel_port->schedule_rx = &atmel_rx_from_ring;
1787 atmel_port->release_rx = NULL;
1790 if (atmel_use_dma_tx(port)) {
1791 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1792 atmel_port->schedule_tx = &atmel_tx_dma;
1793 atmel_port->release_tx = &atmel_release_tx_dma;
1794 } else if (atmel_use_pdc_tx(port)) {
1795 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1796 atmel_port->schedule_tx = &atmel_tx_pdc;
1797 atmel_port->release_tx = &atmel_release_tx_pdc;
1799 atmel_port->prepare_tx = NULL;
1800 atmel_port->schedule_tx = &atmel_tx_chars;
1801 atmel_port->release_tx = NULL;
1806 * Get ip name usart or uart
1808 static void atmel_get_ip_name(struct uart_port *port)
1810 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1811 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1813 u32 usart, dbgu_uart, new_uart;
1814 /* ASCII decoding for IP version */
1815 usart = 0x55534152; /* USAR(T) */
1816 dbgu_uart = 0x44424755; /* DBGU */
1817 new_uart = 0x55415254; /* UART */
1820 * Only USART devices from at91sam9260 SOC implement fractional
1821 * baudrate. It is available for all asynchronous modes, with the
1822 * following restriction: the sampling clock's duty cycle is not
1825 atmel_port->has_frac_baudrate = false;
1826 atmel_port->has_hw_timer = false;
1827 atmel_port->is_usart = false;
1829 if (name == new_uart) {
1830 dev_dbg(port->dev, "Uart with hw timer");
1831 atmel_port->has_hw_timer = true;
1832 atmel_port->rtor = ATMEL_UA_RTOR;
1833 } else if (name == usart) {
1834 dev_dbg(port->dev, "Usart\n");
1835 atmel_port->has_frac_baudrate = true;
1836 atmel_port->has_hw_timer = true;
1837 atmel_port->is_usart = true;
1838 atmel_port->rtor = ATMEL_US_RTOR;
1839 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1841 case 0x814: /* sama5d2 */
1843 case 0x701: /* sama5d4 */
1844 atmel_port->fidi_min = 3;
1845 atmel_port->fidi_max = 65535;
1847 case 0x502: /* sam9x5, sama5d3 */
1848 atmel_port->fidi_min = 3;
1849 atmel_port->fidi_max = 2047;
1852 atmel_port->fidi_min = 1;
1853 atmel_port->fidi_max = 2047;
1855 } else if (name == dbgu_uart) {
1856 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1858 /* fallback for older SoCs: use version field */
1859 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1864 dev_dbg(port->dev, "This version is usart\n");
1865 atmel_port->has_frac_baudrate = true;
1866 atmel_port->has_hw_timer = true;
1867 atmel_port->is_usart = true;
1868 atmel_port->rtor = ATMEL_US_RTOR;
1872 dev_dbg(port->dev, "This version is uart\n");
1875 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1881 * Perform initialization and enable port for reception
1883 static int atmel_startup(struct uart_port *port)
1885 struct platform_device *pdev = to_platform_device(port->dev);
1886 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1890 * Ensure that no interrupts are enabled otherwise when
1891 * request_irq() is called we could get stuck trying to
1892 * handle an unexpected interrupt
1894 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1895 atmel_port->ms_irq_enabled = false;
1900 retval = request_irq(port->irq, atmel_interrupt,
1901 IRQF_SHARED | IRQF_COND_SUSPEND,
1902 dev_name(&pdev->dev), port);
1904 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1908 atomic_set(&atmel_port->tasklet_shutdown, 0);
1909 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1910 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1913 * Initialize DMA (if necessary)
1915 atmel_init_property(atmel_port, pdev);
1916 atmel_set_ops(port);
1918 if (atmel_port->prepare_rx) {
1919 retval = atmel_port->prepare_rx(port);
1921 atmel_set_ops(port);
1924 if (atmel_port->prepare_tx) {
1925 retval = atmel_port->prepare_tx(port);
1927 atmel_set_ops(port);
1931 * Enable FIFO when available
1933 if (atmel_port->fifo_size) {
1934 unsigned int txrdym = ATMEL_US_ONE_DATA;
1935 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1938 atmel_uart_writel(port, ATMEL_US_CR,
1943 if (atmel_use_dma_tx(port))
1944 txrdym = ATMEL_US_FOUR_DATA;
1946 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1947 if (atmel_port->rts_high &&
1948 atmel_port->rts_low)
1949 fmr |= ATMEL_US_FRTSC |
1950 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1951 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1953 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1956 /* Save current CSR for comparison in atmel_tasklet_func() */
1957 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1960 * Finally, enable the serial port
1962 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1963 /* enable xmit & rcvr */
1964 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1965 atmel_port->tx_stopped = false;
1967 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1969 if (atmel_use_pdc_rx(port)) {
1970 /* set UART timeout */
1971 if (!atmel_port->has_hw_timer) {
1972 mod_timer(&atmel_port->uart_timer,
1973 jiffies + uart_poll_timeout(port));
1974 /* set USART timeout */
1976 atmel_uart_writel(port, atmel_port->rtor,
1978 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1980 atmel_uart_writel(port, ATMEL_US_IER,
1981 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1983 /* enable PDC controller */
1984 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1985 } else if (atmel_use_dma_rx(port)) {
1986 /* set UART timeout */
1987 if (!atmel_port->has_hw_timer) {
1988 mod_timer(&atmel_port->uart_timer,
1989 jiffies + uart_poll_timeout(port));
1990 /* set USART timeout */
1992 atmel_uart_writel(port, atmel_port->rtor,
1994 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1996 atmel_uart_writel(port, ATMEL_US_IER,
2000 /* enable receive only */
2001 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2008 * Flush any TX data submitted for DMA. Called when the TX circular
2011 static void atmel_flush_buffer(struct uart_port *port)
2013 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2015 if (atmel_use_pdc_tx(port)) {
2016 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2017 atmel_port->pdc_tx.ofs = 0;
2020 * in uart_flush_buffer(), the xmit circular buffer has just
2021 * been cleared, so we have to reset tx_len accordingly.
2023 atmel_port->tx_len = 0;
2029 static void atmel_shutdown(struct uart_port *port)
2031 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2033 /* Disable modem control lines interrupts */
2034 atmel_disable_ms(port);
2036 /* Disable interrupts at device level */
2037 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2039 /* Prevent spurious interrupts from scheduling the tasklet */
2040 atomic_inc(&atmel_port->tasklet_shutdown);
2043 * Prevent any tasklets being scheduled during
2046 del_timer_sync(&atmel_port->uart_timer);
2048 /* Make sure that no interrupt is on the fly */
2049 synchronize_irq(port->irq);
2052 * Clear out any scheduled tasklets before
2053 * we destroy the buffers
2055 tasklet_kill(&atmel_port->tasklet_rx);
2056 tasklet_kill(&atmel_port->tasklet_tx);
2059 * Ensure everything is stopped and
2060 * disable port and break condition.
2062 atmel_stop_rx(port);
2063 atmel_stop_tx(port);
2065 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2068 * Shut-down the DMA.
2070 if (atmel_port->release_rx)
2071 atmel_port->release_rx(port);
2072 if (atmel_port->release_tx)
2073 atmel_port->release_tx(port);
2076 * Reset ring buffer pointers
2078 atmel_port->rx_ring.head = 0;
2079 atmel_port->rx_ring.tail = 0;
2082 * Free the interrupts
2084 free_irq(port->irq, port);
2086 atmel_flush_buffer(port);
2090 * Power / Clock management.
2092 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2093 unsigned int oldstate)
2095 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2098 case UART_PM_STATE_ON:
2100 * Enable the peripheral clock for this serial port.
2101 * This is called on uart_open() or a resume event.
2103 clk_prepare_enable(atmel_port->clk);
2105 /* re-enable interrupts if we disabled some on suspend */
2106 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2108 case UART_PM_STATE_OFF:
2109 /* Back up the interrupt mask and disable all interrupts */
2110 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2111 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2114 * Disable the peripheral clock for this serial port.
2115 * This is called on uart_close() or a suspend event.
2117 clk_disable_unprepare(atmel_port->clk);
2118 if (__clk_is_enabled(atmel_port->gclk))
2119 clk_disable_unprepare(atmel_port->gclk);
2122 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2127 * Change the port parameters
2129 static void atmel_set_termios(struct uart_port *port,
2130 struct ktermios *termios,
2131 const struct ktermios *old)
2133 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2134 unsigned long flags;
2135 unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
2136 unsigned int baud, actual_baud, gclk_rate;
2139 /* save the current mode register */
2140 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2142 /* reset the mode, clock divisor, parity, stop bits and data size */
2143 if (atmel_port->is_usart)
2144 mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL |
2145 ATMEL_US_USCLKS | ATMEL_US_USMODE);
2147 mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER);
2149 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2152 switch (termios->c_cflag & CSIZE) {
2154 mode |= ATMEL_US_CHRL_5;
2157 mode |= ATMEL_US_CHRL_6;
2160 mode |= ATMEL_US_CHRL_7;
2163 mode |= ATMEL_US_CHRL_8;
2168 if (termios->c_cflag & CSTOPB)
2169 mode |= ATMEL_US_NBSTOP_2;
2172 if (termios->c_cflag & PARENB) {
2173 /* Mark or Space parity */
2174 if (termios->c_cflag & CMSPAR) {
2175 if (termios->c_cflag & PARODD)
2176 mode |= ATMEL_US_PAR_MARK;
2178 mode |= ATMEL_US_PAR_SPACE;
2179 } else if (termios->c_cflag & PARODD)
2180 mode |= ATMEL_US_PAR_ODD;
2182 mode |= ATMEL_US_PAR_EVEN;
2184 mode |= ATMEL_US_PAR_NONE;
2186 uart_port_lock_irqsave(port, &flags);
2188 port->read_status_mask = ATMEL_US_OVRE;
2189 if (termios->c_iflag & INPCK)
2190 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2191 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2192 port->read_status_mask |= ATMEL_US_RXBRK;
2194 if (atmel_use_pdc_rx(port))
2195 /* need to enable error interrupts */
2196 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2199 * Characters to ignore
2201 port->ignore_status_mask = 0;
2202 if (termios->c_iflag & IGNPAR)
2203 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2204 if (termios->c_iflag & IGNBRK) {
2205 port->ignore_status_mask |= ATMEL_US_RXBRK;
2207 * If we're ignoring parity and break indicators,
2208 * ignore overruns too (for real raw support).
2210 if (termios->c_iflag & IGNPAR)
2211 port->ignore_status_mask |= ATMEL_US_OVRE;
2213 /* TODO: Ignore all characters if CREAD is set.*/
2215 /* update the per-port timeout */
2216 uart_update_timeout(port, termios->c_cflag, baud);
2219 * save/disable interrupts. The tty layer will ensure that the
2220 * transmitter is empty if requested by the caller, so there's
2221 * no need to wait for it here.
2223 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2224 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2226 /* disable receiver and transmitter */
2227 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2228 atmel_port->tx_stopped = true;
2231 if (port->rs485.flags & SER_RS485_ENABLED) {
2232 atmel_uart_writel(port, ATMEL_US_TTGR,
2233 port->rs485.delay_rts_after_send);
2234 mode |= ATMEL_US_USMODE_RS485;
2235 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2236 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2237 /* select mck clock, and output */
2238 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2239 /* set max iterations */
2240 mode |= ATMEL_US_MAX_ITER(3);
2241 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2242 == SER_ISO7816_T(0))
2243 mode |= ATMEL_US_USMODE_ISO7816_T0;
2245 mode |= ATMEL_US_USMODE_ISO7816_T1;
2246 } else if (termios->c_cflag & CRTSCTS) {
2247 /* RS232 with hardware handshake (RTS/CTS) */
2248 if (atmel_use_fifo(port) &&
2249 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2251 * with ATMEL_US_USMODE_HWHS set, the controller will
2252 * be able to drive the RTS pin high/low when the RX
2253 * FIFO is above RXFTHRES/below RXFTHRES2.
2254 * It will also disable the transmitter when the CTS
2256 * This mode is not activated if CTS pin is a GPIO
2257 * because in this case, the transmitter is always
2258 * disabled (there must be an internal pull-up
2259 * responsible for this behaviour).
2260 * If the RTS pin is a GPIO, the controller won't be
2261 * able to drive it according to the FIFO thresholds,
2262 * but it will be handled by the driver.
2264 mode |= ATMEL_US_USMODE_HWHS;
2267 * For platforms without FIFO, the flow control is
2268 * handled by the driver.
2270 mode |= ATMEL_US_USMODE_NORMAL;
2273 /* RS232 without hadware handshake */
2274 mode |= ATMEL_US_USMODE_NORMAL;
2278 * Set the baud rate:
2279 * Fractional baudrate allows to setup output frequency more
2280 * accurately. This feature is enabled only when using normal mode.
2281 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2282 * Currently, OVER is always set to 0 so we get
2283 * baudrate = selected clock / (16 * (CD + FP / 8))
2285 * 8 CD + FP = selected clock / (2 * baudrate)
2287 if (atmel_port->has_frac_baudrate) {
2288 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2290 fp = div & ATMEL_US_FP_MASK;
2292 cd = uart_get_divisor(port, baud);
2296 * If the current value of the Clock Divisor surpasses the 16 bit
2297 * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral
2298 * Clock implicitly divided by 8.
2299 * If the IP is UART however, keep the highest possible value for
2300 * the CD and avoid needless division of CD, since UART IP's do not
2301 * support implicit division of the Peripheral Clock.
2303 if (atmel_port->is_usart && cd > ATMEL_US_CD) {
2305 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2307 cd = min_t(unsigned int, cd, ATMEL_US_CD);
2311 * If there is no Fractional Part, there is a high chance that
2312 * we may be able to generate a baudrate closer to the desired one
2313 * if we use the GCLK as the clock source driving the baudrate
2316 if (!atmel_port->has_frac_baudrate) {
2317 if (__clk_is_enabled(atmel_port->gclk))
2318 clk_disable_unprepare(atmel_port->gclk);
2319 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
2320 actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
2321 if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
2322 abs(atmel_error_rate(baud, gclk_rate / 16))) {
2323 clk_set_rate(atmel_port->gclk, 16 * baud);
2324 ret = clk_prepare_enable(atmel_port->gclk);
2328 if (atmel_port->is_usart) {
2329 mode &= ~ATMEL_US_USCLKS;
2330 mode |= ATMEL_US_USCLKS_GCLK;
2332 mode |= ATMEL_UA_BRSRCCK;
2336 * Set the Clock Divisor for GCLK to 1.
2337 * Since we were able to generate the smallest
2338 * multiple of the desired baudrate times 16,
2339 * then we surely can generate a bigger multiple
2340 * with the exact error rate for an equally increased
2341 * CD. Thus no need to take into account
2342 * a higher value for CD.
2349 quot = cd | fp << ATMEL_US_FP_OFFSET;
2351 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2352 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2354 /* set the mode, clock divisor, parity, stop bits and data size */
2355 atmel_uart_writel(port, ATMEL_US_MR, mode);
2358 * when switching the mode, set the RTS line state according to the
2359 * new mode, otherwise keep the former state
2361 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2362 unsigned int rts_state;
2364 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2365 /* let the hardware control the RTS line */
2366 rts_state = ATMEL_US_RTSDIS;
2368 /* force RTS line to low level */
2369 rts_state = ATMEL_US_RTSEN;
2372 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2375 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2376 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2377 atmel_port->tx_stopped = false;
2379 /* restore interrupts */
2380 atmel_uart_writel(port, ATMEL_US_IER, imr);
2382 /* CTS flow-control and modem-status interrupts */
2383 if (UART_ENABLE_MS(port, termios->c_cflag))
2384 atmel_enable_ms(port);
2386 atmel_disable_ms(port);
2388 uart_port_unlock_irqrestore(port, flags);
2391 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2393 if (termios->c_line == N_PPS) {
2394 port->flags |= UPF_HARDPPS_CD;
2395 uart_port_lock_irq(port);
2396 atmel_enable_ms(port);
2397 uart_port_unlock_irq(port);
2399 port->flags &= ~UPF_HARDPPS_CD;
2400 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2401 uart_port_lock_irq(port);
2402 atmel_disable_ms(port);
2403 uart_port_unlock_irq(port);
2409 * Return string describing the specified port
2411 static const char *atmel_type(struct uart_port *port)
2413 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2417 * Release the memory region(s) being used by 'port'.
2419 static void atmel_release_port(struct uart_port *port)
2421 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2422 int size = resource_size(mpdev->resource);
2424 release_mem_region(port->mapbase, size);
2426 if (port->flags & UPF_IOREMAP) {
2427 iounmap(port->membase);
2428 port->membase = NULL;
2433 * Request the memory region(s) being used by 'port'.
2435 static int atmel_request_port(struct uart_port *port)
2437 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2438 int size = resource_size(mpdev->resource);
2440 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2443 if (port->flags & UPF_IOREMAP) {
2444 port->membase = ioremap(port->mapbase, size);
2445 if (port->membase == NULL) {
2446 release_mem_region(port->mapbase, size);
2455 * Configure/autoconfigure the port.
2457 static void atmel_config_port(struct uart_port *port, int flags)
2459 if (flags & UART_CONFIG_TYPE) {
2460 port->type = PORT_ATMEL;
2461 atmel_request_port(port);
2466 * Verify the new serial_struct (for TIOCSSERIAL).
2468 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2471 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2473 if (port->irq != ser->irq)
2475 if (ser->io_type != SERIAL_IO_MEM)
2477 if (port->uartclk / 16 != ser->baud_base)
2479 if (port->mapbase != (unsigned long)ser->iomem_base)
2481 if (port->iobase != ser->port)
2488 #ifdef CONFIG_CONSOLE_POLL
2489 static int atmel_poll_get_char(struct uart_port *port)
2491 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2494 return atmel_uart_read_char(port);
2497 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2499 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2502 atmel_uart_write_char(port, ch);
2506 static const struct uart_ops atmel_pops = {
2507 .tx_empty = atmel_tx_empty,
2508 .set_mctrl = atmel_set_mctrl,
2509 .get_mctrl = atmel_get_mctrl,
2510 .stop_tx = atmel_stop_tx,
2511 .start_tx = atmel_start_tx,
2512 .stop_rx = atmel_stop_rx,
2513 .enable_ms = atmel_enable_ms,
2514 .break_ctl = atmel_break_ctl,
2515 .startup = atmel_startup,
2516 .shutdown = atmel_shutdown,
2517 .flush_buffer = atmel_flush_buffer,
2518 .set_termios = atmel_set_termios,
2519 .set_ldisc = atmel_set_ldisc,
2521 .release_port = atmel_release_port,
2522 .request_port = atmel_request_port,
2523 .config_port = atmel_config_port,
2524 .verify_port = atmel_verify_port,
2525 .pm = atmel_serial_pm,
2526 #ifdef CONFIG_CONSOLE_POLL
2527 .poll_get_char = atmel_poll_get_char,
2528 .poll_put_char = atmel_poll_put_char,
2532 static const struct serial_rs485 atmel_rs485_supported = {
2533 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RX_DURING_TX,
2534 .delay_rts_before_send = 1,
2535 .delay_rts_after_send = 1,
2539 * Configure the port from the platform device resource info.
2541 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2542 struct platform_device *pdev)
2545 struct uart_port *port = &atmel_port->uart;
2546 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2548 atmel_init_property(atmel_port, pdev);
2549 atmel_set_ops(port);
2551 port->iotype = UPIO_MEM;
2552 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2553 port->ops = &atmel_pops;
2555 port->dev = &pdev->dev;
2556 port->mapbase = mpdev->resource[0].start;
2557 port->irq = platform_get_irq(mpdev, 0);
2558 port->rs485_config = atmel_config_rs485;
2559 port->rs485_supported = atmel_rs485_supported;
2560 port->iso7816_config = atmel_config_iso7816;
2561 port->membase = NULL;
2563 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2565 ret = uart_get_rs485_mode(port);
2569 port->uartclk = clk_get_rate(atmel_port->clk);
2572 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2575 if (atmel_uart_is_half_duplex(port))
2576 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2577 else if (atmel_use_pdc_tx(port)) {
2578 port->fifosize = PDC_BUFFER_SIZE;
2579 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2581 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2587 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2588 static void atmel_console_putchar(struct uart_port *port, unsigned char ch)
2590 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2592 atmel_uart_write_char(port, ch);
2596 * Interrupts are disabled on entering
2598 static void atmel_console_write(struct console *co, const char *s, u_int count)
2600 struct uart_port *port = &atmel_ports[co->index].uart;
2601 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2602 unsigned int status, imr;
2603 unsigned int pdc_tx;
2606 * First, save IMR and then disable interrupts
2608 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2609 atmel_uart_writel(port, ATMEL_US_IDR,
2610 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2612 /* Store PDC transmit status and disable it */
2613 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2614 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2616 /* Make sure that tx path is actually able to send characters */
2617 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2618 atmel_port->tx_stopped = false;
2620 uart_console_write(port, s, count, atmel_console_putchar);
2623 * Finally, wait for transmitter to become empty
2627 status = atmel_uart_readl(port, ATMEL_US_CSR);
2628 } while (!(status & ATMEL_US_TXRDY));
2630 /* Restore PDC transmit status */
2632 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2634 /* set interrupts back the way they were */
2635 atmel_uart_writel(port, ATMEL_US_IER, imr);
2639 * If the port was already initialised (eg, by a boot loader),
2640 * try to determine the current setup.
2642 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2643 int *parity, int *bits)
2645 unsigned int mr, quot;
2648 * If the baud rate generator isn't running, the port wasn't
2649 * initialized by the boot loader.
2651 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2655 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2656 if (mr == ATMEL_US_CHRL_8)
2661 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2662 if (mr == ATMEL_US_PAR_EVEN)
2664 else if (mr == ATMEL_US_PAR_ODD)
2667 *baud = port->uartclk / (16 * quot);
2670 static int __init atmel_console_setup(struct console *co, char *options)
2672 struct uart_port *port = &atmel_ports[co->index].uart;
2673 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2679 if (port->membase == NULL) {
2680 /* Port not initialized yet - delay setup */
2684 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2685 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2686 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2687 atmel_port->tx_stopped = false;
2690 uart_parse_options(options, &baud, &parity, &bits, &flow);
2692 atmel_console_get_options(port, &baud, &parity, &bits);
2694 return uart_set_options(port, co, baud, parity, bits, flow);
2697 static struct uart_driver atmel_uart;
2699 static struct console atmel_console = {
2700 .name = ATMEL_DEVICENAME,
2701 .write = atmel_console_write,
2702 .device = uart_console_device,
2703 .setup = atmel_console_setup,
2704 .flags = CON_PRINTBUFFER,
2706 .data = &atmel_uart,
2709 static void atmel_serial_early_write(struct console *con, const char *s,
2712 struct earlycon_device *dev = con->data;
2714 uart_console_write(&dev->port, s, n, atmel_console_putchar);
2717 static int __init atmel_early_console_setup(struct earlycon_device *device,
2718 const char *options)
2720 if (!device->port.membase)
2723 device->con->write = atmel_serial_early_write;
2728 OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart",
2729 atmel_early_console_setup);
2730 OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart",
2731 atmel_early_console_setup);
2733 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2736 #define ATMEL_CONSOLE_DEVICE NULL
2739 static struct uart_driver atmel_uart = {
2740 .owner = THIS_MODULE,
2741 .driver_name = "atmel_serial",
2742 .dev_name = ATMEL_DEVICENAME,
2743 .major = SERIAL_ATMEL_MAJOR,
2744 .minor = MINOR_START,
2745 .nr = ATMEL_MAX_UART,
2746 .cons = ATMEL_CONSOLE_DEVICE,
2749 static bool atmel_serial_clk_will_stop(void)
2751 #ifdef CONFIG_ARCH_AT91
2752 return at91_suspend_entering_slow_clock();
2758 static int __maybe_unused atmel_serial_suspend(struct device *dev)
2760 struct uart_port *port = dev_get_drvdata(dev);
2761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2763 if (uart_console(port) && console_suspend_enabled) {
2764 /* Drain the TX shifter */
2765 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2770 if (uart_console(port) && !console_suspend_enabled) {
2771 /* Cache register values as we won't get a full shutdown/startup
2774 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2775 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2776 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2777 atmel_port->cache.rtor = atmel_uart_readl(port,
2779 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2780 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2781 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2784 /* we can not wake up if we're running on slow clock */
2785 atmel_port->may_wakeup = device_may_wakeup(dev);
2786 if (atmel_serial_clk_will_stop()) {
2787 unsigned long flags;
2789 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2790 atmel_port->suspended = true;
2791 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2792 device_set_wakeup_enable(dev, 0);
2795 uart_suspend_port(&atmel_uart, port);
2800 static int __maybe_unused atmel_serial_resume(struct device *dev)
2802 struct uart_port *port = dev_get_drvdata(dev);
2803 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2804 unsigned long flags;
2806 if (uart_console(port) && !console_suspend_enabled) {
2807 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2808 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2809 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2810 atmel_uart_writel(port, atmel_port->rtor,
2811 atmel_port->cache.rtor);
2812 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2814 if (atmel_port->fifo_size) {
2815 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2816 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2817 atmel_uart_writel(port, ATMEL_US_FMR,
2818 atmel_port->cache.fmr);
2819 atmel_uart_writel(port, ATMEL_US_FIER,
2820 atmel_port->cache.fimr);
2822 atmel_start_rx(port);
2825 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2826 if (atmel_port->pending) {
2827 atmel_handle_receive(port, atmel_port->pending);
2828 atmel_handle_status(port, atmel_port->pending,
2829 atmel_port->pending_status);
2830 atmel_handle_transmit(port, atmel_port->pending);
2831 atmel_port->pending = 0;
2833 atmel_port->suspended = false;
2834 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2836 uart_resume_port(&atmel_uart, port);
2837 device_set_wakeup_enable(dev, atmel_port->may_wakeup);
2842 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2843 struct platform_device *pdev)
2845 atmel_port->fifo_size = 0;
2846 atmel_port->rts_low = 0;
2847 atmel_port->rts_high = 0;
2849 if (of_property_read_u32(pdev->dev.of_node,
2851 &atmel_port->fifo_size))
2854 if (!atmel_port->fifo_size)
2857 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2858 atmel_port->fifo_size = 0;
2859 dev_err(&pdev->dev, "Invalid FIFO size\n");
2864 * 0 <= rts_low <= rts_high <= fifo_size
2865 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2866 * to flush their internal TX FIFO, commonly up to 16 data, before
2867 * actually stopping to send new data. So we try to set the RTS High
2868 * Threshold to a reasonably high value respecting this 16 data
2869 * empirical rule when possible.
2871 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2872 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2873 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2874 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2876 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2877 atmel_port->fifo_size);
2878 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2879 atmel_port->rts_high);
2880 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2881 atmel_port->rts_low);
2884 static int atmel_serial_probe(struct platform_device *pdev)
2886 struct atmel_uart_port *atmel_port;
2887 struct device_node *np = pdev->dev.parent->of_node;
2892 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2895 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2896 * as compatible string. This driver is probed by at91-usart mfd driver
2897 * which is just a wrapper over the atmel_serial driver and
2898 * spi-at91-usart driver. All attributes needed by this driver are
2899 * found in of_node of parent.
2901 pdev->dev.of_node = np;
2903 ret = of_alias_get_id(np, "serial");
2905 /* port id not found in platform data nor device-tree aliases:
2906 * auto-enumerate it */
2907 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2909 if (ret >= ATMEL_MAX_UART) {
2914 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2915 /* port already in use */
2920 atmel_port = &atmel_ports[ret];
2921 atmel_port->backup_imr = 0;
2922 atmel_port->uart.line = ret;
2923 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2924 atmel_serial_probe_fifos(atmel_port, pdev);
2926 atomic_set(&atmel_port->tasklet_shutdown, 0);
2927 spin_lock_init(&atmel_port->lock_suspended);
2929 atmel_port->clk = devm_clk_get(&pdev->dev, "usart");
2930 if (IS_ERR(atmel_port->clk)) {
2931 ret = PTR_ERR(atmel_port->clk);
2934 ret = clk_prepare_enable(atmel_port->clk);
2938 atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
2939 if (IS_ERR(atmel_port->gclk)) {
2940 ret = PTR_ERR(atmel_port->gclk);
2941 goto err_clk_disable_unprepare;
2944 ret = atmel_init_port(atmel_port, pdev);
2946 goto err_clk_disable_unprepare;
2948 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2949 if (IS_ERR(atmel_port->gpios)) {
2950 ret = PTR_ERR(atmel_port->gpios);
2951 goto err_clk_disable_unprepare;
2954 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2956 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2957 sizeof(struct atmel_uart_char),
2960 goto err_clk_disable_unprepare;
2961 atmel_port->rx_ring.buf = data;
2964 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2966 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2970 device_init_wakeup(&pdev->dev, 1);
2971 platform_set_drvdata(pdev, atmel_port);
2973 if (rs485_enabled) {
2974 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2975 ATMEL_US_USMODE_NORMAL);
2976 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2981 * Get port name of usart or uart
2983 atmel_get_ip_name(&atmel_port->uart);
2986 * The peripheral clock can now safely be disabled till the port
2989 clk_disable_unprepare(atmel_port->clk);
2994 kfree(atmel_port->rx_ring.buf);
2995 atmel_port->rx_ring.buf = NULL;
2996 err_clk_disable_unprepare:
2997 clk_disable_unprepare(atmel_port->clk);
2998 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
3004 * Even if the driver is not modular, it makes sense to be able to
3005 * unbind a device: there can be many bound devices, and there are
3006 * situations where dynamic binding and unbinding can be useful.
3008 * For example, a connected device can require a specific firmware update
3009 * protocol that needs bitbanging on IO lines, but use the regular serial
3010 * port in the normal case.
3012 static void atmel_serial_remove(struct platform_device *pdev)
3014 struct uart_port *port = platform_get_drvdata(pdev);
3015 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
3017 tasklet_kill(&atmel_port->tasklet_rx);
3018 tasklet_kill(&atmel_port->tasklet_tx);
3020 device_init_wakeup(&pdev->dev, 0);
3022 uart_remove_one_port(&atmel_uart, port);
3024 kfree(atmel_port->rx_ring.buf);
3026 /* "port" is allocated statically, so we shouldn't free it */
3028 clear_bit(port->line, atmel_ports_in_use);
3030 pdev->dev.of_node = NULL;
3033 static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend,
3034 atmel_serial_resume);
3036 static struct platform_driver atmel_serial_driver = {
3037 .probe = atmel_serial_probe,
3038 .remove_new = atmel_serial_remove,
3040 .name = "atmel_usart_serial",
3041 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
3042 .pm = pm_ptr(&atmel_serial_pm_ops),
3046 static int __init atmel_serial_init(void)
3050 ret = uart_register_driver(&atmel_uart);
3054 ret = platform_driver_register(&atmel_serial_driver);
3056 uart_unregister_driver(&atmel_uart);
3060 device_initcall(atmel_serial_init);