2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/atmel_serial.h>
42 #include <linux/uaccess.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/timer.h>
45 #include <linux/gpio.h>
46 #include <linux/gpio/consumer.h>
47 #include <linux/err.h>
48 #include <linux/irq.h>
49 #include <linux/suspend.h>
52 #include <asm/ioctls.h>
54 #define PDC_BUFFER_SIZE 512
55 /* Revisit: We should calculate this based on the actual port settings */
56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
58 /* The minium number of data FIFOs should be able to contain */
59 #define ATMEL_MIN_FIFO_SIZE 8
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
64 #define ATMEL_RTS_HIGH_OFFSET 16
65 #define ATMEL_RTS_LOW_OFFSET 20
67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
71 #include <linux/serial_core.h>
73 #include "serial_mctrl_gpio.h"
75 static void atmel_start_rx(struct uart_port *port);
76 static void atmel_stop_rx(struct uart_port *port);
78 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
80 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
83 #define SERIAL_ATMEL_MAJOR 204
84 #define MINOR_START 154
85 #define ATMEL_DEVICENAME "ttyAT"
89 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
91 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
92 #define MINOR_START 64
93 #define ATMEL_DEVICENAME "ttyS"
97 #define ATMEL_ISR_PASS_LIMIT 256
99 struct atmel_dma_buffer {
102 unsigned int dma_size;
106 struct atmel_uart_char {
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
117 #define ATMEL_SERIAL_RINGSIZE 1024
120 * at91: 6 USARTs and one DBGU port (SAM9260)
123 #define ATMEL_MAX_UART 7
126 * We wrap our port structure around the generic uart_port.
128 struct atmel_uart_port {
129 struct uart_port uart; /* uart */
130 struct clk *clk; /* uart clock */
131 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
132 u32 backup_imr; /* IMR saved during suspend */
133 int break_active; /* break being received */
135 bool use_dma_rx; /* enable DMA receiver */
136 bool use_pdc_rx; /* enable PDC receiver */
137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
140 bool use_dma_tx; /* enable DMA transmitter */
141 bool use_pdc_tx; /* enable PDC transmitter */
142 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
144 spinlock_t lock_tx; /* port lock */
145 spinlock_t lock_rx; /* port lock */
146 struct dma_chan *chan_tx;
147 struct dma_chan *chan_rx;
148 struct dma_async_tx_descriptor *desc_tx;
149 struct dma_async_tx_descriptor *desc_rx;
150 dma_cookie_t cookie_tx;
151 dma_cookie_t cookie_rx;
152 struct scatterlist sg_tx;
153 struct scatterlist sg_rx;
154 struct tasklet_struct tasklet_rx;
155 struct tasklet_struct tasklet_tx;
156 atomic_t tasklet_shutdown;
157 unsigned int irq_status_prev;
160 struct circ_buf rx_ring;
162 struct mctrl_gpios *gpios;
163 unsigned int tx_done_mask;
168 u32 rtor; /* address of receiver timeout register if it exists */
169 bool has_frac_baudrate;
171 struct timer_list uart_timer;
174 unsigned int pending;
175 unsigned int pending_status;
176 spinlock_t lock_suspended;
178 bool hd_start_rx; /* can start RX during half-duplex operation */
180 int (*prepare_rx)(struct uart_port *port);
181 int (*prepare_tx)(struct uart_port *port);
182 void (*schedule_rx)(struct uart_port *port);
183 void (*schedule_tx)(struct uart_port *port);
184 void (*release_rx)(struct uart_port *port);
185 void (*release_tx)(struct uart_port *port);
188 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
189 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
192 static struct console atmel_console;
195 #if defined(CONFIG_OF)
196 static const struct of_device_id atmel_serial_dt_ids[] = {
197 { .compatible = "atmel,at91rm9200-usart" },
198 { .compatible = "atmel,at91sam9260-usart" },
203 static inline struct atmel_uart_port *
204 to_atmel_uart_port(struct uart_port *uart)
206 return container_of(uart, struct atmel_uart_port, uart);
209 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
211 return __raw_readl(port->membase + reg);
214 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
216 __raw_writel(value, port->membase + reg);
221 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
222 static inline u8 atmel_uart_read_char(struct uart_port *port)
224 return __raw_readl(port->membase + ATMEL_US_RHR);
227 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
229 __raw_writel(value, port->membase + ATMEL_US_THR);
234 static inline u8 atmel_uart_read_char(struct uart_port *port)
236 return __raw_readb(port->membase + ATMEL_US_RHR);
239 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
241 __raw_writeb(value, port->membase + ATMEL_US_THR);
246 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
248 return (port->rs485.flags & SER_RS485_ENABLED) &&
249 !(port->rs485.flags & SER_RS485_RX_DURING_TX);
252 #ifdef CONFIG_SERIAL_ATMEL_PDC
253 static bool atmel_use_pdc_rx(struct uart_port *port)
255 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
257 return atmel_port->use_pdc_rx;
260 static bool atmel_use_pdc_tx(struct uart_port *port)
262 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
264 return atmel_port->use_pdc_tx;
267 static bool atmel_use_pdc_rx(struct uart_port *port)
272 static bool atmel_use_pdc_tx(struct uart_port *port)
278 static bool atmel_use_dma_tx(struct uart_port *port)
280 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
282 return atmel_port->use_dma_tx;
285 static bool atmel_use_dma_rx(struct uart_port *port)
287 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
289 return atmel_port->use_dma_rx;
292 static bool atmel_use_fifo(struct uart_port *port)
294 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
296 return atmel_port->fifo_size;
299 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
300 struct tasklet_struct *t)
302 if (!atomic_read(&atmel_port->tasklet_shutdown))
306 static unsigned int atmel_get_lines_status(struct uart_port *port)
308 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
309 unsigned int status, ret = 0;
311 status = atmel_uart_readl(port, ATMEL_US_CSR);
313 mctrl_gpio_get(atmel_port->gpios, &ret);
315 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
318 status &= ~ATMEL_US_CTS;
320 status |= ATMEL_US_CTS;
323 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
326 status &= ~ATMEL_US_DSR;
328 status |= ATMEL_US_DSR;
331 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
334 status &= ~ATMEL_US_RI;
336 status |= ATMEL_US_RI;
339 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
342 status &= ~ATMEL_US_DCD;
344 status |= ATMEL_US_DCD;
350 /* Enable or disable the rs485 support */
351 static int atmel_config_rs485(struct uart_port *port,
352 struct serial_rs485 *rs485conf)
354 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
357 /* Disable interrupts */
358 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
360 mode = atmel_uart_readl(port, ATMEL_US_MR);
362 /* Resetting serial mode to RS232 (0x0) */
363 mode &= ~ATMEL_US_USMODE;
365 port->rs485 = *rs485conf;
367 if (rs485conf->flags & SER_RS485_ENABLED) {
368 dev_dbg(port->dev, "Setting UART to RS485\n");
369 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
370 atmel_uart_writel(port, ATMEL_US_TTGR,
371 rs485conf->delay_rts_after_send);
372 mode |= ATMEL_US_USMODE_RS485;
374 dev_dbg(port->dev, "Setting UART to RS232\n");
375 if (atmel_use_pdc_tx(port))
376 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
379 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
381 atmel_uart_writel(port, ATMEL_US_MR, mode);
383 /* Enable interrupts */
384 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
390 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
392 static u_int atmel_tx_empty(struct uart_port *port)
394 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
400 * Set state of the modem control output lines
402 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
404 unsigned int control = 0;
405 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
406 unsigned int rts_paused, rts_ready;
407 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
409 /* override mode to RS485 if needed, otherwise keep the current mode */
410 if (port->rs485.flags & SER_RS485_ENABLED) {
411 atmel_uart_writel(port, ATMEL_US_TTGR,
412 port->rs485.delay_rts_after_send);
413 mode &= ~ATMEL_US_USMODE;
414 mode |= ATMEL_US_USMODE_RS485;
417 /* set the RTS line state according to the mode */
418 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
419 /* force RTS line to high level */
420 rts_paused = ATMEL_US_RTSEN;
422 /* give the control of the RTS line back to the hardware */
423 rts_ready = ATMEL_US_RTSDIS;
425 /* force RTS line to high level */
426 rts_paused = ATMEL_US_RTSDIS;
428 /* force RTS line to low level */
429 rts_ready = ATMEL_US_RTSEN;
432 if (mctrl & TIOCM_RTS)
433 control |= rts_ready;
435 control |= rts_paused;
437 if (mctrl & TIOCM_DTR)
438 control |= ATMEL_US_DTREN;
440 control |= ATMEL_US_DTRDIS;
442 atmel_uart_writel(port, ATMEL_US_CR, control);
444 mctrl_gpio_set(atmel_port->gpios, mctrl);
446 /* Local loopback mode? */
447 mode &= ~ATMEL_US_CHMODE;
448 if (mctrl & TIOCM_LOOP)
449 mode |= ATMEL_US_CHMODE_LOC_LOOP;
451 mode |= ATMEL_US_CHMODE_NORMAL;
453 atmel_uart_writel(port, ATMEL_US_MR, mode);
457 * Get state of the modem control input lines
459 static u_int atmel_get_mctrl(struct uart_port *port)
461 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
462 unsigned int ret = 0, status;
464 status = atmel_uart_readl(port, ATMEL_US_CSR);
467 * The control signals are active low.
469 if (!(status & ATMEL_US_DCD))
471 if (!(status & ATMEL_US_CTS))
473 if (!(status & ATMEL_US_DSR))
475 if (!(status & ATMEL_US_RI))
478 return mctrl_gpio_get(atmel_port->gpios, &ret);
484 static void atmel_stop_tx(struct uart_port *port)
486 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
488 if (atmel_use_pdc_tx(port)) {
489 /* disable PDC transmit */
490 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
494 * Disable the transmitter.
495 * This is mandatory when DMA is used, otherwise the DMA buffer
496 * is fully transmitted.
498 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
500 /* Disable interrupts */
501 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
503 if (atmel_uart_is_half_duplex(port))
504 if (!atomic_read(&atmel_port->tasklet_shutdown))
505 atmel_start_rx(port);
510 * Start transmitting.
512 static void atmel_start_tx(struct uart_port *port)
514 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
516 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
518 /* The transmitter is already running. Yes, we
522 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
523 if (atmel_uart_is_half_duplex(port))
526 if (atmel_use_pdc_tx(port))
527 /* re-enable PDC transmit */
528 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
530 /* Enable interrupts */
531 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
533 /* re-enable the transmitter */
534 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
538 * start receiving - port is in process of being opened.
540 static void atmel_start_rx(struct uart_port *port)
542 /* reset status and receiver */
543 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
545 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
547 if (atmel_use_pdc_rx(port)) {
548 /* enable PDC controller */
549 atmel_uart_writel(port, ATMEL_US_IER,
550 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
551 port->read_status_mask);
552 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
554 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
559 * Stop receiving - port is in process of being closed.
561 static void atmel_stop_rx(struct uart_port *port)
563 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
565 if (atmel_use_pdc_rx(port)) {
566 /* disable PDC receive */
567 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
568 atmel_uart_writel(port, ATMEL_US_IDR,
569 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
570 port->read_status_mask);
572 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
577 * Enable modem status interrupts
579 static void atmel_enable_ms(struct uart_port *port)
581 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
585 * Interrupt should not be enabled twice
587 if (atmel_port->ms_irq_enabled)
590 atmel_port->ms_irq_enabled = true;
592 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
593 ier |= ATMEL_US_CTSIC;
595 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
596 ier |= ATMEL_US_DSRIC;
598 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
599 ier |= ATMEL_US_RIIC;
601 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
602 ier |= ATMEL_US_DCDIC;
604 atmel_uart_writel(port, ATMEL_US_IER, ier);
606 mctrl_gpio_enable_ms(atmel_port->gpios);
610 * Disable modem status interrupts
612 static void atmel_disable_ms(struct uart_port *port)
614 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
618 * Interrupt should not be disabled twice
620 if (!atmel_port->ms_irq_enabled)
623 atmel_port->ms_irq_enabled = false;
625 mctrl_gpio_disable_ms(atmel_port->gpios);
627 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
628 idr |= ATMEL_US_CTSIC;
630 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
631 idr |= ATMEL_US_DSRIC;
633 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
634 idr |= ATMEL_US_RIIC;
636 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
637 idr |= ATMEL_US_DCDIC;
639 atmel_uart_writel(port, ATMEL_US_IDR, idr);
643 * Control the transmission of a break signal
645 static void atmel_break_ctl(struct uart_port *port, int break_state)
647 if (break_state != 0)
649 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
652 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
656 * Stores the incoming character in the ring buffer
659 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
662 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
663 struct circ_buf *ring = &atmel_port->rx_ring;
664 struct atmel_uart_char *c;
666 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
667 /* Buffer overflow, ignore char */
670 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
674 /* Make sure the character is stored before we update head. */
677 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
681 * Deal with parity, framing and overrun errors.
683 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
686 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
688 if (status & ATMEL_US_RXBRK) {
689 /* ignore side-effect */
690 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
693 if (status & ATMEL_US_PARE)
694 port->icount.parity++;
695 if (status & ATMEL_US_FRAME)
696 port->icount.frame++;
697 if (status & ATMEL_US_OVRE)
698 port->icount.overrun++;
702 * Characters received (called from interrupt handler)
704 static void atmel_rx_chars(struct uart_port *port)
706 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
707 unsigned int status, ch;
709 status = atmel_uart_readl(port, ATMEL_US_CSR);
710 while (status & ATMEL_US_RXRDY) {
711 ch = atmel_uart_read_char(port);
714 * note that the error handling code is
715 * out of the main execution path
717 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
718 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
719 || atmel_port->break_active)) {
722 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
724 if (status & ATMEL_US_RXBRK
725 && !atmel_port->break_active) {
726 atmel_port->break_active = 1;
727 atmel_uart_writel(port, ATMEL_US_IER,
731 * This is either the end-of-break
732 * condition or we've received at
733 * least one character without RXBRK
734 * being set. In both cases, the next
735 * RXBRK will indicate start-of-break.
737 atmel_uart_writel(port, ATMEL_US_IDR,
739 status &= ~ATMEL_US_RXBRK;
740 atmel_port->break_active = 0;
744 atmel_buffer_rx_char(port, status, ch);
745 status = atmel_uart_readl(port, ATMEL_US_CSR);
748 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
752 * Transmit characters (called from tasklet with TXRDY interrupt
755 static void atmel_tx_chars(struct uart_port *port)
757 struct circ_buf *xmit = &port->state->xmit;
758 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
761 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
762 atmel_uart_write_char(port, port->x_char);
766 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
769 while (atmel_uart_readl(port, ATMEL_US_CSR) &
770 atmel_port->tx_done_mask) {
771 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
772 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
774 if (uart_circ_empty(xmit))
778 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
779 uart_write_wakeup(port);
781 if (!uart_circ_empty(xmit))
782 /* Enable interrupts */
783 atmel_uart_writel(port, ATMEL_US_IER,
784 atmel_port->tx_done_mask);
787 static void atmel_complete_tx_dma(void *arg)
789 struct atmel_uart_port *atmel_port = arg;
790 struct uart_port *port = &atmel_port->uart;
791 struct circ_buf *xmit = &port->state->xmit;
792 struct dma_chan *chan = atmel_port->chan_tx;
795 spin_lock_irqsave(&port->lock, flags);
798 dmaengine_terminate_all(chan);
799 xmit->tail += atmel_port->tx_len;
800 xmit->tail &= UART_XMIT_SIZE - 1;
802 port->icount.tx += atmel_port->tx_len;
804 spin_lock_irq(&atmel_port->lock_tx);
805 async_tx_ack(atmel_port->desc_tx);
806 atmel_port->cookie_tx = -EINVAL;
807 atmel_port->desc_tx = NULL;
808 spin_unlock_irq(&atmel_port->lock_tx);
810 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
811 uart_write_wakeup(port);
814 * xmit is a circular buffer so, if we have just send data from
815 * xmit->tail to the end of xmit->buf, now we have to transmit the
816 * remaining data from the beginning of xmit->buf to xmit->head.
818 if (!uart_circ_empty(xmit))
819 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
820 else if (atmel_uart_is_half_duplex(port)) {
822 * DMA done, re-enable TXEMPTY and signal that we can stop
823 * TX and start RX for RS485
825 atmel_port->hd_start_rx = true;
826 atmel_uart_writel(port, ATMEL_US_IER,
827 atmel_port->tx_done_mask);
830 spin_unlock_irqrestore(&port->lock, flags);
833 static void atmel_release_tx_dma(struct uart_port *port)
835 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
836 struct dma_chan *chan = atmel_port->chan_tx;
839 dmaengine_terminate_all(chan);
840 dma_release_channel(chan);
841 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
845 atmel_port->desc_tx = NULL;
846 atmel_port->chan_tx = NULL;
847 atmel_port->cookie_tx = -EINVAL;
851 * Called from tasklet with TXRDY interrupt is disabled.
853 static void atmel_tx_dma(struct uart_port *port)
855 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
856 struct circ_buf *xmit = &port->state->xmit;
857 struct dma_chan *chan = atmel_port->chan_tx;
858 struct dma_async_tx_descriptor *desc;
859 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
860 unsigned int tx_len, part1_len, part2_len, sg_len;
861 dma_addr_t phys_addr;
863 /* Make sure we have an idle channel */
864 if (atmel_port->desc_tx != NULL)
867 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
870 * Port xmit buffer is already mapped,
871 * and it is one page... Just adjust
872 * offsets and lengths. Since it is a circular buffer,
873 * we have to transmit till the end, and then the rest.
874 * Take the port lock to get a
875 * consistent xmit buffer state.
877 tx_len = CIRC_CNT_TO_END(xmit->head,
881 if (atmel_port->fifo_size) {
882 /* multi data mode */
883 part1_len = (tx_len & ~0x3); /* DWORD access */
884 part2_len = (tx_len & 0x3); /* BYTE access */
886 /* single data (legacy) mode */
888 part2_len = tx_len; /* BYTE access only */
891 sg_init_table(sgl, 2);
893 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
896 sg_dma_address(sg) = phys_addr;
897 sg_dma_len(sg) = part1_len;
899 phys_addr += part1_len;
904 sg_dma_address(sg) = phys_addr;
905 sg_dma_len(sg) = part2_len;
909 * save tx_len so atmel_complete_tx_dma() will increase
910 * xmit->tail correctly
912 atmel_port->tx_len = tx_len;
914 desc = dmaengine_prep_slave_sg(chan,
921 dev_err(port->dev, "Failed to send via dma!\n");
925 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
927 atmel_port->desc_tx = desc;
928 desc->callback = atmel_complete_tx_dma;
929 desc->callback_param = atmel_port;
930 atmel_port->cookie_tx = dmaengine_submit(desc);
933 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
934 uart_write_wakeup(port);
937 static int atmel_prepare_tx_dma(struct uart_port *port)
939 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
941 struct dma_slave_config config;
945 dma_cap_set(DMA_SLAVE, mask);
947 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
948 if (atmel_port->chan_tx == NULL)
950 dev_info(port->dev, "using %s for tx DMA transfers\n",
951 dma_chan_name(atmel_port->chan_tx));
953 spin_lock_init(&atmel_port->lock_tx);
954 sg_init_table(&atmel_port->sg_tx, 1);
955 /* UART circular tx buffer is an aligned page. */
956 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
957 sg_set_page(&atmel_port->sg_tx,
958 virt_to_page(port->state->xmit.buf),
960 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
961 nent = dma_map_sg(port->dev,
967 dev_dbg(port->dev, "need to release resource of dma\n");
970 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
971 sg_dma_len(&atmel_port->sg_tx),
972 port->state->xmit.buf,
973 &sg_dma_address(&atmel_port->sg_tx));
976 /* Configure the slave DMA */
977 memset(&config, 0, sizeof(config));
978 config.direction = DMA_MEM_TO_DEV;
979 config.dst_addr_width = (atmel_port->fifo_size) ?
980 DMA_SLAVE_BUSWIDTH_4_BYTES :
981 DMA_SLAVE_BUSWIDTH_1_BYTE;
982 config.dst_addr = port->mapbase + ATMEL_US_THR;
983 config.dst_maxburst = 1;
985 ret = dmaengine_slave_config(atmel_port->chan_tx,
988 dev_err(port->dev, "DMA tx slave configuration failed\n");
995 dev_err(port->dev, "TX channel not available, switch to pio\n");
996 atmel_port->use_dma_tx = 0;
997 if (atmel_port->chan_tx)
998 atmel_release_tx_dma(port);
1002 static void atmel_complete_rx_dma(void *arg)
1004 struct uart_port *port = arg;
1005 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1007 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1010 static void atmel_release_rx_dma(struct uart_port *port)
1012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1013 struct dma_chan *chan = atmel_port->chan_rx;
1016 dmaengine_terminate_all(chan);
1017 dma_release_channel(chan);
1018 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1022 atmel_port->desc_rx = NULL;
1023 atmel_port->chan_rx = NULL;
1024 atmel_port->cookie_rx = -EINVAL;
1027 static void atmel_rx_from_dma(struct uart_port *port)
1029 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1030 struct tty_port *tport = &port->state->port;
1031 struct circ_buf *ring = &atmel_port->rx_ring;
1032 struct dma_chan *chan = atmel_port->chan_rx;
1033 struct dma_tx_state state;
1034 enum dma_status dmastat;
1038 /* Reset the UART timeout early so that we don't miss one */
1039 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1040 dmastat = dmaengine_tx_status(chan,
1041 atmel_port->cookie_rx,
1043 /* Restart a new tasklet if DMA status is error */
1044 if (dmastat == DMA_ERROR) {
1045 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1046 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1047 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1051 /* CPU claims ownership of RX DMA buffer */
1052 dma_sync_sg_for_cpu(port->dev,
1058 * ring->head points to the end of data already written by the DMA.
1059 * ring->tail points to the beginning of data to be read by the
1061 * The current transfer size should not be larger than the dma buffer
1064 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1065 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1067 * At this point ring->head may point to the first byte right after the
1068 * last byte of the dma buffer:
1069 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1071 * However ring->tail must always points inside the dma buffer:
1072 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1074 * Since we use a ring buffer, we have to handle the case
1075 * where head is lower than tail. In such a case, we first read from
1076 * tail to the end of the buffer then reset tail.
1078 if (ring->head < ring->tail) {
1079 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1081 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1083 port->icount.rx += count;
1086 /* Finally we read data from tail to head */
1087 if (ring->tail < ring->head) {
1088 count = ring->head - ring->tail;
1090 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1091 /* Wrap ring->head if needed */
1092 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1094 ring->tail = ring->head;
1095 port->icount.rx += count;
1098 /* USART retreives ownership of RX DMA buffer */
1099 dma_sync_sg_for_device(port->dev,
1105 * Drop the lock here since it might end up calling
1106 * uart_start(), which takes the lock.
1108 spin_unlock(&port->lock);
1109 tty_flip_buffer_push(tport);
1110 spin_lock(&port->lock);
1112 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1115 static int atmel_prepare_rx_dma(struct uart_port *port)
1117 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1118 struct dma_async_tx_descriptor *desc;
1119 dma_cap_mask_t mask;
1120 struct dma_slave_config config;
1121 struct circ_buf *ring;
1124 ring = &atmel_port->rx_ring;
1127 dma_cap_set(DMA_CYCLIC, mask);
1129 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1130 if (atmel_port->chan_rx == NULL)
1132 dev_info(port->dev, "using %s for rx DMA transfers\n",
1133 dma_chan_name(atmel_port->chan_rx));
1135 spin_lock_init(&atmel_port->lock_rx);
1136 sg_init_table(&atmel_port->sg_rx, 1);
1137 /* UART circular rx buffer is an aligned page. */
1138 BUG_ON(!PAGE_ALIGNED(ring->buf));
1139 sg_set_page(&atmel_port->sg_rx,
1140 virt_to_page(ring->buf),
1141 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1142 (unsigned long)ring->buf & ~PAGE_MASK);
1143 nent = dma_map_sg(port->dev,
1149 dev_dbg(port->dev, "need to release resource of dma\n");
1152 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1153 sg_dma_len(&atmel_port->sg_rx),
1155 &sg_dma_address(&atmel_port->sg_rx));
1158 /* Configure the slave DMA */
1159 memset(&config, 0, sizeof(config));
1160 config.direction = DMA_DEV_TO_MEM;
1161 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1162 config.src_addr = port->mapbase + ATMEL_US_RHR;
1163 config.src_maxburst = 1;
1165 ret = dmaengine_slave_config(atmel_port->chan_rx,
1168 dev_err(port->dev, "DMA rx slave configuration failed\n");
1172 * Prepare a cyclic dma transfer, assign 2 descriptors,
1173 * each one is half ring buffer size
1175 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1176 sg_dma_address(&atmel_port->sg_rx),
1177 sg_dma_len(&atmel_port->sg_rx),
1178 sg_dma_len(&atmel_port->sg_rx)/2,
1180 DMA_PREP_INTERRUPT);
1182 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1185 desc->callback = atmel_complete_rx_dma;
1186 desc->callback_param = port;
1187 atmel_port->desc_rx = desc;
1188 atmel_port->cookie_rx = dmaengine_submit(desc);
1193 dev_err(port->dev, "RX channel not available, switch to pio\n");
1194 atmel_port->use_dma_rx = 0;
1195 if (atmel_port->chan_rx)
1196 atmel_release_rx_dma(port);
1200 static void atmel_uart_timer_callback(unsigned long data)
1202 struct uart_port *port = (void *)data;
1203 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1205 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1206 tasklet_schedule(&atmel_port->tasklet_rx);
1207 mod_timer(&atmel_port->uart_timer,
1208 jiffies + uart_poll_timeout(port));
1213 * receive interrupt handler.
1216 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1218 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1220 if (atmel_use_pdc_rx(port)) {
1222 * PDC receive. Just schedule the tasklet and let it
1223 * figure out the details.
1225 * TODO: We're not handling error flags correctly at
1228 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1229 atmel_uart_writel(port, ATMEL_US_IDR,
1230 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1231 atmel_tasklet_schedule(atmel_port,
1232 &atmel_port->tasklet_rx);
1235 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1236 ATMEL_US_FRAME | ATMEL_US_PARE))
1237 atmel_pdc_rxerr(port, pending);
1240 if (atmel_use_dma_rx(port)) {
1241 if (pending & ATMEL_US_TIMEOUT) {
1242 atmel_uart_writel(port, ATMEL_US_IDR,
1244 atmel_tasklet_schedule(atmel_port,
1245 &atmel_port->tasklet_rx);
1249 /* Interrupt receive */
1250 if (pending & ATMEL_US_RXRDY)
1251 atmel_rx_chars(port);
1252 else if (pending & ATMEL_US_RXBRK) {
1254 * End of break detected. If it came along with a
1255 * character, atmel_rx_chars will handle it.
1257 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1258 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1259 atmel_port->break_active = 0;
1264 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1267 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1269 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1271 if (pending & atmel_port->tx_done_mask) {
1272 atmel_uart_writel(port, ATMEL_US_IDR,
1273 atmel_port->tx_done_mask);
1275 /* Start RX if flag was set and FIFO is empty */
1276 if (atmel_port->hd_start_rx) {
1277 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1278 & ATMEL_US_TXEMPTY))
1279 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1281 atmel_port->hd_start_rx = false;
1282 atmel_start_rx(port);
1285 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1290 * status flags interrupt handler.
1293 atmel_handle_status(struct uart_port *port, unsigned int pending,
1294 unsigned int status)
1296 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1297 unsigned int status_change;
1299 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1300 | ATMEL_US_CTSIC)) {
1301 status_change = status ^ atmel_port->irq_status_prev;
1302 atmel_port->irq_status_prev = status;
1304 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1305 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1306 /* TODO: All reads to CSR will clear these interrupts! */
1307 if (status_change & ATMEL_US_RI)
1309 if (status_change & ATMEL_US_DSR)
1311 if (status_change & ATMEL_US_DCD)
1312 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1313 if (status_change & ATMEL_US_CTS)
1314 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1316 wake_up_interruptible(&port->state->port.delta_msr_wait);
1324 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1326 struct uart_port *port = dev_id;
1327 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1328 unsigned int status, pending, mask, pass_counter = 0;
1330 spin_lock(&atmel_port->lock_suspended);
1333 status = atmel_get_lines_status(port);
1334 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1335 pending = status & mask;
1339 if (atmel_port->suspended) {
1340 atmel_port->pending |= pending;
1341 atmel_port->pending_status = status;
1342 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1347 atmel_handle_receive(port, pending);
1348 atmel_handle_status(port, pending, status);
1349 atmel_handle_transmit(port, pending);
1350 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1352 spin_unlock(&atmel_port->lock_suspended);
1354 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1357 static void atmel_release_tx_pdc(struct uart_port *port)
1359 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1360 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1362 dma_unmap_single(port->dev,
1369 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1371 static void atmel_tx_pdc(struct uart_port *port)
1373 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1374 struct circ_buf *xmit = &port->state->xmit;
1375 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1378 /* nothing left to transmit? */
1379 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1382 xmit->tail += pdc->ofs;
1383 xmit->tail &= UART_XMIT_SIZE - 1;
1385 port->icount.tx += pdc->ofs;
1388 /* more to transmit - setup next transfer */
1390 /* disable PDC transmit */
1391 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1393 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1394 dma_sync_single_for_device(port->dev,
1399 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1402 atmel_uart_writel(port, ATMEL_PDC_TPR,
1403 pdc->dma_addr + xmit->tail);
1404 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1405 /* re-enable PDC transmit */
1406 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1407 /* Enable interrupts */
1408 atmel_uart_writel(port, ATMEL_US_IER,
1409 atmel_port->tx_done_mask);
1411 if (atmel_uart_is_half_duplex(port)) {
1412 /* DMA done, stop TX, start RX for RS485 */
1413 atmel_start_rx(port);
1417 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1418 uart_write_wakeup(port);
1421 static int atmel_prepare_tx_pdc(struct uart_port *port)
1423 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1424 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1425 struct circ_buf *xmit = &port->state->xmit;
1427 pdc->buf = xmit->buf;
1428 pdc->dma_addr = dma_map_single(port->dev,
1432 pdc->dma_size = UART_XMIT_SIZE;
1438 static void atmel_rx_from_ring(struct uart_port *port)
1440 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1441 struct circ_buf *ring = &atmel_port->rx_ring;
1443 unsigned int status;
1445 while (ring->head != ring->tail) {
1446 struct atmel_uart_char c;
1448 /* Make sure c is loaded after head. */
1451 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1453 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1460 * note that the error handling code is
1461 * out of the main execution path
1463 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1464 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1465 if (status & ATMEL_US_RXBRK) {
1466 /* ignore side-effect */
1467 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1470 if (uart_handle_break(port))
1473 if (status & ATMEL_US_PARE)
1474 port->icount.parity++;
1475 if (status & ATMEL_US_FRAME)
1476 port->icount.frame++;
1477 if (status & ATMEL_US_OVRE)
1478 port->icount.overrun++;
1480 status &= port->read_status_mask;
1482 if (status & ATMEL_US_RXBRK)
1484 else if (status & ATMEL_US_PARE)
1486 else if (status & ATMEL_US_FRAME)
1491 if (uart_handle_sysrq_char(port, c.ch))
1494 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1498 * Drop the lock here since it might end up calling
1499 * uart_start(), which takes the lock.
1501 spin_unlock(&port->lock);
1502 tty_flip_buffer_push(&port->state->port);
1503 spin_lock(&port->lock);
1506 static void atmel_release_rx_pdc(struct uart_port *port)
1508 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1511 for (i = 0; i < 2; i++) {
1512 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1514 dma_unmap_single(port->dev,
1522 static void atmel_rx_from_pdc(struct uart_port *port)
1524 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1525 struct tty_port *tport = &port->state->port;
1526 struct atmel_dma_buffer *pdc;
1527 int rx_idx = atmel_port->pdc_rx_idx;
1533 /* Reset the UART timeout early so that we don't miss one */
1534 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1536 pdc = &atmel_port->pdc_rx[rx_idx];
1537 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1540 /* If the PDC has switched buffers, RPR won't contain
1541 * any address within the current buffer. Since head
1542 * is unsigned, we just need a one-way comparison to
1545 * In this case, we just need to consume the entire
1546 * buffer and resubmit it for DMA. This will clear the
1547 * ENDRX bit as well, so that we can safely re-enable
1548 * all interrupts below.
1550 head = min(head, pdc->dma_size);
1552 if (likely(head != tail)) {
1553 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1554 pdc->dma_size, DMA_FROM_DEVICE);
1557 * head will only wrap around when we recycle
1558 * the DMA buffer, and when that happens, we
1559 * explicitly set tail to 0. So head will
1560 * always be greater than tail.
1562 count = head - tail;
1564 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1567 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1568 pdc->dma_size, DMA_FROM_DEVICE);
1570 port->icount.rx += count;
1575 * If the current buffer is full, we need to check if
1576 * the next one contains any additional data.
1578 if (head >= pdc->dma_size) {
1580 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1581 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1584 atmel_port->pdc_rx_idx = rx_idx;
1586 } while (head >= pdc->dma_size);
1589 * Drop the lock here since it might end up calling
1590 * uart_start(), which takes the lock.
1592 spin_unlock(&port->lock);
1593 tty_flip_buffer_push(tport);
1594 spin_lock(&port->lock);
1596 atmel_uart_writel(port, ATMEL_US_IER,
1597 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1600 static int atmel_prepare_rx_pdc(struct uart_port *port)
1602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1605 for (i = 0; i < 2; i++) {
1606 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1608 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1609 if (pdc->buf == NULL) {
1611 dma_unmap_single(port->dev,
1612 atmel_port->pdc_rx[0].dma_addr,
1615 kfree(atmel_port->pdc_rx[0].buf);
1617 atmel_port->use_pdc_rx = 0;
1620 pdc->dma_addr = dma_map_single(port->dev,
1624 pdc->dma_size = PDC_BUFFER_SIZE;
1628 atmel_port->pdc_rx_idx = 0;
1630 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1631 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1633 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1634 atmel_port->pdc_rx[1].dma_addr);
1635 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1641 * tasklet handling tty stuff outside the interrupt handler.
1643 static void atmel_tasklet_rx_func(unsigned long data)
1645 struct uart_port *port = (struct uart_port *)data;
1646 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1648 /* The interrupt handler does not take the lock */
1649 spin_lock(&port->lock);
1650 atmel_port->schedule_rx(port);
1651 spin_unlock(&port->lock);
1654 static void atmel_tasklet_tx_func(unsigned long data)
1656 struct uart_port *port = (struct uart_port *)data;
1657 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1659 /* The interrupt handler does not take the lock */
1660 spin_lock(&port->lock);
1661 atmel_port->schedule_tx(port);
1662 spin_unlock(&port->lock);
1665 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1666 struct platform_device *pdev)
1668 struct device_node *np = pdev->dev.of_node;
1669 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1672 /* DMA/PDC usage specification */
1673 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1674 if (of_property_read_bool(np, "dmas")) {
1675 atmel_port->use_dma_rx = true;
1676 atmel_port->use_pdc_rx = false;
1678 atmel_port->use_dma_rx = false;
1679 atmel_port->use_pdc_rx = true;
1682 atmel_port->use_dma_rx = false;
1683 atmel_port->use_pdc_rx = false;
1686 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1687 if (of_property_read_bool(np, "dmas")) {
1688 atmel_port->use_dma_tx = true;
1689 atmel_port->use_pdc_tx = false;
1691 atmel_port->use_dma_tx = false;
1692 atmel_port->use_pdc_tx = true;
1695 atmel_port->use_dma_tx = false;
1696 atmel_port->use_pdc_tx = false;
1700 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1701 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1702 atmel_port->use_dma_rx = false;
1703 atmel_port->use_dma_tx = false;
1708 static void atmel_init_rs485(struct uart_port *port,
1709 struct platform_device *pdev)
1711 struct device_node *np = pdev->dev.of_node;
1712 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1715 struct serial_rs485 *rs485conf = &port->rs485;
1717 /* rs485 properties */
1718 if (of_property_read_u32_array(np, "rs485-rts-delay",
1719 rs485_delay, 2) == 0) {
1720 rs485conf->delay_rts_before_send = rs485_delay[0];
1721 rs485conf->delay_rts_after_send = rs485_delay[1];
1722 rs485conf->flags = 0;
1725 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1726 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1728 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1730 rs485conf->flags |= SER_RS485_ENABLED;
1732 port->rs485 = pdata->rs485;
1737 static void atmel_set_ops(struct uart_port *port)
1739 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1741 if (atmel_use_dma_rx(port)) {
1742 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1743 atmel_port->schedule_rx = &atmel_rx_from_dma;
1744 atmel_port->release_rx = &atmel_release_rx_dma;
1745 } else if (atmel_use_pdc_rx(port)) {
1746 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1747 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1748 atmel_port->release_rx = &atmel_release_rx_pdc;
1750 atmel_port->prepare_rx = NULL;
1751 atmel_port->schedule_rx = &atmel_rx_from_ring;
1752 atmel_port->release_rx = NULL;
1755 if (atmel_use_dma_tx(port)) {
1756 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1757 atmel_port->schedule_tx = &atmel_tx_dma;
1758 atmel_port->release_tx = &atmel_release_tx_dma;
1759 } else if (atmel_use_pdc_tx(port)) {
1760 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1761 atmel_port->schedule_tx = &atmel_tx_pdc;
1762 atmel_port->release_tx = &atmel_release_tx_pdc;
1764 atmel_port->prepare_tx = NULL;
1765 atmel_port->schedule_tx = &atmel_tx_chars;
1766 atmel_port->release_tx = NULL;
1771 * Get ip name usart or uart
1773 static void atmel_get_ip_name(struct uart_port *port)
1775 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1776 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1778 u32 usart, dbgu_uart, new_uart;
1779 /* ASCII decoding for IP version */
1780 usart = 0x55534152; /* USAR(T) */
1781 dbgu_uart = 0x44424755; /* DBGU */
1782 new_uart = 0x55415254; /* UART */
1785 * Only USART devices from at91sam9260 SOC implement fractional
1788 atmel_port->has_frac_baudrate = false;
1789 atmel_port->has_hw_timer = false;
1791 if (name == new_uart) {
1792 dev_dbg(port->dev, "Uart with hw timer");
1793 atmel_port->has_hw_timer = true;
1794 atmel_port->rtor = ATMEL_UA_RTOR;
1795 } else if (name == usart) {
1796 dev_dbg(port->dev, "Usart\n");
1797 atmel_port->has_frac_baudrate = true;
1798 atmel_port->has_hw_timer = true;
1799 atmel_port->rtor = ATMEL_US_RTOR;
1800 } else if (name == dbgu_uart) {
1801 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1803 /* fallback for older SoCs: use version field */
1804 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1809 dev_dbg(port->dev, "This version is usart\n");
1810 atmel_port->has_frac_baudrate = true;
1811 atmel_port->has_hw_timer = true;
1812 atmel_port->rtor = ATMEL_US_RTOR;
1816 dev_dbg(port->dev, "This version is uart\n");
1819 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1825 * Perform initialization and enable port for reception
1827 static int atmel_startup(struct uart_port *port)
1829 struct platform_device *pdev = to_platform_device(port->dev);
1830 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1834 * Ensure that no interrupts are enabled otherwise when
1835 * request_irq() is called we could get stuck trying to
1836 * handle an unexpected interrupt
1838 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1839 atmel_port->ms_irq_enabled = false;
1844 retval = request_irq(port->irq, atmel_interrupt,
1845 IRQF_SHARED | IRQF_COND_SUSPEND,
1846 dev_name(&pdev->dev), port);
1848 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1852 atomic_set(&atmel_port->tasklet_shutdown, 0);
1853 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1854 (unsigned long)port);
1855 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1856 (unsigned long)port);
1859 * Initialize DMA (if necessary)
1861 atmel_init_property(atmel_port, pdev);
1862 atmel_set_ops(port);
1864 if (atmel_port->prepare_rx) {
1865 retval = atmel_port->prepare_rx(port);
1867 atmel_set_ops(port);
1870 if (atmel_port->prepare_tx) {
1871 retval = atmel_port->prepare_tx(port);
1873 atmel_set_ops(port);
1877 * Enable FIFO when available
1879 if (atmel_port->fifo_size) {
1880 unsigned int txrdym = ATMEL_US_ONE_DATA;
1881 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1884 atmel_uart_writel(port, ATMEL_US_CR,
1889 if (atmel_use_dma_tx(port))
1890 txrdym = ATMEL_US_FOUR_DATA;
1892 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1893 if (atmel_port->rts_high &&
1894 atmel_port->rts_low)
1895 fmr |= ATMEL_US_FRTSC |
1896 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1897 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1899 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1902 /* Save current CSR for comparison in atmel_tasklet_func() */
1903 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1906 * Finally, enable the serial port
1908 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1909 /* enable xmit & rcvr */
1910 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1912 setup_timer(&atmel_port->uart_timer,
1913 atmel_uart_timer_callback,
1914 (unsigned long)port);
1916 if (atmel_use_pdc_rx(port)) {
1917 /* set UART timeout */
1918 if (!atmel_port->has_hw_timer) {
1919 mod_timer(&atmel_port->uart_timer,
1920 jiffies + uart_poll_timeout(port));
1921 /* set USART timeout */
1923 atmel_uart_writel(port, atmel_port->rtor,
1925 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1927 atmel_uart_writel(port, ATMEL_US_IER,
1928 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1930 /* enable PDC controller */
1931 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1932 } else if (atmel_use_dma_rx(port)) {
1933 /* set UART timeout */
1934 if (!atmel_port->has_hw_timer) {
1935 mod_timer(&atmel_port->uart_timer,
1936 jiffies + uart_poll_timeout(port));
1937 /* set USART timeout */
1939 atmel_uart_writel(port, atmel_port->rtor,
1941 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1943 atmel_uart_writel(port, ATMEL_US_IER,
1947 /* enable receive only */
1948 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1955 * Flush any TX data submitted for DMA. Called when the TX circular
1958 static void atmel_flush_buffer(struct uart_port *port)
1960 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1962 if (atmel_use_pdc_tx(port)) {
1963 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1964 atmel_port->pdc_tx.ofs = 0;
1967 * in uart_flush_buffer(), the xmit circular buffer has just
1968 * been cleared, so we have to reset tx_len accordingly.
1970 atmel_port->tx_len = 0;
1976 static void atmel_shutdown(struct uart_port *port)
1978 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1980 /* Disable modem control lines interrupts */
1981 atmel_disable_ms(port);
1983 /* Disable interrupts at device level */
1984 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1986 /* Prevent spurious interrupts from scheduling the tasklet */
1987 atomic_inc(&atmel_port->tasklet_shutdown);
1990 * Prevent any tasklets being scheduled during
1993 del_timer_sync(&atmel_port->uart_timer);
1995 /* Make sure that no interrupt is on the fly */
1996 synchronize_irq(port->irq);
1999 * Clear out any scheduled tasklets before
2000 * we destroy the buffers
2002 tasklet_kill(&atmel_port->tasklet_rx);
2003 tasklet_kill(&atmel_port->tasklet_tx);
2006 * Ensure everything is stopped and
2007 * disable port and break condition.
2009 atmel_stop_rx(port);
2010 atmel_stop_tx(port);
2012 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2015 * Shut-down the DMA.
2017 if (atmel_port->release_rx)
2018 atmel_port->release_rx(port);
2019 if (atmel_port->release_tx)
2020 atmel_port->release_tx(port);
2023 * Reset ring buffer pointers
2025 atmel_port->rx_ring.head = 0;
2026 atmel_port->rx_ring.tail = 0;
2029 * Free the interrupts
2031 free_irq(port->irq, port);
2033 atmel_flush_buffer(port);
2037 * Power / Clock management.
2039 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2040 unsigned int oldstate)
2042 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2047 * Enable the peripheral clock for this serial port.
2048 * This is called on uart_open() or a resume event.
2050 clk_prepare_enable(atmel_port->clk);
2052 /* re-enable interrupts if we disabled some on suspend */
2053 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2056 /* Back up the interrupt mask and disable all interrupts */
2057 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2058 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2061 * Disable the peripheral clock for this serial port.
2062 * This is called on uart_close() or a suspend event.
2064 clk_disable_unprepare(atmel_port->clk);
2067 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2072 * Change the port parameters
2074 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2075 struct ktermios *old)
2077 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2078 unsigned long flags;
2079 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2081 /* save the current mode register */
2082 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2084 /* reset the mode, clock divisor, parity, stop bits and data size */
2085 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2086 ATMEL_US_PAR | ATMEL_US_USMODE);
2088 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2091 switch (termios->c_cflag & CSIZE) {
2093 mode |= ATMEL_US_CHRL_5;
2096 mode |= ATMEL_US_CHRL_6;
2099 mode |= ATMEL_US_CHRL_7;
2102 mode |= ATMEL_US_CHRL_8;
2107 if (termios->c_cflag & CSTOPB)
2108 mode |= ATMEL_US_NBSTOP_2;
2111 if (termios->c_cflag & PARENB) {
2112 /* Mark or Space parity */
2113 if (termios->c_cflag & CMSPAR) {
2114 if (termios->c_cflag & PARODD)
2115 mode |= ATMEL_US_PAR_MARK;
2117 mode |= ATMEL_US_PAR_SPACE;
2118 } else if (termios->c_cflag & PARODD)
2119 mode |= ATMEL_US_PAR_ODD;
2121 mode |= ATMEL_US_PAR_EVEN;
2123 mode |= ATMEL_US_PAR_NONE;
2125 spin_lock_irqsave(&port->lock, flags);
2127 port->read_status_mask = ATMEL_US_OVRE;
2128 if (termios->c_iflag & INPCK)
2129 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2130 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2131 port->read_status_mask |= ATMEL_US_RXBRK;
2133 if (atmel_use_pdc_rx(port))
2134 /* need to enable error interrupts */
2135 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2138 * Characters to ignore
2140 port->ignore_status_mask = 0;
2141 if (termios->c_iflag & IGNPAR)
2142 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2143 if (termios->c_iflag & IGNBRK) {
2144 port->ignore_status_mask |= ATMEL_US_RXBRK;
2146 * If we're ignoring parity and break indicators,
2147 * ignore overruns too (for real raw support).
2149 if (termios->c_iflag & IGNPAR)
2150 port->ignore_status_mask |= ATMEL_US_OVRE;
2152 /* TODO: Ignore all characters if CREAD is set.*/
2154 /* update the per-port timeout */
2155 uart_update_timeout(port, termios->c_cflag, baud);
2158 * save/disable interrupts. The tty layer will ensure that the
2159 * transmitter is empty if requested by the caller, so there's
2160 * no need to wait for it here.
2162 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2163 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2165 /* disable receiver and transmitter */
2166 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2169 if (port->rs485.flags & SER_RS485_ENABLED) {
2170 atmel_uart_writel(port, ATMEL_US_TTGR,
2171 port->rs485.delay_rts_after_send);
2172 mode |= ATMEL_US_USMODE_RS485;
2173 } else if (termios->c_cflag & CRTSCTS) {
2174 /* RS232 with hardware handshake (RTS/CTS) */
2175 if (atmel_use_fifo(port) &&
2176 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2178 * with ATMEL_US_USMODE_HWHS set, the controller will
2179 * be able to drive the RTS pin high/low when the RX
2180 * FIFO is above RXFTHRES/below RXFTHRES2.
2181 * It will also disable the transmitter when the CTS
2183 * This mode is not activated if CTS pin is a GPIO
2184 * because in this case, the transmitter is always
2185 * disabled (there must be an internal pull-up
2186 * responsible for this behaviour).
2187 * If the RTS pin is a GPIO, the controller won't be
2188 * able to drive it according to the FIFO thresholds,
2189 * but it will be handled by the driver.
2191 mode |= ATMEL_US_USMODE_HWHS;
2194 * For platforms without FIFO, the flow control is
2195 * handled by the driver.
2197 mode |= ATMEL_US_USMODE_NORMAL;
2200 /* RS232 without hadware handshake */
2201 mode |= ATMEL_US_USMODE_NORMAL;
2205 * Set the baud rate:
2206 * Fractional baudrate allows to setup output frequency more
2207 * accurately. This feature is enabled only when using normal mode.
2208 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2209 * Currently, OVER is always set to 0 so we get
2210 * baudrate = selected clock / (16 * (CD + FP / 8))
2212 * 8 CD + FP = selected clock / (2 * baudrate)
2214 if (atmel_port->has_frac_baudrate &&
2215 (mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_NORMAL) {
2216 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2218 fp = div & ATMEL_US_FP_MASK;
2220 cd = uart_get_divisor(port, baud);
2223 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2225 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2227 quot = cd | fp << ATMEL_US_FP_OFFSET;
2229 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2231 /* set the mode, clock divisor, parity, stop bits and data size */
2232 atmel_uart_writel(port, ATMEL_US_MR, mode);
2235 * when switching the mode, set the RTS line state according to the
2236 * new mode, otherwise keep the former state
2238 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2239 unsigned int rts_state;
2241 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2242 /* let the hardware control the RTS line */
2243 rts_state = ATMEL_US_RTSDIS;
2245 /* force RTS line to low level */
2246 rts_state = ATMEL_US_RTSEN;
2249 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2252 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2253 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2255 /* restore interrupts */
2256 atmel_uart_writel(port, ATMEL_US_IER, imr);
2258 /* CTS flow-control and modem-status interrupts */
2259 if (UART_ENABLE_MS(port, termios->c_cflag))
2260 atmel_enable_ms(port);
2262 atmel_disable_ms(port);
2264 spin_unlock_irqrestore(&port->lock, flags);
2267 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2269 if (termios->c_line == N_PPS) {
2270 port->flags |= UPF_HARDPPS_CD;
2271 spin_lock_irq(&port->lock);
2272 atmel_enable_ms(port);
2273 spin_unlock_irq(&port->lock);
2275 port->flags &= ~UPF_HARDPPS_CD;
2276 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2277 spin_lock_irq(&port->lock);
2278 atmel_disable_ms(port);
2279 spin_unlock_irq(&port->lock);
2285 * Return string describing the specified port
2287 static const char *atmel_type(struct uart_port *port)
2289 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2293 * Release the memory region(s) being used by 'port'.
2295 static void atmel_release_port(struct uart_port *port)
2297 struct platform_device *pdev = to_platform_device(port->dev);
2298 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2300 release_mem_region(port->mapbase, size);
2302 if (port->flags & UPF_IOREMAP) {
2303 iounmap(port->membase);
2304 port->membase = NULL;
2309 * Request the memory region(s) being used by 'port'.
2311 static int atmel_request_port(struct uart_port *port)
2313 struct platform_device *pdev = to_platform_device(port->dev);
2314 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2316 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2319 if (port->flags & UPF_IOREMAP) {
2320 port->membase = ioremap(port->mapbase, size);
2321 if (port->membase == NULL) {
2322 release_mem_region(port->mapbase, size);
2331 * Configure/autoconfigure the port.
2333 static void atmel_config_port(struct uart_port *port, int flags)
2335 if (flags & UART_CONFIG_TYPE) {
2336 port->type = PORT_ATMEL;
2337 atmel_request_port(port);
2342 * Verify the new serial_struct (for TIOCSSERIAL).
2344 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2347 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2349 if (port->irq != ser->irq)
2351 if (ser->io_type != SERIAL_IO_MEM)
2353 if (port->uartclk / 16 != ser->baud_base)
2355 if (port->mapbase != (unsigned long)ser->iomem_base)
2357 if (port->iobase != ser->port)
2364 #ifdef CONFIG_CONSOLE_POLL
2365 static int atmel_poll_get_char(struct uart_port *port)
2367 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2370 return atmel_uart_read_char(port);
2373 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2375 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2378 atmel_uart_write_char(port, ch);
2382 static const struct uart_ops atmel_pops = {
2383 .tx_empty = atmel_tx_empty,
2384 .set_mctrl = atmel_set_mctrl,
2385 .get_mctrl = atmel_get_mctrl,
2386 .stop_tx = atmel_stop_tx,
2387 .start_tx = atmel_start_tx,
2388 .stop_rx = atmel_stop_rx,
2389 .enable_ms = atmel_enable_ms,
2390 .break_ctl = atmel_break_ctl,
2391 .startup = atmel_startup,
2392 .shutdown = atmel_shutdown,
2393 .flush_buffer = atmel_flush_buffer,
2394 .set_termios = atmel_set_termios,
2395 .set_ldisc = atmel_set_ldisc,
2397 .release_port = atmel_release_port,
2398 .request_port = atmel_request_port,
2399 .config_port = atmel_config_port,
2400 .verify_port = atmel_verify_port,
2401 .pm = atmel_serial_pm,
2402 #ifdef CONFIG_CONSOLE_POLL
2403 .poll_get_char = atmel_poll_get_char,
2404 .poll_put_char = atmel_poll_put_char,
2409 * Configure the port from the platform device resource info.
2411 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2412 struct platform_device *pdev)
2415 struct uart_port *port = &atmel_port->uart;
2416 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2418 atmel_init_property(atmel_port, pdev);
2419 atmel_set_ops(port);
2421 atmel_init_rs485(port, pdev);
2423 port->iotype = UPIO_MEM;
2424 port->flags = UPF_BOOT_AUTOCONF;
2425 port->ops = &atmel_pops;
2427 port->dev = &pdev->dev;
2428 port->mapbase = pdev->resource[0].start;
2429 port->irq = pdev->resource[1].start;
2430 port->rs485_config = atmel_config_rs485;
2432 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2434 if (pdata && pdata->regs) {
2435 /* Already mapped by setup code */
2436 port->membase = pdata->regs;
2438 port->flags |= UPF_IOREMAP;
2439 port->membase = NULL;
2442 /* for console, the clock could already be configured */
2443 if (!atmel_port->clk) {
2444 atmel_port->clk = clk_get(&pdev->dev, "usart");
2445 if (IS_ERR(atmel_port->clk)) {
2446 ret = PTR_ERR(atmel_port->clk);
2447 atmel_port->clk = NULL;
2450 ret = clk_prepare_enable(atmel_port->clk);
2452 clk_put(atmel_port->clk);
2453 atmel_port->clk = NULL;
2456 port->uartclk = clk_get_rate(atmel_port->clk);
2457 clk_disable_unprepare(atmel_port->clk);
2458 /* only enable clock when USART is in use */
2461 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2462 if (port->rs485.flags & SER_RS485_ENABLED)
2463 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2464 else if (atmel_use_pdc_tx(port)) {
2465 port->fifosize = PDC_BUFFER_SIZE;
2466 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2468 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2474 struct platform_device *atmel_default_console_device; /* the serial console device */
2476 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2477 static void atmel_console_putchar(struct uart_port *port, int ch)
2479 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2481 atmel_uart_write_char(port, ch);
2485 * Interrupts are disabled on entering
2487 static void atmel_console_write(struct console *co, const char *s, u_int count)
2489 struct uart_port *port = &atmel_ports[co->index].uart;
2490 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2491 unsigned int status, imr;
2492 unsigned int pdc_tx;
2495 * First, save IMR and then disable interrupts
2497 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2498 atmel_uart_writel(port, ATMEL_US_IDR,
2499 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2501 /* Store PDC transmit status and disable it */
2502 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2503 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2505 /* Make sure that tx path is actually able to send characters */
2506 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2508 uart_console_write(port, s, count, atmel_console_putchar);
2511 * Finally, wait for transmitter to become empty
2515 status = atmel_uart_readl(port, ATMEL_US_CSR);
2516 } while (!(status & ATMEL_US_TXRDY));
2518 /* Restore PDC transmit status */
2520 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2522 /* set interrupts back the way they were */
2523 atmel_uart_writel(port, ATMEL_US_IER, imr);
2527 * If the port was already initialised (eg, by a boot loader),
2528 * try to determine the current setup.
2530 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2531 int *parity, int *bits)
2533 unsigned int mr, quot;
2536 * If the baud rate generator isn't running, the port wasn't
2537 * initialized by the boot loader.
2539 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2543 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2544 if (mr == ATMEL_US_CHRL_8)
2549 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2550 if (mr == ATMEL_US_PAR_EVEN)
2552 else if (mr == ATMEL_US_PAR_ODD)
2556 * The serial core only rounds down when matching this to a
2557 * supported baud rate. Make sure we don't end up slightly
2558 * lower than one of those, as it would make us fall through
2559 * to a much lower baud rate than we really want.
2561 *baud = port->uartclk / (16 * (quot - 1));
2564 static int __init atmel_console_setup(struct console *co, char *options)
2567 struct uart_port *port = &atmel_ports[co->index].uart;
2573 if (port->membase == NULL) {
2574 /* Port not initialized yet - delay setup */
2578 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2582 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2583 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2584 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2587 uart_parse_options(options, &baud, &parity, &bits, &flow);
2589 atmel_console_get_options(port, &baud, &parity, &bits);
2591 return uart_set_options(port, co, baud, parity, bits, flow);
2594 static struct uart_driver atmel_uart;
2596 static struct console atmel_console = {
2597 .name = ATMEL_DEVICENAME,
2598 .write = atmel_console_write,
2599 .device = uart_console_device,
2600 .setup = atmel_console_setup,
2601 .flags = CON_PRINTBUFFER,
2603 .data = &atmel_uart,
2606 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2609 * Early console initialization (before VM subsystem initialized).
2611 static int __init atmel_console_init(void)
2614 if (atmel_default_console_device) {
2615 struct atmel_uart_data *pdata =
2616 dev_get_platdata(&atmel_default_console_device->dev);
2617 int id = pdata->num;
2618 struct atmel_uart_port *atmel_port = &atmel_ports[id];
2620 atmel_port->backup_imr = 0;
2621 atmel_port->uart.line = id;
2623 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2624 ret = atmel_init_port(atmel_port, atmel_default_console_device);
2627 register_console(&atmel_console);
2633 console_initcall(atmel_console_init);
2636 * Late console initialization.
2638 static int __init atmel_late_console_init(void)
2640 if (atmel_default_console_device
2641 && !(atmel_console.flags & CON_ENABLED))
2642 register_console(&atmel_console);
2647 core_initcall(atmel_late_console_init);
2649 static inline bool atmel_is_console_port(struct uart_port *port)
2651 return port->cons && port->cons->index == port->line;
2655 #define ATMEL_CONSOLE_DEVICE NULL
2657 static inline bool atmel_is_console_port(struct uart_port *port)
2663 static struct uart_driver atmel_uart = {
2664 .owner = THIS_MODULE,
2665 .driver_name = "atmel_serial",
2666 .dev_name = ATMEL_DEVICENAME,
2667 .major = SERIAL_ATMEL_MAJOR,
2668 .minor = MINOR_START,
2669 .nr = ATMEL_MAX_UART,
2670 .cons = ATMEL_CONSOLE_DEVICE,
2674 static bool atmel_serial_clk_will_stop(void)
2676 #ifdef CONFIG_ARCH_AT91
2677 return at91_suspend_entering_slow_clock();
2683 static int atmel_serial_suspend(struct platform_device *pdev,
2686 struct uart_port *port = platform_get_drvdata(pdev);
2687 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2689 if (atmel_is_console_port(port) && console_suspend_enabled) {
2690 /* Drain the TX shifter */
2691 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2696 /* we can not wake up if we're running on slow clock */
2697 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2698 if (atmel_serial_clk_will_stop()) {
2699 unsigned long flags;
2701 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2702 atmel_port->suspended = true;
2703 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2704 device_set_wakeup_enable(&pdev->dev, 0);
2707 uart_suspend_port(&atmel_uart, port);
2712 static int atmel_serial_resume(struct platform_device *pdev)
2714 struct uart_port *port = platform_get_drvdata(pdev);
2715 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2716 unsigned long flags;
2718 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2719 if (atmel_port->pending) {
2720 atmel_handle_receive(port, atmel_port->pending);
2721 atmel_handle_status(port, atmel_port->pending,
2722 atmel_port->pending_status);
2723 atmel_handle_transmit(port, atmel_port->pending);
2724 atmel_port->pending = 0;
2726 atmel_port->suspended = false;
2727 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2729 uart_resume_port(&atmel_uart, port);
2730 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2735 #define atmel_serial_suspend NULL
2736 #define atmel_serial_resume NULL
2739 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2740 struct platform_device *pdev)
2742 atmel_port->fifo_size = 0;
2743 atmel_port->rts_low = 0;
2744 atmel_port->rts_high = 0;
2746 if (of_property_read_u32(pdev->dev.of_node,
2748 &atmel_port->fifo_size))
2751 if (!atmel_port->fifo_size)
2754 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2755 atmel_port->fifo_size = 0;
2756 dev_err(&pdev->dev, "Invalid FIFO size\n");
2761 * 0 <= rts_low <= rts_high <= fifo_size
2762 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2763 * to flush their internal TX FIFO, commonly up to 16 data, before
2764 * actually stopping to send new data. So we try to set the RTS High
2765 * Threshold to a reasonably high value respecting this 16 data
2766 * empirical rule when possible.
2768 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2769 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2770 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2771 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2773 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2774 atmel_port->fifo_size);
2775 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2776 atmel_port->rts_high);
2777 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2778 atmel_port->rts_low);
2781 static int atmel_serial_probe(struct platform_device *pdev)
2783 struct atmel_uart_port *atmel_port;
2784 struct device_node *np = pdev->dev.of_node;
2785 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2790 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2793 ret = of_alias_get_id(np, "serial");
2799 /* port id not found in platform data nor device-tree aliases:
2800 * auto-enumerate it */
2801 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2803 if (ret >= ATMEL_MAX_UART) {
2808 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2809 /* port already in use */
2814 atmel_port = &atmel_ports[ret];
2815 atmel_port->backup_imr = 0;
2816 atmel_port->uart.line = ret;
2817 atmel_serial_probe_fifos(atmel_port, pdev);
2819 atomic_set(&atmel_port->tasklet_shutdown, 0);
2820 spin_lock_init(&atmel_port->lock_suspended);
2822 ret = atmel_init_port(atmel_port, pdev);
2826 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2827 if (IS_ERR(atmel_port->gpios)) {
2828 ret = PTR_ERR(atmel_port->gpios);
2832 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2834 data = kmalloc(sizeof(struct atmel_uart_char)
2835 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2837 goto err_alloc_ring;
2838 atmel_port->rx_ring.buf = data;
2841 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2843 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2847 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2848 if (atmel_is_console_port(&atmel_port->uart)
2849 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2851 * The serial core enabled the clock for us, so undo
2852 * the clk_prepare_enable() in atmel_console_setup()
2854 clk_disable_unprepare(atmel_port->clk);
2858 device_init_wakeup(&pdev->dev, 1);
2859 platform_set_drvdata(pdev, atmel_port);
2862 * The peripheral clock has been disabled by atmel_init_port():
2863 * enable it before accessing I/O registers
2865 clk_prepare_enable(atmel_port->clk);
2867 if (rs485_enabled) {
2868 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2869 ATMEL_US_USMODE_NORMAL);
2870 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2875 * Get port name of usart or uart
2877 atmel_get_ip_name(&atmel_port->uart);
2880 * The peripheral clock can now safely be disabled till the port
2883 clk_disable_unprepare(atmel_port->clk);
2888 kfree(atmel_port->rx_ring.buf);
2889 atmel_port->rx_ring.buf = NULL;
2891 if (!atmel_is_console_port(&atmel_port->uart)) {
2892 clk_put(atmel_port->clk);
2893 atmel_port->clk = NULL;
2896 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2902 * Even if the driver is not modular, it makes sense to be able to
2903 * unbind a device: there can be many bound devices, and there are
2904 * situations where dynamic binding and unbinding can be useful.
2906 * For example, a connected device can require a specific firmware update
2907 * protocol that needs bitbanging on IO lines, but use the regular serial
2908 * port in the normal case.
2910 static int atmel_serial_remove(struct platform_device *pdev)
2912 struct uart_port *port = platform_get_drvdata(pdev);
2913 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2916 tasklet_kill(&atmel_port->tasklet_rx);
2917 tasklet_kill(&atmel_port->tasklet_tx);
2919 device_init_wakeup(&pdev->dev, 0);
2921 ret = uart_remove_one_port(&atmel_uart, port);
2923 kfree(atmel_port->rx_ring.buf);
2925 /* "port" is allocated statically, so we shouldn't free it */
2927 clear_bit(port->line, atmel_ports_in_use);
2929 clk_put(atmel_port->clk);
2930 atmel_port->clk = NULL;
2935 static struct platform_driver atmel_serial_driver = {
2936 .probe = atmel_serial_probe,
2937 .remove = atmel_serial_remove,
2938 .suspend = atmel_serial_suspend,
2939 .resume = atmel_serial_resume,
2941 .name = "atmel_usart",
2942 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2946 static int __init atmel_serial_init(void)
2950 ret = uart_register_driver(&atmel_uart);
2954 ret = platform_driver_register(&atmel_serial_driver);
2956 uart_unregister_driver(&atmel_uart);
2960 device_initcall(atmel_serial_init);