1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 * DMA support added by Chip Coldwell.
11 #include <linux/tty.h>
12 #include <linux/ioport.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/serial.h>
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/sysrq.h>
19 #include <linux/tty_flip.h>
20 #include <linux/platform_device.h>
22 #include <linux/of_device.h>
23 #include <linux/of_gpio.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/atmel_pdc.h>
27 #include <linux/uaccess.h>
28 #include <linux/platform_data/atmel.h>
29 #include <linux/timer.h>
30 #include <linux/gpio.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/suspend.h>
38 #include <asm/ioctls.h>
40 #define PDC_BUFFER_SIZE 512
41 /* Revisit: We should calculate this based on the actual port settings */
42 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
44 /* The minium number of data FIFOs should be able to contain */
45 #define ATMEL_MIN_FIFO_SIZE 8
47 * These two offsets are substracted from the RX FIFO size to define the RTS
48 * high and low thresholds
50 #define ATMEL_RTS_HIGH_OFFSET 16
51 #define ATMEL_RTS_LOW_OFFSET 20
53 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
57 #include <linux/serial_core.h>
59 #include "serial_mctrl_gpio.h"
60 #include "atmel_serial.h"
62 static void atmel_start_rx(struct uart_port *port);
63 static void atmel_stop_rx(struct uart_port *port);
65 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
67 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
68 * should coexist with the 8250 driver, such as if we have an external 16C550
70 #define SERIAL_ATMEL_MAJOR 204
71 #define MINOR_START 154
72 #define ATMEL_DEVICENAME "ttyAT"
76 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
77 * name, but it is legally reserved for the 8250 driver. */
78 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
79 #define MINOR_START 64
80 #define ATMEL_DEVICENAME "ttyS"
84 #define ATMEL_ISR_PASS_LIMIT 256
86 struct atmel_dma_buffer {
89 unsigned int dma_size;
93 struct atmel_uart_char {
99 * Be careful, the real size of the ring buffer is
100 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
101 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
104 #define ATMEL_SERIAL_RINGSIZE 1024
107 * at91: 6 USARTs and one DBGU port (SAM9260)
108 * samx7: 3 USARTs and 5 UARTs
110 #define ATMEL_MAX_UART 8
113 * We wrap our port structure around the generic uart_port.
115 struct atmel_uart_port {
116 struct uart_port uart; /* uart */
117 struct clk *clk; /* uart clock */
118 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
119 u32 backup_imr; /* IMR saved during suspend */
120 int break_active; /* break being received */
122 bool use_dma_rx; /* enable DMA receiver */
123 bool use_pdc_rx; /* enable PDC receiver */
124 short pdc_rx_idx; /* current PDC RX buffer */
125 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
127 bool use_dma_tx; /* enable DMA transmitter */
128 bool use_pdc_tx; /* enable PDC transmitter */
129 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
131 spinlock_t lock_tx; /* port lock */
132 spinlock_t lock_rx; /* port lock */
133 struct dma_chan *chan_tx;
134 struct dma_chan *chan_rx;
135 struct dma_async_tx_descriptor *desc_tx;
136 struct dma_async_tx_descriptor *desc_rx;
137 dma_cookie_t cookie_tx;
138 dma_cookie_t cookie_rx;
139 struct scatterlist sg_tx;
140 struct scatterlist sg_rx;
141 struct tasklet_struct tasklet_rx;
142 struct tasklet_struct tasklet_tx;
143 atomic_t tasklet_shutdown;
144 unsigned int irq_status_prev;
147 struct circ_buf rx_ring;
149 struct mctrl_gpios *gpios;
150 unsigned int tx_done_mask;
155 u32 rtor; /* address of receiver timeout register if it exists */
156 bool has_frac_baudrate;
158 struct timer_list uart_timer;
162 unsigned int pending;
163 unsigned int pending_status;
164 spinlock_t lock_suspended;
166 bool hd_start_rx; /* can start RX during half-duplex operation */
181 int (*prepare_rx)(struct uart_port *port);
182 int (*prepare_tx)(struct uart_port *port);
183 void (*schedule_rx)(struct uart_port *port);
184 void (*schedule_tx)(struct uart_port *port);
185 void (*release_rx)(struct uart_port *port);
186 void (*release_tx)(struct uart_port *port);
189 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
190 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
193 static struct console atmel_console;
196 #if defined(CONFIG_OF)
197 static const struct of_device_id atmel_serial_dt_ids[] = {
198 { .compatible = "atmel,at91rm9200-usart" },
199 { .compatible = "atmel,at91sam9260-usart" },
204 static inline struct atmel_uart_port *
205 to_atmel_uart_port(struct uart_port *uart)
207 return container_of(uart, struct atmel_uart_port, uart);
210 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
212 return __raw_readl(port->membase + reg);
215 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
217 __raw_writel(value, port->membase + reg);
220 static inline u8 atmel_uart_read_char(struct uart_port *port)
222 return __raw_readb(port->membase + ATMEL_US_RHR);
225 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
227 __raw_writeb(value, port->membase + ATMEL_US_THR);
230 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
232 return (port->rs485.flags & SER_RS485_ENABLED) &&
233 !(port->rs485.flags & SER_RS485_RX_DURING_TX);
236 #ifdef CONFIG_SERIAL_ATMEL_PDC
237 static bool atmel_use_pdc_rx(struct uart_port *port)
239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
241 return atmel_port->use_pdc_rx;
244 static bool atmel_use_pdc_tx(struct uart_port *port)
246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
248 return atmel_port->use_pdc_tx;
251 static bool atmel_use_pdc_rx(struct uart_port *port)
256 static bool atmel_use_pdc_tx(struct uart_port *port)
262 static bool atmel_use_dma_tx(struct uart_port *port)
264 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
266 return atmel_port->use_dma_tx;
269 static bool atmel_use_dma_rx(struct uart_port *port)
271 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
273 return atmel_port->use_dma_rx;
276 static bool atmel_use_fifo(struct uart_port *port)
278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
280 return atmel_port->fifo_size;
283 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
284 struct tasklet_struct *t)
286 if (!atomic_read(&atmel_port->tasklet_shutdown))
290 static unsigned int atmel_get_lines_status(struct uart_port *port)
292 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
293 unsigned int status, ret = 0;
295 status = atmel_uart_readl(port, ATMEL_US_CSR);
297 mctrl_gpio_get(atmel_port->gpios, &ret);
299 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
302 status &= ~ATMEL_US_CTS;
304 status |= ATMEL_US_CTS;
307 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
310 status &= ~ATMEL_US_DSR;
312 status |= ATMEL_US_DSR;
315 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
318 status &= ~ATMEL_US_RI;
320 status |= ATMEL_US_RI;
323 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
326 status &= ~ATMEL_US_DCD;
328 status |= ATMEL_US_DCD;
334 /* Enable or disable the rs485 support */
335 static int atmel_config_rs485(struct uart_port *port,
336 struct serial_rs485 *rs485conf)
338 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
341 /* Disable interrupts */
342 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
344 mode = atmel_uart_readl(port, ATMEL_US_MR);
346 /* Resetting serial mode to RS232 (0x0) */
347 mode &= ~ATMEL_US_USMODE;
349 port->rs485 = *rs485conf;
351 if (rs485conf->flags & SER_RS485_ENABLED) {
352 dev_dbg(port->dev, "Setting UART to RS485\n");
353 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
354 atmel_uart_writel(port, ATMEL_US_TTGR,
355 rs485conf->delay_rts_after_send);
356 mode |= ATMEL_US_USMODE_RS485;
358 dev_dbg(port->dev, "Setting UART to RS232\n");
359 if (atmel_use_pdc_tx(port))
360 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
363 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
365 atmel_uart_writel(port, ATMEL_US_MR, mode);
367 /* Enable interrupts */
368 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
374 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
376 static u_int atmel_tx_empty(struct uart_port *port)
378 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
380 if (atmel_port->tx_stopped)
382 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
388 * Set state of the modem control output lines
390 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
392 unsigned int control = 0;
393 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
394 unsigned int rts_paused, rts_ready;
395 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
397 /* override mode to RS485 if needed, otherwise keep the current mode */
398 if (port->rs485.flags & SER_RS485_ENABLED) {
399 atmel_uart_writel(port, ATMEL_US_TTGR,
400 port->rs485.delay_rts_after_send);
401 mode &= ~ATMEL_US_USMODE;
402 mode |= ATMEL_US_USMODE_RS485;
405 /* set the RTS line state according to the mode */
406 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
407 /* force RTS line to high level */
408 rts_paused = ATMEL_US_RTSEN;
410 /* give the control of the RTS line back to the hardware */
411 rts_ready = ATMEL_US_RTSDIS;
413 /* force RTS line to high level */
414 rts_paused = ATMEL_US_RTSDIS;
416 /* force RTS line to low level */
417 rts_ready = ATMEL_US_RTSEN;
420 if (mctrl & TIOCM_RTS)
421 control |= rts_ready;
423 control |= rts_paused;
425 if (mctrl & TIOCM_DTR)
426 control |= ATMEL_US_DTREN;
428 control |= ATMEL_US_DTRDIS;
430 atmel_uart_writel(port, ATMEL_US_CR, control);
432 mctrl_gpio_set(atmel_port->gpios, mctrl);
434 /* Local loopback mode? */
435 mode &= ~ATMEL_US_CHMODE;
436 if (mctrl & TIOCM_LOOP)
437 mode |= ATMEL_US_CHMODE_LOC_LOOP;
439 mode |= ATMEL_US_CHMODE_NORMAL;
441 atmel_uart_writel(port, ATMEL_US_MR, mode);
445 * Get state of the modem control input lines
447 static u_int atmel_get_mctrl(struct uart_port *port)
449 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
450 unsigned int ret = 0, status;
452 status = atmel_uart_readl(port, ATMEL_US_CSR);
455 * The control signals are active low.
457 if (!(status & ATMEL_US_DCD))
459 if (!(status & ATMEL_US_CTS))
461 if (!(status & ATMEL_US_DSR))
463 if (!(status & ATMEL_US_RI))
466 return mctrl_gpio_get(atmel_port->gpios, &ret);
472 static void atmel_stop_tx(struct uart_port *port)
474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
476 if (atmel_use_pdc_tx(port)) {
477 /* disable PDC transmit */
478 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
482 * Disable the transmitter.
483 * This is mandatory when DMA is used, otherwise the DMA buffer
484 * is fully transmitted.
486 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
487 atmel_port->tx_stopped = true;
489 /* Disable interrupts */
490 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
492 if (atmel_uart_is_half_duplex(port))
493 if (!atomic_read(&atmel_port->tasklet_shutdown))
494 atmel_start_rx(port);
499 * Start transmitting.
501 static void atmel_start_tx(struct uart_port *port)
503 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
505 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
507 /* The transmitter is already running. Yes, we
511 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
512 if (atmel_uart_is_half_duplex(port))
515 if (atmel_use_pdc_tx(port))
516 /* re-enable PDC transmit */
517 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
519 /* Enable interrupts */
520 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
522 /* re-enable the transmitter */
523 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
524 atmel_port->tx_stopped = false;
528 * start receiving - port is in process of being opened.
530 static void atmel_start_rx(struct uart_port *port)
532 /* reset status and receiver */
533 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
535 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
537 if (atmel_use_pdc_rx(port)) {
538 /* enable PDC controller */
539 atmel_uart_writel(port, ATMEL_US_IER,
540 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
541 port->read_status_mask);
542 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
544 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
549 * Stop receiving - port is in process of being closed.
551 static void atmel_stop_rx(struct uart_port *port)
553 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
555 if (atmel_use_pdc_rx(port)) {
556 /* disable PDC receive */
557 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
558 atmel_uart_writel(port, ATMEL_US_IDR,
559 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
560 port->read_status_mask);
562 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
567 * Enable modem status interrupts
569 static void atmel_enable_ms(struct uart_port *port)
571 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
575 * Interrupt should not be enabled twice
577 if (atmel_port->ms_irq_enabled)
580 atmel_port->ms_irq_enabled = true;
582 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
583 ier |= ATMEL_US_CTSIC;
585 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
586 ier |= ATMEL_US_DSRIC;
588 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
589 ier |= ATMEL_US_RIIC;
591 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
592 ier |= ATMEL_US_DCDIC;
594 atmel_uart_writel(port, ATMEL_US_IER, ier);
596 mctrl_gpio_enable_ms(atmel_port->gpios);
600 * Disable modem status interrupts
602 static void atmel_disable_ms(struct uart_port *port)
604 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
608 * Interrupt should not be disabled twice
610 if (!atmel_port->ms_irq_enabled)
613 atmel_port->ms_irq_enabled = false;
615 mctrl_gpio_disable_ms(atmel_port->gpios);
617 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
618 idr |= ATMEL_US_CTSIC;
620 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
621 idr |= ATMEL_US_DSRIC;
623 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
624 idr |= ATMEL_US_RIIC;
626 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
627 idr |= ATMEL_US_DCDIC;
629 atmel_uart_writel(port, ATMEL_US_IDR, idr);
633 * Control the transmission of a break signal
635 static void atmel_break_ctl(struct uart_port *port, int break_state)
637 if (break_state != 0)
639 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
642 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
646 * Stores the incoming character in the ring buffer
649 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
652 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
653 struct circ_buf *ring = &atmel_port->rx_ring;
654 struct atmel_uart_char *c;
656 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
657 /* Buffer overflow, ignore char */
660 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
664 /* Make sure the character is stored before we update head. */
667 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
671 * Deal with parity, framing and overrun errors.
673 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
676 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
678 if (status & ATMEL_US_RXBRK) {
679 /* ignore side-effect */
680 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
683 if (status & ATMEL_US_PARE)
684 port->icount.parity++;
685 if (status & ATMEL_US_FRAME)
686 port->icount.frame++;
687 if (status & ATMEL_US_OVRE)
688 port->icount.overrun++;
692 * Characters received (called from interrupt handler)
694 static void atmel_rx_chars(struct uart_port *port)
696 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
697 unsigned int status, ch;
699 status = atmel_uart_readl(port, ATMEL_US_CSR);
700 while (status & ATMEL_US_RXRDY) {
701 ch = atmel_uart_read_char(port);
704 * note that the error handling code is
705 * out of the main execution path
707 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
708 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
709 || atmel_port->break_active)) {
712 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
714 if (status & ATMEL_US_RXBRK
715 && !atmel_port->break_active) {
716 atmel_port->break_active = 1;
717 atmel_uart_writel(port, ATMEL_US_IER,
721 * This is either the end-of-break
722 * condition or we've received at
723 * least one character without RXBRK
724 * being set. In both cases, the next
725 * RXBRK will indicate start-of-break.
727 atmel_uart_writel(port, ATMEL_US_IDR,
729 status &= ~ATMEL_US_RXBRK;
730 atmel_port->break_active = 0;
734 atmel_buffer_rx_char(port, status, ch);
735 status = atmel_uart_readl(port, ATMEL_US_CSR);
738 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
742 * Transmit characters (called from tasklet with TXRDY interrupt
745 static void atmel_tx_chars(struct uart_port *port)
747 struct circ_buf *xmit = &port->state->xmit;
748 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
751 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
752 atmel_uart_write_char(port, port->x_char);
756 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
759 while (atmel_uart_readl(port, ATMEL_US_CSR) &
760 atmel_port->tx_done_mask) {
761 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
762 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
764 if (uart_circ_empty(xmit))
768 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
769 uart_write_wakeup(port);
771 if (!uart_circ_empty(xmit))
772 /* Enable interrupts */
773 atmel_uart_writel(port, ATMEL_US_IER,
774 atmel_port->tx_done_mask);
777 static void atmel_complete_tx_dma(void *arg)
779 struct atmel_uart_port *atmel_port = arg;
780 struct uart_port *port = &atmel_port->uart;
781 struct circ_buf *xmit = &port->state->xmit;
782 struct dma_chan *chan = atmel_port->chan_tx;
785 spin_lock_irqsave(&port->lock, flags);
788 dmaengine_terminate_all(chan);
789 xmit->tail += atmel_port->tx_len;
790 xmit->tail &= UART_XMIT_SIZE - 1;
792 port->icount.tx += atmel_port->tx_len;
794 spin_lock_irq(&atmel_port->lock_tx);
795 async_tx_ack(atmel_port->desc_tx);
796 atmel_port->cookie_tx = -EINVAL;
797 atmel_port->desc_tx = NULL;
798 spin_unlock_irq(&atmel_port->lock_tx);
800 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
801 uart_write_wakeup(port);
804 * xmit is a circular buffer so, if we have just send data from
805 * xmit->tail to the end of xmit->buf, now we have to transmit the
806 * remaining data from the beginning of xmit->buf to xmit->head.
808 if (!uart_circ_empty(xmit))
809 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
810 else if (atmel_uart_is_half_duplex(port)) {
812 * DMA done, re-enable TXEMPTY and signal that we can stop
813 * TX and start RX for RS485
815 atmel_port->hd_start_rx = true;
816 atmel_uart_writel(port, ATMEL_US_IER,
817 atmel_port->tx_done_mask);
820 spin_unlock_irqrestore(&port->lock, flags);
823 static void atmel_release_tx_dma(struct uart_port *port)
825 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
826 struct dma_chan *chan = atmel_port->chan_tx;
829 dmaengine_terminate_all(chan);
830 dma_release_channel(chan);
831 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
835 atmel_port->desc_tx = NULL;
836 atmel_port->chan_tx = NULL;
837 atmel_port->cookie_tx = -EINVAL;
841 * Called from tasklet with TXRDY interrupt is disabled.
843 static void atmel_tx_dma(struct uart_port *port)
845 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
846 struct circ_buf *xmit = &port->state->xmit;
847 struct dma_chan *chan = atmel_port->chan_tx;
848 struct dma_async_tx_descriptor *desc;
849 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
850 unsigned int tx_len, part1_len, part2_len, sg_len;
851 dma_addr_t phys_addr;
853 /* Make sure we have an idle channel */
854 if (atmel_port->desc_tx != NULL)
857 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
860 * Port xmit buffer is already mapped,
861 * and it is one page... Just adjust
862 * offsets and lengths. Since it is a circular buffer,
863 * we have to transmit till the end, and then the rest.
864 * Take the port lock to get a
865 * consistent xmit buffer state.
867 tx_len = CIRC_CNT_TO_END(xmit->head,
871 if (atmel_port->fifo_size) {
872 /* multi data mode */
873 part1_len = (tx_len & ~0x3); /* DWORD access */
874 part2_len = (tx_len & 0x3); /* BYTE access */
876 /* single data (legacy) mode */
878 part2_len = tx_len; /* BYTE access only */
881 sg_init_table(sgl, 2);
883 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
886 sg_dma_address(sg) = phys_addr;
887 sg_dma_len(sg) = part1_len;
889 phys_addr += part1_len;
894 sg_dma_address(sg) = phys_addr;
895 sg_dma_len(sg) = part2_len;
899 * save tx_len so atmel_complete_tx_dma() will increase
900 * xmit->tail correctly
902 atmel_port->tx_len = tx_len;
904 desc = dmaengine_prep_slave_sg(chan,
911 dev_err(port->dev, "Failed to send via dma!\n");
915 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
917 atmel_port->desc_tx = desc;
918 desc->callback = atmel_complete_tx_dma;
919 desc->callback_param = atmel_port;
920 atmel_port->cookie_tx = dmaengine_submit(desc);
921 if (dma_submit_error(atmel_port->cookie_tx)) {
922 dev_err(port->dev, "dma_submit_error %d\n",
923 atmel_port->cookie_tx);
927 dma_async_issue_pending(chan);
930 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
931 uart_write_wakeup(port);
934 static int atmel_prepare_tx_dma(struct uart_port *port)
936 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
938 struct dma_slave_config config;
942 dma_cap_set(DMA_SLAVE, mask);
944 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
945 if (atmel_port->chan_tx == NULL)
947 dev_info(port->dev, "using %s for tx DMA transfers\n",
948 dma_chan_name(atmel_port->chan_tx));
950 spin_lock_init(&atmel_port->lock_tx);
951 sg_init_table(&atmel_port->sg_tx, 1);
952 /* UART circular tx buffer is an aligned page. */
953 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
954 sg_set_page(&atmel_port->sg_tx,
955 virt_to_page(port->state->xmit.buf),
957 offset_in_page(port->state->xmit.buf));
958 nent = dma_map_sg(port->dev,
964 dev_dbg(port->dev, "need to release resource of dma\n");
967 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
968 sg_dma_len(&atmel_port->sg_tx),
969 port->state->xmit.buf,
970 &sg_dma_address(&atmel_port->sg_tx));
973 /* Configure the slave DMA */
974 memset(&config, 0, sizeof(config));
975 config.direction = DMA_MEM_TO_DEV;
976 config.dst_addr_width = (atmel_port->fifo_size) ?
977 DMA_SLAVE_BUSWIDTH_4_BYTES :
978 DMA_SLAVE_BUSWIDTH_1_BYTE;
979 config.dst_addr = port->mapbase + ATMEL_US_THR;
980 config.dst_maxburst = 1;
982 ret = dmaengine_slave_config(atmel_port->chan_tx,
985 dev_err(port->dev, "DMA tx slave configuration failed\n");
992 dev_err(port->dev, "TX channel not available, switch to pio\n");
993 atmel_port->use_dma_tx = 0;
994 if (atmel_port->chan_tx)
995 atmel_release_tx_dma(port);
999 static void atmel_complete_rx_dma(void *arg)
1001 struct uart_port *port = arg;
1002 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1004 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1007 static void atmel_release_rx_dma(struct uart_port *port)
1009 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1010 struct dma_chan *chan = atmel_port->chan_rx;
1013 dmaengine_terminate_all(chan);
1014 dma_release_channel(chan);
1015 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1019 atmel_port->desc_rx = NULL;
1020 atmel_port->chan_rx = NULL;
1021 atmel_port->cookie_rx = -EINVAL;
1024 static void atmel_rx_from_dma(struct uart_port *port)
1026 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1027 struct tty_port *tport = &port->state->port;
1028 struct circ_buf *ring = &atmel_port->rx_ring;
1029 struct dma_chan *chan = atmel_port->chan_rx;
1030 struct dma_tx_state state;
1031 enum dma_status dmastat;
1035 /* Reset the UART timeout early so that we don't miss one */
1036 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1037 dmastat = dmaengine_tx_status(chan,
1038 atmel_port->cookie_rx,
1040 /* Restart a new tasklet if DMA status is error */
1041 if (dmastat == DMA_ERROR) {
1042 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1043 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1044 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1048 /* CPU claims ownership of RX DMA buffer */
1049 dma_sync_sg_for_cpu(port->dev,
1055 * ring->head points to the end of data already written by the DMA.
1056 * ring->tail points to the beginning of data to be read by the
1058 * The current transfer size should not be larger than the dma buffer
1061 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1062 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1064 * At this point ring->head may point to the first byte right after the
1065 * last byte of the dma buffer:
1066 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1068 * However ring->tail must always points inside the dma buffer:
1069 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1071 * Since we use a ring buffer, we have to handle the case
1072 * where head is lower than tail. In such a case, we first read from
1073 * tail to the end of the buffer then reset tail.
1075 if (ring->head < ring->tail) {
1076 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1078 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1080 port->icount.rx += count;
1083 /* Finally we read data from tail to head */
1084 if (ring->tail < ring->head) {
1085 count = ring->head - ring->tail;
1087 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1088 /* Wrap ring->head if needed */
1089 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1091 ring->tail = ring->head;
1092 port->icount.rx += count;
1095 /* USART retreives ownership of RX DMA buffer */
1096 dma_sync_sg_for_device(port->dev,
1102 * Drop the lock here since it might end up calling
1103 * uart_start(), which takes the lock.
1105 spin_unlock(&port->lock);
1106 tty_flip_buffer_push(tport);
1107 spin_lock(&port->lock);
1109 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1112 static int atmel_prepare_rx_dma(struct uart_port *port)
1114 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1115 struct dma_async_tx_descriptor *desc;
1116 dma_cap_mask_t mask;
1117 struct dma_slave_config config;
1118 struct circ_buf *ring;
1121 ring = &atmel_port->rx_ring;
1124 dma_cap_set(DMA_CYCLIC, mask);
1126 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1127 if (atmel_port->chan_rx == NULL)
1129 dev_info(port->dev, "using %s for rx DMA transfers\n",
1130 dma_chan_name(atmel_port->chan_rx));
1132 spin_lock_init(&atmel_port->lock_rx);
1133 sg_init_table(&atmel_port->sg_rx, 1);
1134 /* UART circular rx buffer is an aligned page. */
1135 BUG_ON(!PAGE_ALIGNED(ring->buf));
1136 sg_set_page(&atmel_port->sg_rx,
1137 virt_to_page(ring->buf),
1138 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1139 offset_in_page(ring->buf));
1140 nent = dma_map_sg(port->dev,
1146 dev_dbg(port->dev, "need to release resource of dma\n");
1149 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1150 sg_dma_len(&atmel_port->sg_rx),
1152 &sg_dma_address(&atmel_port->sg_rx));
1155 /* Configure the slave DMA */
1156 memset(&config, 0, sizeof(config));
1157 config.direction = DMA_DEV_TO_MEM;
1158 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1159 config.src_addr = port->mapbase + ATMEL_US_RHR;
1160 config.src_maxburst = 1;
1162 ret = dmaengine_slave_config(atmel_port->chan_rx,
1165 dev_err(port->dev, "DMA rx slave configuration failed\n");
1169 * Prepare a cyclic dma transfer, assign 2 descriptors,
1170 * each one is half ring buffer size
1172 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1173 sg_dma_address(&atmel_port->sg_rx),
1174 sg_dma_len(&atmel_port->sg_rx),
1175 sg_dma_len(&atmel_port->sg_rx)/2,
1177 DMA_PREP_INTERRUPT);
1179 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1182 desc->callback = atmel_complete_rx_dma;
1183 desc->callback_param = port;
1184 atmel_port->desc_rx = desc;
1185 atmel_port->cookie_rx = dmaengine_submit(desc);
1186 if (dma_submit_error(atmel_port->cookie_rx)) {
1187 dev_err(port->dev, "dma_submit_error %d\n",
1188 atmel_port->cookie_rx);
1192 dma_async_issue_pending(atmel_port->chan_rx);
1197 dev_err(port->dev, "RX channel not available, switch to pio\n");
1198 atmel_port->use_dma_rx = 0;
1199 if (atmel_port->chan_rx)
1200 atmel_release_rx_dma(port);
1204 static void atmel_uart_timer_callback(struct timer_list *t)
1206 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1208 struct uart_port *port = &atmel_port->uart;
1210 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1211 tasklet_schedule(&atmel_port->tasklet_rx);
1212 mod_timer(&atmel_port->uart_timer,
1213 jiffies + uart_poll_timeout(port));
1218 * receive interrupt handler.
1221 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1223 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1225 if (atmel_use_pdc_rx(port)) {
1227 * PDC receive. Just schedule the tasklet and let it
1228 * figure out the details.
1230 * TODO: We're not handling error flags correctly at
1233 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1234 atmel_uart_writel(port, ATMEL_US_IDR,
1235 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1236 atmel_tasklet_schedule(atmel_port,
1237 &atmel_port->tasklet_rx);
1240 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1241 ATMEL_US_FRAME | ATMEL_US_PARE))
1242 atmel_pdc_rxerr(port, pending);
1245 if (atmel_use_dma_rx(port)) {
1246 if (pending & ATMEL_US_TIMEOUT) {
1247 atmel_uart_writel(port, ATMEL_US_IDR,
1249 atmel_tasklet_schedule(atmel_port,
1250 &atmel_port->tasklet_rx);
1254 /* Interrupt receive */
1255 if (pending & ATMEL_US_RXRDY)
1256 atmel_rx_chars(port);
1257 else if (pending & ATMEL_US_RXBRK) {
1259 * End of break detected. If it came along with a
1260 * character, atmel_rx_chars will handle it.
1262 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1263 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1264 atmel_port->break_active = 0;
1269 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1272 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1276 if (pending & atmel_port->tx_done_mask) {
1277 atmel_uart_writel(port, ATMEL_US_IDR,
1278 atmel_port->tx_done_mask);
1280 /* Start RX if flag was set and FIFO is empty */
1281 if (atmel_port->hd_start_rx) {
1282 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1283 & ATMEL_US_TXEMPTY))
1284 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1286 atmel_port->hd_start_rx = false;
1287 atmel_start_rx(port);
1290 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1295 * status flags interrupt handler.
1298 atmel_handle_status(struct uart_port *port, unsigned int pending,
1299 unsigned int status)
1301 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1302 unsigned int status_change;
1304 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1305 | ATMEL_US_CTSIC)) {
1306 status_change = status ^ atmel_port->irq_status_prev;
1307 atmel_port->irq_status_prev = status;
1309 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1310 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1311 /* TODO: All reads to CSR will clear these interrupts! */
1312 if (status_change & ATMEL_US_RI)
1314 if (status_change & ATMEL_US_DSR)
1316 if (status_change & ATMEL_US_DCD)
1317 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1318 if (status_change & ATMEL_US_CTS)
1319 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1321 wake_up_interruptible(&port->state->port.delta_msr_wait);
1329 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1331 struct uart_port *port = dev_id;
1332 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1333 unsigned int status, pending, mask, pass_counter = 0;
1335 spin_lock(&atmel_port->lock_suspended);
1338 status = atmel_get_lines_status(port);
1339 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1340 pending = status & mask;
1344 if (atmel_port->suspended) {
1345 atmel_port->pending |= pending;
1346 atmel_port->pending_status = status;
1347 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1352 atmel_handle_receive(port, pending);
1353 atmel_handle_status(port, pending, status);
1354 atmel_handle_transmit(port, pending);
1355 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1357 spin_unlock(&atmel_port->lock_suspended);
1359 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1362 static void atmel_release_tx_pdc(struct uart_port *port)
1364 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1365 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1367 dma_unmap_single(port->dev,
1374 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1376 static void atmel_tx_pdc(struct uart_port *port)
1378 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1379 struct circ_buf *xmit = &port->state->xmit;
1380 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1383 /* nothing left to transmit? */
1384 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1387 xmit->tail += pdc->ofs;
1388 xmit->tail &= UART_XMIT_SIZE - 1;
1390 port->icount.tx += pdc->ofs;
1393 /* more to transmit - setup next transfer */
1395 /* disable PDC transmit */
1396 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1398 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1399 dma_sync_single_for_device(port->dev,
1404 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1407 atmel_uart_writel(port, ATMEL_PDC_TPR,
1408 pdc->dma_addr + xmit->tail);
1409 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1410 /* re-enable PDC transmit */
1411 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1412 /* Enable interrupts */
1413 atmel_uart_writel(port, ATMEL_US_IER,
1414 atmel_port->tx_done_mask);
1416 if (atmel_uart_is_half_duplex(port)) {
1417 /* DMA done, stop TX, start RX for RS485 */
1418 atmel_start_rx(port);
1422 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1423 uart_write_wakeup(port);
1426 static int atmel_prepare_tx_pdc(struct uart_port *port)
1428 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1429 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1430 struct circ_buf *xmit = &port->state->xmit;
1432 pdc->buf = xmit->buf;
1433 pdc->dma_addr = dma_map_single(port->dev,
1437 pdc->dma_size = UART_XMIT_SIZE;
1443 static void atmel_rx_from_ring(struct uart_port *port)
1445 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1446 struct circ_buf *ring = &atmel_port->rx_ring;
1448 unsigned int status;
1450 while (ring->head != ring->tail) {
1451 struct atmel_uart_char c;
1453 /* Make sure c is loaded after head. */
1456 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1458 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1465 * note that the error handling code is
1466 * out of the main execution path
1468 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1469 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1470 if (status & ATMEL_US_RXBRK) {
1471 /* ignore side-effect */
1472 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1475 if (uart_handle_break(port))
1478 if (status & ATMEL_US_PARE)
1479 port->icount.parity++;
1480 if (status & ATMEL_US_FRAME)
1481 port->icount.frame++;
1482 if (status & ATMEL_US_OVRE)
1483 port->icount.overrun++;
1485 status &= port->read_status_mask;
1487 if (status & ATMEL_US_RXBRK)
1489 else if (status & ATMEL_US_PARE)
1491 else if (status & ATMEL_US_FRAME)
1496 if (uart_handle_sysrq_char(port, c.ch))
1499 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1503 * Drop the lock here since it might end up calling
1504 * uart_start(), which takes the lock.
1506 spin_unlock(&port->lock);
1507 tty_flip_buffer_push(&port->state->port);
1508 spin_lock(&port->lock);
1511 static void atmel_release_rx_pdc(struct uart_port *port)
1513 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1516 for (i = 0; i < 2; i++) {
1517 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1519 dma_unmap_single(port->dev,
1527 static void atmel_rx_from_pdc(struct uart_port *port)
1529 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1530 struct tty_port *tport = &port->state->port;
1531 struct atmel_dma_buffer *pdc;
1532 int rx_idx = atmel_port->pdc_rx_idx;
1538 /* Reset the UART timeout early so that we don't miss one */
1539 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1541 pdc = &atmel_port->pdc_rx[rx_idx];
1542 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1545 /* If the PDC has switched buffers, RPR won't contain
1546 * any address within the current buffer. Since head
1547 * is unsigned, we just need a one-way comparison to
1550 * In this case, we just need to consume the entire
1551 * buffer and resubmit it for DMA. This will clear the
1552 * ENDRX bit as well, so that we can safely re-enable
1553 * all interrupts below.
1555 head = min(head, pdc->dma_size);
1557 if (likely(head != tail)) {
1558 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1559 pdc->dma_size, DMA_FROM_DEVICE);
1562 * head will only wrap around when we recycle
1563 * the DMA buffer, and when that happens, we
1564 * explicitly set tail to 0. So head will
1565 * always be greater than tail.
1567 count = head - tail;
1569 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1572 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1573 pdc->dma_size, DMA_FROM_DEVICE);
1575 port->icount.rx += count;
1580 * If the current buffer is full, we need to check if
1581 * the next one contains any additional data.
1583 if (head >= pdc->dma_size) {
1585 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1586 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1589 atmel_port->pdc_rx_idx = rx_idx;
1591 } while (head >= pdc->dma_size);
1594 * Drop the lock here since it might end up calling
1595 * uart_start(), which takes the lock.
1597 spin_unlock(&port->lock);
1598 tty_flip_buffer_push(tport);
1599 spin_lock(&port->lock);
1601 atmel_uart_writel(port, ATMEL_US_IER,
1602 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1605 static int atmel_prepare_rx_pdc(struct uart_port *port)
1607 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1610 for (i = 0; i < 2; i++) {
1611 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1613 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1614 if (pdc->buf == NULL) {
1616 dma_unmap_single(port->dev,
1617 atmel_port->pdc_rx[0].dma_addr,
1620 kfree(atmel_port->pdc_rx[0].buf);
1622 atmel_port->use_pdc_rx = 0;
1625 pdc->dma_addr = dma_map_single(port->dev,
1629 pdc->dma_size = PDC_BUFFER_SIZE;
1633 atmel_port->pdc_rx_idx = 0;
1635 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1636 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1638 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1639 atmel_port->pdc_rx[1].dma_addr);
1640 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1646 * tasklet handling tty stuff outside the interrupt handler.
1648 static void atmel_tasklet_rx_func(unsigned long data)
1650 struct uart_port *port = (struct uart_port *)data;
1651 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1653 /* The interrupt handler does not take the lock */
1654 spin_lock(&port->lock);
1655 atmel_port->schedule_rx(port);
1656 spin_unlock(&port->lock);
1659 static void atmel_tasklet_tx_func(unsigned long data)
1661 struct uart_port *port = (struct uart_port *)data;
1662 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1664 /* The interrupt handler does not take the lock */
1665 spin_lock(&port->lock);
1666 atmel_port->schedule_tx(port);
1667 spin_unlock(&port->lock);
1670 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1671 struct platform_device *pdev)
1673 struct device_node *np = pdev->dev.of_node;
1675 /* DMA/PDC usage specification */
1676 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1677 if (of_property_read_bool(np, "dmas")) {
1678 atmel_port->use_dma_rx = true;
1679 atmel_port->use_pdc_rx = false;
1681 atmel_port->use_dma_rx = false;
1682 atmel_port->use_pdc_rx = true;
1685 atmel_port->use_dma_rx = false;
1686 atmel_port->use_pdc_rx = false;
1689 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1690 if (of_property_read_bool(np, "dmas")) {
1691 atmel_port->use_dma_tx = true;
1692 atmel_port->use_pdc_tx = false;
1694 atmel_port->use_dma_tx = false;
1695 atmel_port->use_pdc_tx = true;
1698 atmel_port->use_dma_tx = false;
1699 atmel_port->use_pdc_tx = false;
1703 static void atmel_set_ops(struct uart_port *port)
1705 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1707 if (atmel_use_dma_rx(port)) {
1708 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1709 atmel_port->schedule_rx = &atmel_rx_from_dma;
1710 atmel_port->release_rx = &atmel_release_rx_dma;
1711 } else if (atmel_use_pdc_rx(port)) {
1712 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1713 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1714 atmel_port->release_rx = &atmel_release_rx_pdc;
1716 atmel_port->prepare_rx = NULL;
1717 atmel_port->schedule_rx = &atmel_rx_from_ring;
1718 atmel_port->release_rx = NULL;
1721 if (atmel_use_dma_tx(port)) {
1722 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1723 atmel_port->schedule_tx = &atmel_tx_dma;
1724 atmel_port->release_tx = &atmel_release_tx_dma;
1725 } else if (atmel_use_pdc_tx(port)) {
1726 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1727 atmel_port->schedule_tx = &atmel_tx_pdc;
1728 atmel_port->release_tx = &atmel_release_tx_pdc;
1730 atmel_port->prepare_tx = NULL;
1731 atmel_port->schedule_tx = &atmel_tx_chars;
1732 atmel_port->release_tx = NULL;
1737 * Get ip name usart or uart
1739 static void atmel_get_ip_name(struct uart_port *port)
1741 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1742 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1744 u32 usart, dbgu_uart, new_uart;
1745 /* ASCII decoding for IP version */
1746 usart = 0x55534152; /* USAR(T) */
1747 dbgu_uart = 0x44424755; /* DBGU */
1748 new_uart = 0x55415254; /* UART */
1751 * Only USART devices from at91sam9260 SOC implement fractional
1752 * baudrate. It is available for all asynchronous modes, with the
1753 * following restriction: the sampling clock's duty cycle is not
1756 atmel_port->has_frac_baudrate = false;
1757 atmel_port->has_hw_timer = false;
1759 if (name == new_uart) {
1760 dev_dbg(port->dev, "Uart with hw timer");
1761 atmel_port->has_hw_timer = true;
1762 atmel_port->rtor = ATMEL_UA_RTOR;
1763 } else if (name == usart) {
1764 dev_dbg(port->dev, "Usart\n");
1765 atmel_port->has_frac_baudrate = true;
1766 atmel_port->has_hw_timer = true;
1767 atmel_port->rtor = ATMEL_US_RTOR;
1768 } else if (name == dbgu_uart) {
1769 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1771 /* fallback for older SoCs: use version field */
1772 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1777 dev_dbg(port->dev, "This version is usart\n");
1778 atmel_port->has_frac_baudrate = true;
1779 atmel_port->has_hw_timer = true;
1780 atmel_port->rtor = ATMEL_US_RTOR;
1784 dev_dbg(port->dev, "This version is uart\n");
1787 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1793 * Perform initialization and enable port for reception
1795 static int atmel_startup(struct uart_port *port)
1797 struct platform_device *pdev = to_platform_device(port->dev);
1798 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1802 * Ensure that no interrupts are enabled otherwise when
1803 * request_irq() is called we could get stuck trying to
1804 * handle an unexpected interrupt
1806 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1807 atmel_port->ms_irq_enabled = false;
1812 retval = request_irq(port->irq, atmel_interrupt,
1813 IRQF_SHARED | IRQF_COND_SUSPEND,
1814 dev_name(&pdev->dev), port);
1816 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1820 atomic_set(&atmel_port->tasklet_shutdown, 0);
1821 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1822 (unsigned long)port);
1823 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1824 (unsigned long)port);
1827 * Initialize DMA (if necessary)
1829 atmel_init_property(atmel_port, pdev);
1830 atmel_set_ops(port);
1832 if (atmel_port->prepare_rx) {
1833 retval = atmel_port->prepare_rx(port);
1835 atmel_set_ops(port);
1838 if (atmel_port->prepare_tx) {
1839 retval = atmel_port->prepare_tx(port);
1841 atmel_set_ops(port);
1845 * Enable FIFO when available
1847 if (atmel_port->fifo_size) {
1848 unsigned int txrdym = ATMEL_US_ONE_DATA;
1849 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1852 atmel_uart_writel(port, ATMEL_US_CR,
1857 if (atmel_use_dma_tx(port))
1858 txrdym = ATMEL_US_FOUR_DATA;
1860 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1861 if (atmel_port->rts_high &&
1862 atmel_port->rts_low)
1863 fmr |= ATMEL_US_FRTSC |
1864 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1865 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1867 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1870 /* Save current CSR for comparison in atmel_tasklet_func() */
1871 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1874 * Finally, enable the serial port
1876 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1877 /* enable xmit & rcvr */
1878 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1879 atmel_port->tx_stopped = false;
1881 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1883 if (atmel_use_pdc_rx(port)) {
1884 /* set UART timeout */
1885 if (!atmel_port->has_hw_timer) {
1886 mod_timer(&atmel_port->uart_timer,
1887 jiffies + uart_poll_timeout(port));
1888 /* set USART timeout */
1890 atmel_uart_writel(port, atmel_port->rtor,
1892 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1894 atmel_uart_writel(port, ATMEL_US_IER,
1895 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1897 /* enable PDC controller */
1898 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1899 } else if (atmel_use_dma_rx(port)) {
1900 /* set UART timeout */
1901 if (!atmel_port->has_hw_timer) {
1902 mod_timer(&atmel_port->uart_timer,
1903 jiffies + uart_poll_timeout(port));
1904 /* set USART timeout */
1906 atmel_uart_writel(port, atmel_port->rtor,
1908 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1910 atmel_uart_writel(port, ATMEL_US_IER,
1914 /* enable receive only */
1915 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1922 * Flush any TX data submitted for DMA. Called when the TX circular
1925 static void atmel_flush_buffer(struct uart_port *port)
1927 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1929 if (atmel_use_pdc_tx(port)) {
1930 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1931 atmel_port->pdc_tx.ofs = 0;
1934 * in uart_flush_buffer(), the xmit circular buffer has just
1935 * been cleared, so we have to reset tx_len accordingly.
1937 atmel_port->tx_len = 0;
1943 static void atmel_shutdown(struct uart_port *port)
1945 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1947 /* Disable modem control lines interrupts */
1948 atmel_disable_ms(port);
1950 /* Disable interrupts at device level */
1951 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1953 /* Prevent spurious interrupts from scheduling the tasklet */
1954 atomic_inc(&atmel_port->tasklet_shutdown);
1957 * Prevent any tasklets being scheduled during
1960 del_timer_sync(&atmel_port->uart_timer);
1962 /* Make sure that no interrupt is on the fly */
1963 synchronize_irq(port->irq);
1966 * Clear out any scheduled tasklets before
1967 * we destroy the buffers
1969 tasklet_kill(&atmel_port->tasklet_rx);
1970 tasklet_kill(&atmel_port->tasklet_tx);
1973 * Ensure everything is stopped and
1974 * disable port and break condition.
1976 atmel_stop_rx(port);
1977 atmel_stop_tx(port);
1979 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1982 * Shut-down the DMA.
1984 if (atmel_port->release_rx)
1985 atmel_port->release_rx(port);
1986 if (atmel_port->release_tx)
1987 atmel_port->release_tx(port);
1990 * Reset ring buffer pointers
1992 atmel_port->rx_ring.head = 0;
1993 atmel_port->rx_ring.tail = 0;
1996 * Free the interrupts
1998 free_irq(port->irq, port);
2000 atmel_flush_buffer(port);
2004 * Power / Clock management.
2006 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2007 unsigned int oldstate)
2009 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2014 * Enable the peripheral clock for this serial port.
2015 * This is called on uart_open() or a resume event.
2017 clk_prepare_enable(atmel_port->clk);
2019 /* re-enable interrupts if we disabled some on suspend */
2020 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2023 /* Back up the interrupt mask and disable all interrupts */
2024 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2025 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2028 * Disable the peripheral clock for this serial port.
2029 * This is called on uart_close() or a suspend event.
2031 clk_disable_unprepare(atmel_port->clk);
2034 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2039 * Change the port parameters
2041 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2042 struct ktermios *old)
2044 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2045 unsigned long flags;
2046 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2048 /* save the current mode register */
2049 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2051 /* reset the mode, clock divisor, parity, stop bits and data size */
2052 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2053 ATMEL_US_PAR | ATMEL_US_USMODE);
2055 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2058 switch (termios->c_cflag & CSIZE) {
2060 mode |= ATMEL_US_CHRL_5;
2063 mode |= ATMEL_US_CHRL_6;
2066 mode |= ATMEL_US_CHRL_7;
2069 mode |= ATMEL_US_CHRL_8;
2074 if (termios->c_cflag & CSTOPB)
2075 mode |= ATMEL_US_NBSTOP_2;
2078 if (termios->c_cflag & PARENB) {
2079 /* Mark or Space parity */
2080 if (termios->c_cflag & CMSPAR) {
2081 if (termios->c_cflag & PARODD)
2082 mode |= ATMEL_US_PAR_MARK;
2084 mode |= ATMEL_US_PAR_SPACE;
2085 } else if (termios->c_cflag & PARODD)
2086 mode |= ATMEL_US_PAR_ODD;
2088 mode |= ATMEL_US_PAR_EVEN;
2090 mode |= ATMEL_US_PAR_NONE;
2092 spin_lock_irqsave(&port->lock, flags);
2094 port->read_status_mask = ATMEL_US_OVRE;
2095 if (termios->c_iflag & INPCK)
2096 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2097 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2098 port->read_status_mask |= ATMEL_US_RXBRK;
2100 if (atmel_use_pdc_rx(port))
2101 /* need to enable error interrupts */
2102 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2105 * Characters to ignore
2107 port->ignore_status_mask = 0;
2108 if (termios->c_iflag & IGNPAR)
2109 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2110 if (termios->c_iflag & IGNBRK) {
2111 port->ignore_status_mask |= ATMEL_US_RXBRK;
2113 * If we're ignoring parity and break indicators,
2114 * ignore overruns too (for real raw support).
2116 if (termios->c_iflag & IGNPAR)
2117 port->ignore_status_mask |= ATMEL_US_OVRE;
2119 /* TODO: Ignore all characters if CREAD is set.*/
2121 /* update the per-port timeout */
2122 uart_update_timeout(port, termios->c_cflag, baud);
2125 * save/disable interrupts. The tty layer will ensure that the
2126 * transmitter is empty if requested by the caller, so there's
2127 * no need to wait for it here.
2129 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2130 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2132 /* disable receiver and transmitter */
2133 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2134 atmel_port->tx_stopped = true;
2137 if (port->rs485.flags & SER_RS485_ENABLED) {
2138 atmel_uart_writel(port, ATMEL_US_TTGR,
2139 port->rs485.delay_rts_after_send);
2140 mode |= ATMEL_US_USMODE_RS485;
2141 } else if (termios->c_cflag & CRTSCTS) {
2142 /* RS232 with hardware handshake (RTS/CTS) */
2143 if (atmel_use_fifo(port) &&
2144 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2146 * with ATMEL_US_USMODE_HWHS set, the controller will
2147 * be able to drive the RTS pin high/low when the RX
2148 * FIFO is above RXFTHRES/below RXFTHRES2.
2149 * It will also disable the transmitter when the CTS
2151 * This mode is not activated if CTS pin is a GPIO
2152 * because in this case, the transmitter is always
2153 * disabled (there must be an internal pull-up
2154 * responsible for this behaviour).
2155 * If the RTS pin is a GPIO, the controller won't be
2156 * able to drive it according to the FIFO thresholds,
2157 * but it will be handled by the driver.
2159 mode |= ATMEL_US_USMODE_HWHS;
2162 * For platforms without FIFO, the flow control is
2163 * handled by the driver.
2165 mode |= ATMEL_US_USMODE_NORMAL;
2168 /* RS232 without hadware handshake */
2169 mode |= ATMEL_US_USMODE_NORMAL;
2173 * Set the baud rate:
2174 * Fractional baudrate allows to setup output frequency more
2175 * accurately. This feature is enabled only when using normal mode.
2176 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2177 * Currently, OVER is always set to 0 so we get
2178 * baudrate = selected clock / (16 * (CD + FP / 8))
2180 * 8 CD + FP = selected clock / (2 * baudrate)
2182 if (atmel_port->has_frac_baudrate) {
2183 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2185 fp = div & ATMEL_US_FP_MASK;
2187 cd = uart_get_divisor(port, baud);
2190 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2192 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2194 quot = cd | fp << ATMEL_US_FP_OFFSET;
2196 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2198 /* set the mode, clock divisor, parity, stop bits and data size */
2199 atmel_uart_writel(port, ATMEL_US_MR, mode);
2202 * when switching the mode, set the RTS line state according to the
2203 * new mode, otherwise keep the former state
2205 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2206 unsigned int rts_state;
2208 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2209 /* let the hardware control the RTS line */
2210 rts_state = ATMEL_US_RTSDIS;
2212 /* force RTS line to low level */
2213 rts_state = ATMEL_US_RTSEN;
2216 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2219 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2220 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2221 atmel_port->tx_stopped = false;
2223 /* restore interrupts */
2224 atmel_uart_writel(port, ATMEL_US_IER, imr);
2226 /* CTS flow-control and modem-status interrupts */
2227 if (UART_ENABLE_MS(port, termios->c_cflag))
2228 atmel_enable_ms(port);
2230 atmel_disable_ms(port);
2232 spin_unlock_irqrestore(&port->lock, flags);
2235 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2237 if (termios->c_line == N_PPS) {
2238 port->flags |= UPF_HARDPPS_CD;
2239 spin_lock_irq(&port->lock);
2240 atmel_enable_ms(port);
2241 spin_unlock_irq(&port->lock);
2243 port->flags &= ~UPF_HARDPPS_CD;
2244 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2245 spin_lock_irq(&port->lock);
2246 atmel_disable_ms(port);
2247 spin_unlock_irq(&port->lock);
2253 * Return string describing the specified port
2255 static const char *atmel_type(struct uart_port *port)
2257 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2261 * Release the memory region(s) being used by 'port'.
2263 static void atmel_release_port(struct uart_port *port)
2265 struct platform_device *pdev = to_platform_device(port->dev);
2266 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2268 release_mem_region(port->mapbase, size);
2270 if (port->flags & UPF_IOREMAP) {
2271 iounmap(port->membase);
2272 port->membase = NULL;
2277 * Request the memory region(s) being used by 'port'.
2279 static int atmel_request_port(struct uart_port *port)
2281 struct platform_device *pdev = to_platform_device(port->dev);
2282 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2284 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2287 if (port->flags & UPF_IOREMAP) {
2288 port->membase = ioremap(port->mapbase, size);
2289 if (port->membase == NULL) {
2290 release_mem_region(port->mapbase, size);
2299 * Configure/autoconfigure the port.
2301 static void atmel_config_port(struct uart_port *port, int flags)
2303 if (flags & UART_CONFIG_TYPE) {
2304 port->type = PORT_ATMEL;
2305 atmel_request_port(port);
2310 * Verify the new serial_struct (for TIOCSSERIAL).
2312 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2315 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2317 if (port->irq != ser->irq)
2319 if (ser->io_type != SERIAL_IO_MEM)
2321 if (port->uartclk / 16 != ser->baud_base)
2323 if (port->mapbase != (unsigned long)ser->iomem_base)
2325 if (port->iobase != ser->port)
2332 #ifdef CONFIG_CONSOLE_POLL
2333 static int atmel_poll_get_char(struct uart_port *port)
2335 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2338 return atmel_uart_read_char(port);
2341 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2343 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2346 atmel_uart_write_char(port, ch);
2350 static const struct uart_ops atmel_pops = {
2351 .tx_empty = atmel_tx_empty,
2352 .set_mctrl = atmel_set_mctrl,
2353 .get_mctrl = atmel_get_mctrl,
2354 .stop_tx = atmel_stop_tx,
2355 .start_tx = atmel_start_tx,
2356 .stop_rx = atmel_stop_rx,
2357 .enable_ms = atmel_enable_ms,
2358 .break_ctl = atmel_break_ctl,
2359 .startup = atmel_startup,
2360 .shutdown = atmel_shutdown,
2361 .flush_buffer = atmel_flush_buffer,
2362 .set_termios = atmel_set_termios,
2363 .set_ldisc = atmel_set_ldisc,
2365 .release_port = atmel_release_port,
2366 .request_port = atmel_request_port,
2367 .config_port = atmel_config_port,
2368 .verify_port = atmel_verify_port,
2369 .pm = atmel_serial_pm,
2370 #ifdef CONFIG_CONSOLE_POLL
2371 .poll_get_char = atmel_poll_get_char,
2372 .poll_put_char = atmel_poll_put_char,
2377 * Configure the port from the platform device resource info.
2379 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2380 struct platform_device *pdev)
2383 struct uart_port *port = &atmel_port->uart;
2385 atmel_init_property(atmel_port, pdev);
2386 atmel_set_ops(port);
2388 uart_get_rs485_mode(&pdev->dev, &port->rs485);
2390 port->iotype = UPIO_MEM;
2391 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2392 port->ops = &atmel_pops;
2394 port->dev = &pdev->dev;
2395 port->mapbase = pdev->resource[0].start;
2396 port->irq = pdev->resource[1].start;
2397 port->rs485_config = atmel_config_rs485;
2398 port->membase = NULL;
2400 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2402 /* for console, the clock could already be configured */
2403 if (!atmel_port->clk) {
2404 atmel_port->clk = clk_get(&pdev->dev, "usart");
2405 if (IS_ERR(atmel_port->clk)) {
2406 ret = PTR_ERR(atmel_port->clk);
2407 atmel_port->clk = NULL;
2410 ret = clk_prepare_enable(atmel_port->clk);
2412 clk_put(atmel_port->clk);
2413 atmel_port->clk = NULL;
2416 port->uartclk = clk_get_rate(atmel_port->clk);
2417 clk_disable_unprepare(atmel_port->clk);
2418 /* only enable clock when USART is in use */
2421 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2422 if (port->rs485.flags & SER_RS485_ENABLED)
2423 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2424 else if (atmel_use_pdc_tx(port)) {
2425 port->fifosize = PDC_BUFFER_SIZE;
2426 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2428 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2434 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2435 static void atmel_console_putchar(struct uart_port *port, int ch)
2437 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2439 atmel_uart_write_char(port, ch);
2443 * Interrupts are disabled on entering
2445 static void atmel_console_write(struct console *co, const char *s, u_int count)
2447 struct uart_port *port = &atmel_ports[co->index].uart;
2448 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2449 unsigned int status, imr;
2450 unsigned int pdc_tx;
2453 * First, save IMR and then disable interrupts
2455 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2456 atmel_uart_writel(port, ATMEL_US_IDR,
2457 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2459 /* Store PDC transmit status and disable it */
2460 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2461 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2463 /* Make sure that tx path is actually able to send characters */
2464 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2465 atmel_port->tx_stopped = false;
2467 uart_console_write(port, s, count, atmel_console_putchar);
2470 * Finally, wait for transmitter to become empty
2474 status = atmel_uart_readl(port, ATMEL_US_CSR);
2475 } while (!(status & ATMEL_US_TXRDY));
2477 /* Restore PDC transmit status */
2479 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2481 /* set interrupts back the way they were */
2482 atmel_uart_writel(port, ATMEL_US_IER, imr);
2486 * If the port was already initialised (eg, by a boot loader),
2487 * try to determine the current setup.
2489 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2490 int *parity, int *bits)
2492 unsigned int mr, quot;
2495 * If the baud rate generator isn't running, the port wasn't
2496 * initialized by the boot loader.
2498 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2502 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2503 if (mr == ATMEL_US_CHRL_8)
2508 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2509 if (mr == ATMEL_US_PAR_EVEN)
2511 else if (mr == ATMEL_US_PAR_ODD)
2515 * The serial core only rounds down when matching this to a
2516 * supported baud rate. Make sure we don't end up slightly
2517 * lower than one of those, as it would make us fall through
2518 * to a much lower baud rate than we really want.
2520 *baud = port->uartclk / (16 * (quot - 1));
2523 static int __init atmel_console_setup(struct console *co, char *options)
2526 struct uart_port *port = &atmel_ports[co->index].uart;
2527 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2533 if (port->membase == NULL) {
2534 /* Port not initialized yet - delay setup */
2538 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2542 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2543 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2544 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2545 atmel_port->tx_stopped = false;
2548 uart_parse_options(options, &baud, &parity, &bits, &flow);
2550 atmel_console_get_options(port, &baud, &parity, &bits);
2552 return uart_set_options(port, co, baud, parity, bits, flow);
2555 static struct uart_driver atmel_uart;
2557 static struct console atmel_console = {
2558 .name = ATMEL_DEVICENAME,
2559 .write = atmel_console_write,
2560 .device = uart_console_device,
2561 .setup = atmel_console_setup,
2562 .flags = CON_PRINTBUFFER,
2564 .data = &atmel_uart,
2567 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2569 static inline bool atmel_is_console_port(struct uart_port *port)
2571 return port->cons && port->cons->index == port->line;
2575 #define ATMEL_CONSOLE_DEVICE NULL
2577 static inline bool atmel_is_console_port(struct uart_port *port)
2583 static struct uart_driver atmel_uart = {
2584 .owner = THIS_MODULE,
2585 .driver_name = "atmel_serial",
2586 .dev_name = ATMEL_DEVICENAME,
2587 .major = SERIAL_ATMEL_MAJOR,
2588 .minor = MINOR_START,
2589 .nr = ATMEL_MAX_UART,
2590 .cons = ATMEL_CONSOLE_DEVICE,
2594 static bool atmel_serial_clk_will_stop(void)
2596 #ifdef CONFIG_ARCH_AT91
2597 return at91_suspend_entering_slow_clock();
2603 static int atmel_serial_suspend(struct platform_device *pdev,
2606 struct uart_port *port = platform_get_drvdata(pdev);
2607 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2609 if (atmel_is_console_port(port) && console_suspend_enabled) {
2610 /* Drain the TX shifter */
2611 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2616 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2617 /* Cache register values as we won't get a full shutdown/startup
2620 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2621 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2622 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2623 atmel_port->cache.rtor = atmel_uart_readl(port,
2625 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2626 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2627 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2630 /* we can not wake up if we're running on slow clock */
2631 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2632 if (atmel_serial_clk_will_stop()) {
2633 unsigned long flags;
2635 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2636 atmel_port->suspended = true;
2637 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2638 device_set_wakeup_enable(&pdev->dev, 0);
2641 uart_suspend_port(&atmel_uart, port);
2646 static int atmel_serial_resume(struct platform_device *pdev)
2648 struct uart_port *port = platform_get_drvdata(pdev);
2649 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2650 unsigned long flags;
2652 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2653 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2654 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2655 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2656 atmel_uart_writel(port, atmel_port->rtor,
2657 atmel_port->cache.rtor);
2658 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2660 if (atmel_port->fifo_size) {
2661 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2662 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2663 atmel_uart_writel(port, ATMEL_US_FMR,
2664 atmel_port->cache.fmr);
2665 atmel_uart_writel(port, ATMEL_US_FIER,
2666 atmel_port->cache.fimr);
2668 atmel_start_rx(port);
2671 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2672 if (atmel_port->pending) {
2673 atmel_handle_receive(port, atmel_port->pending);
2674 atmel_handle_status(port, atmel_port->pending,
2675 atmel_port->pending_status);
2676 atmel_handle_transmit(port, atmel_port->pending);
2677 atmel_port->pending = 0;
2679 atmel_port->suspended = false;
2680 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2682 uart_resume_port(&atmel_uart, port);
2683 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2688 #define atmel_serial_suspend NULL
2689 #define atmel_serial_resume NULL
2692 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2693 struct platform_device *pdev)
2695 atmel_port->fifo_size = 0;
2696 atmel_port->rts_low = 0;
2697 atmel_port->rts_high = 0;
2699 if (of_property_read_u32(pdev->dev.of_node,
2701 &atmel_port->fifo_size))
2704 if (!atmel_port->fifo_size)
2707 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2708 atmel_port->fifo_size = 0;
2709 dev_err(&pdev->dev, "Invalid FIFO size\n");
2714 * 0 <= rts_low <= rts_high <= fifo_size
2715 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2716 * to flush their internal TX FIFO, commonly up to 16 data, before
2717 * actually stopping to send new data. So we try to set the RTS High
2718 * Threshold to a reasonably high value respecting this 16 data
2719 * empirical rule when possible.
2721 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2722 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2723 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2724 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2726 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2727 atmel_port->fifo_size);
2728 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2729 atmel_port->rts_high);
2730 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2731 atmel_port->rts_low);
2734 static int atmel_serial_probe(struct platform_device *pdev)
2736 struct atmel_uart_port *atmel_port;
2737 struct device_node *np = pdev->dev.of_node;
2742 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2744 ret = of_alias_get_id(np, "serial");
2746 /* port id not found in platform data nor device-tree aliases:
2747 * auto-enumerate it */
2748 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2750 if (ret >= ATMEL_MAX_UART) {
2755 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2756 /* port already in use */
2761 atmel_port = &atmel_ports[ret];
2762 atmel_port->backup_imr = 0;
2763 atmel_port->uart.line = ret;
2764 atmel_serial_probe_fifos(atmel_port, pdev);
2766 atomic_set(&atmel_port->tasklet_shutdown, 0);
2767 spin_lock_init(&atmel_port->lock_suspended);
2769 ret = atmel_init_port(atmel_port, pdev);
2773 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2774 if (IS_ERR(atmel_port->gpios)) {
2775 ret = PTR_ERR(atmel_port->gpios);
2779 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2781 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2782 sizeof(struct atmel_uart_char),
2785 goto err_alloc_ring;
2786 atmel_port->rx_ring.buf = data;
2789 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2791 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2795 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2796 if (atmel_is_console_port(&atmel_port->uart)
2797 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2799 * The serial core enabled the clock for us, so undo
2800 * the clk_prepare_enable() in atmel_console_setup()
2802 clk_disable_unprepare(atmel_port->clk);
2806 device_init_wakeup(&pdev->dev, 1);
2807 platform_set_drvdata(pdev, atmel_port);
2810 * The peripheral clock has been disabled by atmel_init_port():
2811 * enable it before accessing I/O registers
2813 clk_prepare_enable(atmel_port->clk);
2815 if (rs485_enabled) {
2816 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2817 ATMEL_US_USMODE_NORMAL);
2818 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2823 * Get port name of usart or uart
2825 atmel_get_ip_name(&atmel_port->uart);
2828 * The peripheral clock can now safely be disabled till the port
2831 clk_disable_unprepare(atmel_port->clk);
2836 kfree(atmel_port->rx_ring.buf);
2837 atmel_port->rx_ring.buf = NULL;
2839 if (!atmel_is_console_port(&atmel_port->uart)) {
2840 clk_put(atmel_port->clk);
2841 atmel_port->clk = NULL;
2844 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2850 * Even if the driver is not modular, it makes sense to be able to
2851 * unbind a device: there can be many bound devices, and there are
2852 * situations where dynamic binding and unbinding can be useful.
2854 * For example, a connected device can require a specific firmware update
2855 * protocol that needs bitbanging on IO lines, but use the regular serial
2856 * port in the normal case.
2858 static int atmel_serial_remove(struct platform_device *pdev)
2860 struct uart_port *port = platform_get_drvdata(pdev);
2861 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2864 tasklet_kill(&atmel_port->tasklet_rx);
2865 tasklet_kill(&atmel_port->tasklet_tx);
2867 device_init_wakeup(&pdev->dev, 0);
2869 ret = uart_remove_one_port(&atmel_uart, port);
2871 kfree(atmel_port->rx_ring.buf);
2873 /* "port" is allocated statically, so we shouldn't free it */
2875 clear_bit(port->line, atmel_ports_in_use);
2877 clk_put(atmel_port->clk);
2878 atmel_port->clk = NULL;
2883 static struct platform_driver atmel_serial_driver = {
2884 .probe = atmel_serial_probe,
2885 .remove = atmel_serial_remove,
2886 .suspend = atmel_serial_suspend,
2887 .resume = atmel_serial_resume,
2889 .name = "atmel_usart",
2890 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2894 static int __init atmel_serial_init(void)
2898 ret = uart_register_driver(&atmel_uart);
2902 ret = platform_driver_register(&atmel_serial_driver);
2904 uart_unregister_driver(&atmel_uart);
2908 device_initcall(atmel_serial_init);