1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for AMBA serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
19 #include <linux/module.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/sysrq.h>
24 #include <linux/device.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/serial.h>
31 #include <linux/clk.h>
32 #include <linux/slab.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/scatterlist.h>
36 #include <linux/delay.h>
37 #include <linux/types.h>
39 #include <linux/of_device.h>
40 #include <linux/pinctrl/consumer.h>
41 #include <linux/sizes.h>
43 #include <linux/acpi.h>
45 #include "amba-pl011.h"
49 #define SERIAL_AMBA_MAJOR 204
50 #define SERIAL_AMBA_MINOR 64
51 #define SERIAL_AMBA_NR UART_NR
53 #define AMBA_ISR_PASS_LIMIT 256
55 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
56 #define UART_DUMMY_DR_RX (1 << 16)
58 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
59 [REG_DR] = UART01x_DR,
60 [REG_FR] = UART01x_FR,
61 [REG_LCRH_RX] = UART011_LCRH,
62 [REG_LCRH_TX] = UART011_LCRH,
63 [REG_IBRD] = UART011_IBRD,
64 [REG_FBRD] = UART011_FBRD,
65 [REG_CR] = UART011_CR,
66 [REG_IFLS] = UART011_IFLS,
67 [REG_IMSC] = UART011_IMSC,
68 [REG_RIS] = UART011_RIS,
69 [REG_MIS] = UART011_MIS,
70 [REG_ICR] = UART011_ICR,
71 [REG_DMACR] = UART011_DMACR,
74 /* There is by now at least one vendor with differing details, so handle it */
76 const u16 *reg_offset;
86 bool cts_event_workaround;
90 unsigned int (*get_fifosize)(struct amba_device *dev);
93 static unsigned int get_fifosize_arm(struct amba_device *dev)
95 return amba_rev(dev) < 3 ? 16 : 32;
98 static struct vendor_data vendor_arm = {
99 .reg_offset = pl011_std_offsets,
100 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
101 .fr_busy = UART01x_FR_BUSY,
102 .fr_dsr = UART01x_FR_DSR,
103 .fr_cts = UART01x_FR_CTS,
104 .fr_ri = UART011_FR_RI,
105 .oversampling = false,
106 .dma_threshold = false,
107 .cts_event_workaround = false,
108 .always_enabled = false,
109 .fixed_options = false,
110 .get_fifosize = get_fifosize_arm,
113 static const struct vendor_data vendor_sbsa = {
114 .reg_offset = pl011_std_offsets,
115 .fr_busy = UART01x_FR_BUSY,
116 .fr_dsr = UART01x_FR_DSR,
117 .fr_cts = UART01x_FR_CTS,
118 .fr_ri = UART011_FR_RI,
120 .oversampling = false,
121 .dma_threshold = false,
122 .cts_event_workaround = false,
123 .always_enabled = true,
124 .fixed_options = true,
127 #ifdef CONFIG_ACPI_SPCR_TABLE
128 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
129 .reg_offset = pl011_std_offsets,
130 .fr_busy = UART011_FR_TXFE,
131 .fr_dsr = UART01x_FR_DSR,
132 .fr_cts = UART01x_FR_CTS,
133 .fr_ri = UART011_FR_RI,
134 .inv_fr = UART011_FR_TXFE,
136 .oversampling = false,
137 .dma_threshold = false,
138 .cts_event_workaround = false,
139 .always_enabled = true,
140 .fixed_options = true,
144 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
145 [REG_DR] = UART01x_DR,
146 [REG_ST_DMAWM] = ST_UART011_DMAWM,
147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
148 [REG_FR] = UART01x_FR,
149 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
150 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
151 [REG_IBRD] = UART011_IBRD,
152 [REG_FBRD] = UART011_FBRD,
153 [REG_CR] = UART011_CR,
154 [REG_IFLS] = UART011_IFLS,
155 [REG_IMSC] = UART011_IMSC,
156 [REG_RIS] = UART011_RIS,
157 [REG_MIS] = UART011_MIS,
158 [REG_ICR] = UART011_ICR,
159 [REG_DMACR] = UART011_DMACR,
160 [REG_ST_XFCR] = ST_UART011_XFCR,
161 [REG_ST_XON1] = ST_UART011_XON1,
162 [REG_ST_XON2] = ST_UART011_XON2,
163 [REG_ST_XOFF1] = ST_UART011_XOFF1,
164 [REG_ST_XOFF2] = ST_UART011_XOFF2,
165 [REG_ST_ITCR] = ST_UART011_ITCR,
166 [REG_ST_ITIP] = ST_UART011_ITIP,
167 [REG_ST_ABCR] = ST_UART011_ABCR,
168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
171 static unsigned int get_fifosize_st(struct amba_device *dev)
176 static struct vendor_data vendor_st = {
177 .reg_offset = pl011_st_offsets,
178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
179 .fr_busy = UART01x_FR_BUSY,
180 .fr_dsr = UART01x_FR_DSR,
181 .fr_cts = UART01x_FR_CTS,
182 .fr_ri = UART011_FR_RI,
183 .oversampling = true,
184 .dma_threshold = true,
185 .cts_event_workaround = true,
186 .always_enabled = false,
187 .fixed_options = false,
188 .get_fifosize = get_fifosize_st,
191 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
192 [REG_DR] = ZX_UART011_DR,
193 [REG_FR] = ZX_UART011_FR,
194 [REG_LCRH_RX] = ZX_UART011_LCRH,
195 [REG_LCRH_TX] = ZX_UART011_LCRH,
196 [REG_IBRD] = ZX_UART011_IBRD,
197 [REG_FBRD] = ZX_UART011_FBRD,
198 [REG_CR] = ZX_UART011_CR,
199 [REG_IFLS] = ZX_UART011_IFLS,
200 [REG_IMSC] = ZX_UART011_IMSC,
201 [REG_RIS] = ZX_UART011_RIS,
202 [REG_MIS] = ZX_UART011_MIS,
203 [REG_ICR] = ZX_UART011_ICR,
204 [REG_DMACR] = ZX_UART011_DMACR,
207 static unsigned int get_fifosize_zte(struct amba_device *dev)
212 static struct vendor_data vendor_zte = {
213 .reg_offset = pl011_zte_offsets,
215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
216 .fr_busy = ZX_UART01x_FR_BUSY,
217 .fr_dsr = ZX_UART01x_FR_DSR,
218 .fr_cts = ZX_UART01x_FR_CTS,
219 .fr_ri = ZX_UART011_FR_RI,
220 .get_fifosize = get_fifosize_zte,
223 /* Deals with DMA transactions */
225 struct pl011_dmabuf {
231 struct pl011_dmarx_data {
232 struct dma_chan *chan;
233 struct completion complete;
235 struct pl011_dmabuf dbuf_a;
236 struct pl011_dmabuf dbuf_b;
239 struct timer_list timer;
240 unsigned int last_residue;
241 unsigned long last_jiffies;
243 unsigned int poll_rate;
244 unsigned int poll_timeout;
247 struct pl011_dmatx_data {
248 struct dma_chan *chan;
256 * We wrap our port structure around the generic uart_port.
258 struct uart_amba_port {
259 struct uart_port port;
260 const u16 *reg_offset;
262 const struct vendor_data *vendor;
263 unsigned int dmacr; /* dma control reg */
264 unsigned int im; /* interrupt mask */
265 unsigned int old_status;
266 unsigned int fifosize; /* vendor-specific */
267 unsigned int old_cr; /* state during shutdown */
268 unsigned int fixed_baud; /* vendor-set fixed baud rate */
270 #ifdef CONFIG_DMA_ENGINE
274 struct pl011_dmarx_data dmarx;
275 struct pl011_dmatx_data dmatx;
280 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
283 return uap->reg_offset[reg];
286 static unsigned int pl011_read(const struct uart_amba_port *uap,
289 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
291 return (uap->port.iotype == UPIO_MEM32) ?
292 readl_relaxed(addr) : readw_relaxed(addr);
295 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
298 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
300 if (uap->port.iotype == UPIO_MEM32)
301 writel_relaxed(val, addr);
303 writew_relaxed(val, addr);
307 * Reads up to 256 characters from the FIFO or until it's empty and
308 * inserts them into the TTY layer. Returns the number of characters
309 * read from the FIFO.
311 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
313 unsigned int ch, flag, fifotaken;
317 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
318 status = pl011_read(uap, REG_FR);
319 if (status & UART01x_FR_RXFE)
322 /* Take chars from the FIFO and update status */
323 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
325 uap->port.icount.rx++;
327 if (unlikely(ch & UART_DR_ERROR)) {
328 if (ch & UART011_DR_BE) {
329 ch &= ~(UART011_DR_FE | UART011_DR_PE);
330 uap->port.icount.brk++;
331 if (uart_handle_break(&uap->port))
333 } else if (ch & UART011_DR_PE)
334 uap->port.icount.parity++;
335 else if (ch & UART011_DR_FE)
336 uap->port.icount.frame++;
337 if (ch & UART011_DR_OE)
338 uap->port.icount.overrun++;
340 ch &= uap->port.read_status_mask;
342 if (ch & UART011_DR_BE)
344 else if (ch & UART011_DR_PE)
346 else if (ch & UART011_DR_FE)
350 spin_unlock(&uap->port.lock);
351 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
352 spin_lock(&uap->port.lock);
355 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
363 * All the DMA operation mode stuff goes inside this ifdef.
364 * This assumes that you have a generic DMA device interface,
365 * no custom DMA interfaces are supported.
367 #ifdef CONFIG_DMA_ENGINE
369 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
371 static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db,
372 enum dma_data_direction dir)
374 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE,
375 &db->dma, GFP_KERNEL);
378 db->len = PL011_DMA_BUFFER_SIZE;
383 static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db,
384 enum dma_data_direction dir)
387 dma_free_coherent(chan->device->dev,
388 PL011_DMA_BUFFER_SIZE, db->buf, db->dma);
392 static void pl011_dma_probe(struct uart_amba_port *uap)
394 /* DMA is the sole user of the platform data right now */
395 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
396 struct device *dev = uap->port.dev;
397 struct dma_slave_config tx_conf = {
398 .dst_addr = uap->port.mapbase +
399 pl011_reg_to_offset(uap, REG_DR),
400 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
401 .direction = DMA_MEM_TO_DEV,
402 .dst_maxburst = uap->fifosize >> 1,
405 struct dma_chan *chan;
408 uap->dma_probed = true;
409 chan = dma_request_chan(dev, "tx");
411 if (PTR_ERR(chan) == -EPROBE_DEFER) {
412 uap->dma_probed = false;
416 /* We need platform data */
417 if (!plat || !plat->dma_filter) {
418 dev_info(uap->port.dev, "no DMA platform data\n");
422 /* Try to acquire a generic DMA engine slave TX channel */
424 dma_cap_set(DMA_SLAVE, mask);
426 chan = dma_request_channel(mask, plat->dma_filter,
429 dev_err(uap->port.dev, "no TX DMA channel!\n");
434 dmaengine_slave_config(chan, &tx_conf);
435 uap->dmatx.chan = chan;
437 dev_info(uap->port.dev, "DMA channel TX %s\n",
438 dma_chan_name(uap->dmatx.chan));
440 /* Optionally make use of an RX channel as well */
441 chan = dma_request_slave_channel(dev, "rx");
443 if (!chan && plat && plat->dma_rx_param) {
444 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
447 dev_err(uap->port.dev, "no RX DMA channel!\n");
453 struct dma_slave_config rx_conf = {
454 .src_addr = uap->port.mapbase +
455 pl011_reg_to_offset(uap, REG_DR),
456 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
457 .direction = DMA_DEV_TO_MEM,
458 .src_maxburst = uap->fifosize >> 2,
461 struct dma_slave_caps caps;
464 * Some DMA controllers provide information on their capabilities.
465 * If the controller does, check for suitable residue processing
466 * otherwise assime all is well.
468 if (0 == dma_get_slave_caps(chan, &caps)) {
469 if (caps.residue_granularity ==
470 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
471 dma_release_channel(chan);
472 dev_info(uap->port.dev,
473 "RX DMA disabled - no residue processing\n");
477 dmaengine_slave_config(chan, &rx_conf);
478 uap->dmarx.chan = chan;
480 uap->dmarx.auto_poll_rate = false;
481 if (plat && plat->dma_rx_poll_enable) {
482 /* Set poll rate if specified. */
483 if (plat->dma_rx_poll_rate) {
484 uap->dmarx.auto_poll_rate = false;
485 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
488 * 100 ms defaults to poll rate if not
489 * specified. This will be adjusted with
490 * the baud rate at set_termios.
492 uap->dmarx.auto_poll_rate = true;
493 uap->dmarx.poll_rate = 100;
495 /* 3 secs defaults poll_timeout if not specified. */
496 if (plat->dma_rx_poll_timeout)
497 uap->dmarx.poll_timeout =
498 plat->dma_rx_poll_timeout;
500 uap->dmarx.poll_timeout = 3000;
501 } else if (!plat && dev->of_node) {
502 uap->dmarx.auto_poll_rate = of_property_read_bool(
503 dev->of_node, "auto-poll");
504 if (uap->dmarx.auto_poll_rate) {
507 if (0 == of_property_read_u32(dev->of_node,
509 uap->dmarx.poll_rate = x;
511 uap->dmarx.poll_rate = 100;
512 if (0 == of_property_read_u32(dev->of_node,
513 "poll-timeout-ms", &x))
514 uap->dmarx.poll_timeout = x;
516 uap->dmarx.poll_timeout = 3000;
519 dev_info(uap->port.dev, "DMA channel RX %s\n",
520 dma_chan_name(uap->dmarx.chan));
524 static void pl011_dma_remove(struct uart_amba_port *uap)
527 dma_release_channel(uap->dmatx.chan);
529 dma_release_channel(uap->dmarx.chan);
532 /* Forward declare these for the refill routine */
533 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
534 static void pl011_start_tx_pio(struct uart_amba_port *uap);
537 * The current DMA TX buffer has been sent.
538 * Try to queue up another DMA buffer.
540 static void pl011_dma_tx_callback(void *data)
542 struct uart_amba_port *uap = data;
543 struct pl011_dmatx_data *dmatx = &uap->dmatx;
547 spin_lock_irqsave(&uap->port.lock, flags);
548 if (uap->dmatx.queued)
549 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma,
550 dmatx->len, DMA_TO_DEVICE);
553 uap->dmacr = dmacr & ~UART011_TXDMAE;
554 pl011_write(uap->dmacr, uap, REG_DMACR);
557 * If TX DMA was disabled, it means that we've stopped the DMA for
558 * some reason (eg, XOFF received, or we want to send an X-char.)
560 * Note: we need to be careful here of a potential race between DMA
561 * and the rest of the driver - if the driver disables TX DMA while
562 * a TX buffer completing, we must update the tx queued status to
563 * get further refills (hence we check dmacr).
565 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
566 uart_circ_empty(&uap->port.state->xmit)) {
567 uap->dmatx.queued = false;
568 spin_unlock_irqrestore(&uap->port.lock, flags);
572 if (pl011_dma_tx_refill(uap) <= 0)
574 * We didn't queue a DMA buffer for some reason, but we
575 * have data pending to be sent. Re-enable the TX IRQ.
577 pl011_start_tx_pio(uap);
579 spin_unlock_irqrestore(&uap->port.lock, flags);
583 * Try to refill the TX DMA buffer.
584 * Locking: called with port lock held and IRQs disabled.
586 * 1 if we queued up a TX DMA buffer.
587 * 0 if we didn't want to handle this by DMA
590 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
592 struct pl011_dmatx_data *dmatx = &uap->dmatx;
593 struct dma_chan *chan = dmatx->chan;
594 struct dma_device *dma_dev = chan->device;
595 struct dma_async_tx_descriptor *desc;
596 struct circ_buf *xmit = &uap->port.state->xmit;
600 * Try to avoid the overhead involved in using DMA if the
601 * transaction fits in the first half of the FIFO, by using
602 * the standard interrupt handling. This ensures that we
603 * issue a uart_write_wakeup() at the appropriate time.
605 count = uart_circ_chars_pending(xmit);
606 if (count < (uap->fifosize >> 1)) {
607 uap->dmatx.queued = false;
612 * Bodge: don't send the last character by DMA, as this
613 * will prevent XON from notifying us to restart DMA.
617 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
618 if (count > PL011_DMA_BUFFER_SIZE)
619 count = PL011_DMA_BUFFER_SIZE;
621 if (xmit->tail < xmit->head)
622 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
624 size_t first = UART_XMIT_SIZE - xmit->tail;
629 second = count - first;
631 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
633 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
637 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count,
639 if (dmatx->dma == DMA_MAPPING_ERROR) {
640 uap->dmatx.queued = false;
641 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
645 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV,
646 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
648 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE);
649 uap->dmatx.queued = false;
651 * If DMA cannot be used right now, we complete this
652 * transaction via IRQ and let the TTY layer retry.
654 dev_dbg(uap->port.dev, "TX DMA busy\n");
658 /* Some data to go along to the callback */
659 desc->callback = pl011_dma_tx_callback;
660 desc->callback_param = uap;
662 /* All errors should happen at prepare time */
663 dmaengine_submit(desc);
665 /* Fire the DMA transaction */
666 dma_dev->device_issue_pending(chan);
668 uap->dmacr |= UART011_TXDMAE;
669 pl011_write(uap->dmacr, uap, REG_DMACR);
670 uap->dmatx.queued = true;
673 * Now we know that DMA will fire, so advance the ring buffer
674 * with the stuff we just dispatched.
676 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
677 uap->port.icount.tx += count;
679 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
680 uart_write_wakeup(&uap->port);
686 * We received a transmit interrupt without a pending X-char but with
687 * pending characters.
688 * Locking: called with port lock held and IRQs disabled.
690 * false if we want to use PIO to transmit
691 * true if we queued a DMA buffer
693 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
695 if (!uap->using_tx_dma)
699 * If we already have a TX buffer queued, but received a
700 * TX interrupt, it will be because we've just sent an X-char.
701 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
703 if (uap->dmatx.queued) {
704 uap->dmacr |= UART011_TXDMAE;
705 pl011_write(uap->dmacr, uap, REG_DMACR);
706 uap->im &= ~UART011_TXIM;
707 pl011_write(uap->im, uap, REG_IMSC);
712 * We don't have a TX buffer queued, so try to queue one.
713 * If we successfully queued a buffer, mask the TX IRQ.
715 if (pl011_dma_tx_refill(uap) > 0) {
716 uap->im &= ~UART011_TXIM;
717 pl011_write(uap->im, uap, REG_IMSC);
724 * Stop the DMA transmit (eg, due to received XOFF).
725 * Locking: called with port lock held and IRQs disabled.
727 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
729 if (uap->dmatx.queued) {
730 uap->dmacr &= ~UART011_TXDMAE;
731 pl011_write(uap->dmacr, uap, REG_DMACR);
736 * Try to start a DMA transmit, or in the case of an XON/OFF
737 * character queued for send, try to get that character out ASAP.
738 * Locking: called with port lock held and IRQs disabled.
740 * false if we want the TX IRQ to be enabled
741 * true if we have a buffer queued
743 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
747 if (!uap->using_tx_dma)
750 if (!uap->port.x_char) {
751 /* no X-char, try to push chars out in DMA mode */
754 if (!uap->dmatx.queued) {
755 if (pl011_dma_tx_refill(uap) > 0) {
756 uap->im &= ~UART011_TXIM;
757 pl011_write(uap->im, uap, REG_IMSC);
760 } else if (!(uap->dmacr & UART011_TXDMAE)) {
761 uap->dmacr |= UART011_TXDMAE;
762 pl011_write(uap->dmacr, uap, REG_DMACR);
768 * We have an X-char to send. Disable DMA to prevent it loading
769 * the TX fifo, and then see if we can stuff it into the FIFO.
772 uap->dmacr &= ~UART011_TXDMAE;
773 pl011_write(uap->dmacr, uap, REG_DMACR);
775 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
777 * No space in the FIFO, so enable the transmit interrupt
778 * so we know when there is space. Note that once we've
779 * loaded the character, we should just re-enable DMA.
784 pl011_write(uap->port.x_char, uap, REG_DR);
785 uap->port.icount.tx++;
786 uap->port.x_char = 0;
788 /* Success - restore the DMA state */
790 pl011_write(dmacr, uap, REG_DMACR);
796 * Flush the transmit buffer.
797 * Locking: called with port lock held and IRQs disabled.
799 static void pl011_dma_flush_buffer(struct uart_port *port)
800 __releases(&uap->port.lock)
801 __acquires(&uap->port.lock)
803 struct uart_amba_port *uap =
804 container_of(port, struct uart_amba_port, port);
806 if (!uap->using_tx_dma)
809 dmaengine_terminate_async(uap->dmatx.chan);
811 if (uap->dmatx.queued) {
812 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma,
813 uap->dmatx.len, DMA_TO_DEVICE);
814 uap->dmatx.queued = false;
815 uap->dmacr &= ~UART011_TXDMAE;
816 pl011_write(uap->dmacr, uap, REG_DMACR);
820 static void pl011_dma_rx_callback(void *data);
822 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
824 struct dma_chan *rxchan = uap->dmarx.chan;
825 struct pl011_dmarx_data *dmarx = &uap->dmarx;
826 struct dma_async_tx_descriptor *desc;
827 struct pl011_dmabuf *dbuf;
832 /* Start the RX DMA job */
833 dbuf = uap->dmarx.use_buf_b ?
834 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
835 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len,
837 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
839 * If the DMA engine is busy and cannot prepare a
840 * channel, no big deal, the driver will fall back
841 * to interrupt mode as a result of this error code.
844 uap->dmarx.running = false;
845 dmaengine_terminate_all(rxchan);
849 /* Some data to go along to the callback */
850 desc->callback = pl011_dma_rx_callback;
851 desc->callback_param = uap;
852 dmarx->cookie = dmaengine_submit(desc);
853 dma_async_issue_pending(rxchan);
855 uap->dmacr |= UART011_RXDMAE;
856 pl011_write(uap->dmacr, uap, REG_DMACR);
857 uap->dmarx.running = true;
859 uap->im &= ~UART011_RXIM;
860 pl011_write(uap->im, uap, REG_IMSC);
866 * This is called when either the DMA job is complete, or
867 * the FIFO timeout interrupt occurred. This must be called
868 * with the port spinlock uap->port.lock held.
870 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
871 u32 pending, bool use_buf_b,
874 struct tty_port *port = &uap->port.state->port;
875 struct pl011_dmabuf *dbuf = use_buf_b ?
876 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
878 u32 fifotaken = 0; /* only used for vdbg() */
880 struct pl011_dmarx_data *dmarx = &uap->dmarx;
883 if (uap->dmarx.poll_rate) {
884 /* The data can be taken by polling */
885 dmataken = dbuf->len - dmarx->last_residue;
886 /* Recalculate the pending size */
887 if (pending >= dmataken)
891 /* Pick the remain data from the DMA */
895 * First take all chars in the DMA pipe, then look in the FIFO.
896 * Note that tty_insert_flip_buf() tries to take as many chars
899 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken,
902 uap->port.icount.rx += dma_count;
903 if (dma_count < pending)
904 dev_warn(uap->port.dev,
905 "couldn't insert all characters (TTY is full?)\n");
908 /* Reset the last_residue for Rx DMA poll */
909 if (uap->dmarx.poll_rate)
910 dmarx->last_residue = dbuf->len;
913 * Only continue with trying to read the FIFO if all DMA chars have
916 if (dma_count == pending && readfifo) {
917 /* Clear any error flags */
918 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
919 UART011_FEIS, uap, REG_ICR);
922 * If we read all the DMA'd characters, and we had an
923 * incomplete buffer, that could be due to an rx error, or
924 * maybe we just timed out. Read any pending chars and check
927 * Error conditions will only occur in the FIFO, these will
928 * trigger an immediate interrupt and stop the DMA job, so we
929 * will always find the error in the FIFO, never in the DMA
932 fifotaken = pl011_fifo_to_tty(uap);
935 spin_unlock(&uap->port.lock);
936 dev_vdbg(uap->port.dev,
937 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
938 dma_count, fifotaken);
939 tty_flip_buffer_push(port);
940 spin_lock(&uap->port.lock);
943 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
945 struct pl011_dmarx_data *dmarx = &uap->dmarx;
946 struct dma_chan *rxchan = dmarx->chan;
947 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?
948 &dmarx->dbuf_b : &dmarx->dbuf_a;
950 struct dma_tx_state state;
951 enum dma_status dmastat;
954 * Pause the transfer so we can trust the current counter,
955 * do this before we pause the PL011 block, else we may
958 if (dmaengine_pause(rxchan))
959 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
960 dmastat = rxchan->device->device_tx_status(rxchan,
961 dmarx->cookie, &state);
962 if (dmastat != DMA_PAUSED)
963 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
965 /* Disable RX DMA - incoming data will wait in the FIFO */
966 uap->dmacr &= ~UART011_RXDMAE;
967 pl011_write(uap->dmacr, uap, REG_DMACR);
968 uap->dmarx.running = false;
970 pending = dbuf->len - state.residue;
971 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
972 /* Then we terminate the transfer - we now know our residue */
973 dmaengine_terminate_all(rxchan);
976 * This will take the chars we have so far and insert
977 * into the framework.
979 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
981 /* Switch buffer & re-trigger DMA job */
982 dmarx->use_buf_b = !dmarx->use_buf_b;
983 if (pl011_dma_rx_trigger_dma(uap)) {
984 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
985 "fall back to interrupt mode\n");
986 uap->im |= UART011_RXIM;
987 pl011_write(uap->im, uap, REG_IMSC);
991 static void pl011_dma_rx_callback(void *data)
993 struct uart_amba_port *uap = data;
994 struct pl011_dmarx_data *dmarx = &uap->dmarx;
995 struct dma_chan *rxchan = dmarx->chan;
996 bool lastbuf = dmarx->use_buf_b;
997 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?
998 &dmarx->dbuf_b : &dmarx->dbuf_a;
1000 struct dma_tx_state state;
1004 * This completion interrupt occurs typically when the
1005 * RX buffer is totally stuffed but no timeout has yet
1006 * occurred. When that happens, we just want the RX
1007 * routine to flush out the secondary DMA buffer while
1008 * we immediately trigger the next DMA job.
1010 spin_lock_irq(&uap->port.lock);
1012 * Rx data can be taken by the UART interrupts during
1013 * the DMA irq handler. So we check the residue here.
1015 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1016 pending = dbuf->len - state.residue;
1017 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1018 /* Then we terminate the transfer - we now know our residue */
1019 dmaengine_terminate_all(rxchan);
1021 uap->dmarx.running = false;
1022 dmarx->use_buf_b = !lastbuf;
1023 ret = pl011_dma_rx_trigger_dma(uap);
1025 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1026 spin_unlock_irq(&uap->port.lock);
1028 * Do this check after we picked the DMA chars so we don't
1029 * get some IRQ immediately from RX.
1032 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1033 "fall back to interrupt mode\n");
1034 uap->im |= UART011_RXIM;
1035 pl011_write(uap->im, uap, REG_IMSC);
1040 * Stop accepting received characters, when we're shutting down or
1041 * suspending this port.
1042 * Locking: called with port lock held and IRQs disabled.
1044 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1046 if (!uap->using_rx_dma)
1049 /* FIXME. Just disable the DMA enable */
1050 uap->dmacr &= ~UART011_RXDMAE;
1051 pl011_write(uap->dmacr, uap, REG_DMACR);
1055 * Timer handler for Rx DMA polling.
1056 * Every polling, It checks the residue in the dma buffer and transfer
1057 * data to the tty. Also, last_residue is updated for the next polling.
1059 static void pl011_dma_rx_poll(struct timer_list *t)
1061 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1062 struct tty_port *port = &uap->port.state->port;
1063 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1064 struct dma_chan *rxchan = uap->dmarx.chan;
1065 unsigned long flags = 0;
1066 unsigned int dmataken = 0;
1067 unsigned int size = 0;
1068 struct pl011_dmabuf *dbuf;
1070 struct dma_tx_state state;
1072 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
1073 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1074 if (likely(state.residue < dmarx->last_residue)) {
1075 dmataken = dbuf->len - dmarx->last_residue;
1076 size = dmarx->last_residue - state.residue;
1077 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken,
1079 if (dma_count == size)
1080 dmarx->last_residue = state.residue;
1081 dmarx->last_jiffies = jiffies;
1083 tty_flip_buffer_push(port);
1086 * If no data is received in poll_timeout, the driver will fall back
1087 * to interrupt mode. We will retrigger DMA at the first interrupt.
1089 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1090 > uap->dmarx.poll_timeout) {
1092 spin_lock_irqsave(&uap->port.lock, flags);
1093 pl011_dma_rx_stop(uap);
1094 uap->im |= UART011_RXIM;
1095 pl011_write(uap->im, uap, REG_IMSC);
1096 spin_unlock_irqrestore(&uap->port.lock, flags);
1098 uap->dmarx.running = false;
1099 dmaengine_terminate_all(rxchan);
1100 del_timer(&uap->dmarx.timer);
1102 mod_timer(&uap->dmarx.timer,
1103 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1107 static void pl011_dma_startup(struct uart_amba_port *uap)
1111 if (!uap->dma_probed)
1112 pl011_dma_probe(uap);
1114 if (!uap->dmatx.chan)
1117 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1118 if (!uap->dmatx.buf) {
1119 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1120 uap->port.fifosize = uap->fifosize;
1124 uap->dmatx.len = PL011_DMA_BUFFER_SIZE;
1126 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1127 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1128 uap->using_tx_dma = true;
1130 if (!uap->dmarx.chan)
1133 /* Allocate and map DMA RX buffers */
1134 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1137 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1138 "RX buffer A", ret);
1142 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b,
1145 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1146 "RX buffer B", ret);
1147 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1152 uap->using_rx_dma = true;
1155 /* Turn on DMA error (RX/TX will be enabled on demand) */
1156 uap->dmacr |= UART011_DMAONERR;
1157 pl011_write(uap->dmacr, uap, REG_DMACR);
1160 * ST Micro variants has some specific dma burst threshold
1161 * compensation. Set this to 16 bytes, so burst will only
1162 * be issued above/below 16 bytes.
1164 if (uap->vendor->dma_threshold)
1165 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1168 if (uap->using_rx_dma) {
1169 if (pl011_dma_rx_trigger_dma(uap))
1170 dev_dbg(uap->port.dev, "could not trigger initial "
1171 "RX DMA job, fall back to interrupt mode\n");
1172 if (uap->dmarx.poll_rate) {
1173 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1174 mod_timer(&uap->dmarx.timer,
1176 msecs_to_jiffies(uap->dmarx.poll_rate));
1177 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1178 uap->dmarx.last_jiffies = jiffies;
1183 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1185 if (!(uap->using_tx_dma || uap->using_rx_dma))
1188 /* Disable RX and TX DMA */
1189 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1192 spin_lock_irq(&uap->port.lock);
1193 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1194 pl011_write(uap->dmacr, uap, REG_DMACR);
1195 spin_unlock_irq(&uap->port.lock);
1197 if (uap->using_tx_dma) {
1198 /* In theory, this should already be done by pl011_dma_flush_buffer */
1199 dmaengine_terminate_all(uap->dmatx.chan);
1200 if (uap->dmatx.queued) {
1201 dma_unmap_single(uap->dmatx.chan->device->dev,
1202 uap->dmatx.dma, uap->dmatx.len,
1204 uap->dmatx.queued = false;
1207 kfree(uap->dmatx.buf);
1208 uap->using_tx_dma = false;
1211 if (uap->using_rx_dma) {
1212 dmaengine_terminate_all(uap->dmarx.chan);
1213 /* Clean up the RX DMA */
1214 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE);
1215 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE);
1216 if (uap->dmarx.poll_rate)
1217 del_timer_sync(&uap->dmarx.timer);
1218 uap->using_rx_dma = false;
1222 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1224 return uap->using_rx_dma;
1227 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1229 return uap->using_rx_dma && uap->dmarx.running;
1233 /* Blank functions if the DMA engine is not available */
1234 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1238 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1242 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1246 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1251 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1255 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1260 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1264 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1268 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1273 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1278 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1283 #define pl011_dma_flush_buffer NULL
1286 static void pl011_stop_tx(struct uart_port *port)
1288 struct uart_amba_port *uap =
1289 container_of(port, struct uart_amba_port, port);
1291 uap->im &= ~UART011_TXIM;
1292 pl011_write(uap->im, uap, REG_IMSC);
1293 pl011_dma_tx_stop(uap);
1296 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1298 /* Start TX with programmed I/O only (no DMA) */
1299 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1301 if (pl011_tx_chars(uap, false)) {
1302 uap->im |= UART011_TXIM;
1303 pl011_write(uap->im, uap, REG_IMSC);
1307 static void pl011_start_tx(struct uart_port *port)
1309 struct uart_amba_port *uap =
1310 container_of(port, struct uart_amba_port, port);
1312 if (!pl011_dma_tx_start(uap))
1313 pl011_start_tx_pio(uap);
1316 static void pl011_stop_rx(struct uart_port *port)
1318 struct uart_amba_port *uap =
1319 container_of(port, struct uart_amba_port, port);
1321 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1322 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1323 pl011_write(uap->im, uap, REG_IMSC);
1325 pl011_dma_rx_stop(uap);
1328 static void pl011_throttle_rx(struct uart_port *port)
1330 unsigned long flags;
1332 spin_lock_irqsave(&port->lock, flags);
1333 pl011_stop_rx(port);
1334 spin_unlock_irqrestore(&port->lock, flags);
1337 static void pl011_enable_ms(struct uart_port *port)
1339 struct uart_amba_port *uap =
1340 container_of(port, struct uart_amba_port, port);
1342 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1343 pl011_write(uap->im, uap, REG_IMSC);
1346 static void pl011_rx_chars(struct uart_amba_port *uap)
1347 __releases(&uap->port.lock)
1348 __acquires(&uap->port.lock)
1350 pl011_fifo_to_tty(uap);
1352 spin_unlock(&uap->port.lock);
1353 tty_flip_buffer_push(&uap->port.state->port);
1355 * If we were temporarily out of DMA mode for a while,
1356 * attempt to switch back to DMA mode again.
1358 if (pl011_dma_rx_available(uap)) {
1359 if (pl011_dma_rx_trigger_dma(uap)) {
1360 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1361 "fall back to interrupt mode again\n");
1362 uap->im |= UART011_RXIM;
1363 pl011_write(uap->im, uap, REG_IMSC);
1365 #ifdef CONFIG_DMA_ENGINE
1366 /* Start Rx DMA poll */
1367 if (uap->dmarx.poll_rate) {
1368 uap->dmarx.last_jiffies = jiffies;
1369 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1370 mod_timer(&uap->dmarx.timer,
1372 msecs_to_jiffies(uap->dmarx.poll_rate));
1377 spin_lock(&uap->port.lock);
1380 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1383 if (unlikely(!from_irq) &&
1384 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1385 return false; /* unable to transmit character */
1387 pl011_write(c, uap, REG_DR);
1388 uap->port.icount.tx++;
1393 /* Returns true if tx interrupts have to be (kept) enabled */
1394 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1396 struct circ_buf *xmit = &uap->port.state->xmit;
1397 int count = uap->fifosize >> 1;
1399 if (uap->port.x_char) {
1400 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1402 uap->port.x_char = 0;
1405 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1406 pl011_stop_tx(&uap->port);
1410 /* If we are using DMA mode, try to send some characters. */
1411 if (pl011_dma_tx_irq(uap))
1415 if (likely(from_irq) && count-- == 0)
1418 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1421 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1422 } while (!uart_circ_empty(xmit));
1424 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1425 uart_write_wakeup(&uap->port);
1427 if (uart_circ_empty(xmit)) {
1428 pl011_stop_tx(&uap->port);
1434 static void pl011_modem_status(struct uart_amba_port *uap)
1436 unsigned int status, delta;
1438 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1440 delta = status ^ uap->old_status;
1441 uap->old_status = status;
1446 if (delta & UART01x_FR_DCD)
1447 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1449 if (delta & uap->vendor->fr_dsr)
1450 uap->port.icount.dsr++;
1452 if (delta & uap->vendor->fr_cts)
1453 uart_handle_cts_change(&uap->port,
1454 status & uap->vendor->fr_cts);
1456 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1459 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1461 if (!uap->vendor->cts_event_workaround)
1464 /* workaround to make sure that all bits are unlocked.. */
1465 pl011_write(0x00, uap, REG_ICR);
1468 * WA: introduce 26ns(1 uart clk) delay before W1C;
1469 * single apb access will incur 2 pclk(133.12Mhz) delay,
1470 * so add 2 dummy reads
1472 pl011_read(uap, REG_ICR);
1473 pl011_read(uap, REG_ICR);
1476 static irqreturn_t pl011_int(int irq, void *dev_id)
1478 struct uart_amba_port *uap = dev_id;
1479 unsigned long flags;
1480 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1483 spin_lock_irqsave(&uap->port.lock, flags);
1484 status = pl011_read(uap, REG_RIS) & uap->im;
1487 check_apply_cts_event_workaround(uap);
1489 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1493 if (status & (UART011_RTIS|UART011_RXIS)) {
1494 if (pl011_dma_rx_running(uap))
1495 pl011_dma_rx_irq(uap);
1497 pl011_rx_chars(uap);
1499 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1500 UART011_CTSMIS|UART011_RIMIS))
1501 pl011_modem_status(uap);
1502 if (status & UART011_TXIS)
1503 pl011_tx_chars(uap, true);
1505 if (pass_counter-- == 0)
1508 status = pl011_read(uap, REG_RIS) & uap->im;
1509 } while (status != 0);
1513 spin_unlock_irqrestore(&uap->port.lock, flags);
1515 return IRQ_RETVAL(handled);
1518 static unsigned int pl011_tx_empty(struct uart_port *port)
1520 struct uart_amba_port *uap =
1521 container_of(port, struct uart_amba_port, port);
1523 /* Allow feature register bits to be inverted to work around errata */
1524 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1526 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1530 static unsigned int pl011_get_mctrl(struct uart_port *port)
1532 struct uart_amba_port *uap =
1533 container_of(port, struct uart_amba_port, port);
1534 unsigned int result = 0;
1535 unsigned int status = pl011_read(uap, REG_FR);
1537 #define TIOCMBIT(uartbit, tiocmbit) \
1538 if (status & uartbit) \
1541 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1542 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1543 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1544 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1549 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1551 struct uart_amba_port *uap =
1552 container_of(port, struct uart_amba_port, port);
1555 cr = pl011_read(uap, REG_CR);
1557 #define TIOCMBIT(tiocmbit, uartbit) \
1558 if (mctrl & tiocmbit) \
1563 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1564 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1565 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1566 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1567 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1569 if (port->status & UPSTAT_AUTORTS) {
1570 /* We need to disable auto-RTS if we want to turn RTS off */
1571 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1575 pl011_write(cr, uap, REG_CR);
1578 static void pl011_break_ctl(struct uart_port *port, int break_state)
1580 struct uart_amba_port *uap =
1581 container_of(port, struct uart_amba_port, port);
1582 unsigned long flags;
1585 spin_lock_irqsave(&uap->port.lock, flags);
1586 lcr_h = pl011_read(uap, REG_LCRH_TX);
1587 if (break_state == -1)
1588 lcr_h |= UART01x_LCRH_BRK;
1590 lcr_h &= ~UART01x_LCRH_BRK;
1591 pl011_write(lcr_h, uap, REG_LCRH_TX);
1592 spin_unlock_irqrestore(&uap->port.lock, flags);
1595 #ifdef CONFIG_CONSOLE_POLL
1597 static void pl011_quiesce_irqs(struct uart_port *port)
1599 struct uart_amba_port *uap =
1600 container_of(port, struct uart_amba_port, port);
1602 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1604 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1605 * we simply mask it. start_tx() will unmask it.
1607 * Note we can race with start_tx(), and if the race happens, the
1608 * polling user might get another interrupt just after we clear it.
1609 * But it should be OK and can happen even w/o the race, e.g.
1610 * controller immediately got some new data and raised the IRQ.
1612 * And whoever uses polling routines assumes that it manages the device
1613 * (including tx queue), so we're also fine with start_tx()'s caller
1616 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1620 static int pl011_get_poll_char(struct uart_port *port)
1622 struct uart_amba_port *uap =
1623 container_of(port, struct uart_amba_port, port);
1624 unsigned int status;
1627 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1630 pl011_quiesce_irqs(port);
1632 status = pl011_read(uap, REG_FR);
1633 if (status & UART01x_FR_RXFE)
1634 return NO_POLL_CHAR;
1636 return pl011_read(uap, REG_DR);
1639 static void pl011_put_poll_char(struct uart_port *port,
1642 struct uart_amba_port *uap =
1643 container_of(port, struct uart_amba_port, port);
1645 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1648 pl011_write(ch, uap, REG_DR);
1651 #endif /* CONFIG_CONSOLE_POLL */
1653 static int pl011_hwinit(struct uart_port *port)
1655 struct uart_amba_port *uap =
1656 container_of(port, struct uart_amba_port, port);
1659 /* Optionaly enable pins to be muxed in and configured */
1660 pinctrl_pm_select_default_state(port->dev);
1663 * Try to enable the clock producer.
1665 retval = clk_prepare_enable(uap->clk);
1669 uap->port.uartclk = clk_get_rate(uap->clk);
1671 /* Clear pending error and receive interrupts */
1672 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1673 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1677 * Save interrupts enable mask, and enable RX interrupts in case if
1678 * the interrupt is used for NMI entry.
1680 uap->im = pl011_read(uap, REG_IMSC);
1681 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1683 if (dev_get_platdata(uap->port.dev)) {
1684 struct amba_pl011_data *plat;
1686 plat = dev_get_platdata(uap->port.dev);
1693 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1695 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1696 pl011_reg_to_offset(uap, REG_LCRH_TX);
1699 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1701 pl011_write(lcr_h, uap, REG_LCRH_RX);
1702 if (pl011_split_lcrh(uap)) {
1705 * Wait 10 PCLKs before writing LCRH_TX register,
1706 * to get this delay write read only register 10 times
1708 for (i = 0; i < 10; ++i)
1709 pl011_write(0xff, uap, REG_MIS);
1710 pl011_write(lcr_h, uap, REG_LCRH_TX);
1714 static int pl011_allocate_irq(struct uart_amba_port *uap)
1716 pl011_write(uap->im, uap, REG_IMSC);
1718 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1722 * Enable interrupts, only timeouts when using DMA
1723 * if initial RX DMA job failed, start in interrupt mode
1726 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1728 unsigned long flags;
1731 spin_lock_irqsave(&uap->port.lock, flags);
1733 /* Clear out any spuriously appearing RX interrupts */
1734 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1737 * RXIS is asserted only when the RX FIFO transitions from below
1738 * to above the trigger threshold. If the RX FIFO is already
1739 * full to the threshold this can't happen and RXIS will now be
1740 * stuck off. Drain the RX FIFO explicitly to fix this:
1742 for (i = 0; i < uap->fifosize * 2; ++i) {
1743 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1746 pl011_read(uap, REG_DR);
1749 uap->im = UART011_RTIM;
1750 if (!pl011_dma_rx_running(uap))
1751 uap->im |= UART011_RXIM;
1752 pl011_write(uap->im, uap, REG_IMSC);
1753 spin_unlock_irqrestore(&uap->port.lock, flags);
1756 static void pl011_unthrottle_rx(struct uart_port *port)
1758 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
1759 unsigned long flags;
1761 spin_lock_irqsave(&uap->port.lock, flags);
1763 uap->im = UART011_RTIM;
1764 if (!pl011_dma_rx_running(uap))
1765 uap->im |= UART011_RXIM;
1767 pl011_write(uap->im, uap, REG_IMSC);
1769 spin_unlock_irqrestore(&uap->port.lock, flags);
1772 static int pl011_startup(struct uart_port *port)
1774 struct uart_amba_port *uap =
1775 container_of(port, struct uart_amba_port, port);
1779 retval = pl011_hwinit(port);
1783 retval = pl011_allocate_irq(uap);
1787 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1789 spin_lock_irq(&uap->port.lock);
1791 /* restore RTS and DTR */
1792 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1793 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1794 pl011_write(cr, uap, REG_CR);
1796 spin_unlock_irq(&uap->port.lock);
1799 * initialise the old status of the modem signals
1801 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1804 pl011_dma_startup(uap);
1806 pl011_enable_interrupts(uap);
1811 clk_disable_unprepare(uap->clk);
1815 static int sbsa_uart_startup(struct uart_port *port)
1817 struct uart_amba_port *uap =
1818 container_of(port, struct uart_amba_port, port);
1821 retval = pl011_hwinit(port);
1825 retval = pl011_allocate_irq(uap);
1829 /* The SBSA UART does not support any modem status lines. */
1830 uap->old_status = 0;
1832 pl011_enable_interrupts(uap);
1837 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1842 val = pl011_read(uap, lcrh);
1843 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1844 pl011_write(val, uap, lcrh);
1848 * disable the port. It should not disable RTS and DTR.
1849 * Also RTS and DTR state should be preserved to restore
1850 * it during startup().
1852 static void pl011_disable_uart(struct uart_amba_port *uap)
1856 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1857 spin_lock_irq(&uap->port.lock);
1858 cr = pl011_read(uap, REG_CR);
1860 cr &= UART011_CR_RTS | UART011_CR_DTR;
1861 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1862 pl011_write(cr, uap, REG_CR);
1863 spin_unlock_irq(&uap->port.lock);
1866 * disable break condition and fifos
1868 pl011_shutdown_channel(uap, REG_LCRH_RX);
1869 if (pl011_split_lcrh(uap))
1870 pl011_shutdown_channel(uap, REG_LCRH_TX);
1873 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1875 spin_lock_irq(&uap->port.lock);
1877 /* mask all interrupts and clear all pending ones */
1879 pl011_write(uap->im, uap, REG_IMSC);
1880 pl011_write(0xffff, uap, REG_ICR);
1882 spin_unlock_irq(&uap->port.lock);
1885 static void pl011_shutdown(struct uart_port *port)
1887 struct uart_amba_port *uap =
1888 container_of(port, struct uart_amba_port, port);
1890 pl011_disable_interrupts(uap);
1892 pl011_dma_shutdown(uap);
1894 free_irq(uap->port.irq, uap);
1896 pl011_disable_uart(uap);
1899 * Shut down the clock producer
1901 clk_disable_unprepare(uap->clk);
1902 /* Optionally let pins go into sleep states */
1903 pinctrl_pm_select_sleep_state(port->dev);
1905 if (dev_get_platdata(uap->port.dev)) {
1906 struct amba_pl011_data *plat;
1908 plat = dev_get_platdata(uap->port.dev);
1913 if (uap->port.ops->flush_buffer)
1914 uap->port.ops->flush_buffer(port);
1917 static void sbsa_uart_shutdown(struct uart_port *port)
1919 struct uart_amba_port *uap =
1920 container_of(port, struct uart_amba_port, port);
1922 pl011_disable_interrupts(uap);
1924 free_irq(uap->port.irq, uap);
1926 if (uap->port.ops->flush_buffer)
1927 uap->port.ops->flush_buffer(port);
1931 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1933 port->read_status_mask = UART011_DR_OE | 255;
1934 if (termios->c_iflag & INPCK)
1935 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1936 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1937 port->read_status_mask |= UART011_DR_BE;
1940 * Characters to ignore
1942 port->ignore_status_mask = 0;
1943 if (termios->c_iflag & IGNPAR)
1944 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1945 if (termios->c_iflag & IGNBRK) {
1946 port->ignore_status_mask |= UART011_DR_BE;
1948 * If we're ignoring parity and break indicators,
1949 * ignore overruns too (for real raw support).
1951 if (termios->c_iflag & IGNPAR)
1952 port->ignore_status_mask |= UART011_DR_OE;
1956 * Ignore all characters if CREAD is not set.
1958 if ((termios->c_cflag & CREAD) == 0)
1959 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1963 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1964 struct ktermios *old)
1966 struct uart_amba_port *uap =
1967 container_of(port, struct uart_amba_port, port);
1968 unsigned int lcr_h, old_cr;
1969 unsigned long flags;
1970 unsigned int baud, quot, clkdiv;
1972 if (uap->vendor->oversampling)
1978 * Ask the core to calculate the divisor for us.
1980 baud = uart_get_baud_rate(port, termios, old, 0,
1981 port->uartclk / clkdiv);
1982 #ifdef CONFIG_DMA_ENGINE
1984 * Adjust RX DMA polling rate with baud rate if not specified.
1986 if (uap->dmarx.auto_poll_rate)
1987 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1990 if (baud > port->uartclk/16)
1991 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1993 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1995 switch (termios->c_cflag & CSIZE) {
1997 lcr_h = UART01x_LCRH_WLEN_5;
2000 lcr_h = UART01x_LCRH_WLEN_6;
2003 lcr_h = UART01x_LCRH_WLEN_7;
2006 lcr_h = UART01x_LCRH_WLEN_8;
2009 if (termios->c_cflag & CSTOPB)
2010 lcr_h |= UART01x_LCRH_STP2;
2011 if (termios->c_cflag & PARENB) {
2012 lcr_h |= UART01x_LCRH_PEN;
2013 if (!(termios->c_cflag & PARODD))
2014 lcr_h |= UART01x_LCRH_EPS;
2015 if (termios->c_cflag & CMSPAR)
2016 lcr_h |= UART011_LCRH_SPS;
2018 if (uap->fifosize > 1)
2019 lcr_h |= UART01x_LCRH_FEN;
2021 spin_lock_irqsave(&port->lock, flags);
2024 * Update the per-port timeout.
2026 uart_update_timeout(port, termios->c_cflag, baud);
2028 pl011_setup_status_masks(port, termios);
2030 if (UART_ENABLE_MS(port, termios->c_cflag))
2031 pl011_enable_ms(port);
2033 /* first, disable everything */
2034 old_cr = pl011_read(uap, REG_CR);
2035 pl011_write(0, uap, REG_CR);
2037 if (termios->c_cflag & CRTSCTS) {
2038 if (old_cr & UART011_CR_RTS)
2039 old_cr |= UART011_CR_RTSEN;
2041 old_cr |= UART011_CR_CTSEN;
2042 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2044 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2045 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2048 if (uap->vendor->oversampling) {
2049 if (baud > port->uartclk / 16)
2050 old_cr |= ST_UART011_CR_OVSFACT;
2052 old_cr &= ~ST_UART011_CR_OVSFACT;
2056 * Workaround for the ST Micro oversampling variants to
2057 * increase the bitrate slightly, by lowering the divisor,
2058 * to avoid delayed sampling of start bit at high speeds,
2059 * else we see data corruption.
2061 if (uap->vendor->oversampling) {
2062 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2064 else if ((baud > 3250000) && (quot > 2))
2068 pl011_write(quot & 0x3f, uap, REG_FBRD);
2069 pl011_write(quot >> 6, uap, REG_IBRD);
2072 * ----------v----------v----------v----------v-----
2073 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2074 * REG_FBRD & REG_IBRD.
2075 * ----------^----------^----------^----------^-----
2077 pl011_write_lcr_h(uap, lcr_h);
2078 pl011_write(old_cr, uap, REG_CR);
2080 spin_unlock_irqrestore(&port->lock, flags);
2084 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2085 struct ktermios *old)
2087 struct uart_amba_port *uap =
2088 container_of(port, struct uart_amba_port, port);
2089 unsigned long flags;
2091 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2093 /* The SBSA UART only supports 8n1 without hardware flow control. */
2094 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2095 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2096 termios->c_cflag |= CS8 | CLOCAL;
2098 spin_lock_irqsave(&port->lock, flags);
2099 uart_update_timeout(port, CS8, uap->fixed_baud);
2100 pl011_setup_status_masks(port, termios);
2101 spin_unlock_irqrestore(&port->lock, flags);
2104 static const char *pl011_type(struct uart_port *port)
2106 struct uart_amba_port *uap =
2107 container_of(port, struct uart_amba_port, port);
2108 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2112 * Configure/autoconfigure the port.
2114 static void pl011_config_port(struct uart_port *port, int flags)
2116 if (flags & UART_CONFIG_TYPE)
2117 port->type = PORT_AMBA;
2121 * verify the new serial_struct (for TIOCSSERIAL).
2123 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2126 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2128 if (ser->irq < 0 || ser->irq >= nr_irqs)
2130 if (ser->baud_base < 9600)
2132 if (port->mapbase != (unsigned long) ser->iomem_base)
2137 static const struct uart_ops amba_pl011_pops = {
2138 .tx_empty = pl011_tx_empty,
2139 .set_mctrl = pl011_set_mctrl,
2140 .get_mctrl = pl011_get_mctrl,
2141 .stop_tx = pl011_stop_tx,
2142 .start_tx = pl011_start_tx,
2143 .stop_rx = pl011_stop_rx,
2144 .throttle = pl011_throttle_rx,
2145 .unthrottle = pl011_unthrottle_rx,
2146 .enable_ms = pl011_enable_ms,
2147 .break_ctl = pl011_break_ctl,
2148 .startup = pl011_startup,
2149 .shutdown = pl011_shutdown,
2150 .flush_buffer = pl011_dma_flush_buffer,
2151 .set_termios = pl011_set_termios,
2153 .config_port = pl011_config_port,
2154 .verify_port = pl011_verify_port,
2155 #ifdef CONFIG_CONSOLE_POLL
2156 .poll_init = pl011_hwinit,
2157 .poll_get_char = pl011_get_poll_char,
2158 .poll_put_char = pl011_put_poll_char,
2162 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2166 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2171 static const struct uart_ops sbsa_uart_pops = {
2172 .tx_empty = pl011_tx_empty,
2173 .set_mctrl = sbsa_uart_set_mctrl,
2174 .get_mctrl = sbsa_uart_get_mctrl,
2175 .stop_tx = pl011_stop_tx,
2176 .start_tx = pl011_start_tx,
2177 .stop_rx = pl011_stop_rx,
2178 .startup = sbsa_uart_startup,
2179 .shutdown = sbsa_uart_shutdown,
2180 .set_termios = sbsa_uart_set_termios,
2182 .config_port = pl011_config_port,
2183 .verify_port = pl011_verify_port,
2184 #ifdef CONFIG_CONSOLE_POLL
2185 .poll_init = pl011_hwinit,
2186 .poll_get_char = pl011_get_poll_char,
2187 .poll_put_char = pl011_put_poll_char,
2191 static struct uart_amba_port *amba_ports[UART_NR];
2193 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2195 static void pl011_console_putchar(struct uart_port *port, int ch)
2197 struct uart_amba_port *uap =
2198 container_of(port, struct uart_amba_port, port);
2200 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2202 pl011_write(ch, uap, REG_DR);
2206 pl011_console_write(struct console *co, const char *s, unsigned int count)
2208 struct uart_amba_port *uap = amba_ports[co->index];
2209 unsigned int old_cr = 0, new_cr;
2210 unsigned long flags;
2213 clk_enable(uap->clk);
2215 local_irq_save(flags);
2216 if (uap->port.sysrq)
2218 else if (oops_in_progress)
2219 locked = spin_trylock(&uap->port.lock);
2221 spin_lock(&uap->port.lock);
2224 * First save the CR then disable the interrupts
2226 if (!uap->vendor->always_enabled) {
2227 old_cr = pl011_read(uap, REG_CR);
2228 new_cr = old_cr & ~UART011_CR_CTSEN;
2229 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2230 pl011_write(new_cr, uap, REG_CR);
2233 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2236 * Finally, wait for transmitter to become empty and restore the
2237 * TCR. Allow feature register bits to be inverted to work around
2240 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2241 & uap->vendor->fr_busy)
2243 if (!uap->vendor->always_enabled)
2244 pl011_write(old_cr, uap, REG_CR);
2247 spin_unlock(&uap->port.lock);
2248 local_irq_restore(flags);
2250 clk_disable(uap->clk);
2253 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2254 int *parity, int *bits)
2256 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2257 unsigned int lcr_h, ibrd, fbrd;
2259 lcr_h = pl011_read(uap, REG_LCRH_TX);
2262 if (lcr_h & UART01x_LCRH_PEN) {
2263 if (lcr_h & UART01x_LCRH_EPS)
2269 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2274 ibrd = pl011_read(uap, REG_IBRD);
2275 fbrd = pl011_read(uap, REG_FBRD);
2277 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2279 if (uap->vendor->oversampling) {
2280 if (pl011_read(uap, REG_CR)
2281 & ST_UART011_CR_OVSFACT)
2287 static int pl011_console_setup(struct console *co, char *options)
2289 struct uart_amba_port *uap;
2297 * Check whether an invalid uart number has been specified, and
2298 * if so, search for the first available port that does have
2301 if (co->index >= UART_NR)
2303 uap = amba_ports[co->index];
2307 /* Allow pins to be muxed in and configured */
2308 pinctrl_pm_select_default_state(uap->port.dev);
2310 ret = clk_prepare(uap->clk);
2314 if (dev_get_platdata(uap->port.dev)) {
2315 struct amba_pl011_data *plat;
2317 plat = dev_get_platdata(uap->port.dev);
2322 uap->port.uartclk = clk_get_rate(uap->clk);
2324 if (uap->vendor->fixed_options) {
2325 baud = uap->fixed_baud;
2328 uart_parse_options(options,
2329 &baud, &parity, &bits, &flow);
2331 pl011_console_get_options(uap, &baud, &parity, &bits);
2334 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2338 * pl011_console_match - non-standard console matching
2339 * @co: registering console
2340 * @name: name from console command line
2341 * @idx: index from console command line
2342 * @options: ptr to option string from console command line
2344 * Only attempts to match console command lines of the form:
2345 * console=pl011,mmio|mmio32,<addr>[,<options>]
2346 * console=pl011,0x<addr>[,<options>]
2347 * This form is used to register an initial earlycon boot console and
2348 * replace it with the amba_console at pl011 driver init.
2350 * Performs console setup for a match (as required by interface)
2351 * If no <options> are specified, then assume the h/w is already setup.
2353 * Returns 0 if console matches; otherwise non-zero to use default matching
2355 static int pl011_console_match(struct console *co, char *name, int idx,
2358 unsigned char iotype;
2359 resource_size_t addr;
2363 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2364 * have a distinct console name, so make sure we check for that.
2365 * The actual implementation of the erratum occurs in the probe
2368 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2371 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2374 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2377 /* try to match the port specified on the command line */
2378 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2379 struct uart_port *port;
2384 port = &amba_ports[i]->port;
2386 if (port->mapbase != addr)
2391 return pl011_console_setup(co, options);
2397 static struct uart_driver amba_reg;
2398 static struct console amba_console = {
2400 .write = pl011_console_write,
2401 .device = uart_console_device,
2402 .setup = pl011_console_setup,
2403 .match = pl011_console_match,
2404 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2409 #define AMBA_CONSOLE (&amba_console)
2411 static void qdf2400_e44_putc(struct uart_port *port, int c)
2413 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2415 writel(c, port->membase + UART01x_DR);
2416 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2420 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2422 struct earlycon_device *dev = con->data;
2424 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2427 static void pl011_putc(struct uart_port *port, int c)
2429 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2431 if (port->iotype == UPIO_MEM32)
2432 writel(c, port->membase + UART01x_DR);
2434 writeb(c, port->membase + UART01x_DR);
2435 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2439 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2441 struct earlycon_device *dev = con->data;
2443 uart_console_write(&dev->port, s, n, pl011_putc);
2446 #ifdef CONFIG_CONSOLE_POLL
2447 static int pl011_getc(struct uart_port *port)
2449 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
2450 return NO_POLL_CHAR;
2452 if (port->iotype == UPIO_MEM32)
2453 return readl(port->membase + UART01x_DR);
2455 return readb(port->membase + UART01x_DR);
2458 static int pl011_early_read(struct console *con, char *s, unsigned int n)
2460 struct earlycon_device *dev = con->data;
2461 int ch, num_read = 0;
2463 while (num_read < n) {
2464 ch = pl011_getc(&dev->port);
2465 if (ch == NO_POLL_CHAR)
2474 #define pl011_early_read NULL
2478 * On non-ACPI systems, earlycon is enabled by specifying
2479 * "earlycon=pl011,<address>" on the kernel command line.
2481 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2482 * by specifying only "earlycon" on the command line. Because it requires
2483 * SPCR, the console starts after ACPI is parsed, which is later than a
2484 * traditional early console.
2486 * To get the traditional early console that starts before ACPI is parsed,
2487 * specify the full "earlycon=pl011,<address>" option.
2489 static int __init pl011_early_console_setup(struct earlycon_device *device,
2492 if (!device->port.membase)
2495 device->con->write = pl011_early_write;
2496 device->con->read = pl011_early_read;
2500 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2501 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2504 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2505 * Erratum 44, traditional earlycon can be enabled by specifying
2506 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2508 * Alternatively, you can just specify "earlycon", and the early console
2509 * will be enabled with the information from the SPCR table. In this
2510 * case, the SPCR code will detect the need for the E44 work-around,
2511 * and set the console name to "qdf2400_e44".
2514 qdf2400_e44_early_console_setup(struct earlycon_device *device,
2517 if (!device->port.membase)
2520 device->con->write = qdf2400_e44_early_write;
2523 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2526 #define AMBA_CONSOLE NULL
2529 static struct uart_driver amba_reg = {
2530 .owner = THIS_MODULE,
2531 .driver_name = "ttyAMA",
2532 .dev_name = "ttyAMA",
2533 .major = SERIAL_AMBA_MAJOR,
2534 .minor = SERIAL_AMBA_MINOR,
2536 .cons = AMBA_CONSOLE,
2539 static int pl011_probe_dt_alias(int index, struct device *dev)
2541 struct device_node *np;
2542 static bool seen_dev_with_alias = false;
2543 static bool seen_dev_without_alias = false;
2546 if (!IS_ENABLED(CONFIG_OF))
2553 ret = of_alias_get_id(np, "serial");
2555 seen_dev_without_alias = true;
2558 seen_dev_with_alias = true;
2559 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2560 dev_warn(dev, "requested serial port %d not available.\n", ret);
2565 if (seen_dev_with_alias && seen_dev_without_alias)
2566 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2571 /* unregisters the driver also if no more ports are left */
2572 static void pl011_unregister_port(struct uart_amba_port *uap)
2577 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2578 if (amba_ports[i] == uap)
2579 amba_ports[i] = NULL;
2580 else if (amba_ports[i])
2583 pl011_dma_remove(uap);
2585 uart_unregister_driver(&amba_reg);
2588 static int pl011_find_free_port(void)
2592 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2593 if (amba_ports[i] == NULL)
2599 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2600 struct resource *mmiobase, int index)
2604 base = devm_ioremap_resource(dev, mmiobase);
2606 return PTR_ERR(base);
2608 index = pl011_probe_dt_alias(index, dev);
2611 uap->port.dev = dev;
2612 uap->port.mapbase = mmiobase->start;
2613 uap->port.membase = base;
2614 uap->port.fifosize = uap->fifosize;
2615 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2616 uap->port.flags = UPF_BOOT_AUTOCONF;
2617 uap->port.line = index;
2619 amba_ports[index] = uap;
2624 static int pl011_register_port(struct uart_amba_port *uap)
2628 /* Ensure interrupts from this UART are masked and cleared */
2629 pl011_write(0, uap, REG_IMSC);
2630 pl011_write(0xffff, uap, REG_ICR);
2632 if (!amba_reg.state) {
2633 ret = uart_register_driver(&amba_reg);
2635 dev_err(uap->port.dev,
2636 "Failed to register AMBA-PL011 driver\n");
2637 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2638 if (amba_ports[i] == uap)
2639 amba_ports[i] = NULL;
2644 ret = uart_add_one_port(&amba_reg, &uap->port);
2646 pl011_unregister_port(uap);
2651 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2653 struct uart_amba_port *uap;
2654 struct vendor_data *vendor = id->data;
2657 portnr = pl011_find_free_port();
2661 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2666 uap->clk = devm_clk_get(&dev->dev, NULL);
2667 if (IS_ERR(uap->clk))
2668 return PTR_ERR(uap->clk);
2670 uap->reg_offset = vendor->reg_offset;
2671 uap->vendor = vendor;
2672 uap->fifosize = vendor->get_fifosize(dev);
2673 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2674 uap->port.irq = dev->irq[0];
2675 uap->port.ops = &amba_pl011_pops;
2677 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2679 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2683 amba_set_drvdata(dev, uap);
2685 return pl011_register_port(uap);
2688 static void pl011_remove(struct amba_device *dev)
2690 struct uart_amba_port *uap = amba_get_drvdata(dev);
2692 uart_remove_one_port(&amba_reg, &uap->port);
2693 pl011_unregister_port(uap);
2696 #ifdef CONFIG_PM_SLEEP
2697 static int pl011_suspend(struct device *dev)
2699 struct uart_amba_port *uap = dev_get_drvdata(dev);
2704 return uart_suspend_port(&amba_reg, &uap->port);
2707 static int pl011_resume(struct device *dev)
2709 struct uart_amba_port *uap = dev_get_drvdata(dev);
2714 return uart_resume_port(&amba_reg, &uap->port);
2718 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2720 static int sbsa_uart_probe(struct platform_device *pdev)
2722 struct uart_amba_port *uap;
2728 * Check the mandatory baud rate parameter in the DT node early
2729 * so that we can easily exit with the error.
2731 if (pdev->dev.of_node) {
2732 struct device_node *np = pdev->dev.of_node;
2734 ret = of_property_read_u32(np, "current-speed", &baudrate);
2741 portnr = pl011_find_free_port();
2745 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2750 ret = platform_get_irq(pdev, 0);
2753 uap->port.irq = ret;
2755 #ifdef CONFIG_ACPI_SPCR_TABLE
2756 if (qdf2400_e44_present) {
2757 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2758 uap->vendor = &vendor_qdt_qdf2400_e44;
2761 uap->vendor = &vendor_sbsa;
2763 uap->reg_offset = uap->vendor->reg_offset;
2765 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2766 uap->port.ops = &sbsa_uart_pops;
2767 uap->fixed_baud = baudrate;
2769 snprintf(uap->type, sizeof(uap->type), "SBSA");
2771 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2773 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2777 platform_set_drvdata(pdev, uap);
2779 return pl011_register_port(uap);
2782 static int sbsa_uart_remove(struct platform_device *pdev)
2784 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2786 uart_remove_one_port(&amba_reg, &uap->port);
2787 pl011_unregister_port(uap);
2791 static const struct of_device_id sbsa_uart_of_match[] = {
2792 { .compatible = "arm,sbsa-uart", },
2795 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2797 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2802 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2804 static struct platform_driver arm_sbsa_uart_platform_driver = {
2805 .probe = sbsa_uart_probe,
2806 .remove = sbsa_uart_remove,
2808 .name = "sbsa-uart",
2809 .pm = &pl011_dev_pm_ops,
2810 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2811 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2812 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2816 static const struct amba_id pl011_ids[] = {
2820 .data = &vendor_arm,
2828 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2830 .data = &vendor_zte,
2835 MODULE_DEVICE_TABLE(amba, pl011_ids);
2837 static struct amba_driver pl011_driver = {
2839 .name = "uart-pl011",
2840 .pm = &pl011_dev_pm_ops,
2841 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2843 .id_table = pl011_ids,
2844 .probe = pl011_probe,
2845 .remove = pl011_remove,
2848 static int __init pl011_init(void)
2850 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2852 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2853 pr_warn("could not register SBSA UART platform driver\n");
2854 return amba_driver_register(&pl011_driver);
2857 static void __exit pl011_exit(void)
2859 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2860 amba_driver_unregister(&pl011_driver);
2864 * While this can be a module, if builtin it's most likely the console
2865 * So let's leave module_exit but move module_init to an earlier place
2867 arch_initcall(pl011_init);
2868 module_exit(pl011_exit);
2870 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2871 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2872 MODULE_LICENSE("GPL");