1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for AMBA serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 * This is a generic driver for ARM AMBA-type serial ports. They
11 * have a lot of 16550-like features, but are not register compatible.
12 * Note that although they do have CTS, DCD and DSR inputs, they do
13 * not have an RI input, nor do they have DTR or RTS outputs. If
14 * required, these have to be supplied via some other means (eg, GPIO)
15 * and hooked into this driver.
18 #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/ioport.h>
24 #include <linux/init.h>
25 #include <linux/console.h>
26 #include <linux/sysrq.h>
27 #include <linux/device.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/serial_core.h>
31 #include <linux/serial.h>
32 #include <linux/amba/bus.h>
33 #include <linux/amba/serial.h>
34 #include <linux/clk.h>
35 #include <linux/slab.h>
40 #define SERIAL_AMBA_MAJOR 204
41 #define SERIAL_AMBA_MINOR 16
42 #define SERIAL_AMBA_NR UART_NR
44 #define AMBA_ISR_PASS_LIMIT 256
46 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
47 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
49 #define UART_DUMMY_RSR_RX 256
50 #define UART_PORT_SIZE 64
53 * We wrap our port structure around the generic uart_port.
55 struct uart_amba_port {
56 struct uart_port port;
58 struct amba_device *dev;
59 struct amba_pl010_data *data;
60 unsigned int old_status;
63 static void pl010_stop_tx(struct uart_port *port)
65 struct uart_amba_port *uap =
66 container_of(port, struct uart_amba_port, port);
69 cr = readb(uap->port.membase + UART010_CR);
70 cr &= ~UART010_CR_TIE;
71 writel(cr, uap->port.membase + UART010_CR);
74 static void pl010_start_tx(struct uart_port *port)
76 struct uart_amba_port *uap =
77 container_of(port, struct uart_amba_port, port);
80 cr = readb(uap->port.membase + UART010_CR);
82 writel(cr, uap->port.membase + UART010_CR);
85 static void pl010_stop_rx(struct uart_port *port)
87 struct uart_amba_port *uap =
88 container_of(port, struct uart_amba_port, port);
91 cr = readb(uap->port.membase + UART010_CR);
92 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
93 writel(cr, uap->port.membase + UART010_CR);
96 static void pl010_disable_ms(struct uart_port *port)
98 struct uart_amba_port *uap = (struct uart_amba_port *)port;
101 cr = readb(uap->port.membase + UART010_CR);
102 cr &= ~UART010_CR_MSIE;
103 writel(cr, uap->port.membase + UART010_CR);
106 static void pl010_enable_ms(struct uart_port *port)
108 struct uart_amba_port *uap =
109 container_of(port, struct uart_amba_port, port);
112 cr = readb(uap->port.membase + UART010_CR);
113 cr |= UART010_CR_MSIE;
114 writel(cr, uap->port.membase + UART010_CR);
117 static void pl010_rx_chars(struct uart_amba_port *uap)
119 unsigned int status, ch, flag, rsr, max_count = 256;
121 status = readb(uap->port.membase + UART01x_FR);
122 while (UART_RX_DATA(status) && max_count--) {
123 ch = readb(uap->port.membase + UART01x_DR);
126 uap->port.icount.rx++;
129 * Note that the error handling code is
130 * out of the main execution path
132 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
133 if (unlikely(rsr & UART01x_RSR_ANY)) {
134 writel(0, uap->port.membase + UART01x_ECR);
136 if (rsr & UART01x_RSR_BE) {
137 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
138 uap->port.icount.brk++;
139 if (uart_handle_break(&uap->port))
141 } else if (rsr & UART01x_RSR_PE)
142 uap->port.icount.parity++;
143 else if (rsr & UART01x_RSR_FE)
144 uap->port.icount.frame++;
145 if (rsr & UART01x_RSR_OE)
146 uap->port.icount.overrun++;
148 rsr &= uap->port.read_status_mask;
150 if (rsr & UART01x_RSR_BE)
152 else if (rsr & UART01x_RSR_PE)
154 else if (rsr & UART01x_RSR_FE)
158 if (uart_handle_sysrq_char(&uap->port, ch))
161 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
164 status = readb(uap->port.membase + UART01x_FR);
166 spin_unlock(&uap->port.lock);
167 tty_flip_buffer_push(&uap->port.state->port);
168 spin_lock(&uap->port.lock);
171 static void pl010_tx_chars(struct uart_amba_port *uap)
173 struct circ_buf *xmit = &uap->port.state->xmit;
176 if (uap->port.x_char) {
177 writel(uap->port.x_char, uap->port.membase + UART01x_DR);
178 uap->port.icount.tx++;
179 uap->port.x_char = 0;
182 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
183 pl010_stop_tx(&uap->port);
187 count = uap->port.fifosize >> 1;
189 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
190 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
191 uap->port.icount.tx++;
192 if (uart_circ_empty(xmit))
194 } while (--count > 0);
196 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
197 uart_write_wakeup(&uap->port);
199 if (uart_circ_empty(xmit))
200 pl010_stop_tx(&uap->port);
203 static void pl010_modem_status(struct uart_amba_port *uap)
205 unsigned int status, delta;
207 writel(0, uap->port.membase + UART010_ICR);
209 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
211 delta = status ^ uap->old_status;
212 uap->old_status = status;
217 if (delta & UART01x_FR_DCD)
218 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
220 if (delta & UART01x_FR_DSR)
221 uap->port.icount.dsr++;
223 if (delta & UART01x_FR_CTS)
224 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
226 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
229 static irqreturn_t pl010_int(int irq, void *dev_id)
231 struct uart_amba_port *uap = dev_id;
232 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
235 spin_lock(&uap->port.lock);
237 status = readb(uap->port.membase + UART010_IIR);
240 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
242 if (status & UART010_IIR_MIS)
243 pl010_modem_status(uap);
244 if (status & UART010_IIR_TIS)
247 if (pass_counter-- == 0)
250 status = readb(uap->port.membase + UART010_IIR);
251 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
256 spin_unlock(&uap->port.lock);
258 return IRQ_RETVAL(handled);
261 static unsigned int pl010_tx_empty(struct uart_port *port)
263 struct uart_amba_port *uap =
264 container_of(port, struct uart_amba_port, port);
265 unsigned int status = readb(uap->port.membase + UART01x_FR);
266 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
269 static unsigned int pl010_get_mctrl(struct uart_port *port)
271 struct uart_amba_port *uap =
272 container_of(port, struct uart_amba_port, port);
273 unsigned int result = 0;
276 status = readb(uap->port.membase + UART01x_FR);
277 if (status & UART01x_FR_DCD)
279 if (status & UART01x_FR_DSR)
281 if (status & UART01x_FR_CTS)
287 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
289 struct uart_amba_port *uap =
290 container_of(port, struct uart_amba_port, port);
293 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
296 static void pl010_break_ctl(struct uart_port *port, int break_state)
298 struct uart_amba_port *uap =
299 container_of(port, struct uart_amba_port, port);
303 spin_lock_irqsave(&uap->port.lock, flags);
304 lcr_h = readb(uap->port.membase + UART010_LCRH);
305 if (break_state == -1)
306 lcr_h |= UART01x_LCRH_BRK;
308 lcr_h &= ~UART01x_LCRH_BRK;
309 writel(lcr_h, uap->port.membase + UART010_LCRH);
310 spin_unlock_irqrestore(&uap->port.lock, flags);
313 static int pl010_startup(struct uart_port *port)
315 struct uart_amba_port *uap =
316 container_of(port, struct uart_amba_port, port);
320 * Try to enable the clock producer.
322 retval = clk_prepare_enable(uap->clk);
326 uap->port.uartclk = clk_get_rate(uap->clk);
331 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap);
336 * initialise the old status of the modem signals
338 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
341 * Finally, enable interrupts
343 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
344 uap->port.membase + UART010_CR);
349 clk_disable_unprepare(uap->clk);
354 static void pl010_shutdown(struct uart_port *port)
356 struct uart_amba_port *uap =
357 container_of(port, struct uart_amba_port, port);
362 free_irq(uap->port.irq, uap);
365 * disable all interrupts, disable the port
367 writel(0, uap->port.membase + UART010_CR);
369 /* disable break condition and fifos */
370 writel(readb(uap->port.membase + UART010_LCRH) &
371 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
372 uap->port.membase + UART010_LCRH);
375 * Shut down the clock producer
377 clk_disable_unprepare(uap->clk);
381 pl010_set_termios(struct uart_port *port, struct ktermios *termios,
382 struct ktermios *old)
384 struct uart_amba_port *uap =
385 container_of(port, struct uart_amba_port, port);
386 unsigned int lcr_h, old_cr;
388 unsigned int baud, quot;
391 * Ask the core to calculate the divisor for us.
393 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
394 quot = uart_get_divisor(port, baud);
396 switch (termios->c_cflag & CSIZE) {
398 lcr_h = UART01x_LCRH_WLEN_5;
401 lcr_h = UART01x_LCRH_WLEN_6;
404 lcr_h = UART01x_LCRH_WLEN_7;
407 lcr_h = UART01x_LCRH_WLEN_8;
410 if (termios->c_cflag & CSTOPB)
411 lcr_h |= UART01x_LCRH_STP2;
412 if (termios->c_cflag & PARENB) {
413 lcr_h |= UART01x_LCRH_PEN;
414 if (!(termios->c_cflag & PARODD))
415 lcr_h |= UART01x_LCRH_EPS;
417 if (uap->port.fifosize > 1)
418 lcr_h |= UART01x_LCRH_FEN;
420 spin_lock_irqsave(&uap->port.lock, flags);
423 * Update the per-port timeout.
425 uart_update_timeout(port, termios->c_cflag, baud);
427 uap->port.read_status_mask = UART01x_RSR_OE;
428 if (termios->c_iflag & INPCK)
429 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
430 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
431 uap->port.read_status_mask |= UART01x_RSR_BE;
434 * Characters to ignore
436 uap->port.ignore_status_mask = 0;
437 if (termios->c_iflag & IGNPAR)
438 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
439 if (termios->c_iflag & IGNBRK) {
440 uap->port.ignore_status_mask |= UART01x_RSR_BE;
442 * If we're ignoring parity and break indicators,
443 * ignore overruns too (for real raw support).
445 if (termios->c_iflag & IGNPAR)
446 uap->port.ignore_status_mask |= UART01x_RSR_OE;
450 * Ignore all characters if CREAD is not set.
452 if ((termios->c_cflag & CREAD) == 0)
453 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
455 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
457 if (UART_ENABLE_MS(port, termios->c_cflag))
458 old_cr |= UART010_CR_MSIE;
462 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
463 writel(quot & 0xff, uap->port.membase + UART010_LCRL);
466 * ----------v----------v----------v----------v-----
467 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
468 * ----------^----------^----------^----------^-----
470 writel(lcr_h, uap->port.membase + UART010_LCRH);
471 writel(old_cr, uap->port.membase + UART010_CR);
473 spin_unlock_irqrestore(&uap->port.lock, flags);
476 static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios)
478 if (termios->c_line == N_PPS) {
479 port->flags |= UPF_HARDPPS_CD;
480 spin_lock_irq(&port->lock);
481 pl010_enable_ms(port);
482 spin_unlock_irq(&port->lock);
484 port->flags &= ~UPF_HARDPPS_CD;
485 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
486 spin_lock_irq(&port->lock);
487 pl010_disable_ms(port);
488 spin_unlock_irq(&port->lock);
493 static const char *pl010_type(struct uart_port *port)
495 return port->type == PORT_AMBA ? "AMBA" : NULL;
499 * Release the memory region(s) being used by 'port'
501 static void pl010_release_port(struct uart_port *port)
503 release_mem_region(port->mapbase, UART_PORT_SIZE);
507 * Request the memory region(s) being used by 'port'
509 static int pl010_request_port(struct uart_port *port)
511 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
512 != NULL ? 0 : -EBUSY;
516 * Configure/autoconfigure the port.
518 static void pl010_config_port(struct uart_port *port, int flags)
520 if (flags & UART_CONFIG_TYPE) {
521 port->type = PORT_AMBA;
522 pl010_request_port(port);
527 * verify the new serial_struct (for TIOCSSERIAL).
529 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
532 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
534 if (ser->irq < 0 || ser->irq >= nr_irqs)
536 if (ser->baud_base < 9600)
541 static const struct uart_ops amba_pl010_pops = {
542 .tx_empty = pl010_tx_empty,
543 .set_mctrl = pl010_set_mctrl,
544 .get_mctrl = pl010_get_mctrl,
545 .stop_tx = pl010_stop_tx,
546 .start_tx = pl010_start_tx,
547 .stop_rx = pl010_stop_rx,
548 .enable_ms = pl010_enable_ms,
549 .break_ctl = pl010_break_ctl,
550 .startup = pl010_startup,
551 .shutdown = pl010_shutdown,
552 .set_termios = pl010_set_termios,
553 .set_ldisc = pl010_set_ldisc,
555 .release_port = pl010_release_port,
556 .request_port = pl010_request_port,
557 .config_port = pl010_config_port,
558 .verify_port = pl010_verify_port,
561 static struct uart_amba_port *amba_ports[UART_NR];
563 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
565 static void pl010_console_putchar(struct uart_port *port, int ch)
567 struct uart_amba_port *uap =
568 container_of(port, struct uart_amba_port, port);
572 status = readb(uap->port.membase + UART01x_FR);
574 } while (!UART_TX_READY(status));
575 writel(ch, uap->port.membase + UART01x_DR);
579 pl010_console_write(struct console *co, const char *s, unsigned int count)
581 struct uart_amba_port *uap = amba_ports[co->index];
582 unsigned int status, old_cr;
584 clk_enable(uap->clk);
587 * First save the CR then disable the interrupts
589 old_cr = readb(uap->port.membase + UART010_CR);
590 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
592 uart_console_write(&uap->port, s, count, pl010_console_putchar);
595 * Finally, wait for transmitter to become empty
596 * and restore the TCR
599 status = readb(uap->port.membase + UART01x_FR);
601 } while (status & UART01x_FR_BUSY);
602 writel(old_cr, uap->port.membase + UART010_CR);
604 clk_disable(uap->clk);
608 pl010_console_get_options(struct uart_amba_port *uap, int *baud,
609 int *parity, int *bits)
611 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
612 unsigned int lcr_h, quot;
613 lcr_h = readb(uap->port.membase + UART010_LCRH);
616 if (lcr_h & UART01x_LCRH_PEN) {
617 if (lcr_h & UART01x_LCRH_EPS)
623 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
628 quot = readb(uap->port.membase + UART010_LCRL) |
629 readb(uap->port.membase + UART010_LCRM) << 8;
630 *baud = uap->port.uartclk / (16 * (quot + 1));
634 static int __init pl010_console_setup(struct console *co, char *options)
636 struct uart_amba_port *uap;
644 * Check whether an invalid uart number has been specified, and
645 * if so, search for the first available port that does have
648 if (co->index >= UART_NR)
650 uap = amba_ports[co->index];
654 ret = clk_prepare(uap->clk);
658 uap->port.uartclk = clk_get_rate(uap->clk);
661 uart_parse_options(options, &baud, &parity, &bits, &flow);
663 pl010_console_get_options(uap, &baud, &parity, &bits);
665 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
668 static struct uart_driver amba_reg;
669 static struct console amba_console = {
671 .write = pl010_console_write,
672 .device = uart_console_device,
673 .setup = pl010_console_setup,
674 .flags = CON_PRINTBUFFER,
679 #define AMBA_CONSOLE &amba_console
681 #define AMBA_CONSOLE NULL
684 static DEFINE_MUTEX(amba_reg_lock);
685 static struct uart_driver amba_reg = {
686 .owner = THIS_MODULE,
687 .driver_name = "ttyAM",
689 .major = SERIAL_AMBA_MAJOR,
690 .minor = SERIAL_AMBA_MINOR,
692 .cons = AMBA_CONSOLE,
695 static int pl010_probe(struct amba_device *dev, const struct amba_id *id)
697 struct uart_amba_port *uap;
701 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
702 if (amba_ports[i] == NULL)
705 if (i == ARRAY_SIZE(amba_ports))
708 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
713 base = devm_ioremap(&dev->dev, dev->res.start,
714 resource_size(&dev->res));
718 uap->clk = devm_clk_get(&dev->dev, NULL);
719 if (IS_ERR(uap->clk))
720 return PTR_ERR(uap->clk);
722 uap->port.dev = &dev->dev;
723 uap->port.mapbase = dev->res.start;
724 uap->port.membase = base;
725 uap->port.iotype = UPIO_MEM;
726 uap->port.irq = dev->irq[0];
727 uap->port.fifosize = 16;
728 uap->port.ops = &amba_pl010_pops;
729 uap->port.flags = UPF_BOOT_AUTOCONF;
732 uap->data = dev_get_platdata(&dev->dev);
736 amba_set_drvdata(dev, uap);
738 mutex_lock(&amba_reg_lock);
739 if (!amba_reg.state) {
740 ret = uart_register_driver(&amba_reg);
742 mutex_unlock(&amba_reg_lock);
743 dev_err(uap->port.dev,
744 "Failed to register AMBA-PL010 driver\n");
748 mutex_unlock(&amba_reg_lock);
750 ret = uart_add_one_port(&amba_reg, &uap->port);
752 amba_ports[i] = NULL;
757 static int pl010_remove(struct amba_device *dev)
759 struct uart_amba_port *uap = amba_get_drvdata(dev);
763 uart_remove_one_port(&amba_reg, &uap->port);
765 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
766 if (amba_ports[i] == uap)
767 amba_ports[i] = NULL;
768 else if (amba_ports[i])
772 uart_unregister_driver(&amba_reg);
777 #ifdef CONFIG_PM_SLEEP
778 static int pl010_suspend(struct device *dev)
780 struct uart_amba_port *uap = dev_get_drvdata(dev);
783 uart_suspend_port(&amba_reg, &uap->port);
788 static int pl010_resume(struct device *dev)
790 struct uart_amba_port *uap = dev_get_drvdata(dev);
793 uart_resume_port(&amba_reg, &uap->port);
799 static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume);
801 static const struct amba_id pl010_ids[] = {
809 MODULE_DEVICE_TABLE(amba, pl010_ids);
811 static struct amba_driver pl010_driver = {
813 .name = "uart-pl010",
814 .pm = &pl010_dev_pm_ops,
816 .id_table = pl010_ids,
817 .probe = pl010_probe,
818 .remove = pl010_remove,
821 static int __init pl010_init(void)
823 printk(KERN_INFO "Serial: AMBA driver\n");
825 return amba_driver_register(&pl010_driver);
828 static void __exit pl010_exit(void)
830 amba_driver_unregister(&pl010_driver);
833 module_init(pl010_init);
834 module_exit(pl010_exit);
836 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
837 MODULE_DESCRIPTION("ARM AMBA serial port driver");
838 MODULE_LICENSE("GPL");