2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/console.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
24 /* Most (but not all) of UniPhier UART devices have 64-depth FIFO. */
25 #define UNIPHIER_UART_DEFAULT_FIFO_SIZE 64
28 * This hardware is similar to 8250, but its register map is a bit different:
29 * - MMIO32 (regshift = 2)
30 * - FCR is not at 2, but 3
31 * - LCR and MCR are not at 3 and 4, they share 4
32 * - No SCR (Instead, CHAR can be used as a scratch register)
33 * - Divisor latch at 9, no divisor latch access bit
36 #define UNIPHIER_UART_REGSHIFT 2
38 /* bit[15:8] = CHAR, bit[7:0] = FCR */
39 #define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT))
40 /* bit[15:8] = LCR, bit[7:0] = MCR */
41 #define UNIPHIER_UART_LCR_MCR (4 << (UNIPHIER_UART_REGSHIFT))
42 /* Divisor Latch Register */
43 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT))
45 struct uniphier8250_priv {
48 spinlock_t atomic_write_lock;
51 #ifdef CONFIG_SERIAL_8250_CONSOLE
52 static int __init uniphier_early_console_setup(struct earlycon_device *device,
55 if (!device->port.membase)
58 /* This hardware always expects MMIO32 register interface. */
59 device->port.iotype = UPIO_MEM32;
60 device->port.regshift = UNIPHIER_UART_REGSHIFT;
63 * Do not touch the divisor register in early_serial8250_setup();
64 * we assume it has been initialized by a boot loader.
68 return early_serial8250_setup(device, options);
70 OF_EARLYCON_DECLARE(uniphier, "socionext,uniphier-uart",
71 uniphier_early_console_setup);
75 * The register map is slightly different from that of 8250.
76 * IO callbacks must be overridden for correct access to FCR, LCR, MCR and SCR.
78 static unsigned int uniphier_serial_in(struct uart_port *p, int offset)
80 unsigned int valshift = 0;
84 /* No SCR for this hardware. Use CHAR as a scratch register */
86 offset = UNIPHIER_UART_CHAR_FCR;
92 offset = UNIPHIER_UART_LCR_MCR;
95 offset <<= UNIPHIER_UART_REGSHIFT;
100 * The return value must be masked with 0xff because some registers
101 * share the same offset that must be accessed by 32-bit write/read.
102 * 8 or 16 bit access to this hardware result in unexpected behavior.
104 return (readl(p->membase + offset) >> valshift) & 0xff;
107 static void uniphier_serial_out(struct uart_port *p, int offset, int value)
109 unsigned int valshift = 0;
114 /* No SCR for this hardware. Use CHAR as a scratch register */
118 offset = UNIPHIER_UART_CHAR_FCR;
122 /* Divisor latch access bit does not exist. */
123 value &= ~UART_LCR_DLAB;
126 offset = UNIPHIER_UART_LCR_MCR;
129 offset <<= UNIPHIER_UART_REGSHIFT;
135 writel(value, p->membase + offset);
138 * Special case: two registers share the same address that
139 * must be 32-bit accessed. As this is not longer atomic safe,
140 * take a lock just in case.
142 struct uniphier8250_priv *priv = p->private_data;
146 spin_lock_irqsave(&priv->atomic_write_lock, flags);
147 tmp = readl(p->membase + offset);
148 tmp &= ~(0xff << valshift);
149 tmp |= value << valshift;
150 writel(tmp, p->membase + offset);
151 spin_unlock_irqrestore(&priv->atomic_write_lock, flags);
156 * This hardware does not have the divisor latch access bit.
157 * The divisor latch register exists at different address.
158 * Override dl_read/write callbacks.
160 static int uniphier_serial_dl_read(struct uart_8250_port *up)
162 return readl(up->port.membase + UNIPHIER_UART_DLR);
165 static void uniphier_serial_dl_write(struct uart_8250_port *up, int value)
167 writel(value, up->port.membase + UNIPHIER_UART_DLR);
170 static int uniphier_of_serial_setup(struct device *dev, struct uart_port *port,
171 struct uniphier8250_priv *priv)
175 struct device_node *np = dev->of_node;
177 ret = of_alias_get_id(np, "serial");
179 dev_err(dev, "failed to get alias id\n");
184 /* Get clk rate through clk driver */
185 priv->clk = devm_clk_get(dev, NULL);
186 if (IS_ERR(priv->clk)) {
187 dev_err(dev, "failed to get clock\n");
188 return PTR_ERR(priv->clk);
191 ret = clk_prepare_enable(priv->clk);
195 port->uartclk = clk_get_rate(priv->clk);
197 /* Check for fifo size */
198 if (of_property_read_u32(np, "fifo-size", &prop) == 0)
199 port->fifosize = prop;
201 port->fifosize = UNIPHIER_UART_DEFAULT_FIFO_SIZE;
206 static int uniphier_uart_probe(struct platform_device *pdev)
208 struct device *dev = &pdev->dev;
209 struct uart_8250_port up;
210 struct uniphier8250_priv *priv;
211 struct resource *regs;
212 void __iomem *membase;
216 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
218 dev_err(dev, "failed to get memory resource\n");
222 membase = devm_ioremap(dev, regs->start, resource_size(regs));
226 irq = platform_get_irq(pdev, 0);
228 dev_err(dev, "failed to get IRQ number\n");
232 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
236 memset(&up, 0, sizeof(up));
238 ret = uniphier_of_serial_setup(dev, &up.port, priv);
242 spin_lock_init(&priv->atomic_write_lock);
245 up.port.private_data = priv;
246 up.port.mapbase = regs->start;
247 up.port.mapsize = resource_size(regs);
248 up.port.membase = membase;
251 up.port.type = PORT_16550A;
252 up.port.iotype = UPIO_MEM32;
253 up.port.regshift = UNIPHIER_UART_REGSHIFT;
254 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE;
255 up.capabilities = UART_CAP_FIFO;
257 up.port.serial_in = uniphier_serial_in;
258 up.port.serial_out = uniphier_serial_out;
259 up.dl_read = uniphier_serial_dl_read;
260 up.dl_write = uniphier_serial_dl_write;
262 ret = serial8250_register_8250_port(&up);
264 dev_err(dev, "failed to register 8250 port\n");
265 clk_disable_unprepare(priv->clk);
270 platform_set_drvdata(pdev, priv);
275 static int uniphier_uart_remove(struct platform_device *pdev)
277 struct uniphier8250_priv *priv = platform_get_drvdata(pdev);
279 serial8250_unregister_port(priv->line);
280 clk_disable_unprepare(priv->clk);
285 static int __maybe_unused uniphier_uart_suspend(struct device *dev)
287 struct uniphier8250_priv *priv = dev_get_drvdata(dev);
288 struct uart_8250_port *up = serial8250_get_port(priv->line);
290 serial8250_suspend_port(priv->line);
292 if (!uart_console(&up->port) || console_suspend_enabled)
293 clk_disable_unprepare(priv->clk);
298 static int __maybe_unused uniphier_uart_resume(struct device *dev)
300 struct uniphier8250_priv *priv = dev_get_drvdata(dev);
301 struct uart_8250_port *up = serial8250_get_port(priv->line);
304 if (!uart_console(&up->port) || console_suspend_enabled) {
305 ret = clk_prepare_enable(priv->clk);
310 serial8250_resume_port(priv->line);
315 static const struct dev_pm_ops uniphier_uart_pm_ops = {
316 SET_SYSTEM_SLEEP_PM_OPS(uniphier_uart_suspend, uniphier_uart_resume)
319 static const struct of_device_id uniphier_uart_match[] = {
320 { .compatible = "socionext,uniphier-uart" },
323 MODULE_DEVICE_TABLE(of, uniphier_uart_match);
325 static struct platform_driver uniphier_uart_platform_driver = {
326 .probe = uniphier_uart_probe,
327 .remove = uniphier_uart_remove,
329 .name = "uniphier-uart",
330 .of_match_table = uniphier_uart_match,
331 .pm = &uniphier_uart_pm_ops,
334 module_platform_driver(uniphier_uart_platform_driver);
336 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
337 MODULE_DESCRIPTION("UniPhier UART driver");
338 MODULE_LICENSE("GPL");