1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/irq.h>
19 #include <linux/console.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/sysrq.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/tty.h>
25 #include <linux/ratelimit.h>
26 #include <linux/tty_flip.h>
27 #include <linux/serial.h>
28 #include <linux/serial_8250.h>
29 #include <linux/nmi.h>
30 #include <linux/mutex.h>
31 #include <linux/slab.h>
32 #include <linux/uaccess.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/ktime.h>
41 /* Nuvoton NPCM timeout register */
42 #define UART_NPCM_TOR 7
43 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
49 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
51 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
54 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
57 * Here we define the default xmit fifo size used for each type of UART.
59 static const struct serial8250_config uart_config[] = {
84 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
85 .rxtrig_bytes = {1, 4, 8, 14},
86 .flags = UART_CAP_FIFO,
97 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
103 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
105 .rxtrig_bytes = {8, 16, 24, 28},
106 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
112 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
114 .rxtrig_bytes = {1, 16, 32, 56},
115 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
123 .name = "16C950/954",
126 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
127 .rxtrig_bytes = {16, 32, 112, 120},
128 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
129 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
135 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
137 .rxtrig_bytes = {8, 16, 56, 60},
138 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
144 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
145 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
151 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
152 .flags = UART_CAP_FIFO,
158 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
159 .flags = UART_CAP_FIFO | UART_NATSEMI,
165 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
166 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
172 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
173 .flags = UART_CAP_FIFO,
179 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
180 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
186 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
187 .flags = UART_CAP_FIFO | UART_CAP_AFE,
193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 .rxtrig_bytes = {1, 4, 8, 14},
196 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
212 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
219 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
220 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
221 .flags = UART_CAP_FIFO,
223 [PORT_BRCM_TRUMANAGE] = {
227 .flags = UART_CAP_HFIFO,
232 [PORT_ALTR_16550_F32] = {
233 .name = "Altera 16550 FIFO32",
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .rxtrig_bytes = {1, 8, 16, 30},
238 .flags = UART_CAP_FIFO | UART_CAP_AFE,
240 [PORT_ALTR_16550_F64] = {
241 .name = "Altera 16550 FIFO64",
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .rxtrig_bytes = {1, 16, 32, 62},
246 .flags = UART_CAP_FIFO | UART_CAP_AFE,
248 [PORT_ALTR_16550_F128] = {
249 .name = "Altera 16550 FIFO128",
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .rxtrig_bytes = {1, 32, 64, 126},
254 .flags = UART_CAP_FIFO | UART_CAP_AFE,
257 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
258 * workaround of errata A-008006 which states that tx_loadsz should
259 * be configured less than Maximum supported fifo bytes.
261 [PORT_16550A_FSL64] = {
262 .name = "16550A_FSL64",
265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
267 .flags = UART_CAP_FIFO,
270 .name = "Palmchip BK-3103",
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .rxtrig_bytes = {1, 4, 8, 14},
275 .flags = UART_CAP_FIFO,
278 .name = "TI DA8xx/66AK2x",
281 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
283 .rxtrig_bytes = {1, 4, 8, 14},
284 .flags = UART_CAP_FIFO | UART_CAP_AFE,
287 .name = "MediaTek BTIF",
290 .fcr = UART_FCR_ENABLE_FIFO |
291 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
292 .flags = UART_CAP_FIFO,
295 .name = "Nuvoton 16550",
298 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
299 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
300 .rxtrig_bytes = {1, 4, 8, 14},
301 .flags = UART_CAP_FIFO,
307 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
308 .rxtrig_bytes = {1, 32, 64, 112},
309 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
313 /* Uart divisor latch read */
314 static int default_serial_dl_read(struct uart_8250_port *up)
316 /* Assign these in pieces to truncate any bits above 7. */
317 unsigned char dll = serial_in(up, UART_DLL);
318 unsigned char dlm = serial_in(up, UART_DLM);
320 return dll | dlm << 8;
323 /* Uart divisor latch write */
324 static void default_serial_dl_write(struct uart_8250_port *up, int value)
326 serial_out(up, UART_DLL, value & 0xff);
327 serial_out(up, UART_DLM, value >> 8 & 0xff);
330 #ifdef CONFIG_SERIAL_8250_RT288X
332 /* Au1x00/RT288x UART hardware has a weird register layout */
333 static const s8 au_io_in_map[8] = {
341 -1, /* UART_SCR (unmapped) */
344 static const s8 au_io_out_map[8] = {
350 -1, /* UART_LSR (unmapped) */
351 -1, /* UART_MSR (unmapped) */
352 -1, /* UART_SCR (unmapped) */
355 unsigned int au_serial_in(struct uart_port *p, int offset)
357 if (offset >= ARRAY_SIZE(au_io_in_map))
359 offset = au_io_in_map[offset];
362 return __raw_readl(p->membase + (offset << p->regshift));
365 void au_serial_out(struct uart_port *p, int offset, int value)
367 if (offset >= ARRAY_SIZE(au_io_out_map))
369 offset = au_io_out_map[offset];
372 __raw_writel(value, p->membase + (offset << p->regshift));
375 /* Au1x00 haven't got a standard divisor latch */
376 static int au_serial_dl_read(struct uart_8250_port *up)
378 return __raw_readl(up->port.membase + 0x28);
381 static void au_serial_dl_write(struct uart_8250_port *up, int value)
383 __raw_writel(value, up->port.membase + 0x28);
388 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
390 offset = offset << p->regshift;
391 outb(p->hub6 - 1 + offset, p->iobase);
392 return inb(p->iobase + 1);
395 static void hub6_serial_out(struct uart_port *p, int offset, int value)
397 offset = offset << p->regshift;
398 outb(p->hub6 - 1 + offset, p->iobase);
399 outb(value, p->iobase + 1);
402 static unsigned int mem_serial_in(struct uart_port *p, int offset)
404 offset = offset << p->regshift;
405 return readb(p->membase + offset);
408 static void mem_serial_out(struct uart_port *p, int offset, int value)
410 offset = offset << p->regshift;
411 writeb(value, p->membase + offset);
414 static void mem16_serial_out(struct uart_port *p, int offset, int value)
416 offset = offset << p->regshift;
417 writew(value, p->membase + offset);
420 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
422 offset = offset << p->regshift;
423 return readw(p->membase + offset);
426 static void mem32_serial_out(struct uart_port *p, int offset, int value)
428 offset = offset << p->regshift;
429 writel(value, p->membase + offset);
432 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
434 offset = offset << p->regshift;
435 return readl(p->membase + offset);
438 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
440 offset = offset << p->regshift;
441 iowrite32be(value, p->membase + offset);
444 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
446 offset = offset << p->regshift;
447 return ioread32be(p->membase + offset);
450 static unsigned int io_serial_in(struct uart_port *p, int offset)
452 offset = offset << p->regshift;
453 return inb(p->iobase + offset);
456 static void io_serial_out(struct uart_port *p, int offset, int value)
458 offset = offset << p->regshift;
459 outb(value, p->iobase + offset);
462 static int serial8250_default_handle_irq(struct uart_port *port);
464 static void set_io_from_upio(struct uart_port *p)
466 struct uart_8250_port *up = up_to_u8250p(p);
468 up->dl_read = default_serial_dl_read;
469 up->dl_write = default_serial_dl_write;
473 p->serial_in = hub6_serial_in;
474 p->serial_out = hub6_serial_out;
478 p->serial_in = mem_serial_in;
479 p->serial_out = mem_serial_out;
483 p->serial_in = mem16_serial_in;
484 p->serial_out = mem16_serial_out;
488 p->serial_in = mem32_serial_in;
489 p->serial_out = mem32_serial_out;
493 p->serial_in = mem32be_serial_in;
494 p->serial_out = mem32be_serial_out;
497 #ifdef CONFIG_SERIAL_8250_RT288X
499 p->serial_in = au_serial_in;
500 p->serial_out = au_serial_out;
501 up->dl_read = au_serial_dl_read;
502 up->dl_write = au_serial_dl_write;
507 p->serial_in = io_serial_in;
508 p->serial_out = io_serial_out;
511 /* Remember loaded iotype */
512 up->cur_iotype = p->iotype;
513 p->handle_irq = serial8250_default_handle_irq;
517 serial_port_out_sync(struct uart_port *p, int offset, int value)
525 p->serial_out(p, offset, value);
526 p->serial_in(p, UART_LCR); /* safe, no side-effects */
529 p->serial_out(p, offset, value);
536 static void serial8250_clear_fifos(struct uart_8250_port *p)
538 if (p->capabilities & UART_CAP_FIFO) {
539 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
540 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
541 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
542 serial_out(p, UART_FCR, 0);
546 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
547 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
549 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
551 serial8250_clear_fifos(p);
552 serial_out(p, UART_FCR, p->fcr);
554 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
556 void serial8250_rpm_get(struct uart_8250_port *p)
558 if (!(p->capabilities & UART_CAP_RPM))
560 pm_runtime_get_sync(p->port.dev);
562 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
564 void serial8250_rpm_put(struct uart_8250_port *p)
566 if (!(p->capabilities & UART_CAP_RPM))
568 pm_runtime_mark_last_busy(p->port.dev);
569 pm_runtime_put_autosuspend(p->port.dev);
571 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
574 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
575 * @p: uart_8250_port port instance
577 * The function is used to start rs485 software emulating on the
578 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
579 * transmission. The function is idempotent, so it is safe to call it
582 * The caller MUST enable interrupt on empty shift register before
583 * calling serial8250_em485_init(). This interrupt is not a part of
584 * 8250 standard, but implementation defined.
586 * The function is supposed to be called from .rs485_config callback
587 * or from any other callback protected with p->port.lock spinlock.
589 * See also serial8250_em485_destroy()
591 * Return 0 - success, -errno - otherwise
593 static int serial8250_em485_init(struct uart_8250_port *p)
598 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
602 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
604 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
606 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
607 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
609 p->em485->active_timer = NULL;
610 p->em485->tx_stopped = true;
613 if (p->em485->tx_stopped)
620 * serial8250_em485_destroy() - put uart_8250_port into normal state
621 * @p: uart_8250_port port instance
623 * The function is used to stop rs485 software emulating on the
624 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
625 * call it multiple times.
627 * The function is supposed to be called from .rs485_config callback
628 * or from any other callback protected with p->port.lock spinlock.
630 * See also serial8250_em485_init()
632 void serial8250_em485_destroy(struct uart_8250_port *p)
637 hrtimer_cancel(&p->em485->start_tx_timer);
638 hrtimer_cancel(&p->em485->stop_tx_timer);
643 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
646 * serial8250_em485_config() - generic ->rs485_config() callback
648 * @rs485: rs485 settings
650 * Generic callback usable by 8250 uart drivers to activate rs485 settings
651 * if the uart is incapable of driving RTS as a Transmit Enable signal in
652 * hardware, relying on software emulation instead.
654 int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
656 struct uart_8250_port *up = up_to_u8250p(port);
658 /* pick sane settings if the user hasn't */
659 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
660 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
661 rs485->flags |= SER_RS485_RTS_ON_SEND;
662 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
665 gpiod_set_value(port->rs485_term_gpio,
666 rs485->flags & SER_RS485_TERMINATE_BUS);
669 * Both serial8250_em485_init() and serial8250_em485_destroy()
672 if (rs485->flags & SER_RS485_ENABLED)
673 return serial8250_em485_init(up);
675 serial8250_em485_destroy(up);
678 EXPORT_SYMBOL_GPL(serial8250_em485_config);
681 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
682 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
683 * empty and the HW can idle again.
685 void serial8250_rpm_get_tx(struct uart_8250_port *p)
687 unsigned char rpm_active;
689 if (!(p->capabilities & UART_CAP_RPM))
692 rpm_active = xchg(&p->rpm_tx_active, 1);
695 pm_runtime_get_sync(p->port.dev);
697 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
699 void serial8250_rpm_put_tx(struct uart_8250_port *p)
701 unsigned char rpm_active;
703 if (!(p->capabilities & UART_CAP_RPM))
706 rpm_active = xchg(&p->rpm_tx_active, 0);
709 pm_runtime_mark_last_busy(p->port.dev);
710 pm_runtime_put_autosuspend(p->port.dev);
712 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
715 * IER sleep support. UARTs which have EFRs need the "extended
716 * capability" bit enabled. Note that on XR16C850s, we need to
717 * reset LCR to write to IER.
719 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
721 unsigned char lcr = 0, efr = 0;
723 serial8250_rpm_get(p);
725 if (p->capabilities & UART_CAP_SLEEP) {
726 if (p->capabilities & UART_CAP_EFR) {
727 lcr = serial_in(p, UART_LCR);
728 efr = serial_in(p, UART_EFR);
729 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
730 serial_out(p, UART_EFR, UART_EFR_ECB);
731 serial_out(p, UART_LCR, 0);
733 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
734 if (p->capabilities & UART_CAP_EFR) {
735 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
736 serial_out(p, UART_EFR, efr);
737 serial_out(p, UART_LCR, lcr);
741 serial8250_rpm_put(p);
744 #ifdef CONFIG_SERIAL_8250_RSA
746 * Attempts to turn on the RSA FIFO. Returns zero on failure.
747 * We set the port uart clock rate if we succeed.
749 static int __enable_rsa(struct uart_8250_port *up)
754 mode = serial_in(up, UART_RSA_MSR);
755 result = mode & UART_RSA_MSR_FIFO;
758 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
759 mode = serial_in(up, UART_RSA_MSR);
760 result = mode & UART_RSA_MSR_FIFO;
764 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
769 static void enable_rsa(struct uart_8250_port *up)
771 if (up->port.type == PORT_RSA) {
772 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
773 spin_lock_irq(&up->port.lock);
775 spin_unlock_irq(&up->port.lock);
777 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
778 serial_out(up, UART_RSA_FRR, 0);
783 * Attempts to turn off the RSA FIFO. Returns zero on failure.
784 * It is unknown why interrupts were disabled in here. However,
785 * the caller is expected to preserve this behaviour by grabbing
786 * the spinlock before calling this function.
788 static void disable_rsa(struct uart_8250_port *up)
793 if (up->port.type == PORT_RSA &&
794 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
795 spin_lock_irq(&up->port.lock);
797 mode = serial_in(up, UART_RSA_MSR);
798 result = !(mode & UART_RSA_MSR_FIFO);
801 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
802 mode = serial_in(up, UART_RSA_MSR);
803 result = !(mode & UART_RSA_MSR_FIFO);
807 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
808 spin_unlock_irq(&up->port.lock);
811 #endif /* CONFIG_SERIAL_8250_RSA */
814 * This is a quickie test to see how big the FIFO is.
815 * It doesn't work at all the time, more's the pity.
817 static int size_fifo(struct uart_8250_port *up)
819 unsigned char old_fcr, old_mcr, old_lcr;
820 unsigned short old_dl;
823 old_lcr = serial_in(up, UART_LCR);
824 serial_out(up, UART_LCR, 0);
825 old_fcr = serial_in(up, UART_FCR);
826 old_mcr = serial8250_in_MCR(up);
827 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
828 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
829 serial8250_out_MCR(up, UART_MCR_LOOP);
830 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
831 old_dl = serial_dl_read(up);
832 serial_dl_write(up, 0x0001);
833 serial_out(up, UART_LCR, 0x03);
834 for (count = 0; count < 256; count++)
835 serial_out(up, UART_TX, count);
836 mdelay(20);/* FIXME - schedule_timeout */
837 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
838 (count < 256); count++)
839 serial_in(up, UART_RX);
840 serial_out(up, UART_FCR, old_fcr);
841 serial8250_out_MCR(up, old_mcr);
842 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
843 serial_dl_write(up, old_dl);
844 serial_out(up, UART_LCR, old_lcr);
850 * Read UART ID using the divisor method - set DLL and DLM to zero
851 * and the revision will be in DLL and device type in DLM. We
852 * preserve the device state across this.
854 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
856 unsigned char old_lcr;
857 unsigned int id, old_dl;
859 old_lcr = serial_in(p, UART_LCR);
860 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
861 old_dl = serial_dl_read(p);
862 serial_dl_write(p, 0);
863 id = serial_dl_read(p);
864 serial_dl_write(p, old_dl);
866 serial_out(p, UART_LCR, old_lcr);
872 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
873 * When this function is called we know it is at least a StarTech
874 * 16650 V2, but it might be one of several StarTech UARTs, or one of
875 * its clones. (We treat the broken original StarTech 16650 V1 as a
876 * 16550, and why not? Startech doesn't seem to even acknowledge its
879 * What evil have men's minds wrought...
881 static void autoconfig_has_efr(struct uart_8250_port *up)
883 unsigned int id1, id2, id3, rev;
886 * Everything with an EFR has SLEEP
888 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
891 * First we check to see if it's an Oxford Semiconductor UART.
893 * If we have to do this here because some non-National
894 * Semiconductor clone chips lock up if you try writing to the
895 * LSR register (which serial_icr_read does)
899 * Check for Oxford Semiconductor 16C950.
901 * EFR [4] must be set else this test fails.
903 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
904 * claims that it's needed for 952 dual UART's (which are not
905 * recommended for new designs).
908 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
909 serial_out(up, UART_EFR, UART_EFR_ECB);
910 serial_out(up, UART_LCR, 0x00);
911 id1 = serial_icr_read(up, UART_ID1);
912 id2 = serial_icr_read(up, UART_ID2);
913 id3 = serial_icr_read(up, UART_ID3);
914 rev = serial_icr_read(up, UART_REV);
916 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
918 if (id1 == 0x16 && id2 == 0xC9 &&
919 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
920 up->port.type = PORT_16C950;
923 * Enable work around for the Oxford Semiconductor 952 rev B
924 * chip which causes it to seriously miscalculate baud rates
927 if (id3 == 0x52 && rev == 0x01)
928 up->bugs |= UART_BUG_QUOT;
933 * We check for a XR16C850 by setting DLL and DLM to 0, and then
934 * reading back DLL and DLM. The chip type depends on the DLM
936 * 0x10 - XR16C850 and the DLL contains the chip revision.
940 id1 = autoconfig_read_divisor_id(up);
941 DEBUG_AUTOCONF("850id=%04x ", id1);
944 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
945 up->port.type = PORT_16850;
950 * It wasn't an XR16C850.
952 * We distinguish between the '654 and the '650 by counting
953 * how many bytes are in the FIFO. I'm using this for now,
954 * since that's the technique that was sent to me in the
955 * serial driver update, but I'm not convinced this works.
956 * I've had problems doing this in the past. -TYT
958 if (size_fifo(up) == 64)
959 up->port.type = PORT_16654;
961 up->port.type = PORT_16650V2;
965 * We detected a chip without a FIFO. Only two fall into
966 * this category - the original 8250 and the 16450. The
967 * 16450 has a scratch register (accessible with LCR=0)
969 static void autoconfig_8250(struct uart_8250_port *up)
971 unsigned char scratch, status1, status2;
973 up->port.type = PORT_8250;
975 scratch = serial_in(up, UART_SCR);
976 serial_out(up, UART_SCR, 0xa5);
977 status1 = serial_in(up, UART_SCR);
978 serial_out(up, UART_SCR, 0x5a);
979 status2 = serial_in(up, UART_SCR);
980 serial_out(up, UART_SCR, scratch);
982 if (status1 == 0xa5 && status2 == 0x5a)
983 up->port.type = PORT_16450;
986 static int broken_efr(struct uart_8250_port *up)
989 * Exar ST16C2550 "A2" devices incorrectly detect as
990 * having an EFR, and report an ID of 0x0201. See
991 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
993 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1000 * We know that the chip has FIFOs. Does it have an EFR? The
1001 * EFR is located in the same register position as the IIR and
1002 * we know the top two bits of the IIR are currently set. The
1003 * EFR should contain zero. Try to read the EFR.
1005 static void autoconfig_16550a(struct uart_8250_port *up)
1007 unsigned char status1, status2;
1008 unsigned int iersave;
1010 up->port.type = PORT_16550A;
1011 up->capabilities |= UART_CAP_FIFO;
1013 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
1014 !(up->port.flags & UPF_FULL_PROBE))
1018 * Check for presence of the EFR when DLAB is set.
1019 * Only ST16C650V1 UARTs pass this test.
1021 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1022 if (serial_in(up, UART_EFR) == 0) {
1023 serial_out(up, UART_EFR, 0xA8);
1024 if (serial_in(up, UART_EFR) != 0) {
1025 DEBUG_AUTOCONF("EFRv1 ");
1026 up->port.type = PORT_16650;
1027 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1029 serial_out(up, UART_LCR, 0);
1030 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1032 status1 = serial_in(up, UART_IIR) >> 5;
1033 serial_out(up, UART_FCR, 0);
1034 serial_out(up, UART_LCR, 0);
1037 up->port.type = PORT_16550A_FSL64;
1039 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1041 serial_out(up, UART_EFR, 0);
1046 * Maybe it requires 0xbf to be written to the LCR.
1047 * (other ST16C650V2 UARTs, TI16C752A, etc)
1049 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1050 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1051 DEBUG_AUTOCONF("EFRv2 ");
1052 autoconfig_has_efr(up);
1057 * Check for a National Semiconductor SuperIO chip.
1058 * Attempt to switch to bank 2, read the value of the LOOP bit
1059 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1060 * switch back to bank 2, read it from EXCR1 again and check
1061 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1063 serial_out(up, UART_LCR, 0);
1064 status1 = serial8250_in_MCR(up);
1065 serial_out(up, UART_LCR, 0xE0);
1066 status2 = serial_in(up, 0x02); /* EXCR1 */
1068 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1069 serial_out(up, UART_LCR, 0);
1070 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1071 serial_out(up, UART_LCR, 0xE0);
1072 status2 = serial_in(up, 0x02); /* EXCR1 */
1073 serial_out(up, UART_LCR, 0);
1074 serial8250_out_MCR(up, status1);
1076 if ((status2 ^ status1) & UART_MCR_LOOP) {
1077 unsigned short quot;
1079 serial_out(up, UART_LCR, 0xE0);
1081 quot = serial_dl_read(up);
1084 if (ns16550a_goto_highspeed(up))
1085 serial_dl_write(up, quot);
1087 serial_out(up, UART_LCR, 0);
1089 up->port.uartclk = 921600*16;
1090 up->port.type = PORT_NS16550A;
1091 up->capabilities |= UART_NATSEMI;
1097 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1098 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1099 * Try setting it with and without DLAB set. Cheap clones
1100 * set bit 5 without DLAB set.
1102 serial_out(up, UART_LCR, 0);
1103 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1104 status1 = serial_in(up, UART_IIR) >> 5;
1105 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1106 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1107 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1108 status2 = serial_in(up, UART_IIR) >> 5;
1109 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1110 serial_out(up, UART_LCR, 0);
1112 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1114 if (status1 == 6 && status2 == 7) {
1115 up->port.type = PORT_16750;
1116 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1121 * Try writing and reading the UART_IER_UUE bit (b6).
1122 * If it works, this is probably one of the Xscale platform's
1124 * We're going to explicitly set the UUE bit to 0 before
1125 * trying to write and read a 1 just to make sure it's not
1126 * already a 1 and maybe locked there before we even start start.
1128 iersave = serial_in(up, UART_IER);
1129 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1130 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1132 * OK it's in a known zero state, try writing and reading
1133 * without disturbing the current state of the other bits.
1135 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1136 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1139 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1141 DEBUG_AUTOCONF("Xscale ");
1142 up->port.type = PORT_XSCALE;
1143 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1148 * If we got here we couldn't force the IER_UUE bit to 0.
1149 * Log it and continue.
1151 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1153 serial_out(up, UART_IER, iersave);
1156 * We distinguish between 16550A and U6 16550A by counting
1157 * how many bytes are in the FIFO.
1159 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1160 up->port.type = PORT_U6_16550A;
1161 up->capabilities |= UART_CAP_AFE;
1166 * This routine is called by rs_init() to initialize a specific serial
1167 * port. It determines what type of UART chip this serial port is
1168 * using: 8250, 16450, 16550, 16550A. The important question is
1169 * whether or not this UART is a 16550A or not, since this will
1170 * determine whether or not we can use its FIFO features or not.
1172 static void autoconfig(struct uart_8250_port *up)
1174 unsigned char status1, scratch, scratch2, scratch3;
1175 unsigned char save_lcr, save_mcr;
1176 struct uart_port *port = &up->port;
1177 unsigned long flags;
1178 unsigned int old_capabilities;
1180 if (!port->iobase && !port->mapbase && !port->membase)
1183 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1184 port->name, port->iobase, port->membase);
1187 * We really do need global IRQs disabled here - we're going to
1188 * be frobbing the chips IRQ enable register to see if it exists.
1190 spin_lock_irqsave(&port->lock, flags);
1192 up->capabilities = 0;
1195 if (!(port->flags & UPF_BUGGY_UART)) {
1197 * Do a simple existence test first; if we fail this,
1198 * there's no point trying anything else.
1200 * 0x80 is used as a nonsense port to prevent against
1201 * false positives due to ISA bus float. The
1202 * assumption is that 0x80 is a non-existent port;
1203 * which should be safe since include/asm/io.h also
1204 * makes this assumption.
1206 * Note: this is safe as long as MCR bit 4 is clear
1207 * and the device is in "PC" mode.
1209 scratch = serial_in(up, UART_IER);
1210 serial_out(up, UART_IER, 0);
1215 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1216 * 16C754B) allow only to modify them if an EFR bit is set.
1218 scratch2 = serial_in(up, UART_IER) & 0x0f;
1219 serial_out(up, UART_IER, 0x0F);
1223 scratch3 = serial_in(up, UART_IER) & 0x0f;
1224 serial_out(up, UART_IER, scratch);
1225 if (scratch2 != 0 || scratch3 != 0x0F) {
1227 * We failed; there's nothing here
1229 spin_unlock_irqrestore(&port->lock, flags);
1230 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1231 scratch2, scratch3);
1236 save_mcr = serial8250_in_MCR(up);
1237 save_lcr = serial_in(up, UART_LCR);
1240 * Check to see if a UART is really there. Certain broken
1241 * internal modems based on the Rockwell chipset fail this
1242 * test, because they apparently don't implement the loopback
1243 * test mode. So this test is skipped on the COM 1 through
1244 * COM 4 ports. This *should* be safe, since no board
1245 * manufacturer would be stupid enough to design a board
1246 * that conflicts with COM 1-4 --- we hope!
1248 if (!(port->flags & UPF_SKIP_TEST)) {
1249 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1250 status1 = serial_in(up, UART_MSR) & 0xF0;
1251 serial8250_out_MCR(up, save_mcr);
1252 if (status1 != 0x90) {
1253 spin_unlock_irqrestore(&port->lock, flags);
1254 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1261 * We're pretty sure there's a port here. Lets find out what
1262 * type of port it is. The IIR top two bits allows us to find
1263 * out if it's 8250 or 16450, 16550, 16550A or later. This
1264 * determines what we test for next.
1266 * We also initialise the EFR (if any) to zero for later. The
1267 * EFR occupies the same register location as the FCR and IIR.
1269 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1270 serial_out(up, UART_EFR, 0);
1271 serial_out(up, UART_LCR, 0);
1273 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1275 /* Assign this as it is to truncate any bits above 7. */
1276 scratch = serial_in(up, UART_IIR);
1278 switch (scratch >> 6) {
1280 autoconfig_8250(up);
1283 port->type = PORT_UNKNOWN;
1286 port->type = PORT_16550;
1289 autoconfig_16550a(up);
1293 #ifdef CONFIG_SERIAL_8250_RSA
1295 * Only probe for RSA ports if we got the region.
1297 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1299 port->type = PORT_RSA;
1302 serial_out(up, UART_LCR, save_lcr);
1304 port->fifosize = uart_config[up->port.type].fifo_size;
1305 old_capabilities = up->capabilities;
1306 up->capabilities = uart_config[port->type].flags;
1307 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1309 if (port->type == PORT_UNKNOWN)
1315 #ifdef CONFIG_SERIAL_8250_RSA
1316 if (port->type == PORT_RSA)
1317 serial_out(up, UART_RSA_FRR, 0);
1319 serial8250_out_MCR(up, save_mcr);
1320 serial8250_clear_fifos(up);
1321 serial_in(up, UART_RX);
1322 if (up->capabilities & UART_CAP_UUE)
1323 serial_out(up, UART_IER, UART_IER_UUE);
1325 serial_out(up, UART_IER, 0);
1328 spin_unlock_irqrestore(&port->lock, flags);
1331 * Check if the device is a Fintek F81216A
1333 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1334 fintek_8250_probe(up);
1336 if (up->capabilities != old_capabilities) {
1337 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1338 old_capabilities, up->capabilities);
1341 DEBUG_AUTOCONF("iir=%d ", scratch);
1342 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1345 static void autoconfig_irq(struct uart_8250_port *up)
1347 struct uart_port *port = &up->port;
1348 unsigned char save_mcr, save_ier;
1349 unsigned char save_ICP = 0;
1350 unsigned int ICP = 0;
1354 if (port->flags & UPF_FOURPORT) {
1355 ICP = (port->iobase & 0xfe0) | 0x1f;
1356 save_ICP = inb_p(ICP);
1361 /* forget possible initially masked and pending IRQ */
1362 probe_irq_off(probe_irq_on());
1363 save_mcr = serial8250_in_MCR(up);
1364 save_ier = serial_in(up, UART_IER);
1365 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1367 irqs = probe_irq_on();
1368 serial8250_out_MCR(up, 0);
1370 if (port->flags & UPF_FOURPORT) {
1371 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1373 serial8250_out_MCR(up,
1374 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1376 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1377 serial_in(up, UART_LSR);
1378 serial_in(up, UART_RX);
1379 serial_in(up, UART_IIR);
1380 serial_in(up, UART_MSR);
1381 serial_out(up, UART_TX, 0xFF);
1383 irq = probe_irq_off(irqs);
1385 serial8250_out_MCR(up, save_mcr);
1386 serial_out(up, UART_IER, save_ier);
1388 if (port->flags & UPF_FOURPORT)
1389 outb_p(save_ICP, ICP);
1391 port->irq = (irq > 0) ? irq : 0;
1394 static void serial8250_stop_rx(struct uart_port *port)
1396 struct uart_8250_port *up = up_to_u8250p(port);
1398 serial8250_rpm_get(up);
1400 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1401 up->port.read_status_mask &= ~UART_LSR_DR;
1402 serial_port_out(port, UART_IER, up->ier);
1404 serial8250_rpm_put(up);
1408 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1409 * @p: uart 8250 port
1411 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1413 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1415 unsigned char mcr = serial8250_in_MCR(p);
1417 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1418 mcr |= UART_MCR_RTS;
1420 mcr &= ~UART_MCR_RTS;
1421 serial8250_out_MCR(p, mcr);
1424 * Empty the RX FIFO, we are not interested in anything
1425 * received during the half-duplex transmission.
1426 * Enable previously disabled RX interrupts.
1428 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1429 serial8250_clear_and_reinit_fifos(p);
1431 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1432 serial_port_out(&p->port, UART_IER, p->ier);
1435 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1437 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1439 struct uart_8250_em485 *em485;
1440 struct uart_8250_port *p;
1441 unsigned long flags;
1443 em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1446 serial8250_rpm_get(p);
1447 spin_lock_irqsave(&p->port.lock, flags);
1448 if (em485->active_timer == &em485->stop_tx_timer) {
1449 p->rs485_stop_tx(p);
1450 em485->active_timer = NULL;
1451 em485->tx_stopped = true;
1453 spin_unlock_irqrestore(&p->port.lock, flags);
1454 serial8250_rpm_put(p);
1455 return HRTIMER_NORESTART;
1458 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1460 long sec = msec / 1000;
1461 long nsec = (msec % 1000) * 1000000;
1462 ktime_t t = ktime_set(sec, nsec);
1464 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1467 static void __stop_tx_rs485(struct uart_8250_port *p)
1469 struct uart_8250_em485 *em485 = p->em485;
1472 * rs485_stop_tx() is going to set RTS according to config
1473 * AND flush RX FIFO if required.
1475 if (p->port.rs485.delay_rts_after_send > 0) {
1476 em485->active_timer = &em485->stop_tx_timer;
1477 start_hrtimer_ms(&em485->stop_tx_timer,
1478 p->port.rs485.delay_rts_after_send);
1480 p->rs485_stop_tx(p);
1481 em485->active_timer = NULL;
1482 em485->tx_stopped = true;
1486 static inline void __do_stop_tx(struct uart_8250_port *p)
1488 if (serial8250_clear_THRI(p))
1489 serial8250_rpm_put_tx(p);
1492 static inline void __stop_tx(struct uart_8250_port *p)
1494 struct uart_8250_em485 *em485 = p->em485;
1497 unsigned char lsr = serial_in(p, UART_LSR);
1498 p->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1501 * To provide required timeing and allow FIFO transfer,
1502 * __stop_tx_rs485() must be called only when both FIFO and
1503 * shift register are empty. It is for device driver to enable
1504 * interrupt on TEMT.
1506 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1514 static void serial8250_stop_tx(struct uart_port *port)
1516 struct uart_8250_port *up = up_to_u8250p(port);
1518 serial8250_rpm_get(up);
1522 * We really want to stop the transmitter from sending.
1524 if (port->type == PORT_16C950) {
1525 up->acr |= UART_ACR_TXDIS;
1526 serial_icr_write(up, UART_ACR, up->acr);
1528 serial8250_rpm_put(up);
1531 static inline void __start_tx(struct uart_port *port)
1533 struct uart_8250_port *up = up_to_u8250p(port);
1535 if (up->dma && !up->dma->tx_dma(up))
1538 if (serial8250_set_THRI(up)) {
1539 if (up->bugs & UART_BUG_TXEN) {
1542 lsr = serial_in(up, UART_LSR);
1543 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1544 if (lsr & UART_LSR_THRE)
1545 serial8250_tx_chars(up);
1550 * Re-enable the transmitter if we disabled it.
1552 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1553 up->acr &= ~UART_ACR_TXDIS;
1554 serial_icr_write(up, UART_ACR, up->acr);
1559 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1560 * @up: uart 8250 port
1562 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1563 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1564 * (Some chips use inverse semantics.) Further assumes that reception is
1565 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1566 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1568 void serial8250_em485_start_tx(struct uart_8250_port *up)
1570 unsigned char mcr = serial8250_in_MCR(up);
1572 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1573 serial8250_stop_rx(&up->port);
1575 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1576 mcr |= UART_MCR_RTS;
1578 mcr &= ~UART_MCR_RTS;
1579 serial8250_out_MCR(up, mcr);
1581 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1583 static inline void start_tx_rs485(struct uart_port *port)
1585 struct uart_8250_port *up = up_to_u8250p(port);
1586 struct uart_8250_em485 *em485 = up->em485;
1589 * While serial8250_em485_handle_stop_tx() is a noop if
1590 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1591 * the timer is still armed and triggers only after the current bunch of
1592 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1593 * So cancel the timer. There is still a theoretical race condition if
1594 * the timer is already running and only comes around to check for
1595 * em485->active_timer when &em485->stop_tx_timer is armed again.
1597 if (em485->active_timer == &em485->stop_tx_timer)
1598 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1600 em485->active_timer = NULL;
1602 if (em485->tx_stopped) {
1603 em485->tx_stopped = false;
1605 up->rs485_start_tx(up);
1607 if (up->port.rs485.delay_rts_before_send > 0) {
1608 em485->active_timer = &em485->start_tx_timer;
1609 start_hrtimer_ms(&em485->start_tx_timer,
1610 up->port.rs485.delay_rts_before_send);
1618 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1620 struct uart_8250_em485 *em485;
1621 struct uart_8250_port *p;
1622 unsigned long flags;
1624 em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1627 spin_lock_irqsave(&p->port.lock, flags);
1628 if (em485->active_timer == &em485->start_tx_timer) {
1629 __start_tx(&p->port);
1630 em485->active_timer = NULL;
1632 spin_unlock_irqrestore(&p->port.lock, flags);
1633 return HRTIMER_NORESTART;
1636 static void serial8250_start_tx(struct uart_port *port)
1638 struct uart_8250_port *up = up_to_u8250p(port);
1639 struct uart_8250_em485 *em485 = up->em485;
1641 serial8250_rpm_get_tx(up);
1644 em485->active_timer == &em485->start_tx_timer)
1648 start_tx_rs485(port);
1653 static void serial8250_throttle(struct uart_port *port)
1655 port->throttle(port);
1658 static void serial8250_unthrottle(struct uart_port *port)
1660 port->unthrottle(port);
1663 static void serial8250_disable_ms(struct uart_port *port)
1665 struct uart_8250_port *up = up_to_u8250p(port);
1667 /* no MSR capabilities */
1668 if (up->bugs & UART_BUG_NOMSR)
1671 mctrl_gpio_disable_ms(up->gpios);
1673 up->ier &= ~UART_IER_MSI;
1674 serial_port_out(port, UART_IER, up->ier);
1677 static void serial8250_enable_ms(struct uart_port *port)
1679 struct uart_8250_port *up = up_to_u8250p(port);
1681 /* no MSR capabilities */
1682 if (up->bugs & UART_BUG_NOMSR)
1685 mctrl_gpio_enable_ms(up->gpios);
1687 up->ier |= UART_IER_MSI;
1689 serial8250_rpm_get(up);
1690 serial_port_out(port, UART_IER, up->ier);
1691 serial8250_rpm_put(up);
1694 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1696 struct uart_port *port = &up->port;
1698 char flag = TTY_NORMAL;
1700 if (likely(lsr & UART_LSR_DR))
1701 ch = serial_in(up, UART_RX);
1704 * Intel 82571 has a Serial Over Lan device that will
1705 * set UART_LSR_BI without setting UART_LSR_DR when
1706 * it receives a break. To avoid reading from the
1707 * receive buffer without UART_LSR_DR bit set, we
1708 * just force the read character to be 0
1714 lsr |= up->lsr_saved_flags;
1715 up->lsr_saved_flags = 0;
1717 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1718 if (lsr & UART_LSR_BI) {
1719 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1722 * We do the SysRQ and SAK checking
1723 * here because otherwise the break
1724 * may get masked by ignore_status_mask
1725 * or read_status_mask.
1727 if (uart_handle_break(port))
1729 } else if (lsr & UART_LSR_PE)
1730 port->icount.parity++;
1731 else if (lsr & UART_LSR_FE)
1732 port->icount.frame++;
1733 if (lsr & UART_LSR_OE)
1734 port->icount.overrun++;
1737 * Mask off conditions which should be ignored.
1739 lsr &= port->read_status_mask;
1741 if (lsr & UART_LSR_BI) {
1742 dev_dbg(port->dev, "handling break\n");
1744 } else if (lsr & UART_LSR_PE)
1746 else if (lsr & UART_LSR_FE)
1749 if (uart_prepare_sysrq_char(port, ch))
1752 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1754 EXPORT_SYMBOL_GPL(serial8250_read_char);
1757 * serial8250_rx_chars: processes according to the passed in LSR
1758 * value, and returns the remaining LSR bits not handled
1759 * by this Rx routine.
1761 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1763 struct uart_port *port = &up->port;
1764 int max_count = 256;
1767 serial8250_read_char(up, lsr);
1768 if (--max_count == 0)
1770 lsr = serial_in(up, UART_LSR);
1771 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1773 tty_flip_buffer_push(&port->state->port);
1776 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1778 void serial8250_tx_chars(struct uart_8250_port *up)
1780 struct uart_port *port = &up->port;
1781 struct circ_buf *xmit = &port->state->xmit;
1785 uart_xchar_out(port, UART_TX);
1788 if (uart_tx_stopped(port)) {
1789 serial8250_stop_tx(port);
1792 if (uart_circ_empty(xmit)) {
1797 count = up->tx_loadsz;
1799 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1800 if (up->bugs & UART_BUG_TXRACE) {
1802 * The Aspeed BMC virtual UARTs have a bug where data
1803 * may get stuck in the BMC's Tx FIFO from bursts of
1804 * writes on the APB interface.
1806 * Delay back-to-back writes by a read cycle to avoid
1807 * stalling the VUART. Read a register that won't have
1808 * side-effects and discard the result.
1810 serial_in(up, UART_SCR);
1812 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1814 if (uart_circ_empty(xmit))
1816 if ((up->capabilities & UART_CAP_HFIFO) &&
1817 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1819 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1820 if ((up->capabilities & UART_CAP_MINI) &&
1821 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1823 } while (--count > 0);
1825 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1826 uart_write_wakeup(port);
1829 * With RPM enabled, we have to wait until the FIFO is empty before the
1830 * HW can go idle. So we get here once again with empty FIFO and disable
1831 * the interrupt and RPM in __stop_tx()
1833 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1836 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1838 /* Caller holds uart port lock */
1839 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1841 struct uart_port *port = &up->port;
1842 unsigned int status = serial_in(up, UART_MSR);
1844 status |= up->msr_saved_flags;
1845 up->msr_saved_flags = 0;
1846 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1847 port->state != NULL) {
1848 if (status & UART_MSR_TERI)
1850 if (status & UART_MSR_DDSR)
1852 if (status & UART_MSR_DDCD)
1853 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1854 if (status & UART_MSR_DCTS)
1855 uart_handle_cts_change(port, status & UART_MSR_CTS);
1857 wake_up_interruptible(&port->state->port.delta_msr_wait);
1862 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1864 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1866 switch (iir & 0x3f) {
1868 if (!up->dma->rx_running)
1872 case UART_IIR_RX_TIMEOUT:
1873 serial8250_rx_dma_flush(up);
1876 return up->dma->rx_dma(up);
1880 * This handles the interrupt from one port.
1882 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1884 unsigned char status;
1885 unsigned long flags;
1886 struct uart_8250_port *up = up_to_u8250p(port);
1887 struct tty_port *tport = &port->state->port;
1888 bool skip_rx = false;
1890 if (iir & UART_IIR_NO_INT)
1893 spin_lock_irqsave(&port->lock, flags);
1895 status = serial_port_in(port, UART_LSR);
1898 * If port is stopped and there are no error conditions in the
1899 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1900 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1901 * control when FIFO occupancy reaches preset threshold, thus
1902 * halting RX. This only works when auto HW flow control is
1905 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1906 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1907 !(port->read_status_mask & UART_LSR_DR))
1910 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1913 d = irq_get_irq_data(port->irq);
1914 if (d && irqd_is_wakeup_set(d))
1915 pm_wakeup_event(tport->tty->dev, 0);
1916 if (!up->dma || handle_rx_dma(up, iir))
1917 status = serial8250_rx_chars(up, status);
1919 serial8250_modem_status(up);
1920 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1921 (up->ier & UART_IER_THRI))
1922 serial8250_tx_chars(up);
1924 uart_unlock_and_check_sysrq(port, flags);
1927 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1929 static int serial8250_default_handle_irq(struct uart_port *port)
1931 struct uart_8250_port *up = up_to_u8250p(port);
1935 serial8250_rpm_get(up);
1937 iir = serial_port_in(port, UART_IIR);
1938 ret = serial8250_handle_irq(port, iir);
1940 serial8250_rpm_put(up);
1945 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1946 * have a programmable TX threshold that triggers the THRE interrupt in
1947 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1948 * has space available. Load it up with tx_loadsz bytes.
1950 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1952 unsigned long flags;
1953 unsigned int iir = serial_port_in(port, UART_IIR);
1955 /* TX Threshold IRQ triggered so load up FIFO */
1956 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1957 struct uart_8250_port *up = up_to_u8250p(port);
1959 spin_lock_irqsave(&port->lock, flags);
1960 serial8250_tx_chars(up);
1961 spin_unlock_irqrestore(&port->lock, flags);
1964 iir = serial_port_in(port, UART_IIR);
1965 return serial8250_handle_irq(port, iir);
1968 static unsigned int serial8250_tx_empty(struct uart_port *port)
1970 struct uart_8250_port *up = up_to_u8250p(port);
1971 unsigned int result = 0;
1972 unsigned long flags;
1975 serial8250_rpm_get(up);
1977 spin_lock_irqsave(&port->lock, flags);
1978 if (!serial8250_tx_dma_running(up)) {
1979 lsr = serial_port_in(port, UART_LSR);
1980 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1982 if ((lsr & BOTH_EMPTY) == BOTH_EMPTY)
1983 result = TIOCSER_TEMT;
1985 spin_unlock_irqrestore(&port->lock, flags);
1987 serial8250_rpm_put(up);
1992 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1994 struct uart_8250_port *up = up_to_u8250p(port);
1995 unsigned int status;
1998 serial8250_rpm_get(up);
1999 status = serial8250_modem_status(up);
2000 serial8250_rpm_put(up);
2002 val = serial8250_MSR_to_TIOCM(status);
2004 return mctrl_gpio_get(up->gpios, &val);
2008 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2010 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2012 if (port->get_mctrl)
2013 return port->get_mctrl(port);
2014 return serial8250_do_get_mctrl(port);
2017 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2019 struct uart_8250_port *up = up_to_u8250p(port);
2022 mcr = serial8250_TIOCM_to_MCR(mctrl);
2024 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2026 serial8250_out_MCR(up, mcr);
2028 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2030 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2032 if (port->rs485.flags & SER_RS485_ENABLED)
2035 if (port->set_mctrl)
2036 port->set_mctrl(port, mctrl);
2038 serial8250_do_set_mctrl(port, mctrl);
2041 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2043 struct uart_8250_port *up = up_to_u8250p(port);
2044 unsigned long flags;
2046 serial8250_rpm_get(up);
2047 spin_lock_irqsave(&port->lock, flags);
2048 if (break_state == -1)
2049 up->lcr |= UART_LCR_SBC;
2051 up->lcr &= ~UART_LCR_SBC;
2052 serial_port_out(port, UART_LCR, up->lcr);
2053 spin_unlock_irqrestore(&port->lock, flags);
2054 serial8250_rpm_put(up);
2058 * Wait for transmitter & holding register to empty
2060 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2062 unsigned int status, tmout = 10000;
2064 /* Wait up to 10ms for the character(s) to be sent. */
2066 status = serial_in(up, UART_LSR);
2068 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2070 if ((status & bits) == bits)
2075 touch_nmi_watchdog();
2078 /* Wait up to 1s for flow control if necessary */
2079 if (up->port.flags & UPF_CONS_FLOW) {
2080 for (tmout = 1000000; tmout; tmout--) {
2081 unsigned int msr = serial_in(up, UART_MSR);
2082 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2083 if (msr & UART_MSR_CTS)
2086 touch_nmi_watchdog();
2091 #ifdef CONFIG_CONSOLE_POLL
2093 * Console polling routines for writing and reading from the uart while
2094 * in an interrupt or debug context.
2097 static int serial8250_get_poll_char(struct uart_port *port)
2099 struct uart_8250_port *up = up_to_u8250p(port);
2103 serial8250_rpm_get(up);
2105 lsr = serial_port_in(port, UART_LSR);
2107 if (!(lsr & UART_LSR_DR)) {
2108 status = NO_POLL_CHAR;
2112 status = serial_port_in(port, UART_RX);
2114 serial8250_rpm_put(up);
2119 static void serial8250_put_poll_char(struct uart_port *port,
2123 struct uart_8250_port *up = up_to_u8250p(port);
2125 serial8250_rpm_get(up);
2127 * First save the IER then disable the interrupts
2129 ier = serial_port_in(port, UART_IER);
2130 if (up->capabilities & UART_CAP_UUE)
2131 serial_port_out(port, UART_IER, UART_IER_UUE);
2133 serial_port_out(port, UART_IER, 0);
2135 wait_for_xmitr(up, BOTH_EMPTY);
2137 * Send the character out.
2139 serial_port_out(port, UART_TX, c);
2142 * Finally, wait for transmitter to become empty
2143 * and restore the IER
2145 wait_for_xmitr(up, BOTH_EMPTY);
2146 serial_port_out(port, UART_IER, ier);
2147 serial8250_rpm_put(up);
2150 #endif /* CONFIG_CONSOLE_POLL */
2152 int serial8250_do_startup(struct uart_port *port)
2154 struct uart_8250_port *up = up_to_u8250p(port);
2155 unsigned long flags;
2156 unsigned char lsr, iir;
2159 if (!port->fifosize)
2160 port->fifosize = uart_config[port->type].fifo_size;
2162 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2163 if (!up->capabilities)
2164 up->capabilities = uart_config[port->type].flags;
2167 if (port->iotype != up->cur_iotype)
2168 set_io_from_upio(port);
2170 serial8250_rpm_get(up);
2171 if (port->type == PORT_16C950) {
2172 /* Wake up and initialize UART */
2174 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2175 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2176 serial_port_out(port, UART_IER, 0);
2177 serial_port_out(port, UART_LCR, 0);
2178 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2179 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2180 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2181 serial_port_out(port, UART_LCR, 0);
2184 if (port->type == PORT_DA830) {
2185 /* Reset the port */
2186 serial_port_out(port, UART_IER, 0);
2187 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2190 /* Enable Tx, Rx and free run mode */
2191 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2192 UART_DA830_PWREMU_MGMT_UTRST |
2193 UART_DA830_PWREMU_MGMT_URRST |
2194 UART_DA830_PWREMU_MGMT_FREE);
2197 if (port->type == PORT_NPCM) {
2199 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2200 * register). Enable it, and set TIOC (timeout interrupt
2201 * comparator) to be 0x20 for correct operation.
2203 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2206 #ifdef CONFIG_SERIAL_8250_RSA
2208 * If this is an RSA port, see if we can kick it up to the
2209 * higher speed clock.
2215 * Clear the FIFO buffers and disable them.
2216 * (they will be reenabled in set_termios())
2218 serial8250_clear_fifos(up);
2221 * Clear the interrupt registers.
2223 serial_port_in(port, UART_LSR);
2224 serial_port_in(port, UART_RX);
2225 serial_port_in(port, UART_IIR);
2226 serial_port_in(port, UART_MSR);
2229 * At this point, there's no way the LSR could still be 0xff;
2230 * if it is, then bail out, because there's likely no UART
2233 if (!(port->flags & UPF_BUGGY_UART) &&
2234 (serial_port_in(port, UART_LSR) == 0xff)) {
2235 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2241 * For a XR16C850, we need to set the trigger levels
2243 if (port->type == PORT_16850) {
2246 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2248 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2249 serial_port_out(port, UART_FCTR,
2250 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2251 serial_port_out(port, UART_TRG, UART_TRG_96);
2252 serial_port_out(port, UART_FCTR,
2253 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2254 serial_port_out(port, UART_TRG, UART_TRG_96);
2256 serial_port_out(port, UART_LCR, 0);
2260 * For the Altera 16550 variants, set TX threshold trigger level.
2262 if (((port->type == PORT_ALTR_16550_F32) ||
2263 (port->type == PORT_ALTR_16550_F64) ||
2264 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2265 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2266 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2267 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2269 serial_port_out(port, UART_ALTR_AFR,
2270 UART_ALTR_EN_TXFIFO_LW);
2271 serial_port_out(port, UART_ALTR_TX_LOW,
2272 port->fifosize - up->tx_loadsz);
2273 port->handle_irq = serial8250_tx_threshold_handle_irq;
2277 /* Check if we need to have shared IRQs */
2278 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2279 up->port.irqflags |= IRQF_SHARED;
2281 retval = up->ops->setup_irq(up);
2285 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2288 if (port->irqflags & IRQF_SHARED)
2289 disable_irq_nosync(port->irq);
2292 * Test for UARTs that do not reassert THRE when the
2293 * transmitter is idle and the interrupt has already
2294 * been cleared. Real 16550s should always reassert
2295 * this interrupt whenever the transmitter is idle and
2296 * the interrupt is enabled. Delays are necessary to
2297 * allow register changes to become visible.
2299 spin_lock_irqsave(&port->lock, flags);
2301 wait_for_xmitr(up, UART_LSR_THRE);
2302 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2303 udelay(1); /* allow THRE to set */
2304 iir1 = serial_port_in(port, UART_IIR);
2305 serial_port_out(port, UART_IER, 0);
2306 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2307 udelay(1); /* allow a working UART time to re-assert THRE */
2308 iir = serial_port_in(port, UART_IIR);
2309 serial_port_out(port, UART_IER, 0);
2311 spin_unlock_irqrestore(&port->lock, flags);
2313 if (port->irqflags & IRQF_SHARED)
2314 enable_irq(port->irq);
2317 * If the interrupt is not reasserted, or we otherwise
2318 * don't trust the iir, setup a timer to kick the UART
2319 * on a regular basis.
2321 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2322 up->port.flags & UPF_BUG_THRE) {
2323 up->bugs |= UART_BUG_THRE;
2327 up->ops->setup_timer(up);
2330 * Now, initialize the UART
2332 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2334 spin_lock_irqsave(&port->lock, flags);
2335 if (up->port.flags & UPF_FOURPORT) {
2337 up->port.mctrl |= TIOCM_OUT1;
2340 * Most PC uarts need OUT2 raised to enable interrupts.
2343 up->port.mctrl |= TIOCM_OUT2;
2345 serial8250_set_mctrl(port, port->mctrl);
2348 * Serial over Lan (SoL) hack:
2349 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2350 * used for Serial Over Lan. Those chips take a longer time than a
2351 * normal serial device to signalize that a transmission data was
2352 * queued. Due to that, the above test generally fails. One solution
2353 * would be to delay the reading of iir. However, this is not
2354 * reliable, since the timeout is variable. So, let's just don't
2355 * test if we receive TX irq. This way, we'll never enable
2358 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2359 goto dont_test_tx_en;
2362 * Do a quick test to see if we receive an interrupt when we enable
2365 serial_port_out(port, UART_IER, UART_IER_THRI);
2366 lsr = serial_port_in(port, UART_LSR);
2367 iir = serial_port_in(port, UART_IIR);
2368 serial_port_out(port, UART_IER, 0);
2370 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2371 if (!(up->bugs & UART_BUG_TXEN)) {
2372 up->bugs |= UART_BUG_TXEN;
2373 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2376 up->bugs &= ~UART_BUG_TXEN;
2380 spin_unlock_irqrestore(&port->lock, flags);
2383 * Clear the interrupt registers again for luck, and clear the
2384 * saved flags to avoid getting false values from polling
2385 * routines or the previous session.
2387 serial_port_in(port, UART_LSR);
2388 serial_port_in(port, UART_RX);
2389 serial_port_in(port, UART_IIR);
2390 serial_port_in(port, UART_MSR);
2391 up->lsr_saved_flags = 0;
2392 up->msr_saved_flags = 0;
2395 * Request DMA channels for both RX and TX.
2398 const char *msg = NULL;
2400 if (uart_console(port))
2401 msg = "forbid DMA for kernel console";
2402 else if (serial8250_request_dma(up))
2403 msg = "failed to request DMA";
2405 dev_warn_ratelimited(port->dev, "%s\n", msg);
2411 * Set the IER shadow for rx interrupts but defer actual interrupt
2412 * enable until after the FIFOs are enabled; otherwise, an already-
2413 * active sender can swamp the interrupt handler with "too much work".
2415 up->ier = UART_IER_RLSI | UART_IER_RDI;
2417 if (port->flags & UPF_FOURPORT) {
2420 * Enable interrupts on the AST Fourport board
2422 icp = (port->iobase & 0xfe0) | 0x01f;
2428 serial8250_rpm_put(up);
2431 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2433 static int serial8250_startup(struct uart_port *port)
2436 return port->startup(port);
2437 return serial8250_do_startup(port);
2440 void serial8250_do_shutdown(struct uart_port *port)
2442 struct uart_8250_port *up = up_to_u8250p(port);
2443 unsigned long flags;
2445 serial8250_rpm_get(up);
2447 * Disable interrupts from this port
2449 spin_lock_irqsave(&port->lock, flags);
2451 serial_port_out(port, UART_IER, 0);
2452 spin_unlock_irqrestore(&port->lock, flags);
2454 synchronize_irq(port->irq);
2457 serial8250_release_dma(up);
2459 spin_lock_irqsave(&port->lock, flags);
2460 if (port->flags & UPF_FOURPORT) {
2461 /* reset interrupts on the AST Fourport board */
2462 inb((port->iobase & 0xfe0) | 0x1f);
2463 port->mctrl |= TIOCM_OUT1;
2465 port->mctrl &= ~TIOCM_OUT2;
2467 serial8250_set_mctrl(port, port->mctrl);
2468 spin_unlock_irqrestore(&port->lock, flags);
2471 * Disable break condition and FIFOs
2473 serial_port_out(port, UART_LCR,
2474 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2475 serial8250_clear_fifos(up);
2477 #ifdef CONFIG_SERIAL_8250_RSA
2479 * Reset the RSA board back to 115kbps compat mode.
2485 * Read data port to reset things, and then unlink from
2488 serial_port_in(port, UART_RX);
2489 serial8250_rpm_put(up);
2491 up->ops->release_irq(up);
2493 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2495 static void serial8250_shutdown(struct uart_port *port)
2498 port->shutdown(port);
2500 serial8250_do_shutdown(port);
2503 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2504 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2507 struct uart_port *port = &up->port;
2509 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2512 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2516 struct uart_8250_port *up = up_to_u8250p(port);
2520 * Handle magic divisors for baud rates above baud_base on
2521 * SMSC SuperIO chips.
2524 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2525 baud == (port->uartclk/4))
2527 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2528 baud == (port->uartclk/8))
2530 else if (up->port.type == PORT_NPCM)
2531 quot = npcm_get_divisor(up, baud);
2533 quot = uart_get_divisor(port, baud);
2536 * Oxford Semi 952 rev B workaround
2538 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2544 static unsigned int serial8250_get_divisor(struct uart_port *port,
2548 if (port->get_divisor)
2549 return port->get_divisor(port, baud, frac);
2551 return serial8250_do_get_divisor(port, baud, frac);
2554 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2559 switch (c_cflag & CSIZE) {
2561 cval = UART_LCR_WLEN5;
2564 cval = UART_LCR_WLEN6;
2567 cval = UART_LCR_WLEN7;
2571 cval = UART_LCR_WLEN8;
2575 if (c_cflag & CSTOPB)
2576 cval |= UART_LCR_STOP;
2577 if (c_cflag & PARENB)
2578 cval |= UART_LCR_PARITY;
2579 if (!(c_cflag & PARODD))
2580 cval |= UART_LCR_EPAR;
2582 if (c_cflag & CMSPAR)
2583 cval |= UART_LCR_SPAR;
2589 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2590 unsigned int quot, unsigned int quot_frac)
2592 struct uart_8250_port *up = up_to_u8250p(port);
2594 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2595 if (is_omap1510_8250(up)) {
2596 if (baud == 115200) {
2598 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2600 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2604 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2605 * otherwise just set DLAB
2607 if (up->capabilities & UART_NATSEMI)
2608 serial_port_out(port, UART_LCR, 0xe0);
2610 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2612 serial_dl_write(up, quot);
2614 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2616 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2617 unsigned int quot, unsigned int quot_frac)
2619 if (port->set_divisor)
2620 port->set_divisor(port, baud, quot, quot_frac);
2622 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2625 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2626 struct ktermios *termios,
2627 struct ktermios *old)
2629 unsigned int tolerance = port->uartclk / 100;
2634 * Handle magic divisors for baud rates above baud_base on SMSC
2635 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2636 * disable divisor values beyond 32767, which are unavailable.
2638 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2639 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2640 max = (port->uartclk + tolerance) / 4;
2642 min = port->uartclk / 16 / UART_DIV_MAX;
2643 max = (port->uartclk + tolerance) / 16;
2647 * Ask the core to calculate the divisor for us.
2648 * Allow 1% tolerance at the upper limit so uart clks marginally
2649 * slower than nominal still match standard baud rates without
2650 * causing transmission errors.
2652 return uart_get_baud_rate(port, termios, old, min, max);
2656 * Note in order to avoid the tty port mutex deadlock don't use the next method
2657 * within the uart port callbacks. Primarily it's supposed to be utilized to
2658 * handle a sudden reference clock rate change.
2660 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2662 struct uart_8250_port *up = up_to_u8250p(port);
2663 struct tty_port *tport = &port->state->port;
2664 unsigned int baud, quot, frac = 0;
2665 struct ktermios *termios;
2666 struct tty_struct *tty;
2667 unsigned long flags;
2669 tty = tty_port_tty_get(tport);
2671 mutex_lock(&tport->mutex);
2672 port->uartclk = uartclk;
2673 mutex_unlock(&tport->mutex);
2677 down_write(&tty->termios_rwsem);
2678 mutex_lock(&tport->mutex);
2680 if (port->uartclk == uartclk)
2683 port->uartclk = uartclk;
2685 if (!tty_port_initialized(tport))
2688 termios = &tty->termios;
2690 baud = serial8250_get_baud_rate(port, termios, NULL);
2691 quot = serial8250_get_divisor(port, baud, &frac);
2693 serial8250_rpm_get(up);
2694 spin_lock_irqsave(&port->lock, flags);
2696 uart_update_timeout(port, termios->c_cflag, baud);
2698 serial8250_set_divisor(port, baud, quot, frac);
2699 serial_port_out(port, UART_LCR, up->lcr);
2701 spin_unlock_irqrestore(&port->lock, flags);
2702 serial8250_rpm_put(up);
2705 mutex_unlock(&tport->mutex);
2706 up_write(&tty->termios_rwsem);
2709 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2712 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2713 struct ktermios *old)
2715 struct uart_8250_port *up = up_to_u8250p(port);
2717 unsigned long flags;
2718 unsigned int baud, quot, frac = 0;
2720 if (up->capabilities & UART_CAP_MINI) {
2721 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2722 if ((termios->c_cflag & CSIZE) == CS5 ||
2723 (termios->c_cflag & CSIZE) == CS6)
2724 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2726 cval = serial8250_compute_lcr(up, termios->c_cflag);
2728 baud = serial8250_get_baud_rate(port, termios, old);
2729 quot = serial8250_get_divisor(port, baud, &frac);
2732 * Ok, we're now changing the port state. Do it with
2733 * interrupts disabled.
2735 serial8250_rpm_get(up);
2736 spin_lock_irqsave(&port->lock, flags);
2738 up->lcr = cval; /* Save computed LCR */
2740 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2741 if (baud < 2400 && !up->dma) {
2742 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2743 up->fcr |= UART_FCR_TRIGGER_1;
2748 * MCR-based auto flow control. When AFE is enabled, RTS will be
2749 * deasserted when the receive FIFO contains more characters than
2750 * the trigger, or the MCR RTS bit is cleared.
2752 if (up->capabilities & UART_CAP_AFE) {
2753 up->mcr &= ~UART_MCR_AFE;
2754 if (termios->c_cflag & CRTSCTS)
2755 up->mcr |= UART_MCR_AFE;
2759 * Update the per-port timeout.
2761 uart_update_timeout(port, termios->c_cflag, baud);
2763 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2764 if (termios->c_iflag & INPCK)
2765 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2766 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2767 port->read_status_mask |= UART_LSR_BI;
2770 * Characteres to ignore
2772 port->ignore_status_mask = 0;
2773 if (termios->c_iflag & IGNPAR)
2774 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2775 if (termios->c_iflag & IGNBRK) {
2776 port->ignore_status_mask |= UART_LSR_BI;
2778 * If we're ignoring parity and break indicators,
2779 * ignore overruns too (for real raw support).
2781 if (termios->c_iflag & IGNPAR)
2782 port->ignore_status_mask |= UART_LSR_OE;
2786 * ignore all characters if CREAD is not set
2788 if ((termios->c_cflag & CREAD) == 0)
2789 port->ignore_status_mask |= UART_LSR_DR;
2792 * CTS flow control flag and modem status interrupts
2794 up->ier &= ~UART_IER_MSI;
2795 if (!(up->bugs & UART_BUG_NOMSR) &&
2796 UART_ENABLE_MS(&up->port, termios->c_cflag))
2797 up->ier |= UART_IER_MSI;
2798 if (up->capabilities & UART_CAP_UUE)
2799 up->ier |= UART_IER_UUE;
2800 if (up->capabilities & UART_CAP_RTOIE)
2801 up->ier |= UART_IER_RTOIE;
2803 serial_port_out(port, UART_IER, up->ier);
2805 if (up->capabilities & UART_CAP_EFR) {
2806 unsigned char efr = 0;
2808 * TI16C752/Startech hardware flow control. FIXME:
2809 * - TI16C752 requires control thresholds to be set.
2810 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2812 if (termios->c_cflag & CRTSCTS)
2813 efr |= UART_EFR_CTS;
2815 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2816 if (port->flags & UPF_EXAR_EFR)
2817 serial_port_out(port, UART_XR_EFR, efr);
2819 serial_port_out(port, UART_EFR, efr);
2822 serial8250_set_divisor(port, baud, quot, frac);
2825 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2826 * is written without DLAB set, this mode will be disabled.
2828 if (port->type == PORT_16750)
2829 serial_port_out(port, UART_FCR, up->fcr);
2831 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2832 if (port->type != PORT_16750) {
2833 /* emulated UARTs (Lucent Venus 167x) need two steps */
2834 if (up->fcr & UART_FCR_ENABLE_FIFO)
2835 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2836 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2838 serial8250_set_mctrl(port, port->mctrl);
2839 spin_unlock_irqrestore(&port->lock, flags);
2840 serial8250_rpm_put(up);
2842 /* Don't rewrite B0 */
2843 if (tty_termios_baud_rate(termios))
2844 tty_termios_encode_baud_rate(termios, baud, baud);
2846 EXPORT_SYMBOL(serial8250_do_set_termios);
2849 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2850 struct ktermios *old)
2852 if (port->set_termios)
2853 port->set_termios(port, termios, old);
2855 serial8250_do_set_termios(port, termios, old);
2858 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2860 if (termios->c_line == N_PPS) {
2861 port->flags |= UPF_HARDPPS_CD;
2862 spin_lock_irq(&port->lock);
2863 serial8250_enable_ms(port);
2864 spin_unlock_irq(&port->lock);
2866 port->flags &= ~UPF_HARDPPS_CD;
2867 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2868 spin_lock_irq(&port->lock);
2869 serial8250_disable_ms(port);
2870 spin_unlock_irq(&port->lock);
2874 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2877 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2879 if (port->set_ldisc)
2880 port->set_ldisc(port, termios);
2882 serial8250_do_set_ldisc(port, termios);
2885 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2886 unsigned int oldstate)
2888 struct uart_8250_port *p = up_to_u8250p(port);
2890 serial8250_set_sleep(p, state != 0);
2892 EXPORT_SYMBOL(serial8250_do_pm);
2895 serial8250_pm(struct uart_port *port, unsigned int state,
2896 unsigned int oldstate)
2899 port->pm(port, state, oldstate);
2901 serial8250_do_pm(port, state, oldstate);
2904 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2906 if (pt->port.mapsize)
2907 return pt->port.mapsize;
2908 if (pt->port.iotype == UPIO_AU) {
2909 if (pt->port.type == PORT_RT2880)
2913 if (is_omap1_8250(pt))
2914 return 0x16 << pt->port.regshift;
2916 return 8 << pt->port.regshift;
2920 * Resource handling.
2922 static int serial8250_request_std_resource(struct uart_8250_port *up)
2924 unsigned int size = serial8250_port_size(up);
2925 struct uart_port *port = &up->port;
2928 switch (port->iotype) {
2935 if (!port->mapbase) {
2940 if (!request_mem_region(port->mapbase, size, "serial")) {
2945 if (port->flags & UPF_IOREMAP) {
2946 port->membase = ioremap(port->mapbase, size);
2947 if (!port->membase) {
2948 release_mem_region(port->mapbase, size);
2956 if (!request_region(port->iobase, size, "serial"))
2963 static void serial8250_release_std_resource(struct uart_8250_port *up)
2965 unsigned int size = serial8250_port_size(up);
2966 struct uart_port *port = &up->port;
2968 switch (port->iotype) {
2978 if (port->flags & UPF_IOREMAP) {
2979 iounmap(port->membase);
2980 port->membase = NULL;
2983 release_mem_region(port->mapbase, size);
2988 release_region(port->iobase, size);
2993 static void serial8250_release_port(struct uart_port *port)
2995 struct uart_8250_port *up = up_to_u8250p(port);
2997 serial8250_release_std_resource(up);
3000 static int serial8250_request_port(struct uart_port *port)
3002 struct uart_8250_port *up = up_to_u8250p(port);
3004 return serial8250_request_std_resource(up);
3007 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3009 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3010 unsigned char bytes;
3012 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3014 return bytes ? bytes : -EOPNOTSUPP;
3017 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3019 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3022 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3025 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3026 if (bytes < conf_type->rxtrig_bytes[i])
3027 /* Use the nearest lower value */
3028 return (--i) << UART_FCR_R_TRIG_SHIFT;
3031 return UART_FCR_R_TRIG_11;
3034 static int do_get_rxtrig(struct tty_port *port)
3036 struct uart_state *state = container_of(port, struct uart_state, port);
3037 struct uart_port *uport = state->uart_port;
3038 struct uart_8250_port *up = up_to_u8250p(uport);
3040 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3043 return fcr_get_rxtrig_bytes(up);
3046 static int do_serial8250_get_rxtrig(struct tty_port *port)
3050 mutex_lock(&port->mutex);
3051 rxtrig_bytes = do_get_rxtrig(port);
3052 mutex_unlock(&port->mutex);
3054 return rxtrig_bytes;
3057 static ssize_t rx_trig_bytes_show(struct device *dev,
3058 struct device_attribute *attr, char *buf)
3060 struct tty_port *port = dev_get_drvdata(dev);
3063 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3064 if (rxtrig_bytes < 0)
3065 return rxtrig_bytes;
3067 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
3070 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3072 struct uart_state *state = container_of(port, struct uart_state, port);
3073 struct uart_port *uport = state->uart_port;
3074 struct uart_8250_port *up = up_to_u8250p(uport);
3077 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3080 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3084 serial8250_clear_fifos(up);
3085 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3086 up->fcr |= (unsigned char)rxtrig;
3087 serial_out(up, UART_FCR, up->fcr);
3091 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3095 mutex_lock(&port->mutex);
3096 ret = do_set_rxtrig(port, bytes);
3097 mutex_unlock(&port->mutex);
3102 static ssize_t rx_trig_bytes_store(struct device *dev,
3103 struct device_attribute *attr, const char *buf, size_t count)
3105 struct tty_port *port = dev_get_drvdata(dev);
3106 unsigned char bytes;
3112 ret = kstrtou8(buf, 10, &bytes);
3116 ret = do_serial8250_set_rxtrig(port, bytes);
3123 static DEVICE_ATTR_RW(rx_trig_bytes);
3125 static struct attribute *serial8250_dev_attrs[] = {
3126 &dev_attr_rx_trig_bytes.attr,
3130 static struct attribute_group serial8250_dev_attr_group = {
3131 .attrs = serial8250_dev_attrs,
3134 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3136 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3138 if (conf_type->rxtrig_bytes[0])
3139 up->port.attr_group = &serial8250_dev_attr_group;
3142 static void serial8250_config_port(struct uart_port *port, int flags)
3144 struct uart_8250_port *up = up_to_u8250p(port);
3148 * Find the region that we can probe for. This in turn
3149 * tells us whether we can probe for the type of port.
3151 ret = serial8250_request_std_resource(up);
3155 if (port->iotype != up->cur_iotype)
3156 set_io_from_upio(port);
3158 if (flags & UART_CONFIG_TYPE)
3161 /* if access method is AU, it is a 16550 with a quirk */
3162 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3163 up->bugs |= UART_BUG_NOMSR;
3165 /* HW bugs may trigger IRQ while IIR == NO_INT */
3166 if (port->type == PORT_TEGRA)
3167 up->bugs |= UART_BUG_NOMSR;
3169 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3172 if (port->type == PORT_UNKNOWN)
3173 serial8250_release_std_resource(up);
3175 register_dev_spec_attr_grp(up);
3176 up->fcr = uart_config[up->port.type].fcr;
3180 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3182 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3183 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3184 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3185 ser->type == PORT_STARTECH)
3190 static const char *serial8250_type(struct uart_port *port)
3192 int type = port->type;
3194 if (type >= ARRAY_SIZE(uart_config))
3196 return uart_config[type].name;
3199 static const struct uart_ops serial8250_pops = {
3200 .tx_empty = serial8250_tx_empty,
3201 .set_mctrl = serial8250_set_mctrl,
3202 .get_mctrl = serial8250_get_mctrl,
3203 .stop_tx = serial8250_stop_tx,
3204 .start_tx = serial8250_start_tx,
3205 .throttle = serial8250_throttle,
3206 .unthrottle = serial8250_unthrottle,
3207 .stop_rx = serial8250_stop_rx,
3208 .enable_ms = serial8250_enable_ms,
3209 .break_ctl = serial8250_break_ctl,
3210 .startup = serial8250_startup,
3211 .shutdown = serial8250_shutdown,
3212 .set_termios = serial8250_set_termios,
3213 .set_ldisc = serial8250_set_ldisc,
3214 .pm = serial8250_pm,
3215 .type = serial8250_type,
3216 .release_port = serial8250_release_port,
3217 .request_port = serial8250_request_port,
3218 .config_port = serial8250_config_port,
3219 .verify_port = serial8250_verify_port,
3220 #ifdef CONFIG_CONSOLE_POLL
3221 .poll_get_char = serial8250_get_poll_char,
3222 .poll_put_char = serial8250_put_poll_char,
3226 void serial8250_init_port(struct uart_8250_port *up)
3228 struct uart_port *port = &up->port;
3230 spin_lock_init(&port->lock);
3232 port->ops = &serial8250_pops;
3233 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3235 up->cur_iotype = 0xFF;
3237 EXPORT_SYMBOL_GPL(serial8250_init_port);
3239 void serial8250_set_defaults(struct uart_8250_port *up)
3241 struct uart_port *port = &up->port;
3243 if (up->port.flags & UPF_FIXED_TYPE) {
3244 unsigned int type = up->port.type;
3246 if (!up->port.fifosize)
3247 up->port.fifosize = uart_config[type].fifo_size;
3249 up->tx_loadsz = uart_config[type].tx_loadsz;
3250 if (!up->capabilities)
3251 up->capabilities = uart_config[type].flags;
3254 set_io_from_upio(port);
3256 /* default dma handlers */
3258 if (!up->dma->tx_dma)
3259 up->dma->tx_dma = serial8250_tx_dma;
3260 if (!up->dma->rx_dma)
3261 up->dma->rx_dma = serial8250_rx_dma;
3264 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3266 #ifdef CONFIG_SERIAL_8250_CONSOLE
3268 static void serial8250_console_putchar(struct uart_port *port, int ch)
3270 struct uart_8250_port *up = up_to_u8250p(port);
3272 wait_for_xmitr(up, UART_LSR_THRE);
3273 serial_port_out(port, UART_TX, ch);
3277 * Restore serial console when h/w power-off detected
3279 static void serial8250_console_restore(struct uart_8250_port *up)
3281 struct uart_port *port = &up->port;
3282 struct ktermios termios;
3283 unsigned int baud, quot, frac = 0;
3285 termios.c_cflag = port->cons->cflag;
3286 termios.c_ispeed = port->cons->ispeed;
3287 termios.c_ospeed = port->cons->ospeed;
3288 if (port->state->port.tty && termios.c_cflag == 0) {
3289 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3290 termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3291 termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3294 baud = serial8250_get_baud_rate(port, &termios, NULL);
3295 quot = serial8250_get_divisor(port, baud, &frac);
3297 serial8250_set_divisor(port, baud, quot, frac);
3298 serial_port_out(port, UART_LCR, up->lcr);
3299 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3303 * Print a string to the serial port trying not to disturb
3304 * any possible real use of the port...
3306 * The console_lock must be held when we get here.
3308 * Doing runtime PM is really a bad idea for the kernel console.
3309 * Thus, we assume the function is called when device is powered up.
3311 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3314 struct uart_8250_em485 *em485 = up->em485;
3315 struct uart_port *port = &up->port;
3316 unsigned long flags;
3320 touch_nmi_watchdog();
3322 if (oops_in_progress)
3323 locked = spin_trylock_irqsave(&port->lock, flags);
3325 spin_lock_irqsave(&port->lock, flags);
3328 * First save the IER then disable the interrupts
3330 ier = serial_port_in(port, UART_IER);
3332 if (up->capabilities & UART_CAP_UUE)
3333 serial_port_out(port, UART_IER, UART_IER_UUE);
3335 serial_port_out(port, UART_IER, 0);
3337 /* check scratch reg to see if port powered off during system sleep */
3338 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3339 serial8250_console_restore(up);
3344 if (em485->tx_stopped)
3345 up->rs485_start_tx(up);
3346 mdelay(port->rs485.delay_rts_before_send);
3349 uart_console_write(port, s, count, serial8250_console_putchar);
3352 * Finally, wait for transmitter to become empty
3353 * and restore the IER
3355 wait_for_xmitr(up, BOTH_EMPTY);
3358 mdelay(port->rs485.delay_rts_after_send);
3359 if (em485->tx_stopped)
3360 up->rs485_stop_tx(up);
3363 serial_port_out(port, UART_IER, ier);
3366 * The receive handling will happen properly because the
3367 * receive ready bit will still be set; it is not cleared
3368 * on read. However, modem control will not, we must
3369 * call it if we have saved something in the saved flags
3370 * while processing with interrupts off.
3372 if (up->msr_saved_flags)
3373 serial8250_modem_status(up);
3376 spin_unlock_irqrestore(&port->lock, flags);
3379 static unsigned int probe_baud(struct uart_port *port)
3381 unsigned char lcr, dll, dlm;
3384 lcr = serial_port_in(port, UART_LCR);
3385 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3386 dll = serial_port_in(port, UART_DLL);
3387 dlm = serial_port_in(port, UART_DLM);
3388 serial_port_out(port, UART_LCR, lcr);
3390 quot = (dlm << 8) | dll;
3391 return (port->uartclk / 16) / quot;
3394 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3402 if (!port->iobase && !port->membase)
3406 uart_parse_options(options, &baud, &parity, &bits, &flow);
3408 baud = probe_baud(port);
3410 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3415 pm_runtime_get_sync(port->dev);
3420 int serial8250_console_exit(struct uart_port *port)
3423 pm_runtime_put_sync(port->dev);
3428 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3430 MODULE_LICENSE("GPL");