2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/ktime.h>
48 * These are definitions for the Exar XR17V35X and XR17(C|D)15X
50 #define UART_EXAR_INT0 0x80
51 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
52 #define UART_EXAR_DVID 0x8d /* Device identification */
54 /* Nuvoton NPCM timeout register */
55 #define UART_NPCM_TOR 7
56 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
62 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
64 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
67 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
70 * Here we define the default xmit fifo size used for each type of UART.
72 static const struct serial8250_config uart_config[] = {
97 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
98 .rxtrig_bytes = {1, 4, 8, 14},
99 .flags = UART_CAP_FIFO,
110 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
116 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
118 .rxtrig_bytes = {8, 16, 24, 28},
119 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
125 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
127 .rxtrig_bytes = {1, 16, 32, 56},
128 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
136 .name = "16C950/954",
139 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
140 .rxtrig_bytes = {16, 32, 112, 120},
141 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
142 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
148 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
150 .rxtrig_bytes = {8, 16, 56, 60},
151 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
157 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
158 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
164 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
165 .flags = UART_CAP_FIFO,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO | UART_NATSEMI,
178 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
179 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
185 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 .flags = UART_CAP_FIFO,
192 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
193 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO | UART_CAP_AFE,
206 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
208 .rxtrig_bytes = {1, 4, 8, 14},
209 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
216 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
225 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
232 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
233 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
234 .flags = UART_CAP_FIFO,
236 [PORT_BRCM_TRUMANAGE] = {
240 .flags = UART_CAP_HFIFO,
245 [PORT_ALTR_16550_F32] = {
246 .name = "Altera 16550 FIFO32",
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .flags = UART_CAP_FIFO | UART_CAP_AFE,
252 [PORT_ALTR_16550_F64] = {
253 .name = "Altera 16550 FIFO64",
256 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
257 .flags = UART_CAP_FIFO | UART_CAP_AFE,
259 [PORT_ALTR_16550_F128] = {
260 .name = "Altera 16550 FIFO128",
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
264 .flags = UART_CAP_FIFO | UART_CAP_AFE,
267 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
268 * workaround of errata A-008006 which states that tx_loadsz should
269 * be configured less than Maximum supported fifo bytes.
271 [PORT_16550A_FSL64] = {
272 .name = "16550A_FSL64",
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
277 .flags = UART_CAP_FIFO,
280 .name = "Palmchip BK-3103",
283 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
284 .rxtrig_bytes = {1, 4, 8, 14},
285 .flags = UART_CAP_FIFO,
288 .name = "TI DA8xx/66AK2x",
291 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
293 .rxtrig_bytes = {1, 4, 8, 14},
294 .flags = UART_CAP_FIFO | UART_CAP_AFE,
297 .name = "MediaTek BTIF",
300 .fcr = UART_FCR_ENABLE_FIFO |
301 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
302 .flags = UART_CAP_FIFO,
305 .name = "Nuvoton 16550",
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
309 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
310 .rxtrig_bytes = {1, 4, 8, 14},
311 .flags = UART_CAP_FIFO,
315 /* Uart divisor latch read */
316 static int default_serial_dl_read(struct uart_8250_port *up)
318 /* Assign these in pieces to truncate any bits above 7. */
319 unsigned char dll = serial_in(up, UART_DLL);
320 unsigned char dlm = serial_in(up, UART_DLM);
322 return dll | dlm << 8;
325 /* Uart divisor latch write */
326 static void default_serial_dl_write(struct uart_8250_port *up, int value)
328 serial_out(up, UART_DLL, value & 0xff);
329 serial_out(up, UART_DLM, value >> 8 & 0xff);
332 #ifdef CONFIG_SERIAL_8250_RT288X
334 /* Au1x00/RT288x UART hardware has a weird register layout */
335 static const s8 au_io_in_map[8] = {
343 -1, /* UART_SCR (unmapped) */
346 static const s8 au_io_out_map[8] = {
352 -1, /* UART_LSR (unmapped) */
353 -1, /* UART_MSR (unmapped) */
354 -1, /* UART_SCR (unmapped) */
357 unsigned int au_serial_in(struct uart_port *p, int offset)
359 if (offset >= ARRAY_SIZE(au_io_in_map))
361 offset = au_io_in_map[offset];
364 return __raw_readl(p->membase + (offset << p->regshift));
367 void au_serial_out(struct uart_port *p, int offset, int value)
369 if (offset >= ARRAY_SIZE(au_io_out_map))
371 offset = au_io_out_map[offset];
374 __raw_writel(value, p->membase + (offset << p->regshift));
377 /* Au1x00 haven't got a standard divisor latch */
378 static int au_serial_dl_read(struct uart_8250_port *up)
380 return __raw_readl(up->port.membase + 0x28);
383 static void au_serial_dl_write(struct uart_8250_port *up, int value)
385 __raw_writel(value, up->port.membase + 0x28);
390 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
392 offset = offset << p->regshift;
393 outb(p->hub6 - 1 + offset, p->iobase);
394 return inb(p->iobase + 1);
397 static void hub6_serial_out(struct uart_port *p, int offset, int value)
399 offset = offset << p->regshift;
400 outb(p->hub6 - 1 + offset, p->iobase);
401 outb(value, p->iobase + 1);
404 static unsigned int mem_serial_in(struct uart_port *p, int offset)
406 offset = offset << p->regshift;
407 return readb(p->membase + offset);
410 static void mem_serial_out(struct uart_port *p, int offset, int value)
412 offset = offset << p->regshift;
413 writeb(value, p->membase + offset);
416 static void mem16_serial_out(struct uart_port *p, int offset, int value)
418 offset = offset << p->regshift;
419 writew(value, p->membase + offset);
422 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
424 offset = offset << p->regshift;
425 return readw(p->membase + offset);
428 static void mem32_serial_out(struct uart_port *p, int offset, int value)
430 offset = offset << p->regshift;
431 writel(value, p->membase + offset);
434 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
436 offset = offset << p->regshift;
437 return readl(p->membase + offset);
440 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
442 offset = offset << p->regshift;
443 iowrite32be(value, p->membase + offset);
446 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
448 offset = offset << p->regshift;
449 return ioread32be(p->membase + offset);
452 static unsigned int io_serial_in(struct uart_port *p, int offset)
454 offset = offset << p->regshift;
455 return inb(p->iobase + offset);
458 static void io_serial_out(struct uart_port *p, int offset, int value)
460 offset = offset << p->regshift;
461 outb(value, p->iobase + offset);
464 static int serial8250_default_handle_irq(struct uart_port *port);
466 static void set_io_from_upio(struct uart_port *p)
468 struct uart_8250_port *up = up_to_u8250p(p);
470 up->dl_read = default_serial_dl_read;
471 up->dl_write = default_serial_dl_write;
475 p->serial_in = hub6_serial_in;
476 p->serial_out = hub6_serial_out;
480 p->serial_in = mem_serial_in;
481 p->serial_out = mem_serial_out;
485 p->serial_in = mem16_serial_in;
486 p->serial_out = mem16_serial_out;
490 p->serial_in = mem32_serial_in;
491 p->serial_out = mem32_serial_out;
495 p->serial_in = mem32be_serial_in;
496 p->serial_out = mem32be_serial_out;
499 #ifdef CONFIG_SERIAL_8250_RT288X
501 p->serial_in = au_serial_in;
502 p->serial_out = au_serial_out;
503 up->dl_read = au_serial_dl_read;
504 up->dl_write = au_serial_dl_write;
509 p->serial_in = io_serial_in;
510 p->serial_out = io_serial_out;
513 /* Remember loaded iotype */
514 up->cur_iotype = p->iotype;
515 p->handle_irq = serial8250_default_handle_irq;
519 serial_port_out_sync(struct uart_port *p, int offset, int value)
527 p->serial_out(p, offset, value);
528 p->serial_in(p, UART_LCR); /* safe, no side-effects */
531 p->serial_out(p, offset, value);
538 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
540 serial_out(up, UART_SCR, offset);
541 serial_out(up, UART_ICR, value);
544 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
548 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
549 serial_out(up, UART_SCR, offset);
550 value = serial_in(up, UART_ICR);
551 serial_icr_write(up, UART_ACR, up->acr);
559 static void serial8250_clear_fifos(struct uart_8250_port *p)
561 if (p->capabilities & UART_CAP_FIFO) {
562 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
563 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
564 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
565 serial_out(p, UART_FCR, 0);
569 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
571 unsigned char mcr = serial8250_in_MCR(p);
573 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
576 mcr &= ~UART_MCR_RTS;
577 serial8250_out_MCR(p, mcr);
580 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
581 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
583 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
585 serial8250_clear_fifos(p);
586 serial_out(p, UART_FCR, p->fcr);
588 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
590 void serial8250_rpm_get(struct uart_8250_port *p)
592 if (!(p->capabilities & UART_CAP_RPM))
594 pm_runtime_get_sync(p->port.dev);
596 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
598 void serial8250_rpm_put(struct uart_8250_port *p)
600 if (!(p->capabilities & UART_CAP_RPM))
602 pm_runtime_mark_last_busy(p->port.dev);
603 pm_runtime_put_autosuspend(p->port.dev);
605 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
608 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
609 * @p: uart_8250_port port instance
611 * The function is used to start rs485 software emulating on the
612 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
613 * transmission. The function is idempotent, so it is safe to call it
616 * The caller MUST enable interrupt on empty shift register before
617 * calling serial8250_em485_init(). This interrupt is not a part of
618 * 8250 standard, but implementation defined.
620 * The function is supposed to be called from .rs485_config callback
621 * or from any other callback protected with p->port.lock spinlock.
623 * See also serial8250_em485_destroy()
625 * Return 0 - success, -errno - otherwise
627 int serial8250_em485_init(struct uart_8250_port *p)
632 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
636 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
638 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
640 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
641 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
643 p->em485->active_timer = NULL;
644 serial8250_em485_rts_after_send(p);
648 EXPORT_SYMBOL_GPL(serial8250_em485_init);
651 * serial8250_em485_destroy() - put uart_8250_port into normal state
652 * @p: uart_8250_port port instance
654 * The function is used to stop rs485 software emulating on the
655 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
656 * call it multiple times.
658 * The function is supposed to be called from .rs485_config callback
659 * or from any other callback protected with p->port.lock spinlock.
661 * See also serial8250_em485_init()
663 void serial8250_em485_destroy(struct uart_8250_port *p)
668 hrtimer_cancel(&p->em485->start_tx_timer);
669 hrtimer_cancel(&p->em485->stop_tx_timer);
674 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
677 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
678 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
679 * empty and the HW can idle again.
681 void serial8250_rpm_get_tx(struct uart_8250_port *p)
683 unsigned char rpm_active;
685 if (!(p->capabilities & UART_CAP_RPM))
688 rpm_active = xchg(&p->rpm_tx_active, 1);
691 pm_runtime_get_sync(p->port.dev);
693 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
695 void serial8250_rpm_put_tx(struct uart_8250_port *p)
697 unsigned char rpm_active;
699 if (!(p->capabilities & UART_CAP_RPM))
702 rpm_active = xchg(&p->rpm_tx_active, 0);
705 pm_runtime_mark_last_busy(p->port.dev);
706 pm_runtime_put_autosuspend(p->port.dev);
708 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
711 * IER sleep support. UARTs which have EFRs need the "extended
712 * capability" bit enabled. Note that on XR16C850s, we need to
713 * reset LCR to write to IER.
715 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
717 unsigned char lcr = 0, efr = 0;
719 * Exar UARTs have a SLEEP register that enables or disables
720 * each UART to enter sleep mode separately. On the XR17V35x the
721 * register is accessible to each UART at the UART_EXAR_SLEEP
722 * offset but the UART channel may only write to the corresponding
725 serial8250_rpm_get(p);
726 if ((p->port.type == PORT_XR17V35X) ||
727 (p->port.type == PORT_XR17D15X)) {
728 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
732 if (p->capabilities & UART_CAP_SLEEP) {
733 if (p->capabilities & UART_CAP_EFR) {
734 lcr = serial_in(p, UART_LCR);
735 efr = serial_in(p, UART_EFR);
736 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
737 serial_out(p, UART_EFR, UART_EFR_ECB);
738 serial_out(p, UART_LCR, 0);
740 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
741 if (p->capabilities & UART_CAP_EFR) {
742 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
743 serial_out(p, UART_EFR, efr);
744 serial_out(p, UART_LCR, lcr);
748 serial8250_rpm_put(p);
751 #ifdef CONFIG_SERIAL_8250_RSA
753 * Attempts to turn on the RSA FIFO. Returns zero on failure.
754 * We set the port uart clock rate if we succeed.
756 static int __enable_rsa(struct uart_8250_port *up)
761 mode = serial_in(up, UART_RSA_MSR);
762 result = mode & UART_RSA_MSR_FIFO;
765 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
766 mode = serial_in(up, UART_RSA_MSR);
767 result = mode & UART_RSA_MSR_FIFO;
771 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
776 static void enable_rsa(struct uart_8250_port *up)
778 if (up->port.type == PORT_RSA) {
779 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
780 spin_lock_irq(&up->port.lock);
782 spin_unlock_irq(&up->port.lock);
784 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
785 serial_out(up, UART_RSA_FRR, 0);
790 * Attempts to turn off the RSA FIFO. Returns zero on failure.
791 * It is unknown why interrupts were disabled in here. However,
792 * the caller is expected to preserve this behaviour by grabbing
793 * the spinlock before calling this function.
795 static void disable_rsa(struct uart_8250_port *up)
800 if (up->port.type == PORT_RSA &&
801 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
802 spin_lock_irq(&up->port.lock);
804 mode = serial_in(up, UART_RSA_MSR);
805 result = !(mode & UART_RSA_MSR_FIFO);
808 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
809 mode = serial_in(up, UART_RSA_MSR);
810 result = !(mode & UART_RSA_MSR_FIFO);
814 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
815 spin_unlock_irq(&up->port.lock);
818 #endif /* CONFIG_SERIAL_8250_RSA */
821 * This is a quickie test to see how big the FIFO is.
822 * It doesn't work at all the time, more's the pity.
824 static int size_fifo(struct uart_8250_port *up)
826 unsigned char old_fcr, old_mcr, old_lcr;
827 unsigned short old_dl;
830 old_lcr = serial_in(up, UART_LCR);
831 serial_out(up, UART_LCR, 0);
832 old_fcr = serial_in(up, UART_FCR);
833 old_mcr = serial8250_in_MCR(up);
834 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
835 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
836 serial8250_out_MCR(up, UART_MCR_LOOP);
837 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
838 old_dl = serial_dl_read(up);
839 serial_dl_write(up, 0x0001);
840 serial_out(up, UART_LCR, 0x03);
841 for (count = 0; count < 256; count++)
842 serial_out(up, UART_TX, count);
843 mdelay(20);/* FIXME - schedule_timeout */
844 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
845 (count < 256); count++)
846 serial_in(up, UART_RX);
847 serial_out(up, UART_FCR, old_fcr);
848 serial8250_out_MCR(up, old_mcr);
849 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
850 serial_dl_write(up, old_dl);
851 serial_out(up, UART_LCR, old_lcr);
857 * Read UART ID using the divisor method - set DLL and DLM to zero
858 * and the revision will be in DLL and device type in DLM. We
859 * preserve the device state across this.
861 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
863 unsigned char old_lcr;
864 unsigned int id, old_dl;
866 old_lcr = serial_in(p, UART_LCR);
867 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
868 old_dl = serial_dl_read(p);
869 serial_dl_write(p, 0);
870 id = serial_dl_read(p);
871 serial_dl_write(p, old_dl);
873 serial_out(p, UART_LCR, old_lcr);
879 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
880 * When this function is called we know it is at least a StarTech
881 * 16650 V2, but it might be one of several StarTech UARTs, or one of
882 * its clones. (We treat the broken original StarTech 16650 V1 as a
883 * 16550, and why not? Startech doesn't seem to even acknowledge its
886 * What evil have men's minds wrought...
888 static void autoconfig_has_efr(struct uart_8250_port *up)
890 unsigned int id1, id2, id3, rev;
893 * Everything with an EFR has SLEEP
895 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
898 * First we check to see if it's an Oxford Semiconductor UART.
900 * If we have to do this here because some non-National
901 * Semiconductor clone chips lock up if you try writing to the
902 * LSR register (which serial_icr_read does)
906 * Check for Oxford Semiconductor 16C950.
908 * EFR [4] must be set else this test fails.
910 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
911 * claims that it's needed for 952 dual UART's (which are not
912 * recommended for new designs).
915 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
916 serial_out(up, UART_EFR, UART_EFR_ECB);
917 serial_out(up, UART_LCR, 0x00);
918 id1 = serial_icr_read(up, UART_ID1);
919 id2 = serial_icr_read(up, UART_ID2);
920 id3 = serial_icr_read(up, UART_ID3);
921 rev = serial_icr_read(up, UART_REV);
923 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
925 if (id1 == 0x16 && id2 == 0xC9 &&
926 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
927 up->port.type = PORT_16C950;
930 * Enable work around for the Oxford Semiconductor 952 rev B
931 * chip which causes it to seriously miscalculate baud rates
934 if (id3 == 0x52 && rev == 0x01)
935 up->bugs |= UART_BUG_QUOT;
940 * We check for a XR16C850 by setting DLL and DLM to 0, and then
941 * reading back DLL and DLM. The chip type depends on the DLM
943 * 0x10 - XR16C850 and the DLL contains the chip revision.
947 id1 = autoconfig_read_divisor_id(up);
948 DEBUG_AUTOCONF("850id=%04x ", id1);
951 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
952 up->port.type = PORT_16850;
957 * It wasn't an XR16C850.
959 * We distinguish between the '654 and the '650 by counting
960 * how many bytes are in the FIFO. I'm using this for now,
961 * since that's the technique that was sent to me in the
962 * serial driver update, but I'm not convinced this works.
963 * I've had problems doing this in the past. -TYT
965 if (size_fifo(up) == 64)
966 up->port.type = PORT_16654;
968 up->port.type = PORT_16650V2;
972 * We detected a chip without a FIFO. Only two fall into
973 * this category - the original 8250 and the 16450. The
974 * 16450 has a scratch register (accessible with LCR=0)
976 static void autoconfig_8250(struct uart_8250_port *up)
978 unsigned char scratch, status1, status2;
980 up->port.type = PORT_8250;
982 scratch = serial_in(up, UART_SCR);
983 serial_out(up, UART_SCR, 0xa5);
984 status1 = serial_in(up, UART_SCR);
985 serial_out(up, UART_SCR, 0x5a);
986 status2 = serial_in(up, UART_SCR);
987 serial_out(up, UART_SCR, scratch);
989 if (status1 == 0xa5 && status2 == 0x5a)
990 up->port.type = PORT_16450;
993 static int broken_efr(struct uart_8250_port *up)
996 * Exar ST16C2550 "A2" devices incorrectly detect as
997 * having an EFR, and report an ID of 0x0201. See
998 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1000 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1007 * We know that the chip has FIFOs. Does it have an EFR? The
1008 * EFR is located in the same register position as the IIR and
1009 * we know the top two bits of the IIR are currently set. The
1010 * EFR should contain zero. Try to read the EFR.
1012 static void autoconfig_16550a(struct uart_8250_port *up)
1014 unsigned char status1, status2;
1015 unsigned int iersave;
1017 up->port.type = PORT_16550A;
1018 up->capabilities |= UART_CAP_FIFO;
1021 * XR17V35x UARTs have an extra divisor register, DLD
1022 * that gets enabled with when DLAB is set which will
1023 * cause the device to incorrectly match and assign
1024 * port type to PORT_16650. The EFR for this UART is
1025 * found at offset 0x09. Instead check the Deice ID (DVID)
1026 * register for a 2, 4 or 8 port UART.
1028 if (up->port.flags & UPF_EXAR_EFR) {
1029 status1 = serial_in(up, UART_EXAR_DVID);
1030 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
1031 DEBUG_AUTOCONF("Exar XR17V35x ");
1032 up->port.type = PORT_XR17V35X;
1033 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1042 * Check for presence of the EFR when DLAB is set.
1043 * Only ST16C650V1 UARTs pass this test.
1045 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1046 if (serial_in(up, UART_EFR) == 0) {
1047 serial_out(up, UART_EFR, 0xA8);
1048 if (serial_in(up, UART_EFR) != 0) {
1049 DEBUG_AUTOCONF("EFRv1 ");
1050 up->port.type = PORT_16650;
1051 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1053 serial_out(up, UART_LCR, 0);
1054 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1056 status1 = serial_in(up, UART_IIR) >> 5;
1057 serial_out(up, UART_FCR, 0);
1058 serial_out(up, UART_LCR, 0);
1061 up->port.type = PORT_16550A_FSL64;
1063 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1065 serial_out(up, UART_EFR, 0);
1070 * Maybe it requires 0xbf to be written to the LCR.
1071 * (other ST16C650V2 UARTs, TI16C752A, etc)
1073 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1074 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1075 DEBUG_AUTOCONF("EFRv2 ");
1076 autoconfig_has_efr(up);
1081 * Check for a National Semiconductor SuperIO chip.
1082 * Attempt to switch to bank 2, read the value of the LOOP bit
1083 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1084 * switch back to bank 2, read it from EXCR1 again and check
1085 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1087 serial_out(up, UART_LCR, 0);
1088 status1 = serial8250_in_MCR(up);
1089 serial_out(up, UART_LCR, 0xE0);
1090 status2 = serial_in(up, 0x02); /* EXCR1 */
1092 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1093 serial_out(up, UART_LCR, 0);
1094 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1095 serial_out(up, UART_LCR, 0xE0);
1096 status2 = serial_in(up, 0x02); /* EXCR1 */
1097 serial_out(up, UART_LCR, 0);
1098 serial8250_out_MCR(up, status1);
1100 if ((status2 ^ status1) & UART_MCR_LOOP) {
1101 unsigned short quot;
1103 serial_out(up, UART_LCR, 0xE0);
1105 quot = serial_dl_read(up);
1108 if (ns16550a_goto_highspeed(up))
1109 serial_dl_write(up, quot);
1111 serial_out(up, UART_LCR, 0);
1113 up->port.uartclk = 921600*16;
1114 up->port.type = PORT_NS16550A;
1115 up->capabilities |= UART_NATSEMI;
1121 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1122 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1123 * Try setting it with and without DLAB set. Cheap clones
1124 * set bit 5 without DLAB set.
1126 serial_out(up, UART_LCR, 0);
1127 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1128 status1 = serial_in(up, UART_IIR) >> 5;
1129 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1130 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1131 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1132 status2 = serial_in(up, UART_IIR) >> 5;
1133 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1134 serial_out(up, UART_LCR, 0);
1136 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1138 if (status1 == 6 && status2 == 7) {
1139 up->port.type = PORT_16750;
1140 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1145 * Try writing and reading the UART_IER_UUE bit (b6).
1146 * If it works, this is probably one of the Xscale platform's
1148 * We're going to explicitly set the UUE bit to 0 before
1149 * trying to write and read a 1 just to make sure it's not
1150 * already a 1 and maybe locked there before we even start start.
1152 iersave = serial_in(up, UART_IER);
1153 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1154 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1156 * OK it's in a known zero state, try writing and reading
1157 * without disturbing the current state of the other bits.
1159 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1160 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1163 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1165 DEBUG_AUTOCONF("Xscale ");
1166 up->port.type = PORT_XSCALE;
1167 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1172 * If we got here we couldn't force the IER_UUE bit to 0.
1173 * Log it and continue.
1175 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1177 serial_out(up, UART_IER, iersave);
1180 * Exar uarts have EFR in a weird location
1182 if (up->port.flags & UPF_EXAR_EFR) {
1183 DEBUG_AUTOCONF("Exar XR17D15x ");
1184 up->port.type = PORT_XR17D15X;
1185 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1192 * We distinguish between 16550A and U6 16550A by counting
1193 * how many bytes are in the FIFO.
1195 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1196 up->port.type = PORT_U6_16550A;
1197 up->capabilities |= UART_CAP_AFE;
1202 * This routine is called by rs_init() to initialize a specific serial
1203 * port. It determines what type of UART chip this serial port is
1204 * using: 8250, 16450, 16550, 16550A. The important question is
1205 * whether or not this UART is a 16550A or not, since this will
1206 * determine whether or not we can use its FIFO features or not.
1208 static void autoconfig(struct uart_8250_port *up)
1210 unsigned char status1, scratch, scratch2, scratch3;
1211 unsigned char save_lcr, save_mcr;
1212 struct uart_port *port = &up->port;
1213 unsigned long flags;
1214 unsigned int old_capabilities;
1216 if (!port->iobase && !port->mapbase && !port->membase)
1219 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1220 serial_index(port), port->iobase, port->membase);
1223 * We really do need global IRQs disabled here - we're going to
1224 * be frobbing the chips IRQ enable register to see if it exists.
1226 spin_lock_irqsave(&port->lock, flags);
1228 up->capabilities = 0;
1231 if (!(port->flags & UPF_BUGGY_UART)) {
1233 * Do a simple existence test first; if we fail this,
1234 * there's no point trying anything else.
1236 * 0x80 is used as a nonsense port to prevent against
1237 * false positives due to ISA bus float. The
1238 * assumption is that 0x80 is a non-existent port;
1239 * which should be safe since include/asm/io.h also
1240 * makes this assumption.
1242 * Note: this is safe as long as MCR bit 4 is clear
1243 * and the device is in "PC" mode.
1245 scratch = serial_in(up, UART_IER);
1246 serial_out(up, UART_IER, 0);
1251 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1252 * 16C754B) allow only to modify them if an EFR bit is set.
1254 scratch2 = serial_in(up, UART_IER) & 0x0f;
1255 serial_out(up, UART_IER, 0x0F);
1259 scratch3 = serial_in(up, UART_IER) & 0x0f;
1260 serial_out(up, UART_IER, scratch);
1261 if (scratch2 != 0 || scratch3 != 0x0F) {
1263 * We failed; there's nothing here
1265 spin_unlock_irqrestore(&port->lock, flags);
1266 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1267 scratch2, scratch3);
1272 save_mcr = serial8250_in_MCR(up);
1273 save_lcr = serial_in(up, UART_LCR);
1276 * Check to see if a UART is really there. Certain broken
1277 * internal modems based on the Rockwell chipset fail this
1278 * test, because they apparently don't implement the loopback
1279 * test mode. So this test is skipped on the COM 1 through
1280 * COM 4 ports. This *should* be safe, since no board
1281 * manufacturer would be stupid enough to design a board
1282 * that conflicts with COM 1-4 --- we hope!
1284 if (!(port->flags & UPF_SKIP_TEST)) {
1285 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1286 status1 = serial_in(up, UART_MSR) & 0xF0;
1287 serial8250_out_MCR(up, save_mcr);
1288 if (status1 != 0x90) {
1289 spin_unlock_irqrestore(&port->lock, flags);
1290 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1297 * We're pretty sure there's a port here. Lets find out what
1298 * type of port it is. The IIR top two bits allows us to find
1299 * out if it's 8250 or 16450, 16550, 16550A or later. This
1300 * determines what we test for next.
1302 * We also initialise the EFR (if any) to zero for later. The
1303 * EFR occupies the same register location as the FCR and IIR.
1305 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1306 serial_out(up, UART_EFR, 0);
1307 serial_out(up, UART_LCR, 0);
1309 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1311 /* Assign this as it is to truncate any bits above 7. */
1312 scratch = serial_in(up, UART_IIR);
1314 switch (scratch >> 6) {
1316 autoconfig_8250(up);
1319 port->type = PORT_UNKNOWN;
1322 port->type = PORT_16550;
1325 autoconfig_16550a(up);
1329 #ifdef CONFIG_SERIAL_8250_RSA
1331 * Only probe for RSA ports if we got the region.
1333 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1335 port->type = PORT_RSA;
1338 serial_out(up, UART_LCR, save_lcr);
1340 port->fifosize = uart_config[up->port.type].fifo_size;
1341 old_capabilities = up->capabilities;
1342 up->capabilities = uart_config[port->type].flags;
1343 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1345 if (port->type == PORT_UNKNOWN)
1351 #ifdef CONFIG_SERIAL_8250_RSA
1352 if (port->type == PORT_RSA)
1353 serial_out(up, UART_RSA_FRR, 0);
1355 serial8250_out_MCR(up, save_mcr);
1356 serial8250_clear_fifos(up);
1357 serial_in(up, UART_RX);
1358 if (up->capabilities & UART_CAP_UUE)
1359 serial_out(up, UART_IER, UART_IER_UUE);
1361 serial_out(up, UART_IER, 0);
1364 spin_unlock_irqrestore(&port->lock, flags);
1367 * Check if the device is a Fintek F81216A
1369 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1370 fintek_8250_probe(up);
1372 if (up->capabilities != old_capabilities) {
1373 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1374 serial_index(port), old_capabilities,
1378 DEBUG_AUTOCONF("iir=%d ", scratch);
1379 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1382 static void autoconfig_irq(struct uart_8250_port *up)
1384 struct uart_port *port = &up->port;
1385 unsigned char save_mcr, save_ier;
1386 unsigned char save_ICP = 0;
1387 unsigned int ICP = 0;
1391 if (port->flags & UPF_FOURPORT) {
1392 ICP = (port->iobase & 0xfe0) | 0x1f;
1393 save_ICP = inb_p(ICP);
1398 if (uart_console(port))
1401 /* forget possible initially masked and pending IRQ */
1402 probe_irq_off(probe_irq_on());
1403 save_mcr = serial8250_in_MCR(up);
1404 save_ier = serial_in(up, UART_IER);
1405 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1407 irqs = probe_irq_on();
1408 serial8250_out_MCR(up, 0);
1410 if (port->flags & UPF_FOURPORT) {
1411 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1413 serial8250_out_MCR(up,
1414 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1416 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1417 serial_in(up, UART_LSR);
1418 serial_in(up, UART_RX);
1419 serial_in(up, UART_IIR);
1420 serial_in(up, UART_MSR);
1421 serial_out(up, UART_TX, 0xFF);
1423 irq = probe_irq_off(irqs);
1425 serial8250_out_MCR(up, save_mcr);
1426 serial_out(up, UART_IER, save_ier);
1428 if (port->flags & UPF_FOURPORT)
1429 outb_p(save_ICP, ICP);
1431 if (uart_console(port))
1434 port->irq = (irq > 0) ? irq : 0;
1437 static void serial8250_stop_rx(struct uart_port *port)
1439 struct uart_8250_port *up = up_to_u8250p(port);
1441 serial8250_rpm_get(up);
1443 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1444 up->port.read_status_mask &= ~UART_LSR_DR;
1445 serial_port_out(port, UART_IER, up->ier);
1447 serial8250_rpm_put(up);
1450 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1452 serial8250_em485_rts_after_send(p);
1455 * Empty the RX FIFO, we are not interested in anything
1456 * received during the half-duplex transmission.
1457 * Enable previously disabled RX interrupts.
1459 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1460 serial8250_clear_and_reinit_fifos(p);
1462 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1463 serial_port_out(&p->port, UART_IER, p->ier);
1466 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1468 struct uart_8250_em485 *em485;
1469 struct uart_8250_port *p;
1470 unsigned long flags;
1472 em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1475 serial8250_rpm_get(p);
1476 spin_lock_irqsave(&p->port.lock, flags);
1477 if (em485->active_timer == &em485->stop_tx_timer) {
1478 __do_stop_tx_rs485(p);
1479 em485->active_timer = NULL;
1481 spin_unlock_irqrestore(&p->port.lock, flags);
1482 serial8250_rpm_put(p);
1483 return HRTIMER_NORESTART;
1486 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1488 long sec = msec / 1000;
1489 long nsec = (msec % 1000) * 1000000;
1490 ktime_t t = ktime_set(sec, nsec);
1492 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1495 static void __stop_tx_rs485(struct uart_8250_port *p)
1497 struct uart_8250_em485 *em485 = p->em485;
1500 * __do_stop_tx_rs485 is going to set RTS according to config
1501 * AND flush RX FIFO if required.
1503 if (p->port.rs485.delay_rts_after_send > 0) {
1504 em485->active_timer = &em485->stop_tx_timer;
1505 start_hrtimer_ms(&em485->stop_tx_timer,
1506 p->port.rs485.delay_rts_after_send);
1508 __do_stop_tx_rs485(p);
1512 static inline void __do_stop_tx(struct uart_8250_port *p)
1514 if (p->ier & UART_IER_THRI) {
1515 p->ier &= ~UART_IER_THRI;
1516 serial_out(p, UART_IER, p->ier);
1517 serial8250_rpm_put_tx(p);
1521 static inline void __stop_tx(struct uart_8250_port *p)
1523 struct uart_8250_em485 *em485 = p->em485;
1526 unsigned char lsr = serial_in(p, UART_LSR);
1527 p->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1530 * To provide required timeing and allow FIFO transfer,
1531 * __stop_tx_rs485() must be called only when both FIFO and
1532 * shift register are empty. It is for device driver to enable
1533 * interrupt on TEMT.
1535 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1538 em485->active_timer = NULL;
1545 static void serial8250_stop_tx(struct uart_port *port)
1547 struct uart_8250_port *up = up_to_u8250p(port);
1549 serial8250_rpm_get(up);
1553 * We really want to stop the transmitter from sending.
1555 if (port->type == PORT_16C950) {
1556 up->acr |= UART_ACR_TXDIS;
1557 serial_icr_write(up, UART_ACR, up->acr);
1559 serial8250_rpm_put(up);
1562 static inline void __start_tx(struct uart_port *port)
1564 struct uart_8250_port *up = up_to_u8250p(port);
1566 if (up->dma && !up->dma->tx_dma(up))
1569 if (!(up->ier & UART_IER_THRI)) {
1570 up->ier |= UART_IER_THRI;
1571 serial_port_out(port, UART_IER, up->ier);
1573 if (up->bugs & UART_BUG_TXEN) {
1576 lsr = serial_in(up, UART_LSR);
1577 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1578 if (lsr & UART_LSR_THRE)
1579 serial8250_tx_chars(up);
1584 * Re-enable the transmitter if we disabled it.
1586 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1587 up->acr &= ~UART_ACR_TXDIS;
1588 serial_icr_write(up, UART_ACR, up->acr);
1592 static inline void start_tx_rs485(struct uart_port *port)
1594 struct uart_8250_port *up = up_to_u8250p(port);
1595 struct uart_8250_em485 *em485 = up->em485;
1598 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1599 serial8250_stop_rx(&up->port);
1602 * While serial8250_em485_handle_stop_tx() is a noop if
1603 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1604 * the timer is still armed and triggers only after the current bunch of
1605 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1606 * So cancel the timer. There is still a theoretical race condition if
1607 * the timer is already running and only comes around to check for
1608 * em485->active_timer when &em485->stop_tx_timer is armed again.
1610 if (em485->active_timer == &em485->stop_tx_timer)
1611 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1613 em485->active_timer = NULL;
1615 mcr = serial8250_in_MCR(up);
1616 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1617 !!(mcr & UART_MCR_RTS)) {
1618 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1619 mcr |= UART_MCR_RTS;
1621 mcr &= ~UART_MCR_RTS;
1622 serial8250_out_MCR(up, mcr);
1624 if (up->port.rs485.delay_rts_before_send > 0) {
1625 em485->active_timer = &em485->start_tx_timer;
1626 start_hrtimer_ms(&em485->start_tx_timer,
1627 up->port.rs485.delay_rts_before_send);
1635 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1637 struct uart_8250_em485 *em485;
1638 struct uart_8250_port *p;
1639 unsigned long flags;
1641 em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1644 spin_lock_irqsave(&p->port.lock, flags);
1645 if (em485->active_timer == &em485->start_tx_timer) {
1646 __start_tx(&p->port);
1647 em485->active_timer = NULL;
1649 spin_unlock_irqrestore(&p->port.lock, flags);
1650 return HRTIMER_NORESTART;
1653 static void serial8250_start_tx(struct uart_port *port)
1655 struct uart_8250_port *up = up_to_u8250p(port);
1656 struct uart_8250_em485 *em485 = up->em485;
1658 serial8250_rpm_get_tx(up);
1661 em485->active_timer == &em485->start_tx_timer)
1665 start_tx_rs485(port);
1670 static void serial8250_throttle(struct uart_port *port)
1672 port->throttle(port);
1675 static void serial8250_unthrottle(struct uart_port *port)
1677 port->unthrottle(port);
1680 static void serial8250_disable_ms(struct uart_port *port)
1682 struct uart_8250_port *up = up_to_u8250p(port);
1684 /* no MSR capabilities */
1685 if (up->bugs & UART_BUG_NOMSR)
1688 up->ier &= ~UART_IER_MSI;
1689 serial_port_out(port, UART_IER, up->ier);
1692 static void serial8250_enable_ms(struct uart_port *port)
1694 struct uart_8250_port *up = up_to_u8250p(port);
1696 /* no MSR capabilities */
1697 if (up->bugs & UART_BUG_NOMSR)
1700 up->ier |= UART_IER_MSI;
1702 serial8250_rpm_get(up);
1703 serial_port_out(port, UART_IER, up->ier);
1704 serial8250_rpm_put(up);
1707 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1709 struct uart_port *port = &up->port;
1711 char flag = TTY_NORMAL;
1713 if (likely(lsr & UART_LSR_DR))
1714 ch = serial_in(up, UART_RX);
1717 * Intel 82571 has a Serial Over Lan device that will
1718 * set UART_LSR_BI without setting UART_LSR_DR when
1719 * it receives a break. To avoid reading from the
1720 * receive buffer without UART_LSR_DR bit set, we
1721 * just force the read character to be 0
1727 lsr |= up->lsr_saved_flags;
1728 up->lsr_saved_flags = 0;
1730 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1731 if (lsr & UART_LSR_BI) {
1732 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1735 * We do the SysRQ and SAK checking
1736 * here because otherwise the break
1737 * may get masked by ignore_status_mask
1738 * or read_status_mask.
1740 if (uart_handle_break(port))
1742 } else if (lsr & UART_LSR_PE)
1743 port->icount.parity++;
1744 else if (lsr & UART_LSR_FE)
1745 port->icount.frame++;
1746 if (lsr & UART_LSR_OE)
1747 port->icount.overrun++;
1750 * Mask off conditions which should be ignored.
1752 lsr &= port->read_status_mask;
1754 if (lsr & UART_LSR_BI) {
1755 pr_debug("%s: handling break\n", __func__);
1757 } else if (lsr & UART_LSR_PE)
1759 else if (lsr & UART_LSR_FE)
1762 if (uart_handle_sysrq_char(port, ch))
1765 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1769 * serial8250_rx_chars: processes according to the passed in LSR
1770 * value, and returns the remaining LSR bits not handled
1771 * by this Rx routine.
1773 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1775 struct uart_port *port = &up->port;
1776 int max_count = 256;
1779 serial8250_read_char(up, lsr);
1780 if (--max_count == 0)
1782 lsr = serial_in(up, UART_LSR);
1783 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1785 tty_flip_buffer_push(&port->state->port);
1788 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1790 void serial8250_tx_chars(struct uart_8250_port *up)
1792 struct uart_port *port = &up->port;
1793 struct circ_buf *xmit = &port->state->xmit;
1797 serial_out(up, UART_TX, port->x_char);
1802 if (uart_tx_stopped(port)) {
1803 serial8250_stop_tx(port);
1806 if (uart_circ_empty(xmit)) {
1811 count = up->tx_loadsz;
1813 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1814 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1816 if (uart_circ_empty(xmit))
1818 if ((up->capabilities & UART_CAP_HFIFO) &&
1819 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1821 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1822 if ((up->capabilities & UART_CAP_MINI) &&
1823 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1825 } while (--count > 0);
1827 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1828 uart_write_wakeup(port);
1831 * With RPM enabled, we have to wait until the FIFO is empty before the
1832 * HW can go idle. So we get here once again with empty FIFO and disable
1833 * the interrupt and RPM in __stop_tx()
1835 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1838 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1840 /* Caller holds uart port lock */
1841 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1843 struct uart_port *port = &up->port;
1844 unsigned int status = serial_in(up, UART_MSR);
1846 status |= up->msr_saved_flags;
1847 up->msr_saved_flags = 0;
1848 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1849 port->state != NULL) {
1850 if (status & UART_MSR_TERI)
1852 if (status & UART_MSR_DDSR)
1854 if (status & UART_MSR_DDCD)
1855 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1856 if (status & UART_MSR_DCTS)
1857 uart_handle_cts_change(port, status & UART_MSR_CTS);
1859 wake_up_interruptible(&port->state->port.delta_msr_wait);
1864 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1866 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1868 switch (iir & 0x3f) {
1870 if (!up->dma->rx_running)
1874 case UART_IIR_RX_TIMEOUT:
1875 serial8250_rx_dma_flush(up);
1878 return up->dma->rx_dma(up);
1882 * This handles the interrupt from one port.
1884 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1886 unsigned char status;
1887 unsigned long flags;
1888 struct uart_8250_port *up = up_to_u8250p(port);
1889 bool skip_rx = false;
1891 if (iir & UART_IIR_NO_INT)
1894 spin_lock_irqsave(&port->lock, flags);
1896 status = serial_port_in(port, UART_LSR);
1899 * If port is stopped and there are no error conditions in the
1900 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1901 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1902 * control when FIFO occupancy reaches preset threshold, thus
1903 * halting RX. This only works when auto HW flow control is
1906 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1907 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1908 !(port->read_status_mask & UART_LSR_DR))
1911 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1912 if (!up->dma || handle_rx_dma(up, iir))
1913 status = serial8250_rx_chars(up, status);
1915 serial8250_modem_status(up);
1916 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1917 (up->ier & UART_IER_THRI))
1918 serial8250_tx_chars(up);
1920 spin_unlock_irqrestore(&port->lock, flags);
1923 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1925 static int serial8250_default_handle_irq(struct uart_port *port)
1927 struct uart_8250_port *up = up_to_u8250p(port);
1931 serial8250_rpm_get(up);
1933 iir = serial_port_in(port, UART_IIR);
1934 ret = serial8250_handle_irq(port, iir);
1936 serial8250_rpm_put(up);
1941 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1942 * have a programmable TX threshold that triggers the THRE interrupt in
1943 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1944 * has space available. Load it up with tx_loadsz bytes.
1946 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1948 unsigned long flags;
1949 unsigned int iir = serial_port_in(port, UART_IIR);
1951 /* TX Threshold IRQ triggered so load up FIFO */
1952 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1953 struct uart_8250_port *up = up_to_u8250p(port);
1955 spin_lock_irqsave(&port->lock, flags);
1956 serial8250_tx_chars(up);
1957 spin_unlock_irqrestore(&port->lock, flags);
1960 iir = serial_port_in(port, UART_IIR);
1961 return serial8250_handle_irq(port, iir);
1964 static unsigned int serial8250_tx_empty(struct uart_port *port)
1966 struct uart_8250_port *up = up_to_u8250p(port);
1967 unsigned long flags;
1970 serial8250_rpm_get(up);
1972 spin_lock_irqsave(&port->lock, flags);
1973 lsr = serial_port_in(port, UART_LSR);
1974 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1975 spin_unlock_irqrestore(&port->lock, flags);
1977 serial8250_rpm_put(up);
1979 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1982 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1984 struct uart_8250_port *up = up_to_u8250p(port);
1985 unsigned int status;
1988 serial8250_rpm_get(up);
1989 status = serial8250_modem_status(up);
1990 serial8250_rpm_put(up);
1993 if (status & UART_MSR_DCD)
1995 if (status & UART_MSR_RI)
1997 if (status & UART_MSR_DSR)
1999 if (status & UART_MSR_CTS)
2003 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2005 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2007 if (port->get_mctrl)
2008 return port->get_mctrl(port);
2009 return serial8250_do_get_mctrl(port);
2012 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2014 struct uart_8250_port *up = up_to_u8250p(port);
2015 unsigned char mcr = 0;
2017 if (mctrl & TIOCM_RTS)
2018 mcr |= UART_MCR_RTS;
2019 if (mctrl & TIOCM_DTR)
2020 mcr |= UART_MCR_DTR;
2021 if (mctrl & TIOCM_OUT1)
2022 mcr |= UART_MCR_OUT1;
2023 if (mctrl & TIOCM_OUT2)
2024 mcr |= UART_MCR_OUT2;
2025 if (mctrl & TIOCM_LOOP)
2026 mcr |= UART_MCR_LOOP;
2028 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2030 serial8250_out_MCR(up, mcr);
2032 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2034 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2036 if (port->set_mctrl)
2037 port->set_mctrl(port, mctrl);
2039 serial8250_do_set_mctrl(port, mctrl);
2042 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2044 struct uart_8250_port *up = up_to_u8250p(port);
2045 unsigned long flags;
2047 serial8250_rpm_get(up);
2048 spin_lock_irqsave(&port->lock, flags);
2049 if (break_state == -1)
2050 up->lcr |= UART_LCR_SBC;
2052 up->lcr &= ~UART_LCR_SBC;
2053 serial_port_out(port, UART_LCR, up->lcr);
2054 spin_unlock_irqrestore(&port->lock, flags);
2055 serial8250_rpm_put(up);
2059 * Wait for transmitter & holding register to empty
2061 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2063 unsigned int status, tmout = 10000;
2065 /* Wait up to 10ms for the character(s) to be sent. */
2067 status = serial_in(up, UART_LSR);
2069 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2071 if ((status & bits) == bits)
2076 touch_nmi_watchdog();
2079 /* Wait up to 1s for flow control if necessary */
2080 if (up->port.flags & UPF_CONS_FLOW) {
2081 for (tmout = 1000000; tmout; tmout--) {
2082 unsigned int msr = serial_in(up, UART_MSR);
2083 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2084 if (msr & UART_MSR_CTS)
2087 touch_nmi_watchdog();
2092 #ifdef CONFIG_CONSOLE_POLL
2094 * Console polling routines for writing and reading from the uart while
2095 * in an interrupt or debug context.
2098 static int serial8250_get_poll_char(struct uart_port *port)
2100 struct uart_8250_port *up = up_to_u8250p(port);
2104 serial8250_rpm_get(up);
2106 lsr = serial_port_in(port, UART_LSR);
2108 if (!(lsr & UART_LSR_DR)) {
2109 status = NO_POLL_CHAR;
2113 status = serial_port_in(port, UART_RX);
2115 serial8250_rpm_put(up);
2120 static void serial8250_put_poll_char(struct uart_port *port,
2124 struct uart_8250_port *up = up_to_u8250p(port);
2126 serial8250_rpm_get(up);
2128 * First save the IER then disable the interrupts
2130 ier = serial_port_in(port, UART_IER);
2131 if (up->capabilities & UART_CAP_UUE)
2132 serial_port_out(port, UART_IER, UART_IER_UUE);
2134 serial_port_out(port, UART_IER, 0);
2136 wait_for_xmitr(up, BOTH_EMPTY);
2138 * Send the character out.
2140 serial_port_out(port, UART_TX, c);
2143 * Finally, wait for transmitter to become empty
2144 * and restore the IER
2146 wait_for_xmitr(up, BOTH_EMPTY);
2147 serial_port_out(port, UART_IER, ier);
2148 serial8250_rpm_put(up);
2151 #endif /* CONFIG_CONSOLE_POLL */
2153 int serial8250_do_startup(struct uart_port *port)
2155 struct uart_8250_port *up = up_to_u8250p(port);
2156 unsigned long flags;
2157 unsigned char lsr, iir;
2160 if (!port->fifosize)
2161 port->fifosize = uart_config[port->type].fifo_size;
2163 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2164 if (!up->capabilities)
2165 up->capabilities = uart_config[port->type].flags;
2168 if (port->iotype != up->cur_iotype)
2169 set_io_from_upio(port);
2171 serial8250_rpm_get(up);
2172 if (port->type == PORT_16C950) {
2173 /* Wake up and initialize UART */
2175 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2176 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2177 serial_port_out(port, UART_IER, 0);
2178 serial_port_out(port, UART_LCR, 0);
2179 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2180 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2181 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2182 serial_port_out(port, UART_LCR, 0);
2185 if (port->type == PORT_DA830) {
2186 /* Reset the port */
2187 serial_port_out(port, UART_IER, 0);
2188 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2191 /* Enable Tx, Rx and free run mode */
2192 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2193 UART_DA830_PWREMU_MGMT_UTRST |
2194 UART_DA830_PWREMU_MGMT_URRST |
2195 UART_DA830_PWREMU_MGMT_FREE);
2198 if (port->type == PORT_NPCM) {
2200 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2201 * register). Enable it, and set TIOC (timeout interrupt
2202 * comparator) to be 0x20 for correct operation.
2204 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2207 #ifdef CONFIG_SERIAL_8250_RSA
2209 * If this is an RSA port, see if we can kick it up to the
2210 * higher speed clock.
2215 if (port->type == PORT_XR17V35X) {
2217 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2218 * MCR [7:5] and MSR [7:0]
2220 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2223 * Make sure all interrups are masked until initialization is
2224 * complete and the FIFOs are cleared
2226 serial_port_out(port, UART_IER, 0);
2230 * Clear the FIFO buffers and disable them.
2231 * (they will be reenabled in set_termios())
2233 serial8250_clear_fifos(up);
2236 * Clear the interrupt registers.
2238 serial_port_in(port, UART_LSR);
2239 serial_port_in(port, UART_RX);
2240 serial_port_in(port, UART_IIR);
2241 serial_port_in(port, UART_MSR);
2242 if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2243 serial_port_in(port, UART_EXAR_INT0);
2246 * At this point, there's no way the LSR could still be 0xff;
2247 * if it is, then bail out, because there's likely no UART
2250 if (!(port->flags & UPF_BUGGY_UART) &&
2251 (serial_port_in(port, UART_LSR) == 0xff)) {
2252 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2253 serial_index(port));
2259 * For a XR16C850, we need to set the trigger levels
2261 if (port->type == PORT_16850) {
2264 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2266 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2267 serial_port_out(port, UART_FCTR,
2268 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2269 serial_port_out(port, UART_TRG, UART_TRG_96);
2270 serial_port_out(port, UART_FCTR,
2271 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2272 serial_port_out(port, UART_TRG, UART_TRG_96);
2274 serial_port_out(port, UART_LCR, 0);
2278 * For the Altera 16550 variants, set TX threshold trigger level.
2280 if (((port->type == PORT_ALTR_16550_F32) ||
2281 (port->type == PORT_ALTR_16550_F64) ||
2282 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2283 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2284 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2285 pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2286 serial_index(port));
2288 serial_port_out(port, UART_ALTR_AFR,
2289 UART_ALTR_EN_TXFIFO_LW);
2290 serial_port_out(port, UART_ALTR_TX_LOW,
2291 port->fifosize - up->tx_loadsz);
2292 port->handle_irq = serial8250_tx_threshold_handle_irq;
2296 /* Check if we need to have shared IRQs */
2297 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2298 up->port.irqflags |= IRQF_SHARED;
2300 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2303 if (port->irqflags & IRQF_SHARED)
2304 disable_irq_nosync(port->irq);
2307 * Test for UARTs that do not reassert THRE when the
2308 * transmitter is idle and the interrupt has already
2309 * been cleared. Real 16550s should always reassert
2310 * this interrupt whenever the transmitter is idle and
2311 * the interrupt is enabled. Delays are necessary to
2312 * allow register changes to become visible.
2314 spin_lock_irqsave(&port->lock, flags);
2316 wait_for_xmitr(up, UART_LSR_THRE);
2317 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2318 udelay(1); /* allow THRE to set */
2319 iir1 = serial_port_in(port, UART_IIR);
2320 serial_port_out(port, UART_IER, 0);
2321 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2322 udelay(1); /* allow a working UART time to re-assert THRE */
2323 iir = serial_port_in(port, UART_IIR);
2324 serial_port_out(port, UART_IER, 0);
2326 spin_unlock_irqrestore(&port->lock, flags);
2328 if (port->irqflags & IRQF_SHARED)
2329 enable_irq(port->irq);
2332 * If the interrupt is not reasserted, or we otherwise
2333 * don't trust the iir, setup a timer to kick the UART
2334 * on a regular basis.
2336 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2337 up->port.flags & UPF_BUG_THRE) {
2338 up->bugs |= UART_BUG_THRE;
2342 retval = up->ops->setup_irq(up);
2347 * Now, initialize the UART
2349 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2351 spin_lock_irqsave(&port->lock, flags);
2352 if (up->port.flags & UPF_FOURPORT) {
2354 up->port.mctrl |= TIOCM_OUT1;
2357 * Most PC uarts need OUT2 raised to enable interrupts.
2360 up->port.mctrl |= TIOCM_OUT2;
2362 serial8250_set_mctrl(port, port->mctrl);
2365 * Serial over Lan (SoL) hack:
2366 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2367 * used for Serial Over Lan. Those chips take a longer time than a
2368 * normal serial device to signalize that a transmission data was
2369 * queued. Due to that, the above test generally fails. One solution
2370 * would be to delay the reading of iir. However, this is not
2371 * reliable, since the timeout is variable. So, let's just don't
2372 * test if we receive TX irq. This way, we'll never enable
2375 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2376 goto dont_test_tx_en;
2379 * Do a quick test to see if we receive an interrupt when we enable
2382 serial_port_out(port, UART_IER, UART_IER_THRI);
2383 lsr = serial_port_in(port, UART_LSR);
2384 iir = serial_port_in(port, UART_IIR);
2385 serial_port_out(port, UART_IER, 0);
2387 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2388 if (!(up->bugs & UART_BUG_TXEN)) {
2389 up->bugs |= UART_BUG_TXEN;
2390 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2391 serial_index(port));
2394 up->bugs &= ~UART_BUG_TXEN;
2398 spin_unlock_irqrestore(&port->lock, flags);
2401 * Clear the interrupt registers again for luck, and clear the
2402 * saved flags to avoid getting false values from polling
2403 * routines or the previous session.
2405 serial_port_in(port, UART_LSR);
2406 serial_port_in(port, UART_RX);
2407 serial_port_in(port, UART_IIR);
2408 serial_port_in(port, UART_MSR);
2409 if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2410 serial_port_in(port, UART_EXAR_INT0);
2411 up->lsr_saved_flags = 0;
2412 up->msr_saved_flags = 0;
2415 * Request DMA channels for both RX and TX.
2418 retval = serial8250_request_dma(up);
2420 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2421 serial_index(port));
2427 * Set the IER shadow for rx interrupts but defer actual interrupt
2428 * enable until after the FIFOs are enabled; otherwise, an already-
2429 * active sender can swamp the interrupt handler with "too much work".
2431 up->ier = UART_IER_RLSI | UART_IER_RDI;
2433 if (port->flags & UPF_FOURPORT) {
2436 * Enable interrupts on the AST Fourport board
2438 icp = (port->iobase & 0xfe0) | 0x01f;
2444 serial8250_rpm_put(up);
2447 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2449 static int serial8250_startup(struct uart_port *port)
2452 return port->startup(port);
2453 return serial8250_do_startup(port);
2456 void serial8250_do_shutdown(struct uart_port *port)
2458 struct uart_8250_port *up = up_to_u8250p(port);
2459 unsigned long flags;
2461 serial8250_rpm_get(up);
2463 * Disable interrupts from this port
2465 spin_lock_irqsave(&port->lock, flags);
2467 serial_port_out(port, UART_IER, 0);
2468 spin_unlock_irqrestore(&port->lock, flags);
2470 synchronize_irq(port->irq);
2473 serial8250_release_dma(up);
2475 spin_lock_irqsave(&port->lock, flags);
2476 if (port->flags & UPF_FOURPORT) {
2477 /* reset interrupts on the AST Fourport board */
2478 inb((port->iobase & 0xfe0) | 0x1f);
2479 port->mctrl |= TIOCM_OUT1;
2481 port->mctrl &= ~TIOCM_OUT2;
2483 serial8250_set_mctrl(port, port->mctrl);
2484 spin_unlock_irqrestore(&port->lock, flags);
2487 * Disable break condition and FIFOs
2489 serial_port_out(port, UART_LCR,
2490 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2491 serial8250_clear_fifos(up);
2493 #ifdef CONFIG_SERIAL_8250_RSA
2495 * Reset the RSA board back to 115kbps compat mode.
2501 * Read data port to reset things, and then unlink from
2504 serial_port_in(port, UART_RX);
2505 serial8250_rpm_put(up);
2507 up->ops->release_irq(up);
2509 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2511 static void serial8250_shutdown(struct uart_port *port)
2514 port->shutdown(port);
2516 serial8250_do_shutdown(port);
2520 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2521 * Calculate divisor with extra 4-bit fractional portion
2523 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2527 struct uart_port *port = &up->port;
2528 unsigned int quot_16;
2530 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2531 *frac = quot_16 & 0x0f;
2533 return quot_16 >> 4;
2536 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2537 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2540 struct uart_port *port = &up->port;
2542 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2545 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2549 struct uart_port *port = &up->port;
2553 * Handle magic divisors for baud rates above baud_base on
2554 * SMSC SuperIO chips.
2557 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2558 baud == (port->uartclk/4))
2560 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2561 baud == (port->uartclk/8))
2563 else if (up->port.type == PORT_XR17V35X)
2564 quot = xr17v35x_get_divisor(up, baud, frac);
2565 else if (up->port.type == PORT_NPCM)
2566 quot = npcm_get_divisor(up, baud);
2568 quot = uart_get_divisor(port, baud);
2571 * Oxford Semi 952 rev B workaround
2573 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2579 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2584 switch (c_cflag & CSIZE) {
2586 cval = UART_LCR_WLEN5;
2589 cval = UART_LCR_WLEN6;
2592 cval = UART_LCR_WLEN7;
2596 cval = UART_LCR_WLEN8;
2600 if (c_cflag & CSTOPB)
2601 cval |= UART_LCR_STOP;
2602 if (c_cflag & PARENB) {
2603 cval |= UART_LCR_PARITY;
2604 if (up->bugs & UART_BUG_PARITY)
2605 up->fifo_bug = true;
2607 if (!(c_cflag & PARODD))
2608 cval |= UART_LCR_EPAR;
2610 if (c_cflag & CMSPAR)
2611 cval |= UART_LCR_SPAR;
2617 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2618 unsigned int quot, unsigned int quot_frac)
2620 struct uart_8250_port *up = up_to_u8250p(port);
2622 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2623 if (is_omap1510_8250(up)) {
2624 if (baud == 115200) {
2626 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2628 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2632 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2633 * otherwise just set DLAB
2635 if (up->capabilities & UART_NATSEMI)
2636 serial_port_out(port, UART_LCR, 0xe0);
2638 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2640 serial_dl_write(up, quot);
2642 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2643 if (up->port.type == PORT_XR17V35X) {
2644 /* Preserve bits not related to baudrate; DLD[7:4]. */
2645 quot_frac |= serial_port_in(port, 0x2) & 0xf0;
2646 serial_port_out(port, 0x2, quot_frac);
2650 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2651 struct ktermios *termios,
2652 struct ktermios *old)
2655 * Ask the core to calculate the divisor for us.
2656 * Allow 1% tolerance at the upper limit so uart clks marginally
2657 * slower than nominal still match standard baud rates without
2658 * causing transmission errors.
2660 return uart_get_baud_rate(port, termios, old,
2661 port->uartclk / 16 / 0xffff,
2666 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2667 struct ktermios *old)
2669 struct uart_8250_port *up = up_to_u8250p(port);
2671 unsigned long flags;
2672 unsigned int baud, quot, frac = 0;
2674 if (up->capabilities & UART_CAP_MINI) {
2675 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2676 if ((termios->c_cflag & CSIZE) == CS5 ||
2677 (termios->c_cflag & CSIZE) == CS6)
2678 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2680 cval = serial8250_compute_lcr(up, termios->c_cflag);
2682 baud = serial8250_get_baud_rate(port, termios, old);
2683 quot = serial8250_get_divisor(up, baud, &frac);
2686 * Ok, we're now changing the port state. Do it with
2687 * interrupts disabled.
2689 serial8250_rpm_get(up);
2690 spin_lock_irqsave(&port->lock, flags);
2692 up->lcr = cval; /* Save computed LCR */
2694 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2695 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2696 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2697 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2698 up->fcr |= UART_FCR_TRIGGER_1;
2703 * MCR-based auto flow control. When AFE is enabled, RTS will be
2704 * deasserted when the receive FIFO contains more characters than
2705 * the trigger, or the MCR RTS bit is cleared.
2707 if (up->capabilities & UART_CAP_AFE) {
2708 up->mcr &= ~UART_MCR_AFE;
2709 if (termios->c_cflag & CRTSCTS)
2710 up->mcr |= UART_MCR_AFE;
2714 * Update the per-port timeout.
2716 uart_update_timeout(port, termios->c_cflag, baud);
2718 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2719 if (termios->c_iflag & INPCK)
2720 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2721 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2722 port->read_status_mask |= UART_LSR_BI;
2725 * Characteres to ignore
2727 port->ignore_status_mask = 0;
2728 if (termios->c_iflag & IGNPAR)
2729 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2730 if (termios->c_iflag & IGNBRK) {
2731 port->ignore_status_mask |= UART_LSR_BI;
2733 * If we're ignoring parity and break indicators,
2734 * ignore overruns too (for real raw support).
2736 if (termios->c_iflag & IGNPAR)
2737 port->ignore_status_mask |= UART_LSR_OE;
2741 * ignore all characters if CREAD is not set
2743 if ((termios->c_cflag & CREAD) == 0)
2744 port->ignore_status_mask |= UART_LSR_DR;
2747 * CTS flow control flag and modem status interrupts
2749 up->ier &= ~UART_IER_MSI;
2750 if (!(up->bugs & UART_BUG_NOMSR) &&
2751 UART_ENABLE_MS(&up->port, termios->c_cflag))
2752 up->ier |= UART_IER_MSI;
2753 if (up->capabilities & UART_CAP_UUE)
2754 up->ier |= UART_IER_UUE;
2755 if (up->capabilities & UART_CAP_RTOIE)
2756 up->ier |= UART_IER_RTOIE;
2758 serial_port_out(port, UART_IER, up->ier);
2760 if (up->capabilities & UART_CAP_EFR) {
2761 unsigned char efr = 0;
2763 * TI16C752/Startech hardware flow control. FIXME:
2764 * - TI16C752 requires control thresholds to be set.
2765 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2767 if (termios->c_cflag & CRTSCTS)
2768 efr |= UART_EFR_CTS;
2770 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2771 if (port->flags & UPF_EXAR_EFR)
2772 serial_port_out(port, UART_XR_EFR, efr);
2774 serial_port_out(port, UART_EFR, efr);
2777 serial8250_set_divisor(port, baud, quot, frac);
2780 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2781 * is written without DLAB set, this mode will be disabled.
2783 if (port->type == PORT_16750)
2784 serial_port_out(port, UART_FCR, up->fcr);
2786 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2787 if (port->type != PORT_16750) {
2788 /* emulated UARTs (Lucent Venus 167x) need two steps */
2789 if (up->fcr & UART_FCR_ENABLE_FIFO)
2790 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2791 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2793 serial8250_set_mctrl(port, port->mctrl);
2794 spin_unlock_irqrestore(&port->lock, flags);
2795 serial8250_rpm_put(up);
2797 /* Don't rewrite B0 */
2798 if (tty_termios_baud_rate(termios))
2799 tty_termios_encode_baud_rate(termios, baud, baud);
2801 EXPORT_SYMBOL(serial8250_do_set_termios);
2804 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2805 struct ktermios *old)
2807 if (port->set_termios)
2808 port->set_termios(port, termios, old);
2810 serial8250_do_set_termios(port, termios, old);
2813 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2815 if (termios->c_line == N_PPS) {
2816 port->flags |= UPF_HARDPPS_CD;
2817 spin_lock_irq(&port->lock);
2818 serial8250_enable_ms(port);
2819 spin_unlock_irq(&port->lock);
2821 port->flags &= ~UPF_HARDPPS_CD;
2822 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2823 spin_lock_irq(&port->lock);
2824 serial8250_disable_ms(port);
2825 spin_unlock_irq(&port->lock);
2829 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2832 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2834 if (port->set_ldisc)
2835 port->set_ldisc(port, termios);
2837 serial8250_do_set_ldisc(port, termios);
2840 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2841 unsigned int oldstate)
2843 struct uart_8250_port *p = up_to_u8250p(port);
2845 serial8250_set_sleep(p, state != 0);
2847 EXPORT_SYMBOL(serial8250_do_pm);
2850 serial8250_pm(struct uart_port *port, unsigned int state,
2851 unsigned int oldstate)
2854 port->pm(port, state, oldstate);
2856 serial8250_do_pm(port, state, oldstate);
2859 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2861 if (pt->port.mapsize)
2862 return pt->port.mapsize;
2863 if (pt->port.iotype == UPIO_AU) {
2864 if (pt->port.type == PORT_RT2880)
2868 if (is_omap1_8250(pt))
2869 return 0x16 << pt->port.regshift;
2871 return 8 << pt->port.regshift;
2875 * Resource handling.
2877 static int serial8250_request_std_resource(struct uart_8250_port *up)
2879 unsigned int size = serial8250_port_size(up);
2880 struct uart_port *port = &up->port;
2883 switch (port->iotype) {
2890 if (!port->mapbase) {
2895 if (!request_mem_region(port->mapbase, size, "serial")) {
2900 if (port->flags & UPF_IOREMAP) {
2901 port->membase = ioremap_nocache(port->mapbase, size);
2902 if (!port->membase) {
2903 release_mem_region(port->mapbase, size);
2911 if (!request_region(port->iobase, size, "serial"))
2918 static void serial8250_release_std_resource(struct uart_8250_port *up)
2920 unsigned int size = serial8250_port_size(up);
2921 struct uart_port *port = &up->port;
2923 switch (port->iotype) {
2933 if (port->flags & UPF_IOREMAP) {
2934 iounmap(port->membase);
2935 port->membase = NULL;
2938 release_mem_region(port->mapbase, size);
2943 release_region(port->iobase, size);
2948 static void serial8250_release_port(struct uart_port *port)
2950 struct uart_8250_port *up = up_to_u8250p(port);
2952 serial8250_release_std_resource(up);
2955 static int serial8250_request_port(struct uart_port *port)
2957 struct uart_8250_port *up = up_to_u8250p(port);
2959 return serial8250_request_std_resource(up);
2962 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2964 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2965 unsigned char bytes;
2967 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2969 return bytes ? bytes : -EOPNOTSUPP;
2972 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2974 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2977 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2980 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2981 if (bytes < conf_type->rxtrig_bytes[i])
2982 /* Use the nearest lower value */
2983 return (--i) << UART_FCR_R_TRIG_SHIFT;
2986 return UART_FCR_R_TRIG_11;
2989 static int do_get_rxtrig(struct tty_port *port)
2991 struct uart_state *state = container_of(port, struct uart_state, port);
2992 struct uart_port *uport = state->uart_port;
2993 struct uart_8250_port *up = up_to_u8250p(uport);
2995 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2998 return fcr_get_rxtrig_bytes(up);
3001 static int do_serial8250_get_rxtrig(struct tty_port *port)
3005 mutex_lock(&port->mutex);
3006 rxtrig_bytes = do_get_rxtrig(port);
3007 mutex_unlock(&port->mutex);
3009 return rxtrig_bytes;
3012 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
3013 struct device_attribute *attr, char *buf)
3015 struct tty_port *port = dev_get_drvdata(dev);
3018 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3019 if (rxtrig_bytes < 0)
3020 return rxtrig_bytes;
3022 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
3025 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3027 struct uart_state *state = container_of(port, struct uart_state, port);
3028 struct uart_port *uport = state->uart_port;
3029 struct uart_8250_port *up = up_to_u8250p(uport);
3032 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3036 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3040 serial8250_clear_fifos(up);
3041 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3042 up->fcr |= (unsigned char)rxtrig;
3043 serial_out(up, UART_FCR, up->fcr);
3047 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3051 mutex_lock(&port->mutex);
3052 ret = do_set_rxtrig(port, bytes);
3053 mutex_unlock(&port->mutex);
3058 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
3059 struct device_attribute *attr, const char *buf, size_t count)
3061 struct tty_port *port = dev_get_drvdata(dev);
3062 unsigned char bytes;
3068 ret = kstrtou8(buf, 10, &bytes);
3072 ret = do_serial8250_set_rxtrig(port, bytes);
3079 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
3080 serial8250_get_attr_rx_trig_bytes,
3081 serial8250_set_attr_rx_trig_bytes);
3083 static struct attribute *serial8250_dev_attrs[] = {
3084 &dev_attr_rx_trig_bytes.attr,
3088 static struct attribute_group serial8250_dev_attr_group = {
3089 .attrs = serial8250_dev_attrs,
3092 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3094 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3096 if (conf_type->rxtrig_bytes[0])
3097 up->port.attr_group = &serial8250_dev_attr_group;
3100 static void serial8250_config_port(struct uart_port *port, int flags)
3102 struct uart_8250_port *up = up_to_u8250p(port);
3106 * Find the region that we can probe for. This in turn
3107 * tells us whether we can probe for the type of port.
3109 ret = serial8250_request_std_resource(up);
3113 if (port->iotype != up->cur_iotype)
3114 set_io_from_upio(port);
3116 if (flags & UART_CONFIG_TYPE)
3119 /* if access method is AU, it is a 16550 with a quirk */
3120 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3121 up->bugs |= UART_BUG_NOMSR;
3123 /* HW bugs may trigger IRQ while IIR == NO_INT */
3124 if (port->type == PORT_TEGRA)
3125 up->bugs |= UART_BUG_NOMSR;
3127 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3130 if (port->type == PORT_UNKNOWN)
3131 serial8250_release_std_resource(up);
3133 register_dev_spec_attr_grp(up);
3134 up->fcr = uart_config[up->port.type].fcr;
3138 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3140 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3141 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3142 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3143 ser->type == PORT_STARTECH)
3148 static const char *serial8250_type(struct uart_port *port)
3150 int type = port->type;
3152 if (type >= ARRAY_SIZE(uart_config))
3154 return uart_config[type].name;
3157 static const struct uart_ops serial8250_pops = {
3158 .tx_empty = serial8250_tx_empty,
3159 .set_mctrl = serial8250_set_mctrl,
3160 .get_mctrl = serial8250_get_mctrl,
3161 .stop_tx = serial8250_stop_tx,
3162 .start_tx = serial8250_start_tx,
3163 .throttle = serial8250_throttle,
3164 .unthrottle = serial8250_unthrottle,
3165 .stop_rx = serial8250_stop_rx,
3166 .enable_ms = serial8250_enable_ms,
3167 .break_ctl = serial8250_break_ctl,
3168 .startup = serial8250_startup,
3169 .shutdown = serial8250_shutdown,
3170 .set_termios = serial8250_set_termios,
3171 .set_ldisc = serial8250_set_ldisc,
3172 .pm = serial8250_pm,
3173 .type = serial8250_type,
3174 .release_port = serial8250_release_port,
3175 .request_port = serial8250_request_port,
3176 .config_port = serial8250_config_port,
3177 .verify_port = serial8250_verify_port,
3178 #ifdef CONFIG_CONSOLE_POLL
3179 .poll_get_char = serial8250_get_poll_char,
3180 .poll_put_char = serial8250_put_poll_char,
3184 void serial8250_init_port(struct uart_8250_port *up)
3186 struct uart_port *port = &up->port;
3188 spin_lock_init(&port->lock);
3189 port->ops = &serial8250_pops;
3191 up->cur_iotype = 0xFF;
3193 EXPORT_SYMBOL_GPL(serial8250_init_port);
3195 void serial8250_set_defaults(struct uart_8250_port *up)
3197 struct uart_port *port = &up->port;
3199 if (up->port.flags & UPF_FIXED_TYPE) {
3200 unsigned int type = up->port.type;
3202 if (!up->port.fifosize)
3203 up->port.fifosize = uart_config[type].fifo_size;
3205 up->tx_loadsz = uart_config[type].tx_loadsz;
3206 if (!up->capabilities)
3207 up->capabilities = uart_config[type].flags;
3210 set_io_from_upio(port);
3212 /* default dma handlers */
3214 if (!up->dma->tx_dma)
3215 up->dma->tx_dma = serial8250_tx_dma;
3216 if (!up->dma->rx_dma)
3217 up->dma->rx_dma = serial8250_rx_dma;
3220 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3222 #ifdef CONFIG_SERIAL_8250_CONSOLE
3224 static void serial8250_console_putchar(struct uart_port *port, int ch)
3226 struct uart_8250_port *up = up_to_u8250p(port);
3228 wait_for_xmitr(up, UART_LSR_THRE);
3229 serial_port_out(port, UART_TX, ch);
3233 * Restore serial console when h/w power-off detected
3235 static void serial8250_console_restore(struct uart_8250_port *up)
3237 struct uart_port *port = &up->port;
3238 struct ktermios termios;
3239 unsigned int baud, quot, frac = 0;
3241 termios.c_cflag = port->cons->cflag;
3242 termios.c_ispeed = port->cons->ispeed;
3243 termios.c_ospeed = port->cons->ospeed;
3244 if (port->state->port.tty && termios.c_cflag == 0) {
3245 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3246 termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3247 termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3250 baud = serial8250_get_baud_rate(port, &termios, NULL);
3251 quot = serial8250_get_divisor(up, baud, &frac);
3253 serial8250_set_divisor(port, baud, quot, frac);
3254 serial_port_out(port, UART_LCR, up->lcr);
3255 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3259 * Print a string to the serial port trying not to disturb
3260 * any possible real use of the port...
3262 * The console_lock must be held when we get here.
3264 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3267 struct uart_port *port = &up->port;
3268 unsigned long flags;
3272 touch_nmi_watchdog();
3274 serial8250_rpm_get(up);
3278 else if (oops_in_progress)
3279 locked = spin_trylock_irqsave(&port->lock, flags);
3281 spin_lock_irqsave(&port->lock, flags);
3284 * First save the IER then disable the interrupts
3286 ier = serial_port_in(port, UART_IER);
3288 if (up->capabilities & UART_CAP_UUE)
3289 serial_port_out(port, UART_IER, UART_IER_UUE);
3291 serial_port_out(port, UART_IER, 0);
3293 /* check scratch reg to see if port powered off during system sleep */
3294 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3295 serial8250_console_restore(up);
3299 uart_console_write(port, s, count, serial8250_console_putchar);
3302 * Finally, wait for transmitter to become empty
3303 * and restore the IER
3305 wait_for_xmitr(up, BOTH_EMPTY);
3306 serial_port_out(port, UART_IER, ier);
3309 * The receive handling will happen properly because the
3310 * receive ready bit will still be set; it is not cleared
3311 * on read. However, modem control will not, we must
3312 * call it if we have saved something in the saved flags
3313 * while processing with interrupts off.
3315 if (up->msr_saved_flags)
3316 serial8250_modem_status(up);
3319 spin_unlock_irqrestore(&port->lock, flags);
3320 serial8250_rpm_put(up);
3323 static unsigned int probe_baud(struct uart_port *port)
3325 unsigned char lcr, dll, dlm;
3328 lcr = serial_port_in(port, UART_LCR);
3329 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3330 dll = serial_port_in(port, UART_DLL);
3331 dlm = serial_port_in(port, UART_DLM);
3332 serial_port_out(port, UART_LCR, lcr);
3334 quot = (dlm << 8) | dll;
3335 return (port->uartclk / 16) / quot;
3338 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3345 if (!port->iobase && !port->membase)
3349 uart_parse_options(options, &baud, &parity, &bits, &flow);
3351 baud = probe_baud(port);
3353 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3356 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3358 MODULE_LICENSE("GPL");