2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
50 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
52 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
55 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
58 * Here we define the default xmit fifo size used for each type of UART.
60 static const struct serial8250_config uart_config[] = {
85 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
86 .rxtrig_bytes = {1, 4, 8, 14},
87 .flags = UART_CAP_FIFO,
98 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
104 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
106 .rxtrig_bytes = {8, 16, 24, 28},
107 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
113 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
115 .rxtrig_bytes = {1, 16, 32, 56},
116 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
124 .name = "16C950/954",
127 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
128 .rxtrig_bytes = {16, 32, 112, 120},
129 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
130 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
136 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
138 .rxtrig_bytes = {8, 16, 56, 60},
139 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
145 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
153 .flags = UART_CAP_FIFO,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
160 .flags = UART_CAP_FIFO | UART_NATSEMI,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
181 .flags = UART_CAP_FIFO | UART_CAP_AFE,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
188 .flags = UART_CAP_FIFO | UART_CAP_AFE,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
196 .rxtrig_bytes = {1, 4, 8, 14},
197 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
213 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
220 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
221 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
222 .flags = UART_CAP_FIFO,
224 [PORT_BRCM_TRUMANAGE] = {
228 .flags = UART_CAP_HFIFO,
233 [PORT_ALTR_16550_F32] = {
234 .name = "Altera 16550 FIFO32",
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO | UART_CAP_AFE,
240 [PORT_ALTR_16550_F64] = {
241 .name = "Altera 16550 FIFO64",
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
254 /* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
255 workaround of errata A-008006 which states that tx_loadsz should be
256 configured less than Maximum supported fifo bytes */
257 [PORT_16550A_FSL64] = {
258 .name = "16550A_FSL64",
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
263 .flags = UART_CAP_FIFO,
266 .name = "Palmchip BK-3103",
269 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
270 .rxtrig_bytes = {1, 4, 8, 14},
271 .flags = UART_CAP_FIFO,
275 /* Uart divisor latch read */
276 static int default_serial_dl_read(struct uart_8250_port *up)
278 /* Assign these in pieces to truncate any bits above 7. */
279 unsigned char dll = serial_in(up, UART_DLL);
280 unsigned char dlm = serial_in(up, UART_DLM);
282 return dll | dlm << 8;
285 /* Uart divisor latch write */
286 static void default_serial_dl_write(struct uart_8250_port *up, int value)
288 serial_out(up, UART_DLL, value & 0xff);
289 serial_out(up, UART_DLM, value >> 8 & 0xff);
292 #ifdef CONFIG_SERIAL_8250_RT288X
294 /* Au1x00/RT288x UART hardware has a weird register layout */
295 static const s8 au_io_in_map[8] = {
303 -1, /* UART_SCR (unmapped) */
306 static const s8 au_io_out_map[8] = {
312 -1, /* UART_LSR (unmapped) */
313 -1, /* UART_MSR (unmapped) */
314 -1, /* UART_SCR (unmapped) */
317 static unsigned int au_serial_in(struct uart_port *p, int offset)
319 if (offset >= ARRAY_SIZE(au_io_in_map))
321 offset = au_io_in_map[offset];
324 return __raw_readl(p->membase + (offset << p->regshift));
327 static void au_serial_out(struct uart_port *p, int offset, int value)
329 if (offset >= ARRAY_SIZE(au_io_out_map))
331 offset = au_io_out_map[offset];
334 __raw_writel(value, p->membase + (offset << p->regshift));
337 /* Au1x00 haven't got a standard divisor latch */
338 static int au_serial_dl_read(struct uart_8250_port *up)
340 return __raw_readl(up->port.membase + 0x28);
343 static void au_serial_dl_write(struct uart_8250_port *up, int value)
345 __raw_writel(value, up->port.membase + 0x28);
350 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
352 offset = offset << p->regshift;
353 outb(p->hub6 - 1 + offset, p->iobase);
354 return inb(p->iobase + 1);
357 static void hub6_serial_out(struct uart_port *p, int offset, int value)
359 offset = offset << p->regshift;
360 outb(p->hub6 - 1 + offset, p->iobase);
361 outb(value, p->iobase + 1);
364 static unsigned int mem_serial_in(struct uart_port *p, int offset)
366 offset = offset << p->regshift;
367 return readb(p->membase + offset);
370 static void mem_serial_out(struct uart_port *p, int offset, int value)
372 offset = offset << p->regshift;
373 writeb(value, p->membase + offset);
376 static void mem32_serial_out(struct uart_port *p, int offset, int value)
378 offset = offset << p->regshift;
379 writel(value, p->membase + offset);
382 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
384 offset = offset << p->regshift;
385 return readl(p->membase + offset);
388 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
390 offset = offset << p->regshift;
391 iowrite32be(value, p->membase + offset);
394 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
396 offset = offset << p->regshift;
397 return ioread32be(p->membase + offset);
400 static unsigned int io_serial_in(struct uart_port *p, int offset)
402 offset = offset << p->regshift;
403 return inb(p->iobase + offset);
406 static void io_serial_out(struct uart_port *p, int offset, int value)
408 offset = offset << p->regshift;
409 outb(value, p->iobase + offset);
412 static int serial8250_default_handle_irq(struct uart_port *port);
413 static int exar_handle_irq(struct uart_port *port);
415 static void set_io_from_upio(struct uart_port *p)
417 struct uart_8250_port *up = up_to_u8250p(p);
419 up->dl_read = default_serial_dl_read;
420 up->dl_write = default_serial_dl_write;
424 p->serial_in = hub6_serial_in;
425 p->serial_out = hub6_serial_out;
429 p->serial_in = mem_serial_in;
430 p->serial_out = mem_serial_out;
434 p->serial_in = mem32_serial_in;
435 p->serial_out = mem32_serial_out;
439 p->serial_in = mem32be_serial_in;
440 p->serial_out = mem32be_serial_out;
443 #ifdef CONFIG_SERIAL_8250_RT288X
445 p->serial_in = au_serial_in;
446 p->serial_out = au_serial_out;
447 up->dl_read = au_serial_dl_read;
448 up->dl_write = au_serial_dl_write;
453 p->serial_in = io_serial_in;
454 p->serial_out = io_serial_out;
457 /* Remember loaded iotype */
458 up->cur_iotype = p->iotype;
459 p->handle_irq = serial8250_default_handle_irq;
463 serial_port_out_sync(struct uart_port *p, int offset, int value)
470 p->serial_out(p, offset, value);
471 p->serial_in(p, UART_LCR); /* safe, no side-effects */
474 p->serial_out(p, offset, value);
481 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
483 serial_out(up, UART_SCR, offset);
484 serial_out(up, UART_ICR, value);
487 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
491 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
492 serial_out(up, UART_SCR, offset);
493 value = serial_in(up, UART_ICR);
494 serial_icr_write(up, UART_ACR, up->acr);
502 static void serial8250_clear_fifos(struct uart_8250_port *p)
504 if (p->capabilities & UART_CAP_FIFO) {
505 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
506 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
507 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
508 serial_out(p, UART_FCR, 0);
512 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
514 serial8250_clear_fifos(p);
515 serial_out(p, UART_FCR, p->fcr);
517 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
519 void serial8250_rpm_get(struct uart_8250_port *p)
521 if (!(p->capabilities & UART_CAP_RPM))
523 pm_runtime_get_sync(p->port.dev);
525 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
527 void serial8250_rpm_put(struct uart_8250_port *p)
529 if (!(p->capabilities & UART_CAP_RPM))
531 pm_runtime_mark_last_busy(p->port.dev);
532 pm_runtime_put_autosuspend(p->port.dev);
534 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
537 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
538 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
539 * empty and the HW can idle again.
541 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
543 unsigned char rpm_active;
545 if (!(p->capabilities & UART_CAP_RPM))
548 rpm_active = xchg(&p->rpm_tx_active, 1);
551 pm_runtime_get_sync(p->port.dev);
554 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
556 unsigned char rpm_active;
558 if (!(p->capabilities & UART_CAP_RPM))
561 rpm_active = xchg(&p->rpm_tx_active, 0);
564 pm_runtime_mark_last_busy(p->port.dev);
565 pm_runtime_put_autosuspend(p->port.dev);
569 * IER sleep support. UARTs which have EFRs need the "extended
570 * capability" bit enabled. Note that on XR16C850s, we need to
571 * reset LCR to write to IER.
573 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
575 unsigned char lcr = 0, efr = 0;
577 * Exar UARTs have a SLEEP register that enables or disables
578 * each UART to enter sleep mode separately. On the XR17V35x the
579 * register is accessible to each UART at the UART_EXAR_SLEEP
580 * offset but the UART channel may only write to the corresponding
583 serial8250_rpm_get(p);
584 if ((p->port.type == PORT_XR17V35X) ||
585 (p->port.type == PORT_XR17D15X)) {
586 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
590 if (p->capabilities & UART_CAP_SLEEP) {
591 if (p->capabilities & UART_CAP_EFR) {
592 lcr = serial_in(p, UART_LCR);
593 efr = serial_in(p, UART_EFR);
594 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
595 serial_out(p, UART_EFR, UART_EFR_ECB);
596 serial_out(p, UART_LCR, 0);
598 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
599 if (p->capabilities & UART_CAP_EFR) {
600 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
601 serial_out(p, UART_EFR, efr);
602 serial_out(p, UART_LCR, lcr);
606 serial8250_rpm_put(p);
609 #ifdef CONFIG_SERIAL_8250_RSA
611 * Attempts to turn on the RSA FIFO. Returns zero on failure.
612 * We set the port uart clock rate if we succeed.
614 static int __enable_rsa(struct uart_8250_port *up)
619 mode = serial_in(up, UART_RSA_MSR);
620 result = mode & UART_RSA_MSR_FIFO;
623 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
624 mode = serial_in(up, UART_RSA_MSR);
625 result = mode & UART_RSA_MSR_FIFO;
629 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
634 static void enable_rsa(struct uart_8250_port *up)
636 if (up->port.type == PORT_RSA) {
637 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
638 spin_lock_irq(&up->port.lock);
640 spin_unlock_irq(&up->port.lock);
642 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
643 serial_out(up, UART_RSA_FRR, 0);
648 * Attempts to turn off the RSA FIFO. Returns zero on failure.
649 * It is unknown why interrupts were disabled in here. However,
650 * the caller is expected to preserve this behaviour by grabbing
651 * the spinlock before calling this function.
653 static void disable_rsa(struct uart_8250_port *up)
658 if (up->port.type == PORT_RSA &&
659 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
660 spin_lock_irq(&up->port.lock);
662 mode = serial_in(up, UART_RSA_MSR);
663 result = !(mode & UART_RSA_MSR_FIFO);
666 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
667 mode = serial_in(up, UART_RSA_MSR);
668 result = !(mode & UART_RSA_MSR_FIFO);
672 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
673 spin_unlock_irq(&up->port.lock);
676 #endif /* CONFIG_SERIAL_8250_RSA */
679 * This is a quickie test to see how big the FIFO is.
680 * It doesn't work at all the time, more's the pity.
682 static int size_fifo(struct uart_8250_port *up)
684 unsigned char old_fcr, old_mcr, old_lcr;
685 unsigned short old_dl;
688 old_lcr = serial_in(up, UART_LCR);
689 serial_out(up, UART_LCR, 0);
690 old_fcr = serial_in(up, UART_FCR);
691 old_mcr = serial_in(up, UART_MCR);
692 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
693 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
694 serial_out(up, UART_MCR, UART_MCR_LOOP);
695 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
696 old_dl = serial_dl_read(up);
697 serial_dl_write(up, 0x0001);
698 serial_out(up, UART_LCR, 0x03);
699 for (count = 0; count < 256; count++)
700 serial_out(up, UART_TX, count);
701 mdelay(20);/* FIXME - schedule_timeout */
702 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
703 (count < 256); count++)
704 serial_in(up, UART_RX);
705 serial_out(up, UART_FCR, old_fcr);
706 serial_out(up, UART_MCR, old_mcr);
707 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
708 serial_dl_write(up, old_dl);
709 serial_out(up, UART_LCR, old_lcr);
715 * Read UART ID using the divisor method - set DLL and DLM to zero
716 * and the revision will be in DLL and device type in DLM. We
717 * preserve the device state across this.
719 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
721 unsigned char old_lcr;
722 unsigned int id, old_dl;
724 old_lcr = serial_in(p, UART_LCR);
725 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
726 old_dl = serial_dl_read(p);
727 serial_dl_write(p, 0);
728 id = serial_dl_read(p);
729 serial_dl_write(p, old_dl);
731 serial_out(p, UART_LCR, old_lcr);
737 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
738 * When this function is called we know it is at least a StarTech
739 * 16650 V2, but it might be one of several StarTech UARTs, or one of
740 * its clones. (We treat the broken original StarTech 16650 V1 as a
741 * 16550, and why not? Startech doesn't seem to even acknowledge its
744 * What evil have men's minds wrought...
746 static void autoconfig_has_efr(struct uart_8250_port *up)
748 unsigned int id1, id2, id3, rev;
751 * Everything with an EFR has SLEEP
753 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
756 * First we check to see if it's an Oxford Semiconductor UART.
758 * If we have to do this here because some non-National
759 * Semiconductor clone chips lock up if you try writing to the
760 * LSR register (which serial_icr_read does)
764 * Check for Oxford Semiconductor 16C950.
766 * EFR [4] must be set else this test fails.
768 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
769 * claims that it's needed for 952 dual UART's (which are not
770 * recommended for new designs).
773 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
774 serial_out(up, UART_EFR, UART_EFR_ECB);
775 serial_out(up, UART_LCR, 0x00);
776 id1 = serial_icr_read(up, UART_ID1);
777 id2 = serial_icr_read(up, UART_ID2);
778 id3 = serial_icr_read(up, UART_ID3);
779 rev = serial_icr_read(up, UART_REV);
781 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
783 if (id1 == 0x16 && id2 == 0xC9 &&
784 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
785 up->port.type = PORT_16C950;
788 * Enable work around for the Oxford Semiconductor 952 rev B
789 * chip which causes it to seriously miscalculate baud rates
792 if (id3 == 0x52 && rev == 0x01)
793 up->bugs |= UART_BUG_QUOT;
798 * We check for a XR16C850 by setting DLL and DLM to 0, and then
799 * reading back DLL and DLM. The chip type depends on the DLM
801 * 0x10 - XR16C850 and the DLL contains the chip revision.
805 id1 = autoconfig_read_divisor_id(up);
806 DEBUG_AUTOCONF("850id=%04x ", id1);
809 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
810 up->port.type = PORT_16850;
815 * It wasn't an XR16C850.
817 * We distinguish between the '654 and the '650 by counting
818 * how many bytes are in the FIFO. I'm using this for now,
819 * since that's the technique that was sent to me in the
820 * serial driver update, but I'm not convinced this works.
821 * I've had problems doing this in the past. -TYT
823 if (size_fifo(up) == 64)
824 up->port.type = PORT_16654;
826 up->port.type = PORT_16650V2;
830 * We detected a chip without a FIFO. Only two fall into
831 * this category - the original 8250 and the 16450. The
832 * 16450 has a scratch register (accessible with LCR=0)
834 static void autoconfig_8250(struct uart_8250_port *up)
836 unsigned char scratch, status1, status2;
838 up->port.type = PORT_8250;
840 scratch = serial_in(up, UART_SCR);
841 serial_out(up, UART_SCR, 0xa5);
842 status1 = serial_in(up, UART_SCR);
843 serial_out(up, UART_SCR, 0x5a);
844 status2 = serial_in(up, UART_SCR);
845 serial_out(up, UART_SCR, scratch);
847 if (status1 == 0xa5 && status2 == 0x5a)
848 up->port.type = PORT_16450;
851 static int broken_efr(struct uart_8250_port *up)
854 * Exar ST16C2550 "A2" devices incorrectly detect as
855 * having an EFR, and report an ID of 0x0201. See
856 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
858 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
865 * We know that the chip has FIFOs. Does it have an EFR? The
866 * EFR is located in the same register position as the IIR and
867 * we know the top two bits of the IIR are currently set. The
868 * EFR should contain zero. Try to read the EFR.
870 static void autoconfig_16550a(struct uart_8250_port *up)
872 unsigned char status1, status2;
873 unsigned int iersave;
875 up->port.type = PORT_16550A;
876 up->capabilities |= UART_CAP_FIFO;
879 * XR17V35x UARTs have an extra divisor register, DLD
880 * that gets enabled with when DLAB is set which will
881 * cause the device to incorrectly match and assign
882 * port type to PORT_16650. The EFR for this UART is
883 * found at offset 0x09. Instead check the Deice ID (DVID)
884 * register for a 2, 4 or 8 port UART.
886 if (up->port.flags & UPF_EXAR_EFR) {
887 status1 = serial_in(up, UART_EXAR_DVID);
888 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
889 DEBUG_AUTOCONF("Exar XR17V35x ");
890 up->port.type = PORT_XR17V35X;
891 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
900 * Check for presence of the EFR when DLAB is set.
901 * Only ST16C650V1 UARTs pass this test.
903 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
904 if (serial_in(up, UART_EFR) == 0) {
905 serial_out(up, UART_EFR, 0xA8);
906 if (serial_in(up, UART_EFR) != 0) {
907 DEBUG_AUTOCONF("EFRv1 ");
908 up->port.type = PORT_16650;
909 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
911 serial_out(up, UART_LCR, 0);
912 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
914 status1 = serial_in(up, UART_IIR) >> 5;
915 serial_out(up, UART_FCR, 0);
916 serial_out(up, UART_LCR, 0);
919 up->port.type = PORT_16550A_FSL64;
921 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
923 serial_out(up, UART_EFR, 0);
928 * Maybe it requires 0xbf to be written to the LCR.
929 * (other ST16C650V2 UARTs, TI16C752A, etc)
931 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
932 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
933 DEBUG_AUTOCONF("EFRv2 ");
934 autoconfig_has_efr(up);
939 * Check for a National Semiconductor SuperIO chip.
940 * Attempt to switch to bank 2, read the value of the LOOP bit
941 * from EXCR1. Switch back to bank 0, change it in MCR. Then
942 * switch back to bank 2, read it from EXCR1 again and check
943 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
945 serial_out(up, UART_LCR, 0);
946 status1 = serial_in(up, UART_MCR);
947 serial_out(up, UART_LCR, 0xE0);
948 status2 = serial_in(up, 0x02); /* EXCR1 */
950 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
951 serial_out(up, UART_LCR, 0);
952 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
953 serial_out(up, UART_LCR, 0xE0);
954 status2 = serial_in(up, 0x02); /* EXCR1 */
955 serial_out(up, UART_LCR, 0);
956 serial_out(up, UART_MCR, status1);
958 if ((status2 ^ status1) & UART_MCR_LOOP) {
961 serial_out(up, UART_LCR, 0xE0);
963 quot = serial_dl_read(up);
966 if (ns16550a_goto_highspeed(up))
967 serial_dl_write(up, quot);
969 serial_out(up, UART_LCR, 0);
971 up->port.uartclk = 921600*16;
972 up->port.type = PORT_NS16550A;
973 up->capabilities |= UART_NATSEMI;
979 * No EFR. Try to detect a TI16750, which only sets bit 5 of
980 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
981 * Try setting it with and without DLAB set. Cheap clones
982 * set bit 5 without DLAB set.
984 serial_out(up, UART_LCR, 0);
985 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
986 status1 = serial_in(up, UART_IIR) >> 5;
987 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
988 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
989 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
990 status2 = serial_in(up, UART_IIR) >> 5;
991 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
992 serial_out(up, UART_LCR, 0);
994 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
996 if (status1 == 6 && status2 == 7) {
997 up->port.type = PORT_16750;
998 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1003 * Try writing and reading the UART_IER_UUE bit (b6).
1004 * If it works, this is probably one of the Xscale platform's
1006 * We're going to explicitly set the UUE bit to 0 before
1007 * trying to write and read a 1 just to make sure it's not
1008 * already a 1 and maybe locked there before we even start start.
1010 iersave = serial_in(up, UART_IER);
1011 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1012 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1014 * OK it's in a known zero state, try writing and reading
1015 * without disturbing the current state of the other bits.
1017 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1018 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1021 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1023 DEBUG_AUTOCONF("Xscale ");
1024 up->port.type = PORT_XSCALE;
1025 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1030 * If we got here we couldn't force the IER_UUE bit to 0.
1031 * Log it and continue.
1033 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1035 serial_out(up, UART_IER, iersave);
1038 * Exar uarts have EFR in a weird location
1040 if (up->port.flags & UPF_EXAR_EFR) {
1041 DEBUG_AUTOCONF("Exar XR17D15x ");
1042 up->port.type = PORT_XR17D15X;
1043 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1050 * We distinguish between 16550A and U6 16550A by counting
1051 * how many bytes are in the FIFO.
1053 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1054 up->port.type = PORT_U6_16550A;
1055 up->capabilities |= UART_CAP_AFE;
1060 * This routine is called by rs_init() to initialize a specific serial
1061 * port. It determines what type of UART chip this serial port is
1062 * using: 8250, 16450, 16550, 16550A. The important question is
1063 * whether or not this UART is a 16550A or not, since this will
1064 * determine whether or not we can use its FIFO features or not.
1066 static void autoconfig(struct uart_8250_port *up)
1068 unsigned char status1, scratch, scratch2, scratch3;
1069 unsigned char save_lcr, save_mcr;
1070 struct uart_port *port = &up->port;
1071 unsigned long flags;
1072 unsigned int old_capabilities;
1074 if (!port->iobase && !port->mapbase && !port->membase)
1077 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1078 serial_index(port), port->iobase, port->membase);
1081 * We really do need global IRQs disabled here - we're going to
1082 * be frobbing the chips IRQ enable register to see if it exists.
1084 spin_lock_irqsave(&port->lock, flags);
1086 up->capabilities = 0;
1089 if (!(port->flags & UPF_BUGGY_UART)) {
1091 * Do a simple existence test first; if we fail this,
1092 * there's no point trying anything else.
1094 * 0x80 is used as a nonsense port to prevent against
1095 * false positives due to ISA bus float. The
1096 * assumption is that 0x80 is a non-existent port;
1097 * which should be safe since include/asm/io.h also
1098 * makes this assumption.
1100 * Note: this is safe as long as MCR bit 4 is clear
1101 * and the device is in "PC" mode.
1103 scratch = serial_in(up, UART_IER);
1104 serial_out(up, UART_IER, 0);
1109 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1110 * 16C754B) allow only to modify them if an EFR bit is set.
1112 scratch2 = serial_in(up, UART_IER) & 0x0f;
1113 serial_out(up, UART_IER, 0x0F);
1117 scratch3 = serial_in(up, UART_IER) & 0x0f;
1118 serial_out(up, UART_IER, scratch);
1119 if (scratch2 != 0 || scratch3 != 0x0F) {
1121 * We failed; there's nothing here
1123 spin_unlock_irqrestore(&port->lock, flags);
1124 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1125 scratch2, scratch3);
1130 save_mcr = serial_in(up, UART_MCR);
1131 save_lcr = serial_in(up, UART_LCR);
1134 * Check to see if a UART is really there. Certain broken
1135 * internal modems based on the Rockwell chipset fail this
1136 * test, because they apparently don't implement the loopback
1137 * test mode. So this test is skipped on the COM 1 through
1138 * COM 4 ports. This *should* be safe, since no board
1139 * manufacturer would be stupid enough to design a board
1140 * that conflicts with COM 1-4 --- we hope!
1142 if (!(port->flags & UPF_SKIP_TEST)) {
1143 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1144 status1 = serial_in(up, UART_MSR) & 0xF0;
1145 serial_out(up, UART_MCR, save_mcr);
1146 if (status1 != 0x90) {
1147 spin_unlock_irqrestore(&port->lock, flags);
1148 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1155 * We're pretty sure there's a port here. Lets find out what
1156 * type of port it is. The IIR top two bits allows us to find
1157 * out if it's 8250 or 16450, 16550, 16550A or later. This
1158 * determines what we test for next.
1160 * We also initialise the EFR (if any) to zero for later. The
1161 * EFR occupies the same register location as the FCR and IIR.
1163 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1164 serial_out(up, UART_EFR, 0);
1165 serial_out(up, UART_LCR, 0);
1167 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1169 /* Assign this as it is to truncate any bits above 7. */
1170 scratch = serial_in(up, UART_IIR);
1172 switch (scratch >> 6) {
1174 autoconfig_8250(up);
1177 port->type = PORT_UNKNOWN;
1180 port->type = PORT_16550;
1183 autoconfig_16550a(up);
1187 #ifdef CONFIG_SERIAL_8250_RSA
1189 * Only probe for RSA ports if we got the region.
1191 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1193 port->type = PORT_RSA;
1196 serial_out(up, UART_LCR, save_lcr);
1198 port->fifosize = uart_config[up->port.type].fifo_size;
1199 old_capabilities = up->capabilities;
1200 up->capabilities = uart_config[port->type].flags;
1201 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1203 if (port->type == PORT_UNKNOWN)
1209 #ifdef CONFIG_SERIAL_8250_RSA
1210 if (port->type == PORT_RSA)
1211 serial_out(up, UART_RSA_FRR, 0);
1213 serial_out(up, UART_MCR, save_mcr);
1214 serial8250_clear_fifos(up);
1215 serial_in(up, UART_RX);
1216 if (up->capabilities & UART_CAP_UUE)
1217 serial_out(up, UART_IER, UART_IER_UUE);
1219 serial_out(up, UART_IER, 0);
1222 spin_unlock_irqrestore(&port->lock, flags);
1223 if (up->capabilities != old_capabilities) {
1225 "ttyS%d: detected caps %08x should be %08x\n",
1226 serial_index(port), old_capabilities,
1230 DEBUG_AUTOCONF("iir=%d ", scratch);
1231 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1234 static void autoconfig_irq(struct uart_8250_port *up)
1236 struct uart_port *port = &up->port;
1237 unsigned char save_mcr, save_ier;
1238 unsigned char save_ICP = 0;
1239 unsigned int ICP = 0;
1243 if (port->flags & UPF_FOURPORT) {
1244 ICP = (port->iobase & 0xfe0) | 0x1f;
1245 save_ICP = inb_p(ICP);
1250 if (uart_console(port))
1253 /* forget possible initially masked and pending IRQ */
1254 probe_irq_off(probe_irq_on());
1255 save_mcr = serial_in(up, UART_MCR);
1256 save_ier = serial_in(up, UART_IER);
1257 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1259 irqs = probe_irq_on();
1260 serial_out(up, UART_MCR, 0);
1262 if (port->flags & UPF_FOURPORT) {
1263 serial_out(up, UART_MCR,
1264 UART_MCR_DTR | UART_MCR_RTS);
1266 serial_out(up, UART_MCR,
1267 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1269 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1270 serial_in(up, UART_LSR);
1271 serial_in(up, UART_RX);
1272 serial_in(up, UART_IIR);
1273 serial_in(up, UART_MSR);
1274 serial_out(up, UART_TX, 0xFF);
1276 irq = probe_irq_off(irqs);
1278 serial_out(up, UART_MCR, save_mcr);
1279 serial_out(up, UART_IER, save_ier);
1281 if (port->flags & UPF_FOURPORT)
1282 outb_p(save_ICP, ICP);
1284 if (uart_console(port))
1287 port->irq = (irq > 0) ? irq : 0;
1290 static inline void __stop_tx(struct uart_8250_port *p)
1292 if (p->ier & UART_IER_THRI) {
1293 p->ier &= ~UART_IER_THRI;
1294 serial_out(p, UART_IER, p->ier);
1295 serial8250_rpm_put_tx(p);
1299 static void serial8250_stop_tx(struct uart_port *port)
1301 struct uart_8250_port *up = up_to_u8250p(port);
1303 serial8250_rpm_get(up);
1307 * We really want to stop the transmitter from sending.
1309 if (port->type == PORT_16C950) {
1310 up->acr |= UART_ACR_TXDIS;
1311 serial_icr_write(up, UART_ACR, up->acr);
1313 serial8250_rpm_put(up);
1316 static void serial8250_start_tx(struct uart_port *port)
1318 struct uart_8250_port *up = up_to_u8250p(port);
1320 serial8250_rpm_get_tx(up);
1322 if (up->dma && !up->dma->tx_dma(up))
1325 if (!(up->ier & UART_IER_THRI)) {
1326 up->ier |= UART_IER_THRI;
1327 serial_port_out(port, UART_IER, up->ier);
1329 if (up->bugs & UART_BUG_TXEN) {
1331 lsr = serial_in(up, UART_LSR);
1332 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1333 if (lsr & UART_LSR_THRE)
1334 serial8250_tx_chars(up);
1339 * Re-enable the transmitter if we disabled it.
1341 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1342 up->acr &= ~UART_ACR_TXDIS;
1343 serial_icr_write(up, UART_ACR, up->acr);
1347 static void serial8250_throttle(struct uart_port *port)
1349 port->throttle(port);
1352 static void serial8250_unthrottle(struct uart_port *port)
1354 port->unthrottle(port);
1357 static void serial8250_stop_rx(struct uart_port *port)
1359 struct uart_8250_port *up = up_to_u8250p(port);
1361 serial8250_rpm_get(up);
1363 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1364 up->port.read_status_mask &= ~UART_LSR_DR;
1365 serial_port_out(port, UART_IER, up->ier);
1367 serial8250_rpm_put(up);
1370 static void serial8250_disable_ms(struct uart_port *port)
1372 struct uart_8250_port *up =
1373 container_of(port, struct uart_8250_port, port);
1375 /* no MSR capabilities */
1376 if (up->bugs & UART_BUG_NOMSR)
1379 up->ier &= ~UART_IER_MSI;
1380 serial_port_out(port, UART_IER, up->ier);
1383 static void serial8250_enable_ms(struct uart_port *port)
1385 struct uart_8250_port *up = up_to_u8250p(port);
1387 /* no MSR capabilities */
1388 if (up->bugs & UART_BUG_NOMSR)
1391 up->ier |= UART_IER_MSI;
1393 serial8250_rpm_get(up);
1394 serial_port_out(port, UART_IER, up->ier);
1395 serial8250_rpm_put(up);
1399 * serial8250_rx_chars: processes according to the passed in LSR
1400 * value, and returns the remaining LSR bits not handled
1401 * by this Rx routine.
1404 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1406 struct uart_port *port = &up->port;
1408 int max_count = 256;
1412 if (likely(lsr & UART_LSR_DR))
1413 ch = serial_in(up, UART_RX);
1416 * Intel 82571 has a Serial Over Lan device that will
1417 * set UART_LSR_BI without setting UART_LSR_DR when
1418 * it receives a break. To avoid reading from the
1419 * receive buffer without UART_LSR_DR bit set, we
1420 * just force the read character to be 0
1427 lsr |= up->lsr_saved_flags;
1428 up->lsr_saved_flags = 0;
1430 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1431 if (lsr & UART_LSR_BI) {
1432 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1435 * We do the SysRQ and SAK checking
1436 * here because otherwise the break
1437 * may get masked by ignore_status_mask
1438 * or read_status_mask.
1440 if (uart_handle_break(port))
1442 } else if (lsr & UART_LSR_PE)
1443 port->icount.parity++;
1444 else if (lsr & UART_LSR_FE)
1445 port->icount.frame++;
1446 if (lsr & UART_LSR_OE)
1447 port->icount.overrun++;
1450 * Mask off conditions which should be ignored.
1452 lsr &= port->read_status_mask;
1454 if (lsr & UART_LSR_BI) {
1455 DEBUG_INTR("handling break....");
1457 } else if (lsr & UART_LSR_PE)
1459 else if (lsr & UART_LSR_FE)
1462 if (uart_handle_sysrq_char(port, ch))
1465 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1468 lsr = serial_in(up, UART_LSR);
1469 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0));
1470 spin_unlock(&port->lock);
1471 tty_flip_buffer_push(&port->state->port);
1472 spin_lock(&port->lock);
1475 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1477 void serial8250_tx_chars(struct uart_8250_port *up)
1479 struct uart_port *port = &up->port;
1480 struct circ_buf *xmit = &port->state->xmit;
1484 serial_out(up, UART_TX, port->x_char);
1489 if (uart_tx_stopped(port)) {
1490 serial8250_stop_tx(port);
1493 if (uart_circ_empty(xmit)) {
1498 count = up->tx_loadsz;
1500 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1501 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1503 if (uart_circ_empty(xmit))
1505 if (up->capabilities & UART_CAP_HFIFO) {
1506 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1510 } while (--count > 0);
1512 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1513 uart_write_wakeup(port);
1515 DEBUG_INTR("THRE...");
1518 * With RPM enabled, we have to wait until the FIFO is empty before the
1519 * HW can go idle. So we get here once again with empty FIFO and disable
1520 * the interrupt and RPM in __stop_tx()
1522 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1525 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1527 /* Caller holds uart port lock */
1528 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1530 struct uart_port *port = &up->port;
1531 unsigned int status = serial_in(up, UART_MSR);
1533 status |= up->msr_saved_flags;
1534 up->msr_saved_flags = 0;
1535 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1536 port->state != NULL) {
1537 if (status & UART_MSR_TERI)
1539 if (status & UART_MSR_DDSR)
1541 if (status & UART_MSR_DDCD)
1542 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1543 if (status & UART_MSR_DCTS)
1544 uart_handle_cts_change(port, status & UART_MSR_CTS);
1546 wake_up_interruptible(&port->state->port.delta_msr_wait);
1551 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1554 * This handles the interrupt from one port.
1556 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1558 unsigned char status;
1559 unsigned long flags;
1560 struct uart_8250_port *up = up_to_u8250p(port);
1563 if (iir & UART_IIR_NO_INT)
1566 spin_lock_irqsave(&port->lock, flags);
1568 status = serial_port_in(port, UART_LSR);
1570 DEBUG_INTR("status = %x...", status);
1572 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1574 dma_err = up->dma->rx_dma(up, iir);
1576 if (!up->dma || dma_err)
1577 status = serial8250_rx_chars(up, status);
1579 serial8250_modem_status(up);
1580 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1581 (status & UART_LSR_THRE))
1582 serial8250_tx_chars(up);
1584 spin_unlock_irqrestore(&port->lock, flags);
1587 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1589 static int serial8250_default_handle_irq(struct uart_port *port)
1591 struct uart_8250_port *up = up_to_u8250p(port);
1595 serial8250_rpm_get(up);
1597 iir = serial_port_in(port, UART_IIR);
1598 ret = serial8250_handle_irq(port, iir);
1600 serial8250_rpm_put(up);
1605 * These Exar UARTs have an extra interrupt indicator that could
1606 * fire for a few unimplemented interrupts. One of which is a
1607 * wakeup event when coming out of sleep. Put this here just
1608 * to be on the safe side that these interrupts don't go unhandled.
1610 static int exar_handle_irq(struct uart_port *port)
1612 unsigned char int0, int1, int2, int3;
1613 unsigned int iir = serial_port_in(port, UART_IIR);
1616 ret = serial8250_handle_irq(port, iir);
1618 if ((port->type == PORT_XR17V35X) ||
1619 (port->type == PORT_XR17D15X)) {
1620 int0 = serial_port_in(port, 0x80);
1621 int1 = serial_port_in(port, 0x81);
1622 int2 = serial_port_in(port, 0x82);
1623 int3 = serial_port_in(port, 0x83);
1629 static unsigned int serial8250_tx_empty(struct uart_port *port)
1631 struct uart_8250_port *up = up_to_u8250p(port);
1632 unsigned long flags;
1635 serial8250_rpm_get(up);
1637 spin_lock_irqsave(&port->lock, flags);
1638 lsr = serial_port_in(port, UART_LSR);
1639 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1640 spin_unlock_irqrestore(&port->lock, flags);
1642 serial8250_rpm_put(up);
1644 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1647 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1649 struct uart_8250_port *up = up_to_u8250p(port);
1650 unsigned int status;
1653 serial8250_rpm_get(up);
1654 status = serial8250_modem_status(up);
1655 serial8250_rpm_put(up);
1658 if (status & UART_MSR_DCD)
1660 if (status & UART_MSR_RI)
1662 if (status & UART_MSR_DSR)
1664 if (status & UART_MSR_CTS)
1669 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1671 struct uart_8250_port *up = up_to_u8250p(port);
1672 unsigned char mcr = 0;
1674 if (mctrl & TIOCM_RTS)
1675 mcr |= UART_MCR_RTS;
1676 if (mctrl & TIOCM_DTR)
1677 mcr |= UART_MCR_DTR;
1678 if (mctrl & TIOCM_OUT1)
1679 mcr |= UART_MCR_OUT1;
1680 if (mctrl & TIOCM_OUT2)
1681 mcr |= UART_MCR_OUT2;
1682 if (mctrl & TIOCM_LOOP)
1683 mcr |= UART_MCR_LOOP;
1685 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1687 serial_port_out(port, UART_MCR, mcr);
1689 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1691 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1693 if (port->set_mctrl)
1694 port->set_mctrl(port, mctrl);
1696 serial8250_do_set_mctrl(port, mctrl);
1699 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1701 struct uart_8250_port *up = up_to_u8250p(port);
1702 unsigned long flags;
1704 serial8250_rpm_get(up);
1705 spin_lock_irqsave(&port->lock, flags);
1706 if (break_state == -1)
1707 up->lcr |= UART_LCR_SBC;
1709 up->lcr &= ~UART_LCR_SBC;
1710 serial_port_out(port, UART_LCR, up->lcr);
1711 spin_unlock_irqrestore(&port->lock, flags);
1712 serial8250_rpm_put(up);
1716 * Wait for transmitter & holding register to empty
1718 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1720 unsigned int status, tmout = 10000;
1722 /* Wait up to 10ms for the character(s) to be sent. */
1724 status = serial_in(up, UART_LSR);
1726 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1728 if ((status & bits) == bits)
1735 /* Wait up to 1s for flow control if necessary */
1736 if (up->port.flags & UPF_CONS_FLOW) {
1738 for (tmout = 1000000; tmout; tmout--) {
1739 unsigned int msr = serial_in(up, UART_MSR);
1740 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1741 if (msr & UART_MSR_CTS)
1744 touch_nmi_watchdog();
1749 #ifdef CONFIG_CONSOLE_POLL
1751 * Console polling routines for writing and reading from the uart while
1752 * in an interrupt or debug context.
1755 static int serial8250_get_poll_char(struct uart_port *port)
1757 struct uart_8250_port *up = up_to_u8250p(port);
1761 serial8250_rpm_get(up);
1763 lsr = serial_port_in(port, UART_LSR);
1765 if (!(lsr & UART_LSR_DR)) {
1766 status = NO_POLL_CHAR;
1770 status = serial_port_in(port, UART_RX);
1772 serial8250_rpm_put(up);
1777 static void serial8250_put_poll_char(struct uart_port *port,
1781 struct uart_8250_port *up = up_to_u8250p(port);
1783 serial8250_rpm_get(up);
1785 * First save the IER then disable the interrupts
1787 ier = serial_port_in(port, UART_IER);
1788 if (up->capabilities & UART_CAP_UUE)
1789 serial_port_out(port, UART_IER, UART_IER_UUE);
1791 serial_port_out(port, UART_IER, 0);
1793 wait_for_xmitr(up, BOTH_EMPTY);
1795 * Send the character out.
1797 serial_port_out(port, UART_TX, c);
1800 * Finally, wait for transmitter to become empty
1801 * and restore the IER
1803 wait_for_xmitr(up, BOTH_EMPTY);
1804 serial_port_out(port, UART_IER, ier);
1805 serial8250_rpm_put(up);
1808 #endif /* CONFIG_CONSOLE_POLL */
1810 int serial8250_do_startup(struct uart_port *port)
1812 struct uart_8250_port *up = up_to_u8250p(port);
1813 unsigned long flags;
1814 unsigned char lsr, iir;
1817 if (!port->fifosize)
1818 port->fifosize = uart_config[port->type].fifo_size;
1820 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1821 if (!up->capabilities)
1822 up->capabilities = uart_config[port->type].flags;
1825 if (port->iotype != up->cur_iotype)
1826 set_io_from_upio(port);
1828 serial8250_rpm_get(up);
1829 if (port->type == PORT_16C950) {
1830 /* Wake up and initialize UART */
1832 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1833 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1834 serial_port_out(port, UART_IER, 0);
1835 serial_port_out(port, UART_LCR, 0);
1836 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1837 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1838 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1839 serial_port_out(port, UART_LCR, 0);
1842 #ifdef CONFIG_SERIAL_8250_RSA
1844 * If this is an RSA port, see if we can kick it up to the
1845 * higher speed clock.
1850 if (port->type == PORT_XR17V35X) {
1852 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
1853 * MCR [7:5] and MSR [7:0]
1855 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
1858 * Make sure all interrups are masked until initialization is
1859 * complete and the FIFOs are cleared
1861 serial_port_out(port, UART_IER, 0);
1865 * Clear the FIFO buffers and disable them.
1866 * (they will be reenabled in set_termios())
1868 serial8250_clear_fifos(up);
1871 * Clear the interrupt registers.
1873 serial_port_in(port, UART_LSR);
1874 serial_port_in(port, UART_RX);
1875 serial_port_in(port, UART_IIR);
1876 serial_port_in(port, UART_MSR);
1879 * At this point, there's no way the LSR could still be 0xff;
1880 * if it is, then bail out, because there's likely no UART
1883 if (!(port->flags & UPF_BUGGY_UART) &&
1884 (serial_port_in(port, UART_LSR) == 0xff)) {
1885 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1886 serial_index(port));
1892 * For a XR16C850, we need to set the trigger levels
1894 if (port->type == PORT_16850) {
1897 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1899 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1900 serial_port_out(port, UART_FCTR,
1901 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1902 serial_port_out(port, UART_TRG, UART_TRG_96);
1903 serial_port_out(port, UART_FCTR,
1904 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1905 serial_port_out(port, UART_TRG, UART_TRG_96);
1907 serial_port_out(port, UART_LCR, 0);
1913 if (port->irqflags & IRQF_SHARED)
1914 disable_irq_nosync(port->irq);
1917 * Test for UARTs that do not reassert THRE when the
1918 * transmitter is idle and the interrupt has already
1919 * been cleared. Real 16550s should always reassert
1920 * this interrupt whenever the transmitter is idle and
1921 * the interrupt is enabled. Delays are necessary to
1922 * allow register changes to become visible.
1924 spin_lock_irqsave(&port->lock, flags);
1926 wait_for_xmitr(up, UART_LSR_THRE);
1927 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1928 udelay(1); /* allow THRE to set */
1929 iir1 = serial_port_in(port, UART_IIR);
1930 serial_port_out(port, UART_IER, 0);
1931 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1932 udelay(1); /* allow a working UART time to re-assert THRE */
1933 iir = serial_port_in(port, UART_IIR);
1934 serial_port_out(port, UART_IER, 0);
1936 spin_unlock_irqrestore(&port->lock, flags);
1938 if (port->irqflags & IRQF_SHARED)
1939 enable_irq(port->irq);
1942 * If the interrupt is not reasserted, or we otherwise
1943 * don't trust the iir, setup a timer to kick the UART
1944 * on a regular basis.
1946 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
1947 up->port.flags & UPF_BUG_THRE) {
1948 up->bugs |= UART_BUG_THRE;
1952 retval = up->ops->setup_irq(up);
1957 * Now, initialize the UART
1959 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1961 spin_lock_irqsave(&port->lock, flags);
1962 if (up->port.flags & UPF_FOURPORT) {
1964 up->port.mctrl |= TIOCM_OUT1;
1967 * Most PC uarts need OUT2 raised to enable interrupts.
1970 up->port.mctrl |= TIOCM_OUT2;
1972 serial8250_set_mctrl(port, port->mctrl);
1974 /* Serial over Lan (SoL) hack:
1975 Intel 8257x Gigabit ethernet chips have a
1976 16550 emulation, to be used for Serial Over Lan.
1977 Those chips take a longer time than a normal
1978 serial device to signalize that a transmission
1979 data was queued. Due to that, the above test generally
1980 fails. One solution would be to delay the reading of
1981 iir. However, this is not reliable, since the timeout
1982 is variable. So, let's just don't test if we receive
1983 TX irq. This way, we'll never enable UART_BUG_TXEN.
1985 if (up->port.flags & UPF_NO_TXEN_TEST)
1986 goto dont_test_tx_en;
1989 * Do a quick test to see if we receive an
1990 * interrupt when we enable the TX irq.
1992 serial_port_out(port, UART_IER, UART_IER_THRI);
1993 lsr = serial_port_in(port, UART_LSR);
1994 iir = serial_port_in(port, UART_IIR);
1995 serial_port_out(port, UART_IER, 0);
1997 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1998 if (!(up->bugs & UART_BUG_TXEN)) {
1999 up->bugs |= UART_BUG_TXEN;
2000 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2001 serial_index(port));
2004 up->bugs &= ~UART_BUG_TXEN;
2008 spin_unlock_irqrestore(&port->lock, flags);
2011 * Clear the interrupt registers again for luck, and clear the
2012 * saved flags to avoid getting false values from polling
2013 * routines or the previous session.
2015 serial_port_in(port, UART_LSR);
2016 serial_port_in(port, UART_RX);
2017 serial_port_in(port, UART_IIR);
2018 serial_port_in(port, UART_MSR);
2019 up->lsr_saved_flags = 0;
2020 up->msr_saved_flags = 0;
2023 * Request DMA channels for both RX and TX.
2026 retval = serial8250_request_dma(up);
2028 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2029 serial_index(port));
2035 * Set the IER shadow for rx interrupts but defer actual interrupt
2036 * enable until after the FIFOs are enabled; otherwise, an already-
2037 * active sender can swamp the interrupt handler with "too much work".
2039 up->ier = UART_IER_RLSI | UART_IER_RDI;
2041 if (port->flags & UPF_FOURPORT) {
2044 * Enable interrupts on the AST Fourport board
2046 icp = (port->iobase & 0xfe0) | 0x01f;
2052 serial8250_rpm_put(up);
2055 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2057 static int serial8250_startup(struct uart_port *port)
2060 return port->startup(port);
2061 return serial8250_do_startup(port);
2064 void serial8250_do_shutdown(struct uart_port *port)
2066 struct uart_8250_port *up = up_to_u8250p(port);
2067 unsigned long flags;
2069 serial8250_rpm_get(up);
2071 * Disable interrupts from this port
2074 serial_port_out(port, UART_IER, 0);
2077 serial8250_release_dma(up);
2079 spin_lock_irqsave(&port->lock, flags);
2080 if (port->flags & UPF_FOURPORT) {
2081 /* reset interrupts on the AST Fourport board */
2082 inb((port->iobase & 0xfe0) | 0x1f);
2083 port->mctrl |= TIOCM_OUT1;
2085 port->mctrl &= ~TIOCM_OUT2;
2087 serial8250_set_mctrl(port, port->mctrl);
2088 spin_unlock_irqrestore(&port->lock, flags);
2091 * Disable break condition and FIFOs
2093 serial_port_out(port, UART_LCR,
2094 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2095 serial8250_clear_fifos(up);
2097 #ifdef CONFIG_SERIAL_8250_RSA
2099 * Reset the RSA board back to 115kbps compat mode.
2105 * Read data port to reset things, and then unlink from
2108 serial_port_in(port, UART_RX);
2109 serial8250_rpm_put(up);
2111 up->ops->release_irq(up);
2113 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2115 static void serial8250_shutdown(struct uart_port *port)
2118 port->shutdown(port);
2120 serial8250_do_shutdown(port);
2124 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2125 * Calculate divisor with extra 4-bit fractional portion
2127 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2131 struct uart_port *port = &up->port;
2132 unsigned int quot_16;
2134 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2135 *frac = quot_16 & 0x0f;
2137 return quot_16 >> 4;
2140 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2144 struct uart_port *port = &up->port;
2148 * Handle magic divisors for baud rates above baud_base on
2149 * SMSC SuperIO chips.
2152 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2153 baud == (port->uartclk/4))
2155 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2156 baud == (port->uartclk/8))
2158 else if (up->port.type == PORT_XR17V35X)
2159 quot = xr17v35x_get_divisor(up, baud, frac);
2161 quot = uart_get_divisor(port, baud);
2164 * Oxford Semi 952 rev B workaround
2166 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2172 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2177 switch (c_cflag & CSIZE) {
2179 cval = UART_LCR_WLEN5;
2182 cval = UART_LCR_WLEN6;
2185 cval = UART_LCR_WLEN7;
2189 cval = UART_LCR_WLEN8;
2193 if (c_cflag & CSTOPB)
2194 cval |= UART_LCR_STOP;
2195 if (c_cflag & PARENB) {
2196 cval |= UART_LCR_PARITY;
2197 if (up->bugs & UART_BUG_PARITY)
2198 up->fifo_bug = true;
2200 if (!(c_cflag & PARODD))
2201 cval |= UART_LCR_EPAR;
2203 if (c_cflag & CMSPAR)
2204 cval |= UART_LCR_SPAR;
2210 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2211 unsigned int quot, unsigned int quot_frac)
2213 struct uart_8250_port *up = up_to_u8250p(port);
2215 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2216 if (is_omap1510_8250(up)) {
2217 if (baud == 115200) {
2219 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2221 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2225 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2226 * otherwise just set DLAB
2228 if (up->capabilities & UART_NATSEMI)
2229 serial_port_out(port, UART_LCR, 0xe0);
2231 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2233 serial_dl_write(up, quot);
2235 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2236 if (up->port.type == PORT_XR17V35X) {
2237 /* Preserve bits not related to baudrate; DLD[7:4]. */
2238 quot_frac |= serial_port_in(port, 0x2) & 0xf0;
2239 serial_port_out(port, 0x2, quot_frac);
2244 serial8250_get_baud_rate(struct uart_port *port, struct ktermios *termios,
2245 struct ktermios *old)
2247 unsigned int tolerance = port->uartclk / 100;
2250 * Ask the core to calculate the divisor for us.
2251 * Allow 1% tolerance at the upper limit so uart clks marginally
2252 * slower than nominal still match standard baud rates without
2253 * causing transmission errors.
2255 return uart_get_baud_rate(port, termios, old,
2256 port->uartclk / 16 / 0xffff,
2257 (port->uartclk + tolerance) / 16);
2261 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2262 struct ktermios *old)
2264 struct uart_8250_port *up = up_to_u8250p(port);
2266 unsigned long flags;
2267 unsigned int baud, quot, frac = 0;
2269 cval = serial8250_compute_lcr(up, termios->c_cflag);
2271 baud = serial8250_get_baud_rate(port, termios, old);
2272 quot = serial8250_get_divisor(up, baud, &frac);
2275 * Ok, we're now changing the port state. Do it with
2276 * interrupts disabled.
2278 serial8250_rpm_get(up);
2279 spin_lock_irqsave(&port->lock, flags);
2281 up->lcr = cval; /* Save computed LCR */
2283 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2284 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2285 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2286 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2287 up->fcr |= UART_FCR_TRIGGER_1;
2292 * MCR-based auto flow control. When AFE is enabled, RTS will be
2293 * deasserted when the receive FIFO contains more characters than
2294 * the trigger, or the MCR RTS bit is cleared. In the case where
2295 * the remote UART is not using CTS auto flow control, we must
2296 * have sufficient FIFO entries for the latency of the remote
2297 * UART to respond. IOW, at least 32 bytes of FIFO.
2299 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2300 up->mcr &= ~UART_MCR_AFE;
2301 if (termios->c_cflag & CRTSCTS)
2302 up->mcr |= UART_MCR_AFE;
2306 * Update the per-port timeout.
2308 uart_update_timeout(port, termios->c_cflag, baud);
2310 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2311 if (termios->c_iflag & INPCK)
2312 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2313 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2314 port->read_status_mask |= UART_LSR_BI;
2317 * Characteres to ignore
2319 port->ignore_status_mask = 0;
2320 if (termios->c_iflag & IGNPAR)
2321 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2322 if (termios->c_iflag & IGNBRK) {
2323 port->ignore_status_mask |= UART_LSR_BI;
2325 * If we're ignoring parity and break indicators,
2326 * ignore overruns too (for real raw support).
2328 if (termios->c_iflag & IGNPAR)
2329 port->ignore_status_mask |= UART_LSR_OE;
2333 * ignore all characters if CREAD is not set
2335 if ((termios->c_cflag & CREAD) == 0)
2336 port->ignore_status_mask |= UART_LSR_DR;
2339 * CTS flow control flag and modem status interrupts
2341 up->ier &= ~UART_IER_MSI;
2342 if (!(up->bugs & UART_BUG_NOMSR) &&
2343 UART_ENABLE_MS(&up->port, termios->c_cflag))
2344 up->ier |= UART_IER_MSI;
2345 if (up->capabilities & UART_CAP_UUE)
2346 up->ier |= UART_IER_UUE;
2347 if (up->capabilities & UART_CAP_RTOIE)
2348 up->ier |= UART_IER_RTOIE;
2350 serial_port_out(port, UART_IER, up->ier);
2352 if (up->capabilities & UART_CAP_EFR) {
2353 unsigned char efr = 0;
2355 * TI16C752/Startech hardware flow control. FIXME:
2356 * - TI16C752 requires control thresholds to be set.
2357 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2359 if (termios->c_cflag & CRTSCTS)
2360 efr |= UART_EFR_CTS;
2362 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2363 if (port->flags & UPF_EXAR_EFR)
2364 serial_port_out(port, UART_XR_EFR, efr);
2366 serial_port_out(port, UART_EFR, efr);
2369 serial8250_set_divisor(port, baud, quot, frac);
2372 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2373 * is written without DLAB set, this mode will be disabled.
2375 if (port->type == PORT_16750)
2376 serial_port_out(port, UART_FCR, up->fcr);
2378 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2379 if (port->type != PORT_16750) {
2380 /* emulated UARTs (Lucent Venus 167x) need two steps */
2381 if (up->fcr & UART_FCR_ENABLE_FIFO)
2382 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2383 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2385 serial8250_set_mctrl(port, port->mctrl);
2386 spin_unlock_irqrestore(&port->lock, flags);
2387 serial8250_rpm_put(up);
2389 /* Don't rewrite B0 */
2390 if (tty_termios_baud_rate(termios))
2391 tty_termios_encode_baud_rate(termios, baud, baud);
2393 EXPORT_SYMBOL(serial8250_do_set_termios);
2396 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2397 struct ktermios *old)
2399 if (port->set_termios)
2400 port->set_termios(port, termios, old);
2402 serial8250_do_set_termios(port, termios, old);
2406 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2408 if (termios->c_line == N_PPS) {
2409 port->flags |= UPF_HARDPPS_CD;
2410 spin_lock_irq(&port->lock);
2411 serial8250_enable_ms(port);
2412 spin_unlock_irq(&port->lock);
2414 port->flags &= ~UPF_HARDPPS_CD;
2415 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2416 spin_lock_irq(&port->lock);
2417 serial8250_disable_ms(port);
2418 spin_unlock_irq(&port->lock);
2424 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2425 unsigned int oldstate)
2427 struct uart_8250_port *p = up_to_u8250p(port);
2429 serial8250_set_sleep(p, state != 0);
2431 EXPORT_SYMBOL(serial8250_do_pm);
2434 serial8250_pm(struct uart_port *port, unsigned int state,
2435 unsigned int oldstate)
2438 port->pm(port, state, oldstate);
2440 serial8250_do_pm(port, state, oldstate);
2443 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2445 if (pt->port.mapsize)
2446 return pt->port.mapsize;
2447 if (pt->port.iotype == UPIO_AU) {
2448 if (pt->port.type == PORT_RT2880)
2452 if (is_omap1_8250(pt))
2453 return 0x16 << pt->port.regshift;
2455 return 8 << pt->port.regshift;
2459 * Resource handling.
2461 static int serial8250_request_std_resource(struct uart_8250_port *up)
2463 unsigned int size = serial8250_port_size(up);
2464 struct uart_port *port = &up->port;
2467 switch (port->iotype) {
2476 if (!request_mem_region(port->mapbase, size, "serial")) {
2481 if (port->flags & UPF_IOREMAP) {
2482 port->membase = ioremap_nocache(port->mapbase, size);
2483 if (!port->membase) {
2484 release_mem_region(port->mapbase, size);
2492 if (!request_region(port->iobase, size, "serial"))
2499 static void serial8250_release_std_resource(struct uart_8250_port *up)
2501 unsigned int size = serial8250_port_size(up);
2502 struct uart_port *port = &up->port;
2504 switch (port->iotype) {
2513 if (port->flags & UPF_IOREMAP) {
2514 iounmap(port->membase);
2515 port->membase = NULL;
2518 release_mem_region(port->mapbase, size);
2523 release_region(port->iobase, size);
2528 static void serial8250_release_port(struct uart_port *port)
2530 struct uart_8250_port *up = up_to_u8250p(port);
2532 serial8250_release_std_resource(up);
2535 static int serial8250_request_port(struct uart_port *port)
2537 struct uart_8250_port *up = up_to_u8250p(port);
2539 return serial8250_request_std_resource(up);
2542 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2544 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2545 unsigned char bytes;
2547 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2549 return bytes ? bytes : -EOPNOTSUPP;
2552 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2554 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2557 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2560 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2561 if (bytes < conf_type->rxtrig_bytes[i])
2562 /* Use the nearest lower value */
2563 return (--i) << UART_FCR_R_TRIG_SHIFT;
2566 return UART_FCR_R_TRIG_11;
2569 static int do_get_rxtrig(struct tty_port *port)
2571 struct uart_state *state = container_of(port, struct uart_state, port);
2572 struct uart_port *uport = state->uart_port;
2573 struct uart_8250_port *up =
2574 container_of(uport, struct uart_8250_port, port);
2576 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2579 return fcr_get_rxtrig_bytes(up);
2582 static int do_serial8250_get_rxtrig(struct tty_port *port)
2586 mutex_lock(&port->mutex);
2587 rxtrig_bytes = do_get_rxtrig(port);
2588 mutex_unlock(&port->mutex);
2590 return rxtrig_bytes;
2593 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2594 struct device_attribute *attr, char *buf)
2596 struct tty_port *port = dev_get_drvdata(dev);
2599 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2600 if (rxtrig_bytes < 0)
2601 return rxtrig_bytes;
2603 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2606 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2608 struct uart_state *state = container_of(port, struct uart_state, port);
2609 struct uart_port *uport = state->uart_port;
2610 struct uart_8250_port *up =
2611 container_of(uport, struct uart_8250_port, port);
2614 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2618 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2622 serial8250_clear_fifos(up);
2623 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2624 up->fcr |= (unsigned char)rxtrig;
2625 serial_out(up, UART_FCR, up->fcr);
2629 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2633 mutex_lock(&port->mutex);
2634 ret = do_set_rxtrig(port, bytes);
2635 mutex_unlock(&port->mutex);
2640 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2641 struct device_attribute *attr, const char *buf, size_t count)
2643 struct tty_port *port = dev_get_drvdata(dev);
2644 unsigned char bytes;
2650 ret = kstrtou8(buf, 10, &bytes);
2654 ret = do_serial8250_set_rxtrig(port, bytes);
2661 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2662 serial8250_get_attr_rx_trig_bytes,
2663 serial8250_set_attr_rx_trig_bytes);
2665 static struct attribute *serial8250_dev_attrs[] = {
2666 &dev_attr_rx_trig_bytes.attr,
2670 static struct attribute_group serial8250_dev_attr_group = {
2671 .attrs = serial8250_dev_attrs,
2674 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2676 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2678 if (conf_type->rxtrig_bytes[0])
2679 up->port.attr_group = &serial8250_dev_attr_group;
2682 static void serial8250_config_port(struct uart_port *port, int flags)
2684 struct uart_8250_port *up = up_to_u8250p(port);
2688 * Find the region that we can probe for. This in turn
2689 * tells us whether we can probe for the type of port.
2691 ret = serial8250_request_std_resource(up);
2695 if (port->iotype != up->cur_iotype)
2696 set_io_from_upio(port);
2698 if (flags & UART_CONFIG_TYPE)
2701 /* if access method is AU, it is a 16550 with a quirk */
2702 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2703 up->bugs |= UART_BUG_NOMSR;
2705 /* HW bugs may trigger IRQ while IIR == NO_INT */
2706 if (port->type == PORT_TEGRA)
2707 up->bugs |= UART_BUG_NOMSR;
2709 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2712 if (port->type == PORT_UNKNOWN)
2713 serial8250_release_std_resource(up);
2715 /* Fixme: probably not the best place for this */
2716 if ((port->type == PORT_XR17V35X) ||
2717 (port->type == PORT_XR17D15X))
2718 port->handle_irq = exar_handle_irq;
2720 register_dev_spec_attr_grp(up);
2721 up->fcr = uart_config[up->port.type].fcr;
2725 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2727 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2728 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2729 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2730 ser->type == PORT_STARTECH)
2736 serial8250_type(struct uart_port *port)
2738 int type = port->type;
2740 if (type >= ARRAY_SIZE(uart_config))
2742 return uart_config[type].name;
2745 static const struct uart_ops serial8250_pops = {
2746 .tx_empty = serial8250_tx_empty,
2747 .set_mctrl = serial8250_set_mctrl,
2748 .get_mctrl = serial8250_get_mctrl,
2749 .stop_tx = serial8250_stop_tx,
2750 .start_tx = serial8250_start_tx,
2751 .throttle = serial8250_throttle,
2752 .unthrottle = serial8250_unthrottle,
2753 .stop_rx = serial8250_stop_rx,
2754 .enable_ms = serial8250_enable_ms,
2755 .break_ctl = serial8250_break_ctl,
2756 .startup = serial8250_startup,
2757 .shutdown = serial8250_shutdown,
2758 .set_termios = serial8250_set_termios,
2759 .set_ldisc = serial8250_set_ldisc,
2760 .pm = serial8250_pm,
2761 .type = serial8250_type,
2762 .release_port = serial8250_release_port,
2763 .request_port = serial8250_request_port,
2764 .config_port = serial8250_config_port,
2765 .verify_port = serial8250_verify_port,
2766 #ifdef CONFIG_CONSOLE_POLL
2767 .poll_get_char = serial8250_get_poll_char,
2768 .poll_put_char = serial8250_put_poll_char,
2772 void serial8250_init_port(struct uart_8250_port *up)
2774 struct uart_port *port = &up->port;
2776 spin_lock_init(&port->lock);
2777 port->ops = &serial8250_pops;
2779 up->cur_iotype = 0xFF;
2781 EXPORT_SYMBOL_GPL(serial8250_init_port);
2783 void serial8250_set_defaults(struct uart_8250_port *up)
2785 struct uart_port *port = &up->port;
2787 if (up->port.flags & UPF_FIXED_TYPE) {
2788 unsigned int type = up->port.type;
2790 if (!up->port.fifosize)
2791 up->port.fifosize = uart_config[type].fifo_size;
2793 up->tx_loadsz = uart_config[type].tx_loadsz;
2794 if (!up->capabilities)
2795 up->capabilities = uart_config[type].flags;
2798 set_io_from_upio(port);
2800 /* default dma handlers */
2802 if (!up->dma->tx_dma)
2803 up->dma->tx_dma = serial8250_tx_dma;
2804 if (!up->dma->rx_dma)
2805 up->dma->rx_dma = serial8250_rx_dma;
2808 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
2810 #ifdef CONFIG_SERIAL_8250_CONSOLE
2812 static void serial8250_console_putchar(struct uart_port *port, int ch)
2814 struct uart_8250_port *up = up_to_u8250p(port);
2816 wait_for_xmitr(up, UART_LSR_THRE);
2817 serial_port_out(port, UART_TX, ch);
2821 * Restore serial console when h/w power-off detected
2823 static void serial8250_console_restore(struct uart_8250_port *up)
2825 struct uart_port *port = &up->port;
2826 struct ktermios termios;
2827 unsigned int baud, quot, frac = 0;
2829 termios.c_cflag = port->cons->cflag;
2830 if (port->state->port.tty && termios.c_cflag == 0)
2831 termios.c_cflag = port->state->port.tty->termios.c_cflag;
2833 baud = serial8250_get_baud_rate(port, &termios, NULL);
2834 quot = serial8250_get_divisor(up, baud, &frac);
2836 serial8250_set_divisor(port, baud, quot, frac);
2837 serial_port_out(port, UART_LCR, up->lcr);
2838 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
2842 * Print a string to the serial port trying not to disturb
2843 * any possible real use of the port...
2845 * The console_lock must be held when we get here.
2847 void serial8250_console_write(struct uart_8250_port *up, const char *s,
2850 struct uart_port *port = &up->port;
2851 unsigned long flags;
2855 touch_nmi_watchdog();
2857 serial8250_rpm_get(up);
2861 else if (oops_in_progress)
2862 locked = spin_trylock_irqsave(&port->lock, flags);
2864 spin_lock_irqsave(&port->lock, flags);
2867 * First save the IER then disable the interrupts
2869 ier = serial_port_in(port, UART_IER);
2871 if (up->capabilities & UART_CAP_UUE)
2872 serial_port_out(port, UART_IER, UART_IER_UUE);
2874 serial_port_out(port, UART_IER, 0);
2876 /* check scratch reg to see if port powered off during system sleep */
2877 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
2878 serial8250_console_restore(up);
2882 uart_console_write(port, s, count, serial8250_console_putchar);
2885 * Finally, wait for transmitter to become empty
2886 * and restore the IER
2888 wait_for_xmitr(up, BOTH_EMPTY);
2889 serial_port_out(port, UART_IER, ier);
2892 * The receive handling will happen properly because the
2893 * receive ready bit will still be set; it is not cleared
2894 * on read. However, modem control will not, we must
2895 * call it if we have saved something in the saved flags
2896 * while processing with interrupts off.
2898 if (up->msr_saved_flags)
2899 serial8250_modem_status(up);
2902 spin_unlock_irqrestore(&port->lock, flags);
2903 serial8250_rpm_put(up);
2906 static unsigned int probe_baud(struct uart_port *port)
2908 unsigned char lcr, dll, dlm;
2911 lcr = serial_port_in(port, UART_LCR);
2912 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
2913 dll = serial_port_in(port, UART_DLL);
2914 dlm = serial_port_in(port, UART_DLM);
2915 serial_port_out(port, UART_LCR, lcr);
2917 quot = (dlm << 8) | dll;
2918 return (port->uartclk / 16) / quot;
2921 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
2928 if (!port->iobase && !port->membase)
2932 uart_parse_options(options, &baud, &parity, &bits, &flow);
2934 baud = probe_baud(port);
2936 return uart_set_options(port, port->cons, baud, parity, bits, flow);
2939 #endif /* CONFIG_SERIAL_8250_CONSOLE */
2941 MODULE_LICENSE("GPL");