2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/irq.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/serial_8250.h>
36 #include <linux/nmi.h>
37 #include <linux/mutex.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/ktime.h>
49 * These are definitions for the Exar XR17V35X and XR17(C|D)15X
51 #define UART_EXAR_INT0 0x80
52 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
53 #define UART_EXAR_DVID 0x8d /* Device identification */
55 /* Nuvoton NPCM timeout register */
56 #define UART_NPCM_TOR 7
57 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
63 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
65 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
68 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
71 * Here we define the default xmit fifo size used for each type of UART.
73 static const struct serial8250_config uart_config[] = {
98 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
99 .rxtrig_bytes = {1, 4, 8, 14},
100 .flags = UART_CAP_FIFO,
111 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
117 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
119 .rxtrig_bytes = {8, 16, 24, 28},
120 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
126 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
128 .rxtrig_bytes = {1, 16, 32, 56},
129 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
137 .name = "16C950/954",
140 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
141 .rxtrig_bytes = {16, 32, 112, 120},
142 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
143 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
149 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
151 .rxtrig_bytes = {8, 16, 56, 60},
152 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
158 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
159 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
165 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
166 .flags = UART_CAP_FIFO,
172 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
173 .flags = UART_CAP_FIFO | UART_NATSEMI,
179 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
180 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
186 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
187 .flags = UART_CAP_FIFO,
193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
194 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
201 .flags = UART_CAP_FIFO | UART_CAP_AFE,
207 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
209 .rxtrig_bytes = {1, 4, 8, 14},
210 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
216 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
217 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
224 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
226 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
233 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
234 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
235 .flags = UART_CAP_FIFO,
237 [PORT_BRCM_TRUMANAGE] = {
241 .flags = UART_CAP_HFIFO,
246 [PORT_ALTR_16550_F32] = {
247 .name = "Altera 16550 FIFO32",
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 [PORT_ALTR_16550_F64] = {
254 .name = "Altera 16550 FIFO64",
257 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
258 .flags = UART_CAP_FIFO | UART_CAP_AFE,
260 [PORT_ALTR_16550_F128] = {
261 .name = "Altera 16550 FIFO128",
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
265 .flags = UART_CAP_FIFO | UART_CAP_AFE,
268 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
269 * workaround of errata A-008006 which states that tx_loadsz should
270 * be configured less than Maximum supported fifo bytes.
272 [PORT_16550A_FSL64] = {
273 .name = "16550A_FSL64",
276 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
278 .flags = UART_CAP_FIFO,
281 .name = "Palmchip BK-3103",
284 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
285 .rxtrig_bytes = {1, 4, 8, 14},
286 .flags = UART_CAP_FIFO,
289 .name = "TI DA8xx/66AK2x",
292 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
294 .rxtrig_bytes = {1, 4, 8, 14},
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
298 .name = "MediaTek BTIF",
301 .fcr = UART_FCR_ENABLE_FIFO |
302 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
303 .flags = UART_CAP_FIFO,
306 .name = "Nuvoton 16550",
309 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
310 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
311 .rxtrig_bytes = {1, 4, 8, 14},
312 .flags = UART_CAP_FIFO,
316 /* Uart divisor latch read */
317 static int default_serial_dl_read(struct uart_8250_port *up)
319 /* Assign these in pieces to truncate any bits above 7. */
320 unsigned char dll = serial_in(up, UART_DLL);
321 unsigned char dlm = serial_in(up, UART_DLM);
323 return dll | dlm << 8;
326 /* Uart divisor latch write */
327 static void default_serial_dl_write(struct uart_8250_port *up, int value)
329 serial_out(up, UART_DLL, value & 0xff);
330 serial_out(up, UART_DLM, value >> 8 & 0xff);
333 #ifdef CONFIG_SERIAL_8250_RT288X
335 /* Au1x00/RT288x UART hardware has a weird register layout */
336 static const s8 au_io_in_map[8] = {
344 -1, /* UART_SCR (unmapped) */
347 static const s8 au_io_out_map[8] = {
353 -1, /* UART_LSR (unmapped) */
354 -1, /* UART_MSR (unmapped) */
355 -1, /* UART_SCR (unmapped) */
358 unsigned int au_serial_in(struct uart_port *p, int offset)
360 if (offset >= ARRAY_SIZE(au_io_in_map))
362 offset = au_io_in_map[offset];
365 return __raw_readl(p->membase + (offset << p->regshift));
368 void au_serial_out(struct uart_port *p, int offset, int value)
370 if (offset >= ARRAY_SIZE(au_io_out_map))
372 offset = au_io_out_map[offset];
375 __raw_writel(value, p->membase + (offset << p->regshift));
378 /* Au1x00 haven't got a standard divisor latch */
379 static int au_serial_dl_read(struct uart_8250_port *up)
381 return __raw_readl(up->port.membase + 0x28);
384 static void au_serial_dl_write(struct uart_8250_port *up, int value)
386 __raw_writel(value, up->port.membase + 0x28);
391 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
393 offset = offset << p->regshift;
394 outb(p->hub6 - 1 + offset, p->iobase);
395 return inb(p->iobase + 1);
398 static void hub6_serial_out(struct uart_port *p, int offset, int value)
400 offset = offset << p->regshift;
401 outb(p->hub6 - 1 + offset, p->iobase);
402 outb(value, p->iobase + 1);
405 static unsigned int mem_serial_in(struct uart_port *p, int offset)
407 offset = offset << p->regshift;
408 return readb(p->membase + offset);
411 static void mem_serial_out(struct uart_port *p, int offset, int value)
413 offset = offset << p->regshift;
414 writeb(value, p->membase + offset);
417 static void mem16_serial_out(struct uart_port *p, int offset, int value)
419 offset = offset << p->regshift;
420 writew(value, p->membase + offset);
423 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
425 offset = offset << p->regshift;
426 return readw(p->membase + offset);
429 static void mem32_serial_out(struct uart_port *p, int offset, int value)
431 offset = offset << p->regshift;
432 writel(value, p->membase + offset);
435 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
437 offset = offset << p->regshift;
438 return readl(p->membase + offset);
441 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
443 offset = offset << p->regshift;
444 iowrite32be(value, p->membase + offset);
447 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
449 offset = offset << p->regshift;
450 return ioread32be(p->membase + offset);
453 static unsigned int io_serial_in(struct uart_port *p, int offset)
455 offset = offset << p->regshift;
456 return inb(p->iobase + offset);
459 static void io_serial_out(struct uart_port *p, int offset, int value)
461 offset = offset << p->regshift;
462 outb(value, p->iobase + offset);
465 static int serial8250_default_handle_irq(struct uart_port *port);
467 static void set_io_from_upio(struct uart_port *p)
469 struct uart_8250_port *up = up_to_u8250p(p);
471 up->dl_read = default_serial_dl_read;
472 up->dl_write = default_serial_dl_write;
476 p->serial_in = hub6_serial_in;
477 p->serial_out = hub6_serial_out;
481 p->serial_in = mem_serial_in;
482 p->serial_out = mem_serial_out;
486 p->serial_in = mem16_serial_in;
487 p->serial_out = mem16_serial_out;
491 p->serial_in = mem32_serial_in;
492 p->serial_out = mem32_serial_out;
496 p->serial_in = mem32be_serial_in;
497 p->serial_out = mem32be_serial_out;
500 #ifdef CONFIG_SERIAL_8250_RT288X
502 p->serial_in = au_serial_in;
503 p->serial_out = au_serial_out;
504 up->dl_read = au_serial_dl_read;
505 up->dl_write = au_serial_dl_write;
510 p->serial_in = io_serial_in;
511 p->serial_out = io_serial_out;
514 /* Remember loaded iotype */
515 up->cur_iotype = p->iotype;
516 p->handle_irq = serial8250_default_handle_irq;
520 serial_port_out_sync(struct uart_port *p, int offset, int value)
528 p->serial_out(p, offset, value);
529 p->serial_in(p, UART_LCR); /* safe, no side-effects */
532 p->serial_out(p, offset, value);
539 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
541 serial_out(up, UART_SCR, offset);
542 serial_out(up, UART_ICR, value);
545 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
549 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
550 serial_out(up, UART_SCR, offset);
551 value = serial_in(up, UART_ICR);
552 serial_icr_write(up, UART_ACR, up->acr);
560 static void serial8250_clear_fifos(struct uart_8250_port *p)
562 if (p->capabilities & UART_CAP_FIFO) {
563 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
564 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
565 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
566 serial_out(p, UART_FCR, 0);
570 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
572 unsigned char mcr = serial8250_in_MCR(p);
574 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
577 mcr &= ~UART_MCR_RTS;
578 serial8250_out_MCR(p, mcr);
581 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
582 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
584 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
586 serial8250_clear_fifos(p);
587 serial_out(p, UART_FCR, p->fcr);
589 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
591 void serial8250_rpm_get(struct uart_8250_port *p)
593 if (!(p->capabilities & UART_CAP_RPM))
595 pm_runtime_get_sync(p->port.dev);
597 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
599 void serial8250_rpm_put(struct uart_8250_port *p)
601 if (!(p->capabilities & UART_CAP_RPM))
603 pm_runtime_mark_last_busy(p->port.dev);
604 pm_runtime_put_autosuspend(p->port.dev);
606 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
609 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
610 * @p: uart_8250_port port instance
612 * The function is used to start rs485 software emulating on the
613 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
614 * transmission. The function is idempotent, so it is safe to call it
617 * The caller MUST enable interrupt on empty shift register before
618 * calling serial8250_em485_init(). This interrupt is not a part of
619 * 8250 standard, but implementation defined.
621 * The function is supposed to be called from .rs485_config callback
622 * or from any other callback protected with p->port.lock spinlock.
624 * See also serial8250_em485_destroy()
626 * Return 0 - success, -errno - otherwise
628 int serial8250_em485_init(struct uart_8250_port *p)
633 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
637 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
639 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
641 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
642 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
644 p->em485->active_timer = NULL;
645 serial8250_em485_rts_after_send(p);
649 EXPORT_SYMBOL_GPL(serial8250_em485_init);
652 * serial8250_em485_destroy() - put uart_8250_port into normal state
653 * @p: uart_8250_port port instance
655 * The function is used to stop rs485 software emulating on the
656 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
657 * call it multiple times.
659 * The function is supposed to be called from .rs485_config callback
660 * or from any other callback protected with p->port.lock spinlock.
662 * See also serial8250_em485_init()
664 void serial8250_em485_destroy(struct uart_8250_port *p)
669 hrtimer_cancel(&p->em485->start_tx_timer);
670 hrtimer_cancel(&p->em485->stop_tx_timer);
675 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
678 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
679 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
680 * empty and the HW can idle again.
682 void serial8250_rpm_get_tx(struct uart_8250_port *p)
684 unsigned char rpm_active;
686 if (!(p->capabilities & UART_CAP_RPM))
689 rpm_active = xchg(&p->rpm_tx_active, 1);
692 pm_runtime_get_sync(p->port.dev);
694 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
696 void serial8250_rpm_put_tx(struct uart_8250_port *p)
698 unsigned char rpm_active;
700 if (!(p->capabilities & UART_CAP_RPM))
703 rpm_active = xchg(&p->rpm_tx_active, 0);
706 pm_runtime_mark_last_busy(p->port.dev);
707 pm_runtime_put_autosuspend(p->port.dev);
709 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
712 * IER sleep support. UARTs which have EFRs need the "extended
713 * capability" bit enabled. Note that on XR16C850s, we need to
714 * reset LCR to write to IER.
716 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
718 unsigned char lcr = 0, efr = 0;
720 * Exar UARTs have a SLEEP register that enables or disables
721 * each UART to enter sleep mode separately. On the XR17V35x the
722 * register is accessible to each UART at the UART_EXAR_SLEEP
723 * offset but the UART channel may only write to the corresponding
726 serial8250_rpm_get(p);
727 if ((p->port.type == PORT_XR17V35X) ||
728 (p->port.type == PORT_XR17D15X)) {
729 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
733 if (p->capabilities & UART_CAP_SLEEP) {
734 if (p->capabilities & UART_CAP_EFR) {
735 lcr = serial_in(p, UART_LCR);
736 efr = serial_in(p, UART_EFR);
737 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
738 serial_out(p, UART_EFR, UART_EFR_ECB);
739 serial_out(p, UART_LCR, 0);
741 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
742 if (p->capabilities & UART_CAP_EFR) {
743 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
744 serial_out(p, UART_EFR, efr);
745 serial_out(p, UART_LCR, lcr);
749 serial8250_rpm_put(p);
752 #ifdef CONFIG_SERIAL_8250_RSA
754 * Attempts to turn on the RSA FIFO. Returns zero on failure.
755 * We set the port uart clock rate if we succeed.
757 static int __enable_rsa(struct uart_8250_port *up)
762 mode = serial_in(up, UART_RSA_MSR);
763 result = mode & UART_RSA_MSR_FIFO;
766 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
767 mode = serial_in(up, UART_RSA_MSR);
768 result = mode & UART_RSA_MSR_FIFO;
772 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
777 static void enable_rsa(struct uart_8250_port *up)
779 if (up->port.type == PORT_RSA) {
780 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
781 spin_lock_irq(&up->port.lock);
783 spin_unlock_irq(&up->port.lock);
785 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
786 serial_out(up, UART_RSA_FRR, 0);
791 * Attempts to turn off the RSA FIFO. Returns zero on failure.
792 * It is unknown why interrupts were disabled in here. However,
793 * the caller is expected to preserve this behaviour by grabbing
794 * the spinlock before calling this function.
796 static void disable_rsa(struct uart_8250_port *up)
801 if (up->port.type == PORT_RSA &&
802 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
803 spin_lock_irq(&up->port.lock);
805 mode = serial_in(up, UART_RSA_MSR);
806 result = !(mode & UART_RSA_MSR_FIFO);
809 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
810 mode = serial_in(up, UART_RSA_MSR);
811 result = !(mode & UART_RSA_MSR_FIFO);
815 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
816 spin_unlock_irq(&up->port.lock);
819 #endif /* CONFIG_SERIAL_8250_RSA */
822 * This is a quickie test to see how big the FIFO is.
823 * It doesn't work at all the time, more's the pity.
825 static int size_fifo(struct uart_8250_port *up)
827 unsigned char old_fcr, old_mcr, old_lcr;
828 unsigned short old_dl;
831 old_lcr = serial_in(up, UART_LCR);
832 serial_out(up, UART_LCR, 0);
833 old_fcr = serial_in(up, UART_FCR);
834 old_mcr = serial8250_in_MCR(up);
835 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
836 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
837 serial8250_out_MCR(up, UART_MCR_LOOP);
838 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
839 old_dl = serial_dl_read(up);
840 serial_dl_write(up, 0x0001);
841 serial_out(up, UART_LCR, 0x03);
842 for (count = 0; count < 256; count++)
843 serial_out(up, UART_TX, count);
844 mdelay(20);/* FIXME - schedule_timeout */
845 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
846 (count < 256); count++)
847 serial_in(up, UART_RX);
848 serial_out(up, UART_FCR, old_fcr);
849 serial8250_out_MCR(up, old_mcr);
850 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
851 serial_dl_write(up, old_dl);
852 serial_out(up, UART_LCR, old_lcr);
858 * Read UART ID using the divisor method - set DLL and DLM to zero
859 * and the revision will be in DLL and device type in DLM. We
860 * preserve the device state across this.
862 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
864 unsigned char old_lcr;
865 unsigned int id, old_dl;
867 old_lcr = serial_in(p, UART_LCR);
868 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
869 old_dl = serial_dl_read(p);
870 serial_dl_write(p, 0);
871 id = serial_dl_read(p);
872 serial_dl_write(p, old_dl);
874 serial_out(p, UART_LCR, old_lcr);
880 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
881 * When this function is called we know it is at least a StarTech
882 * 16650 V2, but it might be one of several StarTech UARTs, or one of
883 * its clones. (We treat the broken original StarTech 16650 V1 as a
884 * 16550, and why not? Startech doesn't seem to even acknowledge its
887 * What evil have men's minds wrought...
889 static void autoconfig_has_efr(struct uart_8250_port *up)
891 unsigned int id1, id2, id3, rev;
894 * Everything with an EFR has SLEEP
896 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
899 * First we check to see if it's an Oxford Semiconductor UART.
901 * If we have to do this here because some non-National
902 * Semiconductor clone chips lock up if you try writing to the
903 * LSR register (which serial_icr_read does)
907 * Check for Oxford Semiconductor 16C950.
909 * EFR [4] must be set else this test fails.
911 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
912 * claims that it's needed for 952 dual UART's (which are not
913 * recommended for new designs).
916 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
917 serial_out(up, UART_EFR, UART_EFR_ECB);
918 serial_out(up, UART_LCR, 0x00);
919 id1 = serial_icr_read(up, UART_ID1);
920 id2 = serial_icr_read(up, UART_ID2);
921 id3 = serial_icr_read(up, UART_ID3);
922 rev = serial_icr_read(up, UART_REV);
924 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
926 if (id1 == 0x16 && id2 == 0xC9 &&
927 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
928 up->port.type = PORT_16C950;
931 * Enable work around for the Oxford Semiconductor 952 rev B
932 * chip which causes it to seriously miscalculate baud rates
935 if (id3 == 0x52 && rev == 0x01)
936 up->bugs |= UART_BUG_QUOT;
941 * We check for a XR16C850 by setting DLL and DLM to 0, and then
942 * reading back DLL and DLM. The chip type depends on the DLM
944 * 0x10 - XR16C850 and the DLL contains the chip revision.
948 id1 = autoconfig_read_divisor_id(up);
949 DEBUG_AUTOCONF("850id=%04x ", id1);
952 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
953 up->port.type = PORT_16850;
958 * It wasn't an XR16C850.
960 * We distinguish between the '654 and the '650 by counting
961 * how many bytes are in the FIFO. I'm using this for now,
962 * since that's the technique that was sent to me in the
963 * serial driver update, but I'm not convinced this works.
964 * I've had problems doing this in the past. -TYT
966 if (size_fifo(up) == 64)
967 up->port.type = PORT_16654;
969 up->port.type = PORT_16650V2;
973 * We detected a chip without a FIFO. Only two fall into
974 * this category - the original 8250 and the 16450. The
975 * 16450 has a scratch register (accessible with LCR=0)
977 static void autoconfig_8250(struct uart_8250_port *up)
979 unsigned char scratch, status1, status2;
981 up->port.type = PORT_8250;
983 scratch = serial_in(up, UART_SCR);
984 serial_out(up, UART_SCR, 0xa5);
985 status1 = serial_in(up, UART_SCR);
986 serial_out(up, UART_SCR, 0x5a);
987 status2 = serial_in(up, UART_SCR);
988 serial_out(up, UART_SCR, scratch);
990 if (status1 == 0xa5 && status2 == 0x5a)
991 up->port.type = PORT_16450;
994 static int broken_efr(struct uart_8250_port *up)
997 * Exar ST16C2550 "A2" devices incorrectly detect as
998 * having an EFR, and report an ID of 0x0201. See
999 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1001 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1008 * We know that the chip has FIFOs. Does it have an EFR? The
1009 * EFR is located in the same register position as the IIR and
1010 * we know the top two bits of the IIR are currently set. The
1011 * EFR should contain zero. Try to read the EFR.
1013 static void autoconfig_16550a(struct uart_8250_port *up)
1015 unsigned char status1, status2;
1016 unsigned int iersave;
1018 up->port.type = PORT_16550A;
1019 up->capabilities |= UART_CAP_FIFO;
1022 * XR17V35x UARTs have an extra divisor register, DLD
1023 * that gets enabled with when DLAB is set which will
1024 * cause the device to incorrectly match and assign
1025 * port type to PORT_16650. The EFR for this UART is
1026 * found at offset 0x09. Instead check the Deice ID (DVID)
1027 * register for a 2, 4 or 8 port UART.
1029 if (up->port.flags & UPF_EXAR_EFR) {
1030 status1 = serial_in(up, UART_EXAR_DVID);
1031 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
1032 DEBUG_AUTOCONF("Exar XR17V35x ");
1033 up->port.type = PORT_XR17V35X;
1034 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1043 * Check for presence of the EFR when DLAB is set.
1044 * Only ST16C650V1 UARTs pass this test.
1046 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1047 if (serial_in(up, UART_EFR) == 0) {
1048 serial_out(up, UART_EFR, 0xA8);
1049 if (serial_in(up, UART_EFR) != 0) {
1050 DEBUG_AUTOCONF("EFRv1 ");
1051 up->port.type = PORT_16650;
1052 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1054 serial_out(up, UART_LCR, 0);
1055 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1057 status1 = serial_in(up, UART_IIR) >> 5;
1058 serial_out(up, UART_FCR, 0);
1059 serial_out(up, UART_LCR, 0);
1062 up->port.type = PORT_16550A_FSL64;
1064 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1066 serial_out(up, UART_EFR, 0);
1071 * Maybe it requires 0xbf to be written to the LCR.
1072 * (other ST16C650V2 UARTs, TI16C752A, etc)
1074 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1075 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1076 DEBUG_AUTOCONF("EFRv2 ");
1077 autoconfig_has_efr(up);
1082 * Check for a National Semiconductor SuperIO chip.
1083 * Attempt to switch to bank 2, read the value of the LOOP bit
1084 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1085 * switch back to bank 2, read it from EXCR1 again and check
1086 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1088 serial_out(up, UART_LCR, 0);
1089 status1 = serial8250_in_MCR(up);
1090 serial_out(up, UART_LCR, 0xE0);
1091 status2 = serial_in(up, 0x02); /* EXCR1 */
1093 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1094 serial_out(up, UART_LCR, 0);
1095 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1096 serial_out(up, UART_LCR, 0xE0);
1097 status2 = serial_in(up, 0x02); /* EXCR1 */
1098 serial_out(up, UART_LCR, 0);
1099 serial8250_out_MCR(up, status1);
1101 if ((status2 ^ status1) & UART_MCR_LOOP) {
1102 unsigned short quot;
1104 serial_out(up, UART_LCR, 0xE0);
1106 quot = serial_dl_read(up);
1109 if (ns16550a_goto_highspeed(up))
1110 serial_dl_write(up, quot);
1112 serial_out(up, UART_LCR, 0);
1114 up->port.uartclk = 921600*16;
1115 up->port.type = PORT_NS16550A;
1116 up->capabilities |= UART_NATSEMI;
1122 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1123 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1124 * Try setting it with and without DLAB set. Cheap clones
1125 * set bit 5 without DLAB set.
1127 serial_out(up, UART_LCR, 0);
1128 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1129 status1 = serial_in(up, UART_IIR) >> 5;
1130 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1131 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1132 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1133 status2 = serial_in(up, UART_IIR) >> 5;
1134 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1135 serial_out(up, UART_LCR, 0);
1137 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1139 if (status1 == 6 && status2 == 7) {
1140 up->port.type = PORT_16750;
1141 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1146 * Try writing and reading the UART_IER_UUE bit (b6).
1147 * If it works, this is probably one of the Xscale platform's
1149 * We're going to explicitly set the UUE bit to 0 before
1150 * trying to write and read a 1 just to make sure it's not
1151 * already a 1 and maybe locked there before we even start start.
1153 iersave = serial_in(up, UART_IER);
1154 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1155 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1157 * OK it's in a known zero state, try writing and reading
1158 * without disturbing the current state of the other bits.
1160 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1161 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1164 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1166 DEBUG_AUTOCONF("Xscale ");
1167 up->port.type = PORT_XSCALE;
1168 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1173 * If we got here we couldn't force the IER_UUE bit to 0.
1174 * Log it and continue.
1176 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1178 serial_out(up, UART_IER, iersave);
1181 * Exar uarts have EFR in a weird location
1183 if (up->port.flags & UPF_EXAR_EFR) {
1184 DEBUG_AUTOCONF("Exar XR17D15x ");
1185 up->port.type = PORT_XR17D15X;
1186 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1193 * We distinguish between 16550A and U6 16550A by counting
1194 * how many bytes are in the FIFO.
1196 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1197 up->port.type = PORT_U6_16550A;
1198 up->capabilities |= UART_CAP_AFE;
1203 * This routine is called by rs_init() to initialize a specific serial
1204 * port. It determines what type of UART chip this serial port is
1205 * using: 8250, 16450, 16550, 16550A. The important question is
1206 * whether or not this UART is a 16550A or not, since this will
1207 * determine whether or not we can use its FIFO features or not.
1209 static void autoconfig(struct uart_8250_port *up)
1211 unsigned char status1, scratch, scratch2, scratch3;
1212 unsigned char save_lcr, save_mcr;
1213 struct uart_port *port = &up->port;
1214 unsigned long flags;
1215 unsigned int old_capabilities;
1217 if (!port->iobase && !port->mapbase && !port->membase)
1220 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1221 serial_index(port), port->iobase, port->membase);
1224 * We really do need global IRQs disabled here - we're going to
1225 * be frobbing the chips IRQ enable register to see if it exists.
1227 spin_lock_irqsave(&port->lock, flags);
1229 up->capabilities = 0;
1232 if (!(port->flags & UPF_BUGGY_UART)) {
1234 * Do a simple existence test first; if we fail this,
1235 * there's no point trying anything else.
1237 * 0x80 is used as a nonsense port to prevent against
1238 * false positives due to ISA bus float. The
1239 * assumption is that 0x80 is a non-existent port;
1240 * which should be safe since include/asm/io.h also
1241 * makes this assumption.
1243 * Note: this is safe as long as MCR bit 4 is clear
1244 * and the device is in "PC" mode.
1246 scratch = serial_in(up, UART_IER);
1247 serial_out(up, UART_IER, 0);
1252 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1253 * 16C754B) allow only to modify them if an EFR bit is set.
1255 scratch2 = serial_in(up, UART_IER) & 0x0f;
1256 serial_out(up, UART_IER, 0x0F);
1260 scratch3 = serial_in(up, UART_IER) & 0x0f;
1261 serial_out(up, UART_IER, scratch);
1262 if (scratch2 != 0 || scratch3 != 0x0F) {
1264 * We failed; there's nothing here
1266 spin_unlock_irqrestore(&port->lock, flags);
1267 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1268 scratch2, scratch3);
1273 save_mcr = serial8250_in_MCR(up);
1274 save_lcr = serial_in(up, UART_LCR);
1277 * Check to see if a UART is really there. Certain broken
1278 * internal modems based on the Rockwell chipset fail this
1279 * test, because they apparently don't implement the loopback
1280 * test mode. So this test is skipped on the COM 1 through
1281 * COM 4 ports. This *should* be safe, since no board
1282 * manufacturer would be stupid enough to design a board
1283 * that conflicts with COM 1-4 --- we hope!
1285 if (!(port->flags & UPF_SKIP_TEST)) {
1286 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1287 status1 = serial_in(up, UART_MSR) & 0xF0;
1288 serial8250_out_MCR(up, save_mcr);
1289 if (status1 != 0x90) {
1290 spin_unlock_irqrestore(&port->lock, flags);
1291 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1298 * We're pretty sure there's a port here. Lets find out what
1299 * type of port it is. The IIR top two bits allows us to find
1300 * out if it's 8250 or 16450, 16550, 16550A or later. This
1301 * determines what we test for next.
1303 * We also initialise the EFR (if any) to zero for later. The
1304 * EFR occupies the same register location as the FCR and IIR.
1306 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1307 serial_out(up, UART_EFR, 0);
1308 serial_out(up, UART_LCR, 0);
1310 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1312 /* Assign this as it is to truncate any bits above 7. */
1313 scratch = serial_in(up, UART_IIR);
1315 switch (scratch >> 6) {
1317 autoconfig_8250(up);
1320 port->type = PORT_UNKNOWN;
1323 port->type = PORT_16550;
1326 autoconfig_16550a(up);
1330 #ifdef CONFIG_SERIAL_8250_RSA
1332 * Only probe for RSA ports if we got the region.
1334 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1336 port->type = PORT_RSA;
1339 serial_out(up, UART_LCR, save_lcr);
1341 port->fifosize = uart_config[up->port.type].fifo_size;
1342 old_capabilities = up->capabilities;
1343 up->capabilities = uart_config[port->type].flags;
1344 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1346 if (port->type == PORT_UNKNOWN)
1352 #ifdef CONFIG_SERIAL_8250_RSA
1353 if (port->type == PORT_RSA)
1354 serial_out(up, UART_RSA_FRR, 0);
1356 serial8250_out_MCR(up, save_mcr);
1357 serial8250_clear_fifos(up);
1358 serial_in(up, UART_RX);
1359 if (up->capabilities & UART_CAP_UUE)
1360 serial_out(up, UART_IER, UART_IER_UUE);
1362 serial_out(up, UART_IER, 0);
1365 spin_unlock_irqrestore(&port->lock, flags);
1368 * Check if the device is a Fintek F81216A
1370 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1371 fintek_8250_probe(up);
1373 if (up->capabilities != old_capabilities) {
1374 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1375 serial_index(port), old_capabilities,
1379 DEBUG_AUTOCONF("iir=%d ", scratch);
1380 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1383 static void autoconfig_irq(struct uart_8250_port *up)
1385 struct uart_port *port = &up->port;
1386 unsigned char save_mcr, save_ier;
1387 unsigned char save_ICP = 0;
1388 unsigned int ICP = 0;
1392 if (port->flags & UPF_FOURPORT) {
1393 ICP = (port->iobase & 0xfe0) | 0x1f;
1394 save_ICP = inb_p(ICP);
1399 if (uart_console(port))
1402 /* forget possible initially masked and pending IRQ */
1403 probe_irq_off(probe_irq_on());
1404 save_mcr = serial8250_in_MCR(up);
1405 save_ier = serial_in(up, UART_IER);
1406 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1408 irqs = probe_irq_on();
1409 serial8250_out_MCR(up, 0);
1411 if (port->flags & UPF_FOURPORT) {
1412 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1414 serial8250_out_MCR(up,
1415 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1417 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1418 serial_in(up, UART_LSR);
1419 serial_in(up, UART_RX);
1420 serial_in(up, UART_IIR);
1421 serial_in(up, UART_MSR);
1422 serial_out(up, UART_TX, 0xFF);
1424 irq = probe_irq_off(irqs);
1426 serial8250_out_MCR(up, save_mcr);
1427 serial_out(up, UART_IER, save_ier);
1429 if (port->flags & UPF_FOURPORT)
1430 outb_p(save_ICP, ICP);
1432 if (uart_console(port))
1435 port->irq = (irq > 0) ? irq : 0;
1438 static void serial8250_stop_rx(struct uart_port *port)
1440 struct uart_8250_port *up = up_to_u8250p(port);
1442 serial8250_rpm_get(up);
1444 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1445 up->port.read_status_mask &= ~UART_LSR_DR;
1446 serial_port_out(port, UART_IER, up->ier);
1448 serial8250_rpm_put(up);
1451 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1453 serial8250_em485_rts_after_send(p);
1456 * Empty the RX FIFO, we are not interested in anything
1457 * received during the half-duplex transmission.
1458 * Enable previously disabled RX interrupts.
1460 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1461 serial8250_clear_and_reinit_fifos(p);
1463 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1464 serial_port_out(&p->port, UART_IER, p->ier);
1467 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1469 struct uart_8250_em485 *em485;
1470 struct uart_8250_port *p;
1471 unsigned long flags;
1473 em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1476 serial8250_rpm_get(p);
1477 spin_lock_irqsave(&p->port.lock, flags);
1478 if (em485->active_timer == &em485->stop_tx_timer) {
1479 __do_stop_tx_rs485(p);
1480 em485->active_timer = NULL;
1482 spin_unlock_irqrestore(&p->port.lock, flags);
1483 serial8250_rpm_put(p);
1484 return HRTIMER_NORESTART;
1487 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1489 long sec = msec / 1000;
1490 long nsec = (msec % 1000) * 1000000;
1491 ktime_t t = ktime_set(sec, nsec);
1493 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1496 static void __stop_tx_rs485(struct uart_8250_port *p)
1498 struct uart_8250_em485 *em485 = p->em485;
1501 * __do_stop_tx_rs485 is going to set RTS according to config
1502 * AND flush RX FIFO if required.
1504 if (p->port.rs485.delay_rts_after_send > 0) {
1505 em485->active_timer = &em485->stop_tx_timer;
1506 start_hrtimer_ms(&em485->stop_tx_timer,
1507 p->port.rs485.delay_rts_after_send);
1509 __do_stop_tx_rs485(p);
1513 static inline void __do_stop_tx(struct uart_8250_port *p)
1515 if (p->ier & UART_IER_THRI) {
1516 p->ier &= ~UART_IER_THRI;
1517 serial_out(p, UART_IER, p->ier);
1518 serial8250_rpm_put_tx(p);
1522 static inline void __stop_tx(struct uart_8250_port *p)
1524 struct uart_8250_em485 *em485 = p->em485;
1527 unsigned char lsr = serial_in(p, UART_LSR);
1528 p->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1531 * To provide required timeing and allow FIFO transfer,
1532 * __stop_tx_rs485() must be called only when both FIFO and
1533 * shift register are empty. It is for device driver to enable
1534 * interrupt on TEMT.
1536 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1539 em485->active_timer = NULL;
1546 static void serial8250_stop_tx(struct uart_port *port)
1548 struct uart_8250_port *up = up_to_u8250p(port);
1550 serial8250_rpm_get(up);
1554 * We really want to stop the transmitter from sending.
1556 if (port->type == PORT_16C950) {
1557 up->acr |= UART_ACR_TXDIS;
1558 serial_icr_write(up, UART_ACR, up->acr);
1560 serial8250_rpm_put(up);
1563 static inline void __start_tx(struct uart_port *port)
1565 struct uart_8250_port *up = up_to_u8250p(port);
1567 if (up->dma && !up->dma->tx_dma(up))
1570 if (!(up->ier & UART_IER_THRI)) {
1571 up->ier |= UART_IER_THRI;
1572 serial_port_out(port, UART_IER, up->ier);
1574 if (up->bugs & UART_BUG_TXEN) {
1577 lsr = serial_in(up, UART_LSR);
1578 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1579 if (lsr & UART_LSR_THRE)
1580 serial8250_tx_chars(up);
1585 * Re-enable the transmitter if we disabled it.
1587 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1588 up->acr &= ~UART_ACR_TXDIS;
1589 serial_icr_write(up, UART_ACR, up->acr);
1593 static inline void start_tx_rs485(struct uart_port *port)
1595 struct uart_8250_port *up = up_to_u8250p(port);
1596 struct uart_8250_em485 *em485 = up->em485;
1599 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1600 serial8250_stop_rx(&up->port);
1603 * While serial8250_em485_handle_stop_tx() is a noop if
1604 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1605 * the timer is still armed and triggers only after the current bunch of
1606 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1607 * So cancel the timer. There is still a theoretical race condition if
1608 * the timer is already running and only comes around to check for
1609 * em485->active_timer when &em485->stop_tx_timer is armed again.
1611 if (em485->active_timer == &em485->stop_tx_timer)
1612 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1614 em485->active_timer = NULL;
1616 mcr = serial8250_in_MCR(up);
1617 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1618 !!(mcr & UART_MCR_RTS)) {
1619 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1620 mcr |= UART_MCR_RTS;
1622 mcr &= ~UART_MCR_RTS;
1623 serial8250_out_MCR(up, mcr);
1625 if (up->port.rs485.delay_rts_before_send > 0) {
1626 em485->active_timer = &em485->start_tx_timer;
1627 start_hrtimer_ms(&em485->start_tx_timer,
1628 up->port.rs485.delay_rts_before_send);
1636 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1638 struct uart_8250_em485 *em485;
1639 struct uart_8250_port *p;
1640 unsigned long flags;
1642 em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1645 spin_lock_irqsave(&p->port.lock, flags);
1646 if (em485->active_timer == &em485->start_tx_timer) {
1647 __start_tx(&p->port);
1648 em485->active_timer = NULL;
1650 spin_unlock_irqrestore(&p->port.lock, flags);
1651 return HRTIMER_NORESTART;
1654 static void serial8250_start_tx(struct uart_port *port)
1656 struct uart_8250_port *up = up_to_u8250p(port);
1657 struct uart_8250_em485 *em485 = up->em485;
1659 serial8250_rpm_get_tx(up);
1662 em485->active_timer == &em485->start_tx_timer)
1666 start_tx_rs485(port);
1671 static void serial8250_throttle(struct uart_port *port)
1673 port->throttle(port);
1676 static void serial8250_unthrottle(struct uart_port *port)
1678 port->unthrottle(port);
1681 static void serial8250_disable_ms(struct uart_port *port)
1683 struct uart_8250_port *up = up_to_u8250p(port);
1685 /* no MSR capabilities */
1686 if (up->bugs & UART_BUG_NOMSR)
1689 up->ier &= ~UART_IER_MSI;
1690 serial_port_out(port, UART_IER, up->ier);
1693 static void serial8250_enable_ms(struct uart_port *port)
1695 struct uart_8250_port *up = up_to_u8250p(port);
1697 /* no MSR capabilities */
1698 if (up->bugs & UART_BUG_NOMSR)
1701 up->ier |= UART_IER_MSI;
1703 serial8250_rpm_get(up);
1704 serial_port_out(port, UART_IER, up->ier);
1705 serial8250_rpm_put(up);
1708 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1710 struct uart_port *port = &up->port;
1712 char flag = TTY_NORMAL;
1714 if (likely(lsr & UART_LSR_DR))
1715 ch = serial_in(up, UART_RX);
1718 * Intel 82571 has a Serial Over Lan device that will
1719 * set UART_LSR_BI without setting UART_LSR_DR when
1720 * it receives a break. To avoid reading from the
1721 * receive buffer without UART_LSR_DR bit set, we
1722 * just force the read character to be 0
1728 lsr |= up->lsr_saved_flags;
1729 up->lsr_saved_flags = 0;
1731 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1732 if (lsr & UART_LSR_BI) {
1733 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1736 * We do the SysRQ and SAK checking
1737 * here because otherwise the break
1738 * may get masked by ignore_status_mask
1739 * or read_status_mask.
1741 if (uart_handle_break(port))
1743 } else if (lsr & UART_LSR_PE)
1744 port->icount.parity++;
1745 else if (lsr & UART_LSR_FE)
1746 port->icount.frame++;
1747 if (lsr & UART_LSR_OE)
1748 port->icount.overrun++;
1751 * Mask off conditions which should be ignored.
1753 lsr &= port->read_status_mask;
1755 if (lsr & UART_LSR_BI) {
1756 pr_debug("%s: handling break\n", __func__);
1758 } else if (lsr & UART_LSR_PE)
1760 else if (lsr & UART_LSR_FE)
1763 if (uart_handle_sysrq_char(port, ch))
1766 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1770 * serial8250_rx_chars: processes according to the passed in LSR
1771 * value, and returns the remaining LSR bits not handled
1772 * by this Rx routine.
1774 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1776 struct uart_port *port = &up->port;
1777 int max_count = 256;
1780 serial8250_read_char(up, lsr);
1781 if (--max_count == 0)
1783 lsr = serial_in(up, UART_LSR);
1784 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1786 tty_flip_buffer_push(&port->state->port);
1789 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1791 void serial8250_tx_chars(struct uart_8250_port *up)
1793 struct uart_port *port = &up->port;
1794 struct circ_buf *xmit = &port->state->xmit;
1798 serial_out(up, UART_TX, port->x_char);
1803 if (uart_tx_stopped(port)) {
1804 serial8250_stop_tx(port);
1807 if (uart_circ_empty(xmit)) {
1812 count = up->tx_loadsz;
1814 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1815 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1817 if (uart_circ_empty(xmit))
1819 if ((up->capabilities & UART_CAP_HFIFO) &&
1820 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1822 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1823 if ((up->capabilities & UART_CAP_MINI) &&
1824 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1826 } while (--count > 0);
1828 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1829 uart_write_wakeup(port);
1832 * With RPM enabled, we have to wait until the FIFO is empty before the
1833 * HW can go idle. So we get here once again with empty FIFO and disable
1834 * the interrupt and RPM in __stop_tx()
1836 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1839 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1841 /* Caller holds uart port lock */
1842 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1844 struct uart_port *port = &up->port;
1845 unsigned int status = serial_in(up, UART_MSR);
1847 status |= up->msr_saved_flags;
1848 up->msr_saved_flags = 0;
1849 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1850 port->state != NULL) {
1851 if (status & UART_MSR_TERI)
1853 if (status & UART_MSR_DDSR)
1855 if (status & UART_MSR_DDCD)
1856 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1857 if (status & UART_MSR_DCTS)
1858 uart_handle_cts_change(port, status & UART_MSR_CTS);
1860 wake_up_interruptible(&port->state->port.delta_msr_wait);
1865 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1867 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1869 switch (iir & 0x3f) {
1871 if (!up->dma->rx_running)
1875 case UART_IIR_RX_TIMEOUT:
1876 serial8250_rx_dma_flush(up);
1879 return up->dma->rx_dma(up);
1883 * This handles the interrupt from one port.
1885 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1887 unsigned char status;
1888 unsigned long flags;
1889 struct uart_8250_port *up = up_to_u8250p(port);
1890 struct tty_port *tport = &port->state->port;
1891 bool skip_rx = false;
1893 if (iir & UART_IIR_NO_INT)
1896 spin_lock_irqsave(&port->lock, flags);
1898 status = serial_port_in(port, UART_LSR);
1901 * If port is stopped and there are no error conditions in the
1902 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1903 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1904 * control when FIFO occupancy reaches preset threshold, thus
1905 * halting RX. This only works when auto HW flow control is
1908 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1909 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1910 !(port->read_status_mask & UART_LSR_DR))
1913 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1916 d = irq_get_irq_data(port->irq);
1917 if (d && irqd_is_wakeup_set(d))
1918 pm_wakeup_event(tport->tty->dev, 0);
1919 if (!up->dma || handle_rx_dma(up, iir))
1920 status = serial8250_rx_chars(up, status);
1922 serial8250_modem_status(up);
1923 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1924 (up->ier & UART_IER_THRI))
1925 serial8250_tx_chars(up);
1927 spin_unlock_irqrestore(&port->lock, flags);
1930 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1932 static int serial8250_default_handle_irq(struct uart_port *port)
1934 struct uart_8250_port *up = up_to_u8250p(port);
1938 serial8250_rpm_get(up);
1940 iir = serial_port_in(port, UART_IIR);
1941 ret = serial8250_handle_irq(port, iir);
1943 serial8250_rpm_put(up);
1948 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1949 * have a programmable TX threshold that triggers the THRE interrupt in
1950 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1951 * has space available. Load it up with tx_loadsz bytes.
1953 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1955 unsigned long flags;
1956 unsigned int iir = serial_port_in(port, UART_IIR);
1958 /* TX Threshold IRQ triggered so load up FIFO */
1959 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1960 struct uart_8250_port *up = up_to_u8250p(port);
1962 spin_lock_irqsave(&port->lock, flags);
1963 serial8250_tx_chars(up);
1964 spin_unlock_irqrestore(&port->lock, flags);
1967 iir = serial_port_in(port, UART_IIR);
1968 return serial8250_handle_irq(port, iir);
1971 static unsigned int serial8250_tx_empty(struct uart_port *port)
1973 struct uart_8250_port *up = up_to_u8250p(port);
1974 unsigned int result = 0;
1975 unsigned long flags;
1978 serial8250_rpm_get(up);
1980 spin_lock_irqsave(&port->lock, flags);
1981 if (!serial8250_tx_dma_running(up)) {
1982 lsr = serial_port_in(port, UART_LSR);
1983 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1985 if ((lsr & BOTH_EMPTY) == BOTH_EMPTY)
1986 result = TIOCSER_TEMT;
1988 spin_unlock_irqrestore(&port->lock, flags);
1990 serial8250_rpm_put(up);
1995 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1997 struct uart_8250_port *up = up_to_u8250p(port);
1998 unsigned int status;
2001 serial8250_rpm_get(up);
2002 status = serial8250_modem_status(up);
2003 serial8250_rpm_put(up);
2006 if (status & UART_MSR_DCD)
2008 if (status & UART_MSR_RI)
2010 if (status & UART_MSR_DSR)
2012 if (status & UART_MSR_CTS)
2016 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2018 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2020 if (port->get_mctrl)
2021 return port->get_mctrl(port);
2022 return serial8250_do_get_mctrl(port);
2025 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2027 struct uart_8250_port *up = up_to_u8250p(port);
2028 unsigned char mcr = 0;
2030 if (mctrl & TIOCM_RTS)
2031 mcr |= UART_MCR_RTS;
2032 if (mctrl & TIOCM_DTR)
2033 mcr |= UART_MCR_DTR;
2034 if (mctrl & TIOCM_OUT1)
2035 mcr |= UART_MCR_OUT1;
2036 if (mctrl & TIOCM_OUT2)
2037 mcr |= UART_MCR_OUT2;
2038 if (mctrl & TIOCM_LOOP)
2039 mcr |= UART_MCR_LOOP;
2041 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2043 serial8250_out_MCR(up, mcr);
2045 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2047 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2049 if (port->set_mctrl)
2050 port->set_mctrl(port, mctrl);
2052 serial8250_do_set_mctrl(port, mctrl);
2055 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2057 struct uart_8250_port *up = up_to_u8250p(port);
2058 unsigned long flags;
2060 serial8250_rpm_get(up);
2061 spin_lock_irqsave(&port->lock, flags);
2062 if (break_state == -1)
2063 up->lcr |= UART_LCR_SBC;
2065 up->lcr &= ~UART_LCR_SBC;
2066 serial_port_out(port, UART_LCR, up->lcr);
2067 spin_unlock_irqrestore(&port->lock, flags);
2068 serial8250_rpm_put(up);
2072 * Wait for transmitter & holding register to empty
2074 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2076 unsigned int status, tmout = 10000;
2078 /* Wait up to 10ms for the character(s) to be sent. */
2080 status = serial_in(up, UART_LSR);
2082 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2084 if ((status & bits) == bits)
2089 touch_nmi_watchdog();
2092 /* Wait up to 1s for flow control if necessary */
2093 if (up->port.flags & UPF_CONS_FLOW) {
2094 for (tmout = 1000000; tmout; tmout--) {
2095 unsigned int msr = serial_in(up, UART_MSR);
2096 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2097 if (msr & UART_MSR_CTS)
2100 touch_nmi_watchdog();
2105 #ifdef CONFIG_CONSOLE_POLL
2107 * Console polling routines for writing and reading from the uart while
2108 * in an interrupt or debug context.
2111 static int serial8250_get_poll_char(struct uart_port *port)
2113 struct uart_8250_port *up = up_to_u8250p(port);
2117 serial8250_rpm_get(up);
2119 lsr = serial_port_in(port, UART_LSR);
2121 if (!(lsr & UART_LSR_DR)) {
2122 status = NO_POLL_CHAR;
2126 status = serial_port_in(port, UART_RX);
2128 serial8250_rpm_put(up);
2133 static void serial8250_put_poll_char(struct uart_port *port,
2137 struct uart_8250_port *up = up_to_u8250p(port);
2139 serial8250_rpm_get(up);
2141 * First save the IER then disable the interrupts
2143 ier = serial_port_in(port, UART_IER);
2144 if (up->capabilities & UART_CAP_UUE)
2145 serial_port_out(port, UART_IER, UART_IER_UUE);
2147 serial_port_out(port, UART_IER, 0);
2149 wait_for_xmitr(up, BOTH_EMPTY);
2151 * Send the character out.
2153 serial_port_out(port, UART_TX, c);
2156 * Finally, wait for transmitter to become empty
2157 * and restore the IER
2159 wait_for_xmitr(up, BOTH_EMPTY);
2160 serial_port_out(port, UART_IER, ier);
2161 serial8250_rpm_put(up);
2164 #endif /* CONFIG_CONSOLE_POLL */
2166 int serial8250_do_startup(struct uart_port *port)
2168 struct uart_8250_port *up = up_to_u8250p(port);
2169 unsigned long flags;
2170 unsigned char lsr, iir;
2173 if (!port->fifosize)
2174 port->fifosize = uart_config[port->type].fifo_size;
2176 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2177 if (!up->capabilities)
2178 up->capabilities = uart_config[port->type].flags;
2181 if (port->iotype != up->cur_iotype)
2182 set_io_from_upio(port);
2184 serial8250_rpm_get(up);
2185 if (port->type == PORT_16C950) {
2186 /* Wake up and initialize UART */
2188 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2189 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2190 serial_port_out(port, UART_IER, 0);
2191 serial_port_out(port, UART_LCR, 0);
2192 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2193 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2194 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2195 serial_port_out(port, UART_LCR, 0);
2198 if (port->type == PORT_DA830) {
2199 /* Reset the port */
2200 serial_port_out(port, UART_IER, 0);
2201 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2204 /* Enable Tx, Rx and free run mode */
2205 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2206 UART_DA830_PWREMU_MGMT_UTRST |
2207 UART_DA830_PWREMU_MGMT_URRST |
2208 UART_DA830_PWREMU_MGMT_FREE);
2211 if (port->type == PORT_NPCM) {
2213 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2214 * register). Enable it, and set TIOC (timeout interrupt
2215 * comparator) to be 0x20 for correct operation.
2217 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2220 #ifdef CONFIG_SERIAL_8250_RSA
2222 * If this is an RSA port, see if we can kick it up to the
2223 * higher speed clock.
2228 if (port->type == PORT_XR17V35X) {
2230 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2231 * MCR [7:5] and MSR [7:0]
2233 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2236 * Make sure all interrups are masked until initialization is
2237 * complete and the FIFOs are cleared
2239 serial_port_out(port, UART_IER, 0);
2243 * Clear the FIFO buffers and disable them.
2244 * (they will be reenabled in set_termios())
2246 serial8250_clear_fifos(up);
2249 * Clear the interrupt registers.
2251 serial_port_in(port, UART_LSR);
2252 serial_port_in(port, UART_RX);
2253 serial_port_in(port, UART_IIR);
2254 serial_port_in(port, UART_MSR);
2255 if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2256 serial_port_in(port, UART_EXAR_INT0);
2259 * At this point, there's no way the LSR could still be 0xff;
2260 * if it is, then bail out, because there's likely no UART
2263 if (!(port->flags & UPF_BUGGY_UART) &&
2264 (serial_port_in(port, UART_LSR) == 0xff)) {
2265 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2266 serial_index(port));
2272 * For a XR16C850, we need to set the trigger levels
2274 if (port->type == PORT_16850) {
2277 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2279 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2280 serial_port_out(port, UART_FCTR,
2281 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2282 serial_port_out(port, UART_TRG, UART_TRG_96);
2283 serial_port_out(port, UART_FCTR,
2284 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2285 serial_port_out(port, UART_TRG, UART_TRG_96);
2287 serial_port_out(port, UART_LCR, 0);
2291 * For the Altera 16550 variants, set TX threshold trigger level.
2293 if (((port->type == PORT_ALTR_16550_F32) ||
2294 (port->type == PORT_ALTR_16550_F64) ||
2295 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2296 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2297 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2298 pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2299 serial_index(port));
2301 serial_port_out(port, UART_ALTR_AFR,
2302 UART_ALTR_EN_TXFIFO_LW);
2303 serial_port_out(port, UART_ALTR_TX_LOW,
2304 port->fifosize - up->tx_loadsz);
2305 port->handle_irq = serial8250_tx_threshold_handle_irq;
2309 /* Check if we need to have shared IRQs */
2310 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2311 up->port.irqflags |= IRQF_SHARED;
2313 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2316 if (port->irqflags & IRQF_SHARED)
2317 disable_irq_nosync(port->irq);
2320 * Test for UARTs that do not reassert THRE when the
2321 * transmitter is idle and the interrupt has already
2322 * been cleared. Real 16550s should always reassert
2323 * this interrupt whenever the transmitter is idle and
2324 * the interrupt is enabled. Delays are necessary to
2325 * allow register changes to become visible.
2327 spin_lock_irqsave(&port->lock, flags);
2329 wait_for_xmitr(up, UART_LSR_THRE);
2330 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2331 udelay(1); /* allow THRE to set */
2332 iir1 = serial_port_in(port, UART_IIR);
2333 serial_port_out(port, UART_IER, 0);
2334 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2335 udelay(1); /* allow a working UART time to re-assert THRE */
2336 iir = serial_port_in(port, UART_IIR);
2337 serial_port_out(port, UART_IER, 0);
2339 spin_unlock_irqrestore(&port->lock, flags);
2341 if (port->irqflags & IRQF_SHARED)
2342 enable_irq(port->irq);
2345 * If the interrupt is not reasserted, or we otherwise
2346 * don't trust the iir, setup a timer to kick the UART
2347 * on a regular basis.
2349 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2350 up->port.flags & UPF_BUG_THRE) {
2351 up->bugs |= UART_BUG_THRE;
2355 retval = up->ops->setup_irq(up);
2360 * Now, initialize the UART
2362 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2364 spin_lock_irqsave(&port->lock, flags);
2365 if (up->port.flags & UPF_FOURPORT) {
2367 up->port.mctrl |= TIOCM_OUT1;
2370 * Most PC uarts need OUT2 raised to enable interrupts.
2373 up->port.mctrl |= TIOCM_OUT2;
2375 serial8250_set_mctrl(port, port->mctrl);
2378 * Serial over Lan (SoL) hack:
2379 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2380 * used for Serial Over Lan. Those chips take a longer time than a
2381 * normal serial device to signalize that a transmission data was
2382 * queued. Due to that, the above test generally fails. One solution
2383 * would be to delay the reading of iir. However, this is not
2384 * reliable, since the timeout is variable. So, let's just don't
2385 * test if we receive TX irq. This way, we'll never enable
2388 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2389 goto dont_test_tx_en;
2392 * Do a quick test to see if we receive an interrupt when we enable
2395 serial_port_out(port, UART_IER, UART_IER_THRI);
2396 lsr = serial_port_in(port, UART_LSR);
2397 iir = serial_port_in(port, UART_IIR);
2398 serial_port_out(port, UART_IER, 0);
2400 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2401 if (!(up->bugs & UART_BUG_TXEN)) {
2402 up->bugs |= UART_BUG_TXEN;
2403 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2404 serial_index(port));
2407 up->bugs &= ~UART_BUG_TXEN;
2411 spin_unlock_irqrestore(&port->lock, flags);
2414 * Clear the interrupt registers again for luck, and clear the
2415 * saved flags to avoid getting false values from polling
2416 * routines or the previous session.
2418 serial_port_in(port, UART_LSR);
2419 serial_port_in(port, UART_RX);
2420 serial_port_in(port, UART_IIR);
2421 serial_port_in(port, UART_MSR);
2422 if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2423 serial_port_in(port, UART_EXAR_INT0);
2424 up->lsr_saved_flags = 0;
2425 up->msr_saved_flags = 0;
2428 * Request DMA channels for both RX and TX.
2431 retval = serial8250_request_dma(up);
2433 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2434 serial_index(port));
2440 * Set the IER shadow for rx interrupts but defer actual interrupt
2441 * enable until after the FIFOs are enabled; otherwise, an already-
2442 * active sender can swamp the interrupt handler with "too much work".
2444 up->ier = UART_IER_RLSI | UART_IER_RDI;
2446 if (port->flags & UPF_FOURPORT) {
2449 * Enable interrupts on the AST Fourport board
2451 icp = (port->iobase & 0xfe0) | 0x01f;
2457 serial8250_rpm_put(up);
2460 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2462 static int serial8250_startup(struct uart_port *port)
2465 return port->startup(port);
2466 return serial8250_do_startup(port);
2469 void serial8250_do_shutdown(struct uart_port *port)
2471 struct uart_8250_port *up = up_to_u8250p(port);
2472 unsigned long flags;
2474 serial8250_rpm_get(up);
2476 * Disable interrupts from this port
2478 spin_lock_irqsave(&port->lock, flags);
2480 serial_port_out(port, UART_IER, 0);
2481 spin_unlock_irqrestore(&port->lock, flags);
2483 synchronize_irq(port->irq);
2486 serial8250_release_dma(up);
2488 spin_lock_irqsave(&port->lock, flags);
2489 if (port->flags & UPF_FOURPORT) {
2490 /* reset interrupts on the AST Fourport board */
2491 inb((port->iobase & 0xfe0) | 0x1f);
2492 port->mctrl |= TIOCM_OUT1;
2494 port->mctrl &= ~TIOCM_OUT2;
2496 serial8250_set_mctrl(port, port->mctrl);
2497 spin_unlock_irqrestore(&port->lock, flags);
2500 * Disable break condition and FIFOs
2502 serial_port_out(port, UART_LCR,
2503 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2504 serial8250_clear_fifos(up);
2506 #ifdef CONFIG_SERIAL_8250_RSA
2508 * Reset the RSA board back to 115kbps compat mode.
2514 * Read data port to reset things, and then unlink from
2517 serial_port_in(port, UART_RX);
2518 serial8250_rpm_put(up);
2520 up->ops->release_irq(up);
2522 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2524 static void serial8250_shutdown(struct uart_port *port)
2527 port->shutdown(port);
2529 serial8250_do_shutdown(port);
2533 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2534 * Calculate divisor with extra 4-bit fractional portion
2536 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2540 struct uart_port *port = &up->port;
2541 unsigned int quot_16;
2543 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2544 *frac = quot_16 & 0x0f;
2546 return quot_16 >> 4;
2549 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2550 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2553 struct uart_port *port = &up->port;
2555 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2558 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2562 struct uart_port *port = &up->port;
2566 * Handle magic divisors for baud rates above baud_base on
2567 * SMSC SuperIO chips.
2570 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2571 baud == (port->uartclk/4))
2573 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2574 baud == (port->uartclk/8))
2576 else if (up->port.type == PORT_XR17V35X)
2577 quot = xr17v35x_get_divisor(up, baud, frac);
2578 else if (up->port.type == PORT_NPCM)
2579 quot = npcm_get_divisor(up, baud);
2581 quot = uart_get_divisor(port, baud);
2584 * Oxford Semi 952 rev B workaround
2586 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2592 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2597 switch (c_cflag & CSIZE) {
2599 cval = UART_LCR_WLEN5;
2602 cval = UART_LCR_WLEN6;
2605 cval = UART_LCR_WLEN7;
2609 cval = UART_LCR_WLEN8;
2613 if (c_cflag & CSTOPB)
2614 cval |= UART_LCR_STOP;
2615 if (c_cflag & PARENB)
2616 cval |= UART_LCR_PARITY;
2617 if (!(c_cflag & PARODD))
2618 cval |= UART_LCR_EPAR;
2620 if (c_cflag & CMSPAR)
2621 cval |= UART_LCR_SPAR;
2627 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2628 unsigned int quot, unsigned int quot_frac)
2630 struct uart_8250_port *up = up_to_u8250p(port);
2632 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2633 if (is_omap1510_8250(up)) {
2634 if (baud == 115200) {
2636 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2638 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2642 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2643 * otherwise just set DLAB
2645 if (up->capabilities & UART_NATSEMI)
2646 serial_port_out(port, UART_LCR, 0xe0);
2648 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2650 serial_dl_write(up, quot);
2652 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2653 if (up->port.type == PORT_XR17V35X) {
2654 /* Preserve bits not related to baudrate; DLD[7:4]. */
2655 quot_frac |= serial_port_in(port, 0x2) & 0xf0;
2656 serial_port_out(port, 0x2, quot_frac);
2660 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2661 struct ktermios *termios,
2662 struct ktermios *old)
2665 * Ask the core to calculate the divisor for us.
2666 * Allow 1% tolerance at the upper limit so uart clks marginally
2667 * slower than nominal still match standard baud rates without
2668 * causing transmission errors.
2670 return uart_get_baud_rate(port, termios, old,
2671 port->uartclk / 16 / 0xffff,
2676 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2677 struct ktermios *old)
2679 struct uart_8250_port *up = up_to_u8250p(port);
2681 unsigned long flags;
2682 unsigned int baud, quot, frac = 0;
2684 if (up->capabilities & UART_CAP_MINI) {
2685 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2686 if ((termios->c_cflag & CSIZE) == CS5 ||
2687 (termios->c_cflag & CSIZE) == CS6)
2688 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2690 cval = serial8250_compute_lcr(up, termios->c_cflag);
2692 baud = serial8250_get_baud_rate(port, termios, old);
2693 quot = serial8250_get_divisor(up, baud, &frac);
2696 * Ok, we're now changing the port state. Do it with
2697 * interrupts disabled.
2699 serial8250_rpm_get(up);
2700 spin_lock_irqsave(&port->lock, flags);
2702 up->lcr = cval; /* Save computed LCR */
2704 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2705 if (baud < 2400 && !up->dma) {
2706 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2707 up->fcr |= UART_FCR_TRIGGER_1;
2712 * MCR-based auto flow control. When AFE is enabled, RTS will be
2713 * deasserted when the receive FIFO contains more characters than
2714 * the trigger, or the MCR RTS bit is cleared.
2716 if (up->capabilities & UART_CAP_AFE) {
2717 up->mcr &= ~UART_MCR_AFE;
2718 if (termios->c_cflag & CRTSCTS)
2719 up->mcr |= UART_MCR_AFE;
2723 * Update the per-port timeout.
2725 uart_update_timeout(port, termios->c_cflag, baud);
2727 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2728 if (termios->c_iflag & INPCK)
2729 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2730 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2731 port->read_status_mask |= UART_LSR_BI;
2734 * Characteres to ignore
2736 port->ignore_status_mask = 0;
2737 if (termios->c_iflag & IGNPAR)
2738 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2739 if (termios->c_iflag & IGNBRK) {
2740 port->ignore_status_mask |= UART_LSR_BI;
2742 * If we're ignoring parity and break indicators,
2743 * ignore overruns too (for real raw support).
2745 if (termios->c_iflag & IGNPAR)
2746 port->ignore_status_mask |= UART_LSR_OE;
2750 * ignore all characters if CREAD is not set
2752 if ((termios->c_cflag & CREAD) == 0)
2753 port->ignore_status_mask |= UART_LSR_DR;
2756 * CTS flow control flag and modem status interrupts
2758 up->ier &= ~UART_IER_MSI;
2759 if (!(up->bugs & UART_BUG_NOMSR) &&
2760 UART_ENABLE_MS(&up->port, termios->c_cflag))
2761 up->ier |= UART_IER_MSI;
2762 if (up->capabilities & UART_CAP_UUE)
2763 up->ier |= UART_IER_UUE;
2764 if (up->capabilities & UART_CAP_RTOIE)
2765 up->ier |= UART_IER_RTOIE;
2767 serial_port_out(port, UART_IER, up->ier);
2769 if (up->capabilities & UART_CAP_EFR) {
2770 unsigned char efr = 0;
2772 * TI16C752/Startech hardware flow control. FIXME:
2773 * - TI16C752 requires control thresholds to be set.
2774 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2776 if (termios->c_cflag & CRTSCTS)
2777 efr |= UART_EFR_CTS;
2779 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2780 if (port->flags & UPF_EXAR_EFR)
2781 serial_port_out(port, UART_XR_EFR, efr);
2783 serial_port_out(port, UART_EFR, efr);
2786 serial8250_set_divisor(port, baud, quot, frac);
2789 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2790 * is written without DLAB set, this mode will be disabled.
2792 if (port->type == PORT_16750)
2793 serial_port_out(port, UART_FCR, up->fcr);
2795 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2796 if (port->type != PORT_16750) {
2797 /* emulated UARTs (Lucent Venus 167x) need two steps */
2798 if (up->fcr & UART_FCR_ENABLE_FIFO)
2799 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2800 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2802 serial8250_set_mctrl(port, port->mctrl);
2803 spin_unlock_irqrestore(&port->lock, flags);
2804 serial8250_rpm_put(up);
2806 /* Don't rewrite B0 */
2807 if (tty_termios_baud_rate(termios))
2808 tty_termios_encode_baud_rate(termios, baud, baud);
2810 EXPORT_SYMBOL(serial8250_do_set_termios);
2813 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2814 struct ktermios *old)
2816 if (port->set_termios)
2817 port->set_termios(port, termios, old);
2819 serial8250_do_set_termios(port, termios, old);
2822 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2824 if (termios->c_line == N_PPS) {
2825 port->flags |= UPF_HARDPPS_CD;
2826 spin_lock_irq(&port->lock);
2827 serial8250_enable_ms(port);
2828 spin_unlock_irq(&port->lock);
2830 port->flags &= ~UPF_HARDPPS_CD;
2831 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2832 spin_lock_irq(&port->lock);
2833 serial8250_disable_ms(port);
2834 spin_unlock_irq(&port->lock);
2838 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2841 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2843 if (port->set_ldisc)
2844 port->set_ldisc(port, termios);
2846 serial8250_do_set_ldisc(port, termios);
2849 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2850 unsigned int oldstate)
2852 struct uart_8250_port *p = up_to_u8250p(port);
2854 serial8250_set_sleep(p, state != 0);
2856 EXPORT_SYMBOL(serial8250_do_pm);
2859 serial8250_pm(struct uart_port *port, unsigned int state,
2860 unsigned int oldstate)
2863 port->pm(port, state, oldstate);
2865 serial8250_do_pm(port, state, oldstate);
2868 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2870 if (pt->port.mapsize)
2871 return pt->port.mapsize;
2872 if (pt->port.iotype == UPIO_AU) {
2873 if (pt->port.type == PORT_RT2880)
2877 if (is_omap1_8250(pt))
2878 return 0x16 << pt->port.regshift;
2880 return 8 << pt->port.regshift;
2884 * Resource handling.
2886 static int serial8250_request_std_resource(struct uart_8250_port *up)
2888 unsigned int size = serial8250_port_size(up);
2889 struct uart_port *port = &up->port;
2892 switch (port->iotype) {
2899 if (!port->mapbase) {
2904 if (!request_mem_region(port->mapbase, size, "serial")) {
2909 if (port->flags & UPF_IOREMAP) {
2910 port->membase = ioremap_nocache(port->mapbase, size);
2911 if (!port->membase) {
2912 release_mem_region(port->mapbase, size);
2920 if (!request_region(port->iobase, size, "serial"))
2927 static void serial8250_release_std_resource(struct uart_8250_port *up)
2929 unsigned int size = serial8250_port_size(up);
2930 struct uart_port *port = &up->port;
2932 switch (port->iotype) {
2942 if (port->flags & UPF_IOREMAP) {
2943 iounmap(port->membase);
2944 port->membase = NULL;
2947 release_mem_region(port->mapbase, size);
2952 release_region(port->iobase, size);
2957 static void serial8250_release_port(struct uart_port *port)
2959 struct uart_8250_port *up = up_to_u8250p(port);
2961 serial8250_release_std_resource(up);
2964 static int serial8250_request_port(struct uart_port *port)
2966 struct uart_8250_port *up = up_to_u8250p(port);
2968 return serial8250_request_std_resource(up);
2971 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2973 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2974 unsigned char bytes;
2976 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2978 return bytes ? bytes : -EOPNOTSUPP;
2981 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2983 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2986 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2989 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2990 if (bytes < conf_type->rxtrig_bytes[i])
2991 /* Use the nearest lower value */
2992 return (--i) << UART_FCR_R_TRIG_SHIFT;
2995 return UART_FCR_R_TRIG_11;
2998 static int do_get_rxtrig(struct tty_port *port)
3000 struct uart_state *state = container_of(port, struct uart_state, port);
3001 struct uart_port *uport = state->uart_port;
3002 struct uart_8250_port *up = up_to_u8250p(uport);
3004 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3007 return fcr_get_rxtrig_bytes(up);
3010 static int do_serial8250_get_rxtrig(struct tty_port *port)
3014 mutex_lock(&port->mutex);
3015 rxtrig_bytes = do_get_rxtrig(port);
3016 mutex_unlock(&port->mutex);
3018 return rxtrig_bytes;
3021 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
3022 struct device_attribute *attr, char *buf)
3024 struct tty_port *port = dev_get_drvdata(dev);
3027 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3028 if (rxtrig_bytes < 0)
3029 return rxtrig_bytes;
3031 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
3034 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3036 struct uart_state *state = container_of(port, struct uart_state, port);
3037 struct uart_port *uport = state->uart_port;
3038 struct uart_8250_port *up = up_to_u8250p(uport);
3041 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3044 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3048 serial8250_clear_fifos(up);
3049 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3050 up->fcr |= (unsigned char)rxtrig;
3051 serial_out(up, UART_FCR, up->fcr);
3055 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3059 mutex_lock(&port->mutex);
3060 ret = do_set_rxtrig(port, bytes);
3061 mutex_unlock(&port->mutex);
3066 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
3067 struct device_attribute *attr, const char *buf, size_t count)
3069 struct tty_port *port = dev_get_drvdata(dev);
3070 unsigned char bytes;
3076 ret = kstrtou8(buf, 10, &bytes);
3080 ret = do_serial8250_set_rxtrig(port, bytes);
3087 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
3088 serial8250_get_attr_rx_trig_bytes,
3089 serial8250_set_attr_rx_trig_bytes);
3091 static struct attribute *serial8250_dev_attrs[] = {
3092 &dev_attr_rx_trig_bytes.attr,
3096 static struct attribute_group serial8250_dev_attr_group = {
3097 .attrs = serial8250_dev_attrs,
3100 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3102 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3104 if (conf_type->rxtrig_bytes[0])
3105 up->port.attr_group = &serial8250_dev_attr_group;
3108 static void serial8250_config_port(struct uart_port *port, int flags)
3110 struct uart_8250_port *up = up_to_u8250p(port);
3114 * Find the region that we can probe for. This in turn
3115 * tells us whether we can probe for the type of port.
3117 ret = serial8250_request_std_resource(up);
3121 if (port->iotype != up->cur_iotype)
3122 set_io_from_upio(port);
3124 if (flags & UART_CONFIG_TYPE)
3127 /* if access method is AU, it is a 16550 with a quirk */
3128 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3129 up->bugs |= UART_BUG_NOMSR;
3131 /* HW bugs may trigger IRQ while IIR == NO_INT */
3132 if (port->type == PORT_TEGRA)
3133 up->bugs |= UART_BUG_NOMSR;
3135 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3138 if (port->type == PORT_UNKNOWN)
3139 serial8250_release_std_resource(up);
3141 register_dev_spec_attr_grp(up);
3142 up->fcr = uart_config[up->port.type].fcr;
3146 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3148 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3149 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3150 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3151 ser->type == PORT_STARTECH)
3156 static const char *serial8250_type(struct uart_port *port)
3158 int type = port->type;
3160 if (type >= ARRAY_SIZE(uart_config))
3162 return uart_config[type].name;
3165 static const struct uart_ops serial8250_pops = {
3166 .tx_empty = serial8250_tx_empty,
3167 .set_mctrl = serial8250_set_mctrl,
3168 .get_mctrl = serial8250_get_mctrl,
3169 .stop_tx = serial8250_stop_tx,
3170 .start_tx = serial8250_start_tx,
3171 .throttle = serial8250_throttle,
3172 .unthrottle = serial8250_unthrottle,
3173 .stop_rx = serial8250_stop_rx,
3174 .enable_ms = serial8250_enable_ms,
3175 .break_ctl = serial8250_break_ctl,
3176 .startup = serial8250_startup,
3177 .shutdown = serial8250_shutdown,
3178 .set_termios = serial8250_set_termios,
3179 .set_ldisc = serial8250_set_ldisc,
3180 .pm = serial8250_pm,
3181 .type = serial8250_type,
3182 .release_port = serial8250_release_port,
3183 .request_port = serial8250_request_port,
3184 .config_port = serial8250_config_port,
3185 .verify_port = serial8250_verify_port,
3186 #ifdef CONFIG_CONSOLE_POLL
3187 .poll_get_char = serial8250_get_poll_char,
3188 .poll_put_char = serial8250_put_poll_char,
3192 void serial8250_init_port(struct uart_8250_port *up)
3194 struct uart_port *port = &up->port;
3196 spin_lock_init(&port->lock);
3198 port->ops = &serial8250_pops;
3200 up->cur_iotype = 0xFF;
3202 EXPORT_SYMBOL_GPL(serial8250_init_port);
3204 void serial8250_set_defaults(struct uart_8250_port *up)
3206 struct uart_port *port = &up->port;
3208 if (up->port.flags & UPF_FIXED_TYPE) {
3209 unsigned int type = up->port.type;
3211 if (!up->port.fifosize)
3212 up->port.fifosize = uart_config[type].fifo_size;
3214 up->tx_loadsz = uart_config[type].tx_loadsz;
3215 if (!up->capabilities)
3216 up->capabilities = uart_config[type].flags;
3219 set_io_from_upio(port);
3221 /* default dma handlers */
3223 if (!up->dma->tx_dma)
3224 up->dma->tx_dma = serial8250_tx_dma;
3225 if (!up->dma->rx_dma)
3226 up->dma->rx_dma = serial8250_rx_dma;
3229 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3231 #ifdef CONFIG_SERIAL_8250_CONSOLE
3233 static void serial8250_console_putchar(struct uart_port *port, int ch)
3235 struct uart_8250_port *up = up_to_u8250p(port);
3237 wait_for_xmitr(up, UART_LSR_THRE);
3238 serial_port_out(port, UART_TX, ch);
3242 * Restore serial console when h/w power-off detected
3244 static void serial8250_console_restore(struct uart_8250_port *up)
3246 struct uart_port *port = &up->port;
3247 struct ktermios termios;
3248 unsigned int baud, quot, frac = 0;
3250 termios.c_cflag = port->cons->cflag;
3251 termios.c_ispeed = port->cons->ispeed;
3252 termios.c_ospeed = port->cons->ospeed;
3253 if (port->state->port.tty && termios.c_cflag == 0) {
3254 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3255 termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3256 termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3259 baud = serial8250_get_baud_rate(port, &termios, NULL);
3260 quot = serial8250_get_divisor(up, baud, &frac);
3262 serial8250_set_divisor(port, baud, quot, frac);
3263 serial_port_out(port, UART_LCR, up->lcr);
3264 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3268 * Print a string to the serial port trying not to disturb
3269 * any possible real use of the port...
3271 * The console_lock must be held when we get here.
3273 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3276 struct uart_port *port = &up->port;
3277 unsigned long flags;
3281 touch_nmi_watchdog();
3283 serial8250_rpm_get(up);
3287 else if (oops_in_progress)
3288 locked = spin_trylock_irqsave(&port->lock, flags);
3290 spin_lock_irqsave(&port->lock, flags);
3293 * First save the IER then disable the interrupts
3295 ier = serial_port_in(port, UART_IER);
3297 if (up->capabilities & UART_CAP_UUE)
3298 serial_port_out(port, UART_IER, UART_IER_UUE);
3300 serial_port_out(port, UART_IER, 0);
3302 /* check scratch reg to see if port powered off during system sleep */
3303 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3304 serial8250_console_restore(up);
3308 uart_console_write(port, s, count, serial8250_console_putchar);
3311 * Finally, wait for transmitter to become empty
3312 * and restore the IER
3314 wait_for_xmitr(up, BOTH_EMPTY);
3315 serial_port_out(port, UART_IER, ier);
3318 * The receive handling will happen properly because the
3319 * receive ready bit will still be set; it is not cleared
3320 * on read. However, modem control will not, we must
3321 * call it if we have saved something in the saved flags
3322 * while processing with interrupts off.
3324 if (up->msr_saved_flags)
3325 serial8250_modem_status(up);
3328 spin_unlock_irqrestore(&port->lock, flags);
3329 serial8250_rpm_put(up);
3332 static unsigned int probe_baud(struct uart_port *port)
3334 unsigned char lcr, dll, dlm;
3337 lcr = serial_port_in(port, UART_LCR);
3338 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3339 dll = serial_port_in(port, UART_DLL);
3340 dlm = serial_port_in(port, UART_DLM);
3341 serial_port_out(port, UART_LCR, lcr);
3343 quot = (dlm << 8) | dll;
3344 return (port->uartclk / 16) / quot;
3347 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3354 if (!port->iobase && !port->membase)
3358 uart_parse_options(options, &baud, &parity, &bits, &flow);
3360 baud = probe_baud(port);
3362 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3365 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3367 MODULE_LICENSE("GPL");