1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR 7
42 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
48 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
50 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
53 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
56 * Here we define the default xmit fifo size used for each type of UART.
58 static const struct serial8250_config uart_config[] = {
83 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
84 .rxtrig_bytes = {1, 4, 8, 14},
85 .flags = UART_CAP_FIFO,
96 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
102 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
104 .rxtrig_bytes = {8, 16, 24, 28},
105 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
111 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
113 .rxtrig_bytes = {1, 16, 32, 56},
114 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
122 .name = "16C950/954",
125 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
126 .rxtrig_bytes = {16, 32, 112, 120},
127 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
128 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
134 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
136 .rxtrig_bytes = {8, 16, 56, 60},
137 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
143 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
144 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
150 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
151 .flags = UART_CAP_FIFO,
157 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
158 .flags = UART_CAP_FIFO | UART_NATSEMI,
164 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
165 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO,
178 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
179 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
185 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 .flags = UART_CAP_FIFO | UART_CAP_AFE,
192 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
194 .rxtrig_bytes = {1, 4, 8, 14},
195 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
202 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
209 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
211 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
218 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
219 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
220 .flags = UART_CAP_FIFO,
222 [PORT_BRCM_TRUMANAGE] = {
226 .flags = UART_CAP_HFIFO,
231 [PORT_ALTR_16550_F32] = {
232 .name = "Altera 16550 FIFO32",
235 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
236 .rxtrig_bytes = {1, 8, 16, 30},
237 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 [PORT_ALTR_16550_F64] = {
240 .name = "Altera 16550 FIFO64",
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .rxtrig_bytes = {1, 16, 32, 62},
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .rxtrig_bytes = {1, 32, 64, 126},
253 .flags = UART_CAP_FIFO | UART_CAP_AFE,
256 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
257 * workaround of errata A-008006 which states that tx_loadsz should
258 * be configured less than Maximum supported fifo bytes.
260 [PORT_16550A_FSL64] = {
261 .name = "16550A_FSL64",
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
266 .flags = UART_CAP_FIFO,
269 .name = "Palmchip BK-3103",
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .rxtrig_bytes = {1, 4, 8, 14},
274 .flags = UART_CAP_FIFO,
277 .name = "TI DA8xx/66AK2x",
280 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
282 .rxtrig_bytes = {1, 4, 8, 14},
283 .flags = UART_CAP_FIFO | UART_CAP_AFE,
286 .name = "MediaTek BTIF",
289 .fcr = UART_FCR_ENABLE_FIFO |
290 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
291 .flags = UART_CAP_FIFO,
294 .name = "Nuvoton 16550",
297 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
298 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
299 .rxtrig_bytes = {1, 4, 8, 14},
300 .flags = UART_CAP_FIFO,
306 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
307 .rxtrig_bytes = {1, 32, 64, 112},
308 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
312 /* Uart divisor latch read */
313 static int default_serial_dl_read(struct uart_8250_port *up)
315 /* Assign these in pieces to truncate any bits above 7. */
316 unsigned char dll = serial_in(up, UART_DLL);
317 unsigned char dlm = serial_in(up, UART_DLM);
319 return dll | dlm << 8;
322 /* Uart divisor latch write */
323 static void default_serial_dl_write(struct uart_8250_port *up, int value)
325 serial_out(up, UART_DLL, value & 0xff);
326 serial_out(up, UART_DLM, value >> 8 & 0xff);
329 #ifdef CONFIG_SERIAL_8250_RT288X
331 /* Au1x00/RT288x UART hardware has a weird register layout */
332 static const s8 au_io_in_map[8] = {
340 -1, /* UART_SCR (unmapped) */
343 static const s8 au_io_out_map[8] = {
349 -1, /* UART_LSR (unmapped) */
350 -1, /* UART_MSR (unmapped) */
351 -1, /* UART_SCR (unmapped) */
354 unsigned int au_serial_in(struct uart_port *p, int offset)
356 if (offset >= ARRAY_SIZE(au_io_in_map))
358 offset = au_io_in_map[offset];
361 return __raw_readl(p->membase + (offset << p->regshift));
364 void au_serial_out(struct uart_port *p, int offset, int value)
366 if (offset >= ARRAY_SIZE(au_io_out_map))
368 offset = au_io_out_map[offset];
371 __raw_writel(value, p->membase + (offset << p->regshift));
374 /* Au1x00 haven't got a standard divisor latch */
375 static int au_serial_dl_read(struct uart_8250_port *up)
377 return __raw_readl(up->port.membase + 0x28);
380 static void au_serial_dl_write(struct uart_8250_port *up, int value)
382 __raw_writel(value, up->port.membase + 0x28);
387 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
389 offset = offset << p->regshift;
390 outb(p->hub6 - 1 + offset, p->iobase);
391 return inb(p->iobase + 1);
394 static void hub6_serial_out(struct uart_port *p, int offset, int value)
396 offset = offset << p->regshift;
397 outb(p->hub6 - 1 + offset, p->iobase);
398 outb(value, p->iobase + 1);
401 static unsigned int mem_serial_in(struct uart_port *p, int offset)
403 offset = offset << p->regshift;
404 return readb(p->membase + offset);
407 static void mem_serial_out(struct uart_port *p, int offset, int value)
409 offset = offset << p->regshift;
410 writeb(value, p->membase + offset);
413 static void mem16_serial_out(struct uart_port *p, int offset, int value)
415 offset = offset << p->regshift;
416 writew(value, p->membase + offset);
419 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
421 offset = offset << p->regshift;
422 return readw(p->membase + offset);
425 static void mem32_serial_out(struct uart_port *p, int offset, int value)
427 offset = offset << p->regshift;
428 writel(value, p->membase + offset);
431 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
433 offset = offset << p->regshift;
434 return readl(p->membase + offset);
437 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
439 offset = offset << p->regshift;
440 iowrite32be(value, p->membase + offset);
443 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
445 offset = offset << p->regshift;
446 return ioread32be(p->membase + offset);
449 static unsigned int io_serial_in(struct uart_port *p, int offset)
451 offset = offset << p->regshift;
452 return inb(p->iobase + offset);
455 static void io_serial_out(struct uart_port *p, int offset, int value)
457 offset = offset << p->regshift;
458 outb(value, p->iobase + offset);
461 static int serial8250_default_handle_irq(struct uart_port *port);
463 static void set_io_from_upio(struct uart_port *p)
465 struct uart_8250_port *up = up_to_u8250p(p);
467 up->dl_read = default_serial_dl_read;
468 up->dl_write = default_serial_dl_write;
472 p->serial_in = hub6_serial_in;
473 p->serial_out = hub6_serial_out;
477 p->serial_in = mem_serial_in;
478 p->serial_out = mem_serial_out;
482 p->serial_in = mem16_serial_in;
483 p->serial_out = mem16_serial_out;
487 p->serial_in = mem32_serial_in;
488 p->serial_out = mem32_serial_out;
492 p->serial_in = mem32be_serial_in;
493 p->serial_out = mem32be_serial_out;
496 #ifdef CONFIG_SERIAL_8250_RT288X
498 p->serial_in = au_serial_in;
499 p->serial_out = au_serial_out;
500 up->dl_read = au_serial_dl_read;
501 up->dl_write = au_serial_dl_write;
506 p->serial_in = io_serial_in;
507 p->serial_out = io_serial_out;
510 /* Remember loaded iotype */
511 up->cur_iotype = p->iotype;
512 p->handle_irq = serial8250_default_handle_irq;
516 serial_port_out_sync(struct uart_port *p, int offset, int value)
524 p->serial_out(p, offset, value);
525 p->serial_in(p, UART_LCR); /* safe, no side-effects */
528 p->serial_out(p, offset, value);
535 static void serial8250_clear_fifos(struct uart_8250_port *p)
537 if (p->capabilities & UART_CAP_FIFO) {
538 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
539 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
540 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
541 serial_out(p, UART_FCR, 0);
545 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
546 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
548 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
550 serial8250_clear_fifos(p);
551 serial_out(p, UART_FCR, p->fcr);
553 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
555 void serial8250_rpm_get(struct uart_8250_port *p)
557 if (!(p->capabilities & UART_CAP_RPM))
559 pm_runtime_get_sync(p->port.dev);
561 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
563 void serial8250_rpm_put(struct uart_8250_port *p)
565 if (!(p->capabilities & UART_CAP_RPM))
567 pm_runtime_mark_last_busy(p->port.dev);
568 pm_runtime_put_autosuspend(p->port.dev);
570 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
573 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
574 * @p: uart_8250_port port instance
576 * The function is used to start rs485 software emulating on the
577 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
578 * transmission. The function is idempotent, so it is safe to call it
581 * The caller MUST enable interrupt on empty shift register before
582 * calling serial8250_em485_init(). This interrupt is not a part of
583 * 8250 standard, but implementation defined.
585 * The function is supposed to be called from .rs485_config callback
586 * or from any other callback protected with p->port.lock spinlock.
588 * See also serial8250_em485_destroy()
590 * Return 0 - success, -errno - otherwise
592 static int serial8250_em485_init(struct uart_8250_port *p)
597 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
601 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
603 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
605 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
606 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
608 p->em485->active_timer = NULL;
609 p->em485->tx_stopped = true;
612 if (p->em485->tx_stopped)
619 * serial8250_em485_destroy() - put uart_8250_port into normal state
620 * @p: uart_8250_port port instance
622 * The function is used to stop rs485 software emulating on the
623 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
624 * call it multiple times.
626 * The function is supposed to be called from .rs485_config callback
627 * or from any other callback protected with p->port.lock spinlock.
629 * See also serial8250_em485_init()
631 void serial8250_em485_destroy(struct uart_8250_port *p)
636 hrtimer_cancel(&p->em485->start_tx_timer);
637 hrtimer_cancel(&p->em485->stop_tx_timer);
642 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
645 * serial8250_em485_config() - generic ->rs485_config() callback
647 * @rs485: rs485 settings
649 * Generic callback usable by 8250 uart drivers to activate rs485 settings
650 * if the uart is incapable of driving RTS as a Transmit Enable signal in
651 * hardware, relying on software emulation instead.
653 int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
655 struct uart_8250_port *up = up_to_u8250p(port);
657 /* pick sane settings if the user hasn't */
658 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
659 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
660 rs485->flags |= SER_RS485_RTS_ON_SEND;
661 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
664 /* clamp the delays to [0, 100ms] */
665 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
666 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
668 memset(rs485->padding, 0, sizeof(rs485->padding));
669 port->rs485 = *rs485;
671 gpiod_set_value(port->rs485_term_gpio,
672 rs485->flags & SER_RS485_TERMINATE_BUS);
675 * Both serial8250_em485_init() and serial8250_em485_destroy()
678 if (rs485->flags & SER_RS485_ENABLED) {
679 int ret = serial8250_em485_init(up);
682 rs485->flags &= ~SER_RS485_ENABLED;
683 port->rs485.flags &= ~SER_RS485_ENABLED;
688 serial8250_em485_destroy(up);
691 EXPORT_SYMBOL_GPL(serial8250_em485_config);
694 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
695 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
696 * empty and the HW can idle again.
698 void serial8250_rpm_get_tx(struct uart_8250_port *p)
700 unsigned char rpm_active;
702 if (!(p->capabilities & UART_CAP_RPM))
705 rpm_active = xchg(&p->rpm_tx_active, 1);
708 pm_runtime_get_sync(p->port.dev);
710 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
712 void serial8250_rpm_put_tx(struct uart_8250_port *p)
714 unsigned char rpm_active;
716 if (!(p->capabilities & UART_CAP_RPM))
719 rpm_active = xchg(&p->rpm_tx_active, 0);
722 pm_runtime_mark_last_busy(p->port.dev);
723 pm_runtime_put_autosuspend(p->port.dev);
725 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
728 * IER sleep support. UARTs which have EFRs need the "extended
729 * capability" bit enabled. Note that on XR16C850s, we need to
730 * reset LCR to write to IER.
732 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
734 unsigned char lcr = 0, efr = 0;
736 serial8250_rpm_get(p);
738 if (p->capabilities & UART_CAP_SLEEP) {
739 if (p->capabilities & UART_CAP_EFR) {
740 lcr = serial_in(p, UART_LCR);
741 efr = serial_in(p, UART_EFR);
742 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
743 serial_out(p, UART_EFR, UART_EFR_ECB);
744 serial_out(p, UART_LCR, 0);
746 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
747 if (p->capabilities & UART_CAP_EFR) {
748 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
749 serial_out(p, UART_EFR, efr);
750 serial_out(p, UART_LCR, lcr);
754 serial8250_rpm_put(p);
757 #ifdef CONFIG_SERIAL_8250_RSA
759 * Attempts to turn on the RSA FIFO. Returns zero on failure.
760 * We set the port uart clock rate if we succeed.
762 static int __enable_rsa(struct uart_8250_port *up)
767 mode = serial_in(up, UART_RSA_MSR);
768 result = mode & UART_RSA_MSR_FIFO;
771 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
772 mode = serial_in(up, UART_RSA_MSR);
773 result = mode & UART_RSA_MSR_FIFO;
777 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
782 static void enable_rsa(struct uart_8250_port *up)
784 if (up->port.type == PORT_RSA) {
785 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
786 spin_lock_irq(&up->port.lock);
788 spin_unlock_irq(&up->port.lock);
790 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
791 serial_out(up, UART_RSA_FRR, 0);
796 * Attempts to turn off the RSA FIFO. Returns zero on failure.
797 * It is unknown why interrupts were disabled in here. However,
798 * the caller is expected to preserve this behaviour by grabbing
799 * the spinlock before calling this function.
801 static void disable_rsa(struct uart_8250_port *up)
806 if (up->port.type == PORT_RSA &&
807 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
808 spin_lock_irq(&up->port.lock);
810 mode = serial_in(up, UART_RSA_MSR);
811 result = !(mode & UART_RSA_MSR_FIFO);
814 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
815 mode = serial_in(up, UART_RSA_MSR);
816 result = !(mode & UART_RSA_MSR_FIFO);
820 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
821 spin_unlock_irq(&up->port.lock);
824 #endif /* CONFIG_SERIAL_8250_RSA */
827 * This is a quickie test to see how big the FIFO is.
828 * It doesn't work at all the time, more's the pity.
830 static int size_fifo(struct uart_8250_port *up)
832 unsigned char old_fcr, old_mcr, old_lcr;
833 unsigned short old_dl;
836 old_lcr = serial_in(up, UART_LCR);
837 serial_out(up, UART_LCR, 0);
838 old_fcr = serial_in(up, UART_FCR);
839 old_mcr = serial8250_in_MCR(up);
840 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
841 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
842 serial8250_out_MCR(up, UART_MCR_LOOP);
843 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
844 old_dl = serial_dl_read(up);
845 serial_dl_write(up, 0x0001);
846 serial_out(up, UART_LCR, 0x03);
847 for (count = 0; count < 256; count++)
848 serial_out(up, UART_TX, count);
849 mdelay(20);/* FIXME - schedule_timeout */
850 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
851 (count < 256); count++)
852 serial_in(up, UART_RX);
853 serial_out(up, UART_FCR, old_fcr);
854 serial8250_out_MCR(up, old_mcr);
855 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
856 serial_dl_write(up, old_dl);
857 serial_out(up, UART_LCR, old_lcr);
863 * Read UART ID using the divisor method - set DLL and DLM to zero
864 * and the revision will be in DLL and device type in DLM. We
865 * preserve the device state across this.
867 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
869 unsigned char old_lcr;
870 unsigned int id, old_dl;
872 old_lcr = serial_in(p, UART_LCR);
873 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
874 old_dl = serial_dl_read(p);
875 serial_dl_write(p, 0);
876 id = serial_dl_read(p);
877 serial_dl_write(p, old_dl);
879 serial_out(p, UART_LCR, old_lcr);
885 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
886 * When this function is called we know it is at least a StarTech
887 * 16650 V2, but it might be one of several StarTech UARTs, or one of
888 * its clones. (We treat the broken original StarTech 16650 V1 as a
889 * 16550, and why not? Startech doesn't seem to even acknowledge its
892 * What evil have men's minds wrought...
894 static void autoconfig_has_efr(struct uart_8250_port *up)
896 unsigned int id1, id2, id3, rev;
899 * Everything with an EFR has SLEEP
901 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
904 * First we check to see if it's an Oxford Semiconductor UART.
906 * If we have to do this here because some non-National
907 * Semiconductor clone chips lock up if you try writing to the
908 * LSR register (which serial_icr_read does)
912 * Check for Oxford Semiconductor 16C950.
914 * EFR [4] must be set else this test fails.
916 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
917 * claims that it's needed for 952 dual UART's (which are not
918 * recommended for new designs).
921 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
922 serial_out(up, UART_EFR, UART_EFR_ECB);
923 serial_out(up, UART_LCR, 0x00);
924 id1 = serial_icr_read(up, UART_ID1);
925 id2 = serial_icr_read(up, UART_ID2);
926 id3 = serial_icr_read(up, UART_ID3);
927 rev = serial_icr_read(up, UART_REV);
929 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
931 if (id1 == 0x16 && id2 == 0xC9 &&
932 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
933 up->port.type = PORT_16C950;
936 * Enable work around for the Oxford Semiconductor 952 rev B
937 * chip which causes it to seriously miscalculate baud rates
940 if (id3 == 0x52 && rev == 0x01)
941 up->bugs |= UART_BUG_QUOT;
946 * We check for a XR16C850 by setting DLL and DLM to 0, and then
947 * reading back DLL and DLM. The chip type depends on the DLM
949 * 0x10 - XR16C850 and the DLL contains the chip revision.
953 id1 = autoconfig_read_divisor_id(up);
954 DEBUG_AUTOCONF("850id=%04x ", id1);
957 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
958 up->port.type = PORT_16850;
963 * It wasn't an XR16C850.
965 * We distinguish between the '654 and the '650 by counting
966 * how many bytes are in the FIFO. I'm using this for now,
967 * since that's the technique that was sent to me in the
968 * serial driver update, but I'm not convinced this works.
969 * I've had problems doing this in the past. -TYT
971 if (size_fifo(up) == 64)
972 up->port.type = PORT_16654;
974 up->port.type = PORT_16650V2;
978 * We detected a chip without a FIFO. Only two fall into
979 * this category - the original 8250 and the 16450. The
980 * 16450 has a scratch register (accessible with LCR=0)
982 static void autoconfig_8250(struct uart_8250_port *up)
984 unsigned char scratch, status1, status2;
986 up->port.type = PORT_8250;
988 scratch = serial_in(up, UART_SCR);
989 serial_out(up, UART_SCR, 0xa5);
990 status1 = serial_in(up, UART_SCR);
991 serial_out(up, UART_SCR, 0x5a);
992 status2 = serial_in(up, UART_SCR);
993 serial_out(up, UART_SCR, scratch);
995 if (status1 == 0xa5 && status2 == 0x5a)
996 up->port.type = PORT_16450;
999 static int broken_efr(struct uart_8250_port *up)
1002 * Exar ST16C2550 "A2" devices incorrectly detect as
1003 * having an EFR, and report an ID of 0x0201. See
1004 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1006 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1013 * We know that the chip has FIFOs. Does it have an EFR? The
1014 * EFR is located in the same register position as the IIR and
1015 * we know the top two bits of the IIR are currently set. The
1016 * EFR should contain zero. Try to read the EFR.
1018 static void autoconfig_16550a(struct uart_8250_port *up)
1020 unsigned char status1, status2;
1021 unsigned int iersave;
1023 up->port.type = PORT_16550A;
1024 up->capabilities |= UART_CAP_FIFO;
1026 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1030 * Check for presence of the EFR when DLAB is set.
1031 * Only ST16C650V1 UARTs pass this test.
1033 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1034 if (serial_in(up, UART_EFR) == 0) {
1035 serial_out(up, UART_EFR, 0xA8);
1036 if (serial_in(up, UART_EFR) != 0) {
1037 DEBUG_AUTOCONF("EFRv1 ");
1038 up->port.type = PORT_16650;
1039 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1041 serial_out(up, UART_LCR, 0);
1042 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1044 status1 = serial_in(up, UART_IIR) >> 5;
1045 serial_out(up, UART_FCR, 0);
1046 serial_out(up, UART_LCR, 0);
1049 up->port.type = PORT_16550A_FSL64;
1051 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1053 serial_out(up, UART_EFR, 0);
1058 * Maybe it requires 0xbf to be written to the LCR.
1059 * (other ST16C650V2 UARTs, TI16C752A, etc)
1061 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1062 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1063 DEBUG_AUTOCONF("EFRv2 ");
1064 autoconfig_has_efr(up);
1069 * Check for a National Semiconductor SuperIO chip.
1070 * Attempt to switch to bank 2, read the value of the LOOP bit
1071 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1072 * switch back to bank 2, read it from EXCR1 again and check
1073 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1075 serial_out(up, UART_LCR, 0);
1076 status1 = serial8250_in_MCR(up);
1077 serial_out(up, UART_LCR, 0xE0);
1078 status2 = serial_in(up, 0x02); /* EXCR1 */
1080 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1081 serial_out(up, UART_LCR, 0);
1082 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1083 serial_out(up, UART_LCR, 0xE0);
1084 status2 = serial_in(up, 0x02); /* EXCR1 */
1085 serial_out(up, UART_LCR, 0);
1086 serial8250_out_MCR(up, status1);
1088 if ((status2 ^ status1) & UART_MCR_LOOP) {
1089 unsigned short quot;
1091 serial_out(up, UART_LCR, 0xE0);
1093 quot = serial_dl_read(up);
1096 if (ns16550a_goto_highspeed(up))
1097 serial_dl_write(up, quot);
1099 serial_out(up, UART_LCR, 0);
1101 up->port.uartclk = 921600*16;
1102 up->port.type = PORT_NS16550A;
1103 up->capabilities |= UART_NATSEMI;
1109 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1110 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1111 * Try setting it with and without DLAB set. Cheap clones
1112 * set bit 5 without DLAB set.
1114 serial_out(up, UART_LCR, 0);
1115 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1116 status1 = serial_in(up, UART_IIR) >> 5;
1117 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1118 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1119 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1120 status2 = serial_in(up, UART_IIR) >> 5;
1121 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1122 serial_out(up, UART_LCR, 0);
1124 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1126 if (status1 == 6 && status2 == 7) {
1127 up->port.type = PORT_16750;
1128 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1133 * Try writing and reading the UART_IER_UUE bit (b6).
1134 * If it works, this is probably one of the Xscale platform's
1136 * We're going to explicitly set the UUE bit to 0 before
1137 * trying to write and read a 1 just to make sure it's not
1138 * already a 1 and maybe locked there before we even start start.
1140 iersave = serial_in(up, UART_IER);
1141 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1142 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1144 * OK it's in a known zero state, try writing and reading
1145 * without disturbing the current state of the other bits.
1147 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1148 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1151 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1153 DEBUG_AUTOCONF("Xscale ");
1154 up->port.type = PORT_XSCALE;
1155 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1160 * If we got here we couldn't force the IER_UUE bit to 0.
1161 * Log it and continue.
1163 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1165 serial_out(up, UART_IER, iersave);
1168 * We distinguish between 16550A and U6 16550A by counting
1169 * how many bytes are in the FIFO.
1171 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1172 up->port.type = PORT_U6_16550A;
1173 up->capabilities |= UART_CAP_AFE;
1178 * This routine is called by rs_init() to initialize a specific serial
1179 * port. It determines what type of UART chip this serial port is
1180 * using: 8250, 16450, 16550, 16550A. The important question is
1181 * whether or not this UART is a 16550A or not, since this will
1182 * determine whether or not we can use its FIFO features or not.
1184 static void autoconfig(struct uart_8250_port *up)
1186 unsigned char status1, scratch, scratch2, scratch3;
1187 unsigned char save_lcr, save_mcr;
1188 struct uart_port *port = &up->port;
1189 unsigned long flags;
1190 unsigned int old_capabilities;
1192 if (!port->iobase && !port->mapbase && !port->membase)
1195 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1196 port->name, port->iobase, port->membase);
1199 * We really do need global IRQs disabled here - we're going to
1200 * be frobbing the chips IRQ enable register to see if it exists.
1202 spin_lock_irqsave(&port->lock, flags);
1204 up->capabilities = 0;
1207 if (!(port->flags & UPF_BUGGY_UART)) {
1209 * Do a simple existence test first; if we fail this,
1210 * there's no point trying anything else.
1212 * 0x80 is used as a nonsense port to prevent against
1213 * false positives due to ISA bus float. The
1214 * assumption is that 0x80 is a non-existent port;
1215 * which should be safe since include/asm/io.h also
1216 * makes this assumption.
1218 * Note: this is safe as long as MCR bit 4 is clear
1219 * and the device is in "PC" mode.
1221 scratch = serial_in(up, UART_IER);
1222 serial_out(up, UART_IER, 0);
1227 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1228 * 16C754B) allow only to modify them if an EFR bit is set.
1230 scratch2 = serial_in(up, UART_IER) & 0x0f;
1231 serial_out(up, UART_IER, 0x0F);
1235 scratch3 = serial_in(up, UART_IER) & 0x0f;
1236 serial_out(up, UART_IER, scratch);
1237 if (scratch2 != 0 || scratch3 != 0x0F) {
1239 * We failed; there's nothing here
1241 spin_unlock_irqrestore(&port->lock, flags);
1242 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1243 scratch2, scratch3);
1248 save_mcr = serial8250_in_MCR(up);
1249 save_lcr = serial_in(up, UART_LCR);
1252 * Check to see if a UART is really there. Certain broken
1253 * internal modems based on the Rockwell chipset fail this
1254 * test, because they apparently don't implement the loopback
1255 * test mode. So this test is skipped on the COM 1 through
1256 * COM 4 ports. This *should* be safe, since no board
1257 * manufacturer would be stupid enough to design a board
1258 * that conflicts with COM 1-4 --- we hope!
1260 if (!(port->flags & UPF_SKIP_TEST)) {
1261 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1262 status1 = serial_in(up, UART_MSR) & 0xF0;
1263 serial8250_out_MCR(up, save_mcr);
1264 if (status1 != 0x90) {
1265 spin_unlock_irqrestore(&port->lock, flags);
1266 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1273 * We're pretty sure there's a port here. Lets find out what
1274 * type of port it is. The IIR top two bits allows us to find
1275 * out if it's 8250 or 16450, 16550, 16550A or later. This
1276 * determines what we test for next.
1278 * We also initialise the EFR (if any) to zero for later. The
1279 * EFR occupies the same register location as the FCR and IIR.
1281 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1282 serial_out(up, UART_EFR, 0);
1283 serial_out(up, UART_LCR, 0);
1285 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1287 /* Assign this as it is to truncate any bits above 7. */
1288 scratch = serial_in(up, UART_IIR);
1290 switch (scratch >> 6) {
1292 autoconfig_8250(up);
1295 port->type = PORT_UNKNOWN;
1298 port->type = PORT_16550;
1301 autoconfig_16550a(up);
1305 #ifdef CONFIG_SERIAL_8250_RSA
1307 * Only probe for RSA ports if we got the region.
1309 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1311 port->type = PORT_RSA;
1314 serial_out(up, UART_LCR, save_lcr);
1316 port->fifosize = uart_config[up->port.type].fifo_size;
1317 old_capabilities = up->capabilities;
1318 up->capabilities = uart_config[port->type].flags;
1319 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1321 if (port->type == PORT_UNKNOWN)
1327 #ifdef CONFIG_SERIAL_8250_RSA
1328 if (port->type == PORT_RSA)
1329 serial_out(up, UART_RSA_FRR, 0);
1331 serial8250_out_MCR(up, save_mcr);
1332 serial8250_clear_fifos(up);
1333 serial_in(up, UART_RX);
1334 if (up->capabilities & UART_CAP_UUE)
1335 serial_out(up, UART_IER, UART_IER_UUE);
1337 serial_out(up, UART_IER, 0);
1340 spin_unlock_irqrestore(&port->lock, flags);
1343 * Check if the device is a Fintek F81216A
1345 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1346 fintek_8250_probe(up);
1348 if (up->capabilities != old_capabilities) {
1349 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1350 old_capabilities, up->capabilities);
1353 DEBUG_AUTOCONF("iir=%d ", scratch);
1354 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1357 static void autoconfig_irq(struct uart_8250_port *up)
1359 struct uart_port *port = &up->port;
1360 unsigned char save_mcr, save_ier;
1361 unsigned char save_ICP = 0;
1362 unsigned int ICP = 0;
1366 if (port->flags & UPF_FOURPORT) {
1367 ICP = (port->iobase & 0xfe0) | 0x1f;
1368 save_ICP = inb_p(ICP);
1373 if (uart_console(port))
1376 /* forget possible initially masked and pending IRQ */
1377 probe_irq_off(probe_irq_on());
1378 save_mcr = serial8250_in_MCR(up);
1379 save_ier = serial_in(up, UART_IER);
1380 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1382 irqs = probe_irq_on();
1383 serial8250_out_MCR(up, 0);
1385 if (port->flags & UPF_FOURPORT) {
1386 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1388 serial8250_out_MCR(up,
1389 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1391 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1392 serial_in(up, UART_LSR);
1393 serial_in(up, UART_RX);
1394 serial_in(up, UART_IIR);
1395 serial_in(up, UART_MSR);
1396 serial_out(up, UART_TX, 0xFF);
1398 irq = probe_irq_off(irqs);
1400 serial8250_out_MCR(up, save_mcr);
1401 serial_out(up, UART_IER, save_ier);
1403 if (port->flags & UPF_FOURPORT)
1404 outb_p(save_ICP, ICP);
1406 if (uart_console(port))
1409 port->irq = (irq > 0) ? irq : 0;
1412 static void serial8250_stop_rx(struct uart_port *port)
1414 struct uart_8250_port *up = up_to_u8250p(port);
1416 serial8250_rpm_get(up);
1418 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1419 up->port.read_status_mask &= ~UART_LSR_DR;
1420 serial_port_out(port, UART_IER, up->ier);
1422 serial8250_rpm_put(up);
1426 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1427 * @p: uart 8250 port
1429 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1431 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1433 unsigned char mcr = serial8250_in_MCR(p);
1435 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1436 mcr |= UART_MCR_RTS;
1438 mcr &= ~UART_MCR_RTS;
1439 serial8250_out_MCR(p, mcr);
1442 * Empty the RX FIFO, we are not interested in anything
1443 * received during the half-duplex transmission.
1444 * Enable previously disabled RX interrupts.
1446 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1447 serial8250_clear_and_reinit_fifos(p);
1449 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1450 serial_port_out(&p->port, UART_IER, p->ier);
1453 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1455 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1457 struct uart_8250_em485 *em485;
1458 struct uart_8250_port *p;
1459 unsigned long flags;
1461 em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1464 serial8250_rpm_get(p);
1465 spin_lock_irqsave(&p->port.lock, flags);
1466 if (em485->active_timer == &em485->stop_tx_timer) {
1467 p->rs485_stop_tx(p);
1468 em485->active_timer = NULL;
1469 em485->tx_stopped = true;
1471 spin_unlock_irqrestore(&p->port.lock, flags);
1472 serial8250_rpm_put(p);
1473 return HRTIMER_NORESTART;
1476 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1478 long sec = msec / 1000;
1479 long nsec = (msec % 1000) * 1000000;
1480 ktime_t t = ktime_set(sec, nsec);
1482 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1485 static void __stop_tx_rs485(struct uart_8250_port *p)
1487 struct uart_8250_em485 *em485 = p->em485;
1490 * rs485_stop_tx() is going to set RTS according to config
1491 * AND flush RX FIFO if required.
1493 if (p->port.rs485.delay_rts_after_send > 0) {
1494 em485->active_timer = &em485->stop_tx_timer;
1495 start_hrtimer_ms(&em485->stop_tx_timer,
1496 p->port.rs485.delay_rts_after_send);
1498 p->rs485_stop_tx(p);
1499 em485->active_timer = NULL;
1500 em485->tx_stopped = true;
1504 static inline void __do_stop_tx(struct uart_8250_port *p)
1506 if (serial8250_clear_THRI(p))
1507 serial8250_rpm_put_tx(p);
1510 static inline void __stop_tx(struct uart_8250_port *p)
1512 struct uart_8250_em485 *em485 = p->em485;
1515 unsigned char lsr = serial_in(p, UART_LSR);
1516 p->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1519 * To provide required timeing and allow FIFO transfer,
1520 * __stop_tx_rs485() must be called only when both FIFO and
1521 * shift register are empty. It is for device driver to enable
1522 * interrupt on TEMT.
1524 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1532 static void serial8250_stop_tx(struct uart_port *port)
1534 struct uart_8250_port *up = up_to_u8250p(port);
1536 serial8250_rpm_get(up);
1540 * We really want to stop the transmitter from sending.
1542 if (port->type == PORT_16C950) {
1543 up->acr |= UART_ACR_TXDIS;
1544 serial_icr_write(up, UART_ACR, up->acr);
1546 serial8250_rpm_put(up);
1549 static inline void __start_tx(struct uart_port *port)
1551 struct uart_8250_port *up = up_to_u8250p(port);
1553 if (up->dma && !up->dma->tx_dma(up))
1556 if (serial8250_set_THRI(up)) {
1557 if (up->bugs & UART_BUG_TXEN) {
1560 lsr = serial_in(up, UART_LSR);
1561 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1562 if (lsr & UART_LSR_THRE)
1563 serial8250_tx_chars(up);
1568 * Re-enable the transmitter if we disabled it.
1570 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1571 up->acr &= ~UART_ACR_TXDIS;
1572 serial_icr_write(up, UART_ACR, up->acr);
1577 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1578 * @up: uart 8250 port
1580 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1581 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1582 * (Some chips use inverse semantics.) Further assumes that reception is
1583 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1584 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1586 void serial8250_em485_start_tx(struct uart_8250_port *up)
1588 unsigned char mcr = serial8250_in_MCR(up);
1590 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1591 serial8250_stop_rx(&up->port);
1593 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1594 mcr |= UART_MCR_RTS;
1596 mcr &= ~UART_MCR_RTS;
1597 serial8250_out_MCR(up, mcr);
1599 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1601 static inline void start_tx_rs485(struct uart_port *port)
1603 struct uart_8250_port *up = up_to_u8250p(port);
1604 struct uart_8250_em485 *em485 = up->em485;
1607 * While serial8250_em485_handle_stop_tx() is a noop if
1608 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1609 * the timer is still armed and triggers only after the current bunch of
1610 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1611 * So cancel the timer. There is still a theoretical race condition if
1612 * the timer is already running and only comes around to check for
1613 * em485->active_timer when &em485->stop_tx_timer is armed again.
1615 if (em485->active_timer == &em485->stop_tx_timer)
1616 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1618 em485->active_timer = NULL;
1620 if (em485->tx_stopped) {
1621 em485->tx_stopped = false;
1623 up->rs485_start_tx(up);
1625 if (up->port.rs485.delay_rts_before_send > 0) {
1626 em485->active_timer = &em485->start_tx_timer;
1627 start_hrtimer_ms(&em485->start_tx_timer,
1628 up->port.rs485.delay_rts_before_send);
1636 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1638 struct uart_8250_em485 *em485;
1639 struct uart_8250_port *p;
1640 unsigned long flags;
1642 em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1645 spin_lock_irqsave(&p->port.lock, flags);
1646 if (em485->active_timer == &em485->start_tx_timer) {
1647 __start_tx(&p->port);
1648 em485->active_timer = NULL;
1650 spin_unlock_irqrestore(&p->port.lock, flags);
1651 return HRTIMER_NORESTART;
1654 static void serial8250_start_tx(struct uart_port *port)
1656 struct uart_8250_port *up = up_to_u8250p(port);
1657 struct uart_8250_em485 *em485 = up->em485;
1659 serial8250_rpm_get_tx(up);
1662 em485->active_timer == &em485->start_tx_timer)
1666 start_tx_rs485(port);
1671 static void serial8250_throttle(struct uart_port *port)
1673 port->throttle(port);
1676 static void serial8250_unthrottle(struct uart_port *port)
1678 port->unthrottle(port);
1681 static void serial8250_disable_ms(struct uart_port *port)
1683 struct uart_8250_port *up = up_to_u8250p(port);
1685 /* no MSR capabilities */
1686 if (up->bugs & UART_BUG_NOMSR)
1689 mctrl_gpio_disable_ms(up->gpios);
1691 up->ier &= ~UART_IER_MSI;
1692 serial_port_out(port, UART_IER, up->ier);
1695 static void serial8250_enable_ms(struct uart_port *port)
1697 struct uart_8250_port *up = up_to_u8250p(port);
1699 /* no MSR capabilities */
1700 if (up->bugs & UART_BUG_NOMSR)
1703 mctrl_gpio_enable_ms(up->gpios);
1705 up->ier |= UART_IER_MSI;
1707 serial8250_rpm_get(up);
1708 serial_port_out(port, UART_IER, up->ier);
1709 serial8250_rpm_put(up);
1712 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1714 struct uart_port *port = &up->port;
1716 char flag = TTY_NORMAL;
1718 if (likely(lsr & UART_LSR_DR))
1719 ch = serial_in(up, UART_RX);
1722 * Intel 82571 has a Serial Over Lan device that will
1723 * set UART_LSR_BI without setting UART_LSR_DR when
1724 * it receives a break. To avoid reading from the
1725 * receive buffer without UART_LSR_DR bit set, we
1726 * just force the read character to be 0
1732 lsr |= up->lsr_saved_flags;
1733 up->lsr_saved_flags = 0;
1735 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1736 if (lsr & UART_LSR_BI) {
1737 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1740 * We do the SysRQ and SAK checking
1741 * here because otherwise the break
1742 * may get masked by ignore_status_mask
1743 * or read_status_mask.
1745 if (uart_handle_break(port))
1747 } else if (lsr & UART_LSR_PE)
1748 port->icount.parity++;
1749 else if (lsr & UART_LSR_FE)
1750 port->icount.frame++;
1751 if (lsr & UART_LSR_OE)
1752 port->icount.overrun++;
1755 * Mask off conditions which should be ignored.
1757 lsr &= port->read_status_mask;
1759 if (lsr & UART_LSR_BI) {
1760 dev_dbg(port->dev, "handling break\n");
1762 } else if (lsr & UART_LSR_PE)
1764 else if (lsr & UART_LSR_FE)
1767 if (uart_prepare_sysrq_char(port, ch))
1770 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1772 EXPORT_SYMBOL_GPL(serial8250_read_char);
1775 * serial8250_rx_chars: processes according to the passed in LSR
1776 * value, and returns the remaining LSR bits not handled
1777 * by this Rx routine.
1779 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1781 struct uart_port *port = &up->port;
1782 int max_count = 256;
1785 serial8250_read_char(up, lsr);
1786 if (--max_count == 0)
1788 lsr = serial_in(up, UART_LSR);
1789 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1791 tty_flip_buffer_push(&port->state->port);
1794 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1796 void serial8250_tx_chars(struct uart_8250_port *up)
1798 struct uart_port *port = &up->port;
1799 struct circ_buf *xmit = &port->state->xmit;
1803 uart_xchar_out(port, UART_TX);
1806 if (uart_tx_stopped(port)) {
1807 serial8250_stop_tx(port);
1810 if (uart_circ_empty(xmit)) {
1815 count = up->tx_loadsz;
1817 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1818 if (up->bugs & UART_BUG_TXRACE) {
1820 * The Aspeed BMC virtual UARTs have a bug where data
1821 * may get stuck in the BMC's Tx FIFO from bursts of
1822 * writes on the APB interface.
1824 * Delay back-to-back writes by a read cycle to avoid
1825 * stalling the VUART. Read a register that won't have
1826 * side-effects and discard the result.
1828 serial_in(up, UART_SCR);
1830 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1832 if (uart_circ_empty(xmit))
1834 if ((up->capabilities & UART_CAP_HFIFO) &&
1835 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1837 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1838 if ((up->capabilities & UART_CAP_MINI) &&
1839 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1841 } while (--count > 0);
1843 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1844 uart_write_wakeup(port);
1847 * With RPM enabled, we have to wait until the FIFO is empty before the
1848 * HW can go idle. So we get here once again with empty FIFO and disable
1849 * the interrupt and RPM in __stop_tx()
1851 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1854 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1856 /* Caller holds uart port lock */
1857 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1859 struct uart_port *port = &up->port;
1860 unsigned int status = serial_in(up, UART_MSR);
1862 status |= up->msr_saved_flags;
1863 up->msr_saved_flags = 0;
1864 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1865 port->state != NULL) {
1866 if (status & UART_MSR_TERI)
1868 if (status & UART_MSR_DDSR)
1870 if (status & UART_MSR_DDCD)
1871 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1872 if (status & UART_MSR_DCTS)
1873 uart_handle_cts_change(port, status & UART_MSR_CTS);
1875 wake_up_interruptible(&port->state->port.delta_msr_wait);
1880 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1882 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1884 switch (iir & 0x3f) {
1885 case UART_IIR_RX_TIMEOUT:
1886 serial8250_rx_dma_flush(up);
1891 return up->dma->rx_dma(up);
1895 * This handles the interrupt from one port.
1897 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1899 unsigned char status;
1900 unsigned long flags;
1901 struct uart_8250_port *up = up_to_u8250p(port);
1902 bool skip_rx = false;
1904 if (iir & UART_IIR_NO_INT)
1907 spin_lock_irqsave(&port->lock, flags);
1909 status = serial_port_in(port, UART_LSR);
1912 * If port is stopped and there are no error conditions in the
1913 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1914 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1915 * control when FIFO occupancy reaches preset threshold, thus
1916 * halting RX. This only works when auto HW flow control is
1919 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1920 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1921 !(port->read_status_mask & UART_LSR_DR))
1924 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1925 if (!up->dma || handle_rx_dma(up, iir))
1926 status = serial8250_rx_chars(up, status);
1928 serial8250_modem_status(up);
1929 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1930 (up->ier & UART_IER_THRI))
1931 serial8250_tx_chars(up);
1933 uart_unlock_and_check_sysrq(port, flags);
1936 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1938 static int serial8250_default_handle_irq(struct uart_port *port)
1940 struct uart_8250_port *up = up_to_u8250p(port);
1944 serial8250_rpm_get(up);
1946 iir = serial_port_in(port, UART_IIR);
1947 ret = serial8250_handle_irq(port, iir);
1949 serial8250_rpm_put(up);
1954 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1955 * have a programmable TX threshold that triggers the THRE interrupt in
1956 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1957 * has space available. Load it up with tx_loadsz bytes.
1959 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1961 unsigned long flags;
1962 unsigned int iir = serial_port_in(port, UART_IIR);
1964 /* TX Threshold IRQ triggered so load up FIFO */
1965 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1966 struct uart_8250_port *up = up_to_u8250p(port);
1968 spin_lock_irqsave(&port->lock, flags);
1969 serial8250_tx_chars(up);
1970 spin_unlock_irqrestore(&port->lock, flags);
1973 iir = serial_port_in(port, UART_IIR);
1974 return serial8250_handle_irq(port, iir);
1977 static unsigned int serial8250_tx_empty(struct uart_port *port)
1979 struct uart_8250_port *up = up_to_u8250p(port);
1980 unsigned long flags;
1983 serial8250_rpm_get(up);
1985 spin_lock_irqsave(&port->lock, flags);
1986 lsr = serial_port_in(port, UART_LSR);
1987 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1988 spin_unlock_irqrestore(&port->lock, flags);
1990 serial8250_rpm_put(up);
1992 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1995 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1997 struct uart_8250_port *up = up_to_u8250p(port);
1998 unsigned int status;
2001 serial8250_rpm_get(up);
2002 status = serial8250_modem_status(up);
2003 serial8250_rpm_put(up);
2005 val = serial8250_MSR_to_TIOCM(status);
2007 return mctrl_gpio_get(up->gpios, &val);
2011 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2013 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2015 if (port->get_mctrl)
2016 return port->get_mctrl(port);
2017 return serial8250_do_get_mctrl(port);
2020 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2022 struct uart_8250_port *up = up_to_u8250p(port);
2025 mcr = serial8250_TIOCM_to_MCR(mctrl);
2027 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2029 serial8250_out_MCR(up, mcr);
2031 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2033 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2035 if (port->rs485.flags & SER_RS485_ENABLED)
2038 if (port->set_mctrl)
2039 port->set_mctrl(port, mctrl);
2041 serial8250_do_set_mctrl(port, mctrl);
2044 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2046 struct uart_8250_port *up = up_to_u8250p(port);
2047 unsigned long flags;
2049 serial8250_rpm_get(up);
2050 spin_lock_irqsave(&port->lock, flags);
2051 if (break_state == -1)
2052 up->lcr |= UART_LCR_SBC;
2054 up->lcr &= ~UART_LCR_SBC;
2055 serial_port_out(port, UART_LCR, up->lcr);
2056 spin_unlock_irqrestore(&port->lock, flags);
2057 serial8250_rpm_put(up);
2061 * Wait for transmitter & holding register to empty
2063 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2065 unsigned int status, tmout = 10000;
2067 /* Wait up to 10ms for the character(s) to be sent. */
2069 status = serial_in(up, UART_LSR);
2071 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2073 if ((status & bits) == bits)
2078 touch_nmi_watchdog();
2081 /* Wait up to 1s for flow control if necessary */
2082 if (up->port.flags & UPF_CONS_FLOW) {
2083 for (tmout = 1000000; tmout; tmout--) {
2084 unsigned int msr = serial_in(up, UART_MSR);
2085 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2086 if (msr & UART_MSR_CTS)
2089 touch_nmi_watchdog();
2094 #ifdef CONFIG_CONSOLE_POLL
2096 * Console polling routines for writing and reading from the uart while
2097 * in an interrupt or debug context.
2100 static int serial8250_get_poll_char(struct uart_port *port)
2102 struct uart_8250_port *up = up_to_u8250p(port);
2106 serial8250_rpm_get(up);
2108 lsr = serial_port_in(port, UART_LSR);
2110 if (!(lsr & UART_LSR_DR)) {
2111 status = NO_POLL_CHAR;
2115 status = serial_port_in(port, UART_RX);
2117 serial8250_rpm_put(up);
2122 static void serial8250_put_poll_char(struct uart_port *port,
2126 struct uart_8250_port *up = up_to_u8250p(port);
2128 serial8250_rpm_get(up);
2130 * First save the IER then disable the interrupts
2132 ier = serial_port_in(port, UART_IER);
2133 if (up->capabilities & UART_CAP_UUE)
2134 serial_port_out(port, UART_IER, UART_IER_UUE);
2136 serial_port_out(port, UART_IER, 0);
2138 wait_for_xmitr(up, BOTH_EMPTY);
2140 * Send the character out.
2142 serial_port_out(port, UART_TX, c);
2145 * Finally, wait for transmitter to become empty
2146 * and restore the IER
2148 wait_for_xmitr(up, BOTH_EMPTY);
2149 serial_port_out(port, UART_IER, ier);
2150 serial8250_rpm_put(up);
2153 #endif /* CONFIG_CONSOLE_POLL */
2155 int serial8250_do_startup(struct uart_port *port)
2157 struct uart_8250_port *up = up_to_u8250p(port);
2158 unsigned long flags;
2159 unsigned char lsr, iir;
2162 if (!port->fifosize)
2163 port->fifosize = uart_config[port->type].fifo_size;
2165 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2166 if (!up->capabilities)
2167 up->capabilities = uart_config[port->type].flags;
2170 if (port->iotype != up->cur_iotype)
2171 set_io_from_upio(port);
2173 serial8250_rpm_get(up);
2174 if (port->type == PORT_16C950) {
2175 /* Wake up and initialize UART */
2177 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2178 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2179 serial_port_out(port, UART_IER, 0);
2180 serial_port_out(port, UART_LCR, 0);
2181 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2182 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2183 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2184 serial_port_out(port, UART_LCR, 0);
2187 if (port->type == PORT_DA830) {
2188 /* Reset the port */
2189 serial_port_out(port, UART_IER, 0);
2190 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2193 /* Enable Tx, Rx and free run mode */
2194 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2195 UART_DA830_PWREMU_MGMT_UTRST |
2196 UART_DA830_PWREMU_MGMT_URRST |
2197 UART_DA830_PWREMU_MGMT_FREE);
2200 if (port->type == PORT_NPCM) {
2202 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2203 * register). Enable it, and set TIOC (timeout interrupt
2204 * comparator) to be 0x20 for correct operation.
2206 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2209 #ifdef CONFIG_SERIAL_8250_RSA
2211 * If this is an RSA port, see if we can kick it up to the
2212 * higher speed clock.
2218 * Clear the FIFO buffers and disable them.
2219 * (they will be reenabled in set_termios())
2221 serial8250_clear_fifos(up);
2224 * Clear the interrupt registers.
2226 serial_port_in(port, UART_LSR);
2227 serial_port_in(port, UART_RX);
2228 serial_port_in(port, UART_IIR);
2229 serial_port_in(port, UART_MSR);
2232 * At this point, there's no way the LSR could still be 0xff;
2233 * if it is, then bail out, because there's likely no UART
2236 if (!(port->flags & UPF_BUGGY_UART) &&
2237 (serial_port_in(port, UART_LSR) == 0xff)) {
2238 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2244 * For a XR16C850, we need to set the trigger levels
2246 if (port->type == PORT_16850) {
2249 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2251 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2252 serial_port_out(port, UART_FCTR,
2253 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2254 serial_port_out(port, UART_TRG, UART_TRG_96);
2255 serial_port_out(port, UART_FCTR,
2256 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2257 serial_port_out(port, UART_TRG, UART_TRG_96);
2259 serial_port_out(port, UART_LCR, 0);
2263 * For the Altera 16550 variants, set TX threshold trigger level.
2265 if (((port->type == PORT_ALTR_16550_F32) ||
2266 (port->type == PORT_ALTR_16550_F64) ||
2267 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2268 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2269 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2270 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2272 serial_port_out(port, UART_ALTR_AFR,
2273 UART_ALTR_EN_TXFIFO_LW);
2274 serial_port_out(port, UART_ALTR_TX_LOW,
2275 port->fifosize - up->tx_loadsz);
2276 port->handle_irq = serial8250_tx_threshold_handle_irq;
2280 /* Check if we need to have shared IRQs */
2281 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2282 up->port.irqflags |= IRQF_SHARED;
2284 retval = up->ops->setup_irq(up);
2288 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2291 if (port->irqflags & IRQF_SHARED)
2292 disable_irq_nosync(port->irq);
2295 * Test for UARTs that do not reassert THRE when the
2296 * transmitter is idle and the interrupt has already
2297 * been cleared. Real 16550s should always reassert
2298 * this interrupt whenever the transmitter is idle and
2299 * the interrupt is enabled. Delays are necessary to
2300 * allow register changes to become visible.
2302 spin_lock_irqsave(&port->lock, flags);
2304 wait_for_xmitr(up, UART_LSR_THRE);
2305 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2306 udelay(1); /* allow THRE to set */
2307 iir1 = serial_port_in(port, UART_IIR);
2308 serial_port_out(port, UART_IER, 0);
2309 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2310 udelay(1); /* allow a working UART time to re-assert THRE */
2311 iir = serial_port_in(port, UART_IIR);
2312 serial_port_out(port, UART_IER, 0);
2314 spin_unlock_irqrestore(&port->lock, flags);
2316 if (port->irqflags & IRQF_SHARED)
2317 enable_irq(port->irq);
2320 * If the interrupt is not reasserted, or we otherwise
2321 * don't trust the iir, setup a timer to kick the UART
2322 * on a regular basis.
2324 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2325 up->port.flags & UPF_BUG_THRE) {
2326 up->bugs |= UART_BUG_THRE;
2330 up->ops->setup_timer(up);
2333 * Now, initialize the UART
2335 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2337 spin_lock_irqsave(&port->lock, flags);
2338 if (up->port.flags & UPF_FOURPORT) {
2340 up->port.mctrl |= TIOCM_OUT1;
2343 * Most PC uarts need OUT2 raised to enable interrupts.
2346 up->port.mctrl |= TIOCM_OUT2;
2348 serial8250_set_mctrl(port, port->mctrl);
2351 * Serial over Lan (SoL) hack:
2352 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2353 * used for Serial Over Lan. Those chips take a longer time than a
2354 * normal serial device to signalize that a transmission data was
2355 * queued. Due to that, the above test generally fails. One solution
2356 * would be to delay the reading of iir. However, this is not
2357 * reliable, since the timeout is variable. So, let's just don't
2358 * test if we receive TX irq. This way, we'll never enable
2361 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2362 goto dont_test_tx_en;
2365 * Do a quick test to see if we receive an interrupt when we enable
2368 serial_port_out(port, UART_IER, UART_IER_THRI);
2369 lsr = serial_port_in(port, UART_LSR);
2370 iir = serial_port_in(port, UART_IIR);
2371 serial_port_out(port, UART_IER, 0);
2373 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2374 if (!(up->bugs & UART_BUG_TXEN)) {
2375 up->bugs |= UART_BUG_TXEN;
2376 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2379 up->bugs &= ~UART_BUG_TXEN;
2383 spin_unlock_irqrestore(&port->lock, flags);
2386 * Clear the interrupt registers again for luck, and clear the
2387 * saved flags to avoid getting false values from polling
2388 * routines or the previous session.
2390 serial_port_in(port, UART_LSR);
2391 serial_port_in(port, UART_RX);
2392 serial_port_in(port, UART_IIR);
2393 serial_port_in(port, UART_MSR);
2394 up->lsr_saved_flags = 0;
2395 up->msr_saved_flags = 0;
2398 * Request DMA channels for both RX and TX.
2401 const char *msg = NULL;
2403 if (uart_console(port))
2404 msg = "forbid DMA for kernel console";
2405 else if (serial8250_request_dma(up))
2406 msg = "failed to request DMA";
2408 dev_warn_ratelimited(port->dev, "%s\n", msg);
2414 * Set the IER shadow for rx interrupts but defer actual interrupt
2415 * enable until after the FIFOs are enabled; otherwise, an already-
2416 * active sender can swamp the interrupt handler with "too much work".
2418 up->ier = UART_IER_RLSI | UART_IER_RDI;
2420 if (port->flags & UPF_FOURPORT) {
2423 * Enable interrupts on the AST Fourport board
2425 icp = (port->iobase & 0xfe0) | 0x01f;
2431 serial8250_rpm_put(up);
2434 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2436 static int serial8250_startup(struct uart_port *port)
2439 return port->startup(port);
2440 return serial8250_do_startup(port);
2443 void serial8250_do_shutdown(struct uart_port *port)
2445 struct uart_8250_port *up = up_to_u8250p(port);
2446 unsigned long flags;
2448 serial8250_rpm_get(up);
2450 * Disable interrupts from this port
2452 spin_lock_irqsave(&port->lock, flags);
2454 serial_port_out(port, UART_IER, 0);
2455 spin_unlock_irqrestore(&port->lock, flags);
2457 synchronize_irq(port->irq);
2460 serial8250_release_dma(up);
2462 spin_lock_irqsave(&port->lock, flags);
2463 if (port->flags & UPF_FOURPORT) {
2464 /* reset interrupts on the AST Fourport board */
2465 inb((port->iobase & 0xfe0) | 0x1f);
2466 port->mctrl |= TIOCM_OUT1;
2468 port->mctrl &= ~TIOCM_OUT2;
2470 serial8250_set_mctrl(port, port->mctrl);
2471 spin_unlock_irqrestore(&port->lock, flags);
2474 * Disable break condition and FIFOs
2476 serial_port_out(port, UART_LCR,
2477 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2478 serial8250_clear_fifos(up);
2480 #ifdef CONFIG_SERIAL_8250_RSA
2482 * Reset the RSA board back to 115kbps compat mode.
2488 * Read data port to reset things, and then unlink from
2491 serial_port_in(port, UART_RX);
2492 serial8250_rpm_put(up);
2494 up->ops->release_irq(up);
2496 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2498 static void serial8250_shutdown(struct uart_port *port)
2501 port->shutdown(port);
2503 serial8250_do_shutdown(port);
2506 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2507 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2510 struct uart_port *port = &up->port;
2512 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2515 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2519 struct uart_8250_port *up = up_to_u8250p(port);
2523 * Handle magic divisors for baud rates above baud_base on
2524 * SMSC SuperIO chips.
2527 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2528 baud == (port->uartclk/4))
2530 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2531 baud == (port->uartclk/8))
2533 else if (up->port.type == PORT_NPCM)
2534 quot = npcm_get_divisor(up, baud);
2536 quot = uart_get_divisor(port, baud);
2539 * Oxford Semi 952 rev B workaround
2541 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2547 static unsigned int serial8250_get_divisor(struct uart_port *port,
2551 if (port->get_divisor)
2552 return port->get_divisor(port, baud, frac);
2554 return serial8250_do_get_divisor(port, baud, frac);
2557 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2562 switch (c_cflag & CSIZE) {
2564 cval = UART_LCR_WLEN5;
2567 cval = UART_LCR_WLEN6;
2570 cval = UART_LCR_WLEN7;
2574 cval = UART_LCR_WLEN8;
2578 if (c_cflag & CSTOPB)
2579 cval |= UART_LCR_STOP;
2580 if (c_cflag & PARENB) {
2581 cval |= UART_LCR_PARITY;
2582 if (up->bugs & UART_BUG_PARITY)
2583 up->fifo_bug = true;
2585 if (!(c_cflag & PARODD))
2586 cval |= UART_LCR_EPAR;
2588 if (c_cflag & CMSPAR)
2589 cval |= UART_LCR_SPAR;
2595 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2596 unsigned int quot, unsigned int quot_frac)
2598 struct uart_8250_port *up = up_to_u8250p(port);
2600 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2601 if (is_omap1510_8250(up)) {
2602 if (baud == 115200) {
2604 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2606 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2610 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2611 * otherwise just set DLAB
2613 if (up->capabilities & UART_NATSEMI)
2614 serial_port_out(port, UART_LCR, 0xe0);
2616 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2618 serial_dl_write(up, quot);
2620 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2622 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2623 unsigned int quot, unsigned int quot_frac)
2625 if (port->set_divisor)
2626 port->set_divisor(port, baud, quot, quot_frac);
2628 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2631 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2632 struct ktermios *termios,
2633 struct ktermios *old)
2635 unsigned int tolerance = port->uartclk / 100;
2640 * Handle magic divisors for baud rates above baud_base on SMSC
2641 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2642 * disable divisor values beyond 32767, which are unavailable.
2644 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2645 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2646 max = (port->uartclk + tolerance) / 4;
2648 min = port->uartclk / 16 / UART_DIV_MAX;
2649 max = (port->uartclk + tolerance) / 16;
2653 * Ask the core to calculate the divisor for us.
2654 * Allow 1% tolerance at the upper limit so uart clks marginally
2655 * slower than nominal still match standard baud rates without
2656 * causing transmission errors.
2658 return uart_get_baud_rate(port, termios, old, min, max);
2662 * Note in order to avoid the tty port mutex deadlock don't use the next method
2663 * within the uart port callbacks. Primarily it's supposed to be utilized to
2664 * handle a sudden reference clock rate change.
2666 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2668 struct uart_8250_port *up = up_to_u8250p(port);
2669 struct tty_port *tport = &port->state->port;
2670 unsigned int baud, quot, frac = 0;
2671 struct ktermios *termios;
2672 struct tty_struct *tty;
2673 unsigned long flags;
2675 tty = tty_port_tty_get(tport);
2677 mutex_lock(&tport->mutex);
2678 port->uartclk = uartclk;
2679 mutex_unlock(&tport->mutex);
2683 down_write(&tty->termios_rwsem);
2684 mutex_lock(&tport->mutex);
2686 if (port->uartclk == uartclk)
2689 port->uartclk = uartclk;
2691 if (!tty_port_initialized(tport))
2694 termios = &tty->termios;
2696 baud = serial8250_get_baud_rate(port, termios, NULL);
2697 quot = serial8250_get_divisor(port, baud, &frac);
2699 serial8250_rpm_get(up);
2700 spin_lock_irqsave(&port->lock, flags);
2702 uart_update_timeout(port, termios->c_cflag, baud);
2704 serial8250_set_divisor(port, baud, quot, frac);
2705 serial_port_out(port, UART_LCR, up->lcr);
2707 spin_unlock_irqrestore(&port->lock, flags);
2708 serial8250_rpm_put(up);
2711 mutex_unlock(&tport->mutex);
2712 up_write(&tty->termios_rwsem);
2715 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2718 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2719 struct ktermios *old)
2721 struct uart_8250_port *up = up_to_u8250p(port);
2723 unsigned long flags;
2724 unsigned int baud, quot, frac = 0;
2726 if (up->capabilities & UART_CAP_MINI) {
2727 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2728 if ((termios->c_cflag & CSIZE) == CS5 ||
2729 (termios->c_cflag & CSIZE) == CS6)
2730 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2732 cval = serial8250_compute_lcr(up, termios->c_cflag);
2734 baud = serial8250_get_baud_rate(port, termios, old);
2735 quot = serial8250_get_divisor(port, baud, &frac);
2738 * Ok, we're now changing the port state. Do it with
2739 * interrupts disabled.
2741 serial8250_rpm_get(up);
2742 spin_lock_irqsave(&port->lock, flags);
2744 up->lcr = cval; /* Save computed LCR */
2746 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2747 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2748 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2749 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2750 up->fcr |= UART_FCR_TRIGGER_1;
2755 * MCR-based auto flow control. When AFE is enabled, RTS will be
2756 * deasserted when the receive FIFO contains more characters than
2757 * the trigger, or the MCR RTS bit is cleared.
2759 if (up->capabilities & UART_CAP_AFE) {
2760 up->mcr &= ~UART_MCR_AFE;
2761 if (termios->c_cflag & CRTSCTS)
2762 up->mcr |= UART_MCR_AFE;
2766 * Update the per-port timeout.
2768 uart_update_timeout(port, termios->c_cflag, baud);
2770 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2771 if (termios->c_iflag & INPCK)
2772 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2773 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2774 port->read_status_mask |= UART_LSR_BI;
2777 * Characteres to ignore
2779 port->ignore_status_mask = 0;
2780 if (termios->c_iflag & IGNPAR)
2781 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2782 if (termios->c_iflag & IGNBRK) {
2783 port->ignore_status_mask |= UART_LSR_BI;
2785 * If we're ignoring parity and break indicators,
2786 * ignore overruns too (for real raw support).
2788 if (termios->c_iflag & IGNPAR)
2789 port->ignore_status_mask |= UART_LSR_OE;
2793 * ignore all characters if CREAD is not set
2795 if ((termios->c_cflag & CREAD) == 0)
2796 port->ignore_status_mask |= UART_LSR_DR;
2799 * CTS flow control flag and modem status interrupts
2801 up->ier &= ~UART_IER_MSI;
2802 if (!(up->bugs & UART_BUG_NOMSR) &&
2803 UART_ENABLE_MS(&up->port, termios->c_cflag))
2804 up->ier |= UART_IER_MSI;
2805 if (up->capabilities & UART_CAP_UUE)
2806 up->ier |= UART_IER_UUE;
2807 if (up->capabilities & UART_CAP_RTOIE)
2808 up->ier |= UART_IER_RTOIE;
2810 serial_port_out(port, UART_IER, up->ier);
2812 if (up->capabilities & UART_CAP_EFR) {
2813 unsigned char efr = 0;
2815 * TI16C752/Startech hardware flow control. FIXME:
2816 * - TI16C752 requires control thresholds to be set.
2817 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2819 if (termios->c_cflag & CRTSCTS)
2820 efr |= UART_EFR_CTS;
2822 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2823 if (port->flags & UPF_EXAR_EFR)
2824 serial_port_out(port, UART_XR_EFR, efr);
2826 serial_port_out(port, UART_EFR, efr);
2829 serial8250_set_divisor(port, baud, quot, frac);
2832 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2833 * is written without DLAB set, this mode will be disabled.
2835 if (port->type == PORT_16750)
2836 serial_port_out(port, UART_FCR, up->fcr);
2838 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2839 if (port->type != PORT_16750) {
2840 /* emulated UARTs (Lucent Venus 167x) need two steps */
2841 if (up->fcr & UART_FCR_ENABLE_FIFO)
2842 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2843 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2845 serial8250_set_mctrl(port, port->mctrl);
2846 spin_unlock_irqrestore(&port->lock, flags);
2847 serial8250_rpm_put(up);
2849 /* Don't rewrite B0 */
2850 if (tty_termios_baud_rate(termios))
2851 tty_termios_encode_baud_rate(termios, baud, baud);
2853 EXPORT_SYMBOL(serial8250_do_set_termios);
2856 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2857 struct ktermios *old)
2859 if (port->set_termios)
2860 port->set_termios(port, termios, old);
2862 serial8250_do_set_termios(port, termios, old);
2865 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2867 if (termios->c_line == N_PPS) {
2868 port->flags |= UPF_HARDPPS_CD;
2869 spin_lock_irq(&port->lock);
2870 serial8250_enable_ms(port);
2871 spin_unlock_irq(&port->lock);
2873 port->flags &= ~UPF_HARDPPS_CD;
2874 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2875 spin_lock_irq(&port->lock);
2876 serial8250_disable_ms(port);
2877 spin_unlock_irq(&port->lock);
2881 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2884 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2886 if (port->set_ldisc)
2887 port->set_ldisc(port, termios);
2889 serial8250_do_set_ldisc(port, termios);
2892 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2893 unsigned int oldstate)
2895 struct uart_8250_port *p = up_to_u8250p(port);
2897 serial8250_set_sleep(p, state != 0);
2899 EXPORT_SYMBOL(serial8250_do_pm);
2902 serial8250_pm(struct uart_port *port, unsigned int state,
2903 unsigned int oldstate)
2906 port->pm(port, state, oldstate);
2908 serial8250_do_pm(port, state, oldstate);
2911 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2913 if (pt->port.mapsize)
2914 return pt->port.mapsize;
2915 if (pt->port.iotype == UPIO_AU) {
2916 if (pt->port.type == PORT_RT2880)
2920 if (is_omap1_8250(pt))
2921 return 0x16 << pt->port.regshift;
2923 return 8 << pt->port.regshift;
2927 * Resource handling.
2929 static int serial8250_request_std_resource(struct uart_8250_port *up)
2931 unsigned int size = serial8250_port_size(up);
2932 struct uart_port *port = &up->port;
2935 switch (port->iotype) {
2942 if (!port->mapbase) {
2947 if (!request_mem_region(port->mapbase, size, "serial")) {
2952 if (port->flags & UPF_IOREMAP) {
2953 port->membase = ioremap(port->mapbase, size);
2954 if (!port->membase) {
2955 release_mem_region(port->mapbase, size);
2963 if (!request_region(port->iobase, size, "serial"))
2970 static void serial8250_release_std_resource(struct uart_8250_port *up)
2972 unsigned int size = serial8250_port_size(up);
2973 struct uart_port *port = &up->port;
2975 switch (port->iotype) {
2985 if (port->flags & UPF_IOREMAP) {
2986 iounmap(port->membase);
2987 port->membase = NULL;
2990 release_mem_region(port->mapbase, size);
2995 release_region(port->iobase, size);
3000 static void serial8250_release_port(struct uart_port *port)
3002 struct uart_8250_port *up = up_to_u8250p(port);
3004 serial8250_release_std_resource(up);
3007 static int serial8250_request_port(struct uart_port *port)
3009 struct uart_8250_port *up = up_to_u8250p(port);
3011 return serial8250_request_std_resource(up);
3014 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3016 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3017 unsigned char bytes;
3019 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3021 return bytes ? bytes : -EOPNOTSUPP;
3024 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3026 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3029 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3032 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3033 if (bytes < conf_type->rxtrig_bytes[i])
3034 /* Use the nearest lower value */
3035 return (--i) << UART_FCR_R_TRIG_SHIFT;
3038 return UART_FCR_R_TRIG_11;
3041 static int do_get_rxtrig(struct tty_port *port)
3043 struct uart_state *state = container_of(port, struct uart_state, port);
3044 struct uart_port *uport = state->uart_port;
3045 struct uart_8250_port *up = up_to_u8250p(uport);
3047 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3050 return fcr_get_rxtrig_bytes(up);
3053 static int do_serial8250_get_rxtrig(struct tty_port *port)
3057 mutex_lock(&port->mutex);
3058 rxtrig_bytes = do_get_rxtrig(port);
3059 mutex_unlock(&port->mutex);
3061 return rxtrig_bytes;
3064 static ssize_t rx_trig_bytes_show(struct device *dev,
3065 struct device_attribute *attr, char *buf)
3067 struct tty_port *port = dev_get_drvdata(dev);
3070 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3071 if (rxtrig_bytes < 0)
3072 return rxtrig_bytes;
3074 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
3077 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3079 struct uart_state *state = container_of(port, struct uart_state, port);
3080 struct uart_port *uport = state->uart_port;
3081 struct uart_8250_port *up = up_to_u8250p(uport);
3084 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3088 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3092 serial8250_clear_fifos(up);
3093 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3094 up->fcr |= (unsigned char)rxtrig;
3095 serial_out(up, UART_FCR, up->fcr);
3099 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3103 mutex_lock(&port->mutex);
3104 ret = do_set_rxtrig(port, bytes);
3105 mutex_unlock(&port->mutex);
3110 static ssize_t rx_trig_bytes_store(struct device *dev,
3111 struct device_attribute *attr, const char *buf, size_t count)
3113 struct tty_port *port = dev_get_drvdata(dev);
3114 unsigned char bytes;
3120 ret = kstrtou8(buf, 10, &bytes);
3124 ret = do_serial8250_set_rxtrig(port, bytes);
3131 static DEVICE_ATTR_RW(rx_trig_bytes);
3133 static struct attribute *serial8250_dev_attrs[] = {
3134 &dev_attr_rx_trig_bytes.attr,
3138 static struct attribute_group serial8250_dev_attr_group = {
3139 .attrs = serial8250_dev_attrs,
3142 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3144 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3146 if (conf_type->rxtrig_bytes[0])
3147 up->port.attr_group = &serial8250_dev_attr_group;
3150 static void serial8250_config_port(struct uart_port *port, int flags)
3152 struct uart_8250_port *up = up_to_u8250p(port);
3156 * Find the region that we can probe for. This in turn
3157 * tells us whether we can probe for the type of port.
3159 ret = serial8250_request_std_resource(up);
3163 if (port->iotype != up->cur_iotype)
3164 set_io_from_upio(port);
3166 if (flags & UART_CONFIG_TYPE)
3169 /* if access method is AU, it is a 16550 with a quirk */
3170 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3171 up->bugs |= UART_BUG_NOMSR;
3173 /* HW bugs may trigger IRQ while IIR == NO_INT */
3174 if (port->type == PORT_TEGRA)
3175 up->bugs |= UART_BUG_NOMSR;
3177 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3180 if (port->type == PORT_UNKNOWN)
3181 serial8250_release_std_resource(up);
3183 register_dev_spec_attr_grp(up);
3184 up->fcr = uart_config[up->port.type].fcr;
3188 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3190 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3191 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3192 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3193 ser->type == PORT_STARTECH)
3198 static const char *serial8250_type(struct uart_port *port)
3200 int type = port->type;
3202 if (type >= ARRAY_SIZE(uart_config))
3204 return uart_config[type].name;
3207 static const struct uart_ops serial8250_pops = {
3208 .tx_empty = serial8250_tx_empty,
3209 .set_mctrl = serial8250_set_mctrl,
3210 .get_mctrl = serial8250_get_mctrl,
3211 .stop_tx = serial8250_stop_tx,
3212 .start_tx = serial8250_start_tx,
3213 .throttle = serial8250_throttle,
3214 .unthrottle = serial8250_unthrottle,
3215 .stop_rx = serial8250_stop_rx,
3216 .enable_ms = serial8250_enable_ms,
3217 .break_ctl = serial8250_break_ctl,
3218 .startup = serial8250_startup,
3219 .shutdown = serial8250_shutdown,
3220 .set_termios = serial8250_set_termios,
3221 .set_ldisc = serial8250_set_ldisc,
3222 .pm = serial8250_pm,
3223 .type = serial8250_type,
3224 .release_port = serial8250_release_port,
3225 .request_port = serial8250_request_port,
3226 .config_port = serial8250_config_port,
3227 .verify_port = serial8250_verify_port,
3228 #ifdef CONFIG_CONSOLE_POLL
3229 .poll_get_char = serial8250_get_poll_char,
3230 .poll_put_char = serial8250_put_poll_char,
3234 void serial8250_init_port(struct uart_8250_port *up)
3236 struct uart_port *port = &up->port;
3238 spin_lock_init(&port->lock);
3239 port->ops = &serial8250_pops;
3240 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3242 up->cur_iotype = 0xFF;
3244 EXPORT_SYMBOL_GPL(serial8250_init_port);
3246 void serial8250_set_defaults(struct uart_8250_port *up)
3248 struct uart_port *port = &up->port;
3250 if (up->port.flags & UPF_FIXED_TYPE) {
3251 unsigned int type = up->port.type;
3253 if (!up->port.fifosize)
3254 up->port.fifosize = uart_config[type].fifo_size;
3256 up->tx_loadsz = uart_config[type].tx_loadsz;
3257 if (!up->capabilities)
3258 up->capabilities = uart_config[type].flags;
3261 set_io_from_upio(port);
3263 /* default dma handlers */
3265 if (!up->dma->tx_dma)
3266 up->dma->tx_dma = serial8250_tx_dma;
3267 if (!up->dma->rx_dma)
3268 up->dma->rx_dma = serial8250_rx_dma;
3271 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3273 #ifdef CONFIG_SERIAL_8250_CONSOLE
3275 static void serial8250_console_putchar(struct uart_port *port, int ch)
3277 struct uart_8250_port *up = up_to_u8250p(port);
3279 wait_for_xmitr(up, UART_LSR_THRE);
3280 serial_port_out(port, UART_TX, ch);
3284 * Restore serial console when h/w power-off detected
3286 static void serial8250_console_restore(struct uart_8250_port *up)
3288 struct uart_port *port = &up->port;
3289 struct ktermios termios;
3290 unsigned int baud, quot, frac = 0;
3292 termios.c_cflag = port->cons->cflag;
3293 termios.c_ispeed = port->cons->ispeed;
3294 termios.c_ospeed = port->cons->ospeed;
3295 if (port->state->port.tty && termios.c_cflag == 0) {
3296 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3297 termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3298 termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3301 baud = serial8250_get_baud_rate(port, &termios, NULL);
3302 quot = serial8250_get_divisor(port, baud, &frac);
3304 serial8250_set_divisor(port, baud, quot, frac);
3305 serial_port_out(port, UART_LCR, up->lcr);
3306 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3310 * Print a string to the serial port trying not to disturb
3311 * any possible real use of the port...
3313 * The console_lock must be held when we get here.
3315 * Doing runtime PM is really a bad idea for the kernel console.
3316 * Thus, we assume the function is called when device is powered up.
3318 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3321 struct uart_8250_em485 *em485 = up->em485;
3322 struct uart_port *port = &up->port;
3323 unsigned long flags;
3327 touch_nmi_watchdog();
3329 if (oops_in_progress)
3330 locked = spin_trylock_irqsave(&port->lock, flags);
3332 spin_lock_irqsave(&port->lock, flags);
3335 * First save the IER then disable the interrupts
3337 ier = serial_port_in(port, UART_IER);
3339 if (up->capabilities & UART_CAP_UUE)
3340 serial_port_out(port, UART_IER, UART_IER_UUE);
3342 serial_port_out(port, UART_IER, 0);
3344 /* check scratch reg to see if port powered off during system sleep */
3345 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3346 serial8250_console_restore(up);
3351 if (em485->tx_stopped)
3352 up->rs485_start_tx(up);
3353 mdelay(port->rs485.delay_rts_before_send);
3356 uart_console_write(port, s, count, serial8250_console_putchar);
3359 * Finally, wait for transmitter to become empty
3360 * and restore the IER
3362 wait_for_xmitr(up, BOTH_EMPTY);
3365 mdelay(port->rs485.delay_rts_after_send);
3366 if (em485->tx_stopped)
3367 up->rs485_stop_tx(up);
3370 serial_port_out(port, UART_IER, ier);
3373 * The receive handling will happen properly because the
3374 * receive ready bit will still be set; it is not cleared
3375 * on read. However, modem control will not, we must
3376 * call it if we have saved something in the saved flags
3377 * while processing with interrupts off.
3379 if (up->msr_saved_flags)
3380 serial8250_modem_status(up);
3383 spin_unlock_irqrestore(&port->lock, flags);
3386 static unsigned int probe_baud(struct uart_port *port)
3388 unsigned char lcr, dll, dlm;
3391 lcr = serial_port_in(port, UART_LCR);
3392 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3393 dll = serial_port_in(port, UART_DLL);
3394 dlm = serial_port_in(port, UART_DLM);
3395 serial_port_out(port, UART_LCR, lcr);
3397 quot = (dlm << 8) | dll;
3398 return (port->uartclk / 16) / quot;
3401 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3409 if (!port->iobase && !port->membase)
3413 uart_parse_options(options, &baud, &parity, &bits, &flow);
3415 baud = probe_baud(port);
3417 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3422 pm_runtime_get_sync(port->dev);
3427 int serial8250_console_exit(struct uart_port *port)
3430 pm_runtime_put_sync(port->dev);
3435 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3437 MODULE_LICENSE("GPL");