2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/timer.h>
51 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
53 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
56 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
59 * Here we define the default xmit fifo size used for each type of UART.
61 static const struct serial8250_config uart_config[] = {
86 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
87 .rxtrig_bytes = {1, 4, 8, 14},
88 .flags = UART_CAP_FIFO,
99 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
105 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
107 .rxtrig_bytes = {8, 16, 24, 28},
108 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
114 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
116 .rxtrig_bytes = {1, 16, 32, 56},
117 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
125 .name = "16C950/954",
128 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
129 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
130 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
136 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
138 .rxtrig_bytes = {8, 16, 56, 60},
139 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
145 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
153 .flags = UART_CAP_FIFO,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
160 .flags = UART_CAP_FIFO | UART_NATSEMI,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
181 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
188 .flags = UART_CAP_FIFO | UART_CAP_AFE,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
196 .rxtrig_bytes = {1, 4, 8, 14},
197 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
213 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
220 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
221 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
222 .flags = UART_CAP_FIFO,
224 [PORT_BRCM_TRUMANAGE] = {
228 .flags = UART_CAP_HFIFO,
233 [PORT_ALTR_16550_F32] = {
234 .name = "Altera 16550 FIFO32",
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO | UART_CAP_AFE,
240 [PORT_ALTR_16550_F64] = {
241 .name = "Altera 16550 FIFO64",
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
257 * be configured less than Maximum supported fifo bytes.
259 [PORT_16550A_FSL64] = {
260 .name = "16550A_FSL64",
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
265 .flags = UART_CAP_FIFO,
268 .name = "Palmchip BK-3103",
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 .rxtrig_bytes = {1, 4, 8, 14},
273 .flags = UART_CAP_FIFO,
277 /* Uart divisor latch read */
278 static int default_serial_dl_read(struct uart_8250_port *up)
280 /* Assign these in pieces to truncate any bits above 7. */
281 unsigned char dll = serial_in(up, UART_DLL);
282 unsigned char dlm = serial_in(up, UART_DLM);
284 return dll | dlm << 8;
287 /* Uart divisor latch write */
288 static void default_serial_dl_write(struct uart_8250_port *up, int value)
290 serial_out(up, UART_DLL, value & 0xff);
291 serial_out(up, UART_DLM, value >> 8 & 0xff);
294 #ifdef CONFIG_SERIAL_8250_RT288X
296 /* Au1x00/RT288x UART hardware has a weird register layout */
297 static const s8 au_io_in_map[8] = {
305 -1, /* UART_SCR (unmapped) */
308 static const s8 au_io_out_map[8] = {
314 -1, /* UART_LSR (unmapped) */
315 -1, /* UART_MSR (unmapped) */
316 -1, /* UART_SCR (unmapped) */
319 static unsigned int au_serial_in(struct uart_port *p, int offset)
321 if (offset >= ARRAY_SIZE(au_io_in_map))
323 offset = au_io_in_map[offset];
326 return __raw_readl(p->membase + (offset << p->regshift));
329 static void au_serial_out(struct uart_port *p, int offset, int value)
331 if (offset >= ARRAY_SIZE(au_io_out_map))
333 offset = au_io_out_map[offset];
336 __raw_writel(value, p->membase + (offset << p->regshift));
339 /* Au1x00 haven't got a standard divisor latch */
340 static int au_serial_dl_read(struct uart_8250_port *up)
342 return __raw_readl(up->port.membase + 0x28);
345 static void au_serial_dl_write(struct uart_8250_port *up, int value)
347 __raw_writel(value, up->port.membase + 0x28);
352 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
354 offset = offset << p->regshift;
355 outb(p->hub6 - 1 + offset, p->iobase);
356 return inb(p->iobase + 1);
359 static void hub6_serial_out(struct uart_port *p, int offset, int value)
361 offset = offset << p->regshift;
362 outb(p->hub6 - 1 + offset, p->iobase);
363 outb(value, p->iobase + 1);
366 static unsigned int mem_serial_in(struct uart_port *p, int offset)
368 offset = offset << p->regshift;
369 return readb(p->membase + offset);
372 static void mem_serial_out(struct uart_port *p, int offset, int value)
374 offset = offset << p->regshift;
375 writeb(value, p->membase + offset);
378 static void mem16_serial_out(struct uart_port *p, int offset, int value)
380 offset = offset << p->regshift;
381 writew(value, p->membase + offset);
384 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
386 offset = offset << p->regshift;
387 return readw(p->membase + offset);
390 static void mem32_serial_out(struct uart_port *p, int offset, int value)
392 offset = offset << p->regshift;
393 writel(value, p->membase + offset);
396 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
398 offset = offset << p->regshift;
399 return readl(p->membase + offset);
402 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
404 offset = offset << p->regshift;
405 iowrite32be(value, p->membase + offset);
408 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
410 offset = offset << p->regshift;
411 return ioread32be(p->membase + offset);
414 static unsigned int io_serial_in(struct uart_port *p, int offset)
416 offset = offset << p->regshift;
417 return inb(p->iobase + offset);
420 static void io_serial_out(struct uart_port *p, int offset, int value)
422 offset = offset << p->regshift;
423 outb(value, p->iobase + offset);
426 static int serial8250_default_handle_irq(struct uart_port *port);
427 static int exar_handle_irq(struct uart_port *port);
429 static void set_io_from_upio(struct uart_port *p)
431 struct uart_8250_port *up = up_to_u8250p(p);
433 up->dl_read = default_serial_dl_read;
434 up->dl_write = default_serial_dl_write;
438 p->serial_in = hub6_serial_in;
439 p->serial_out = hub6_serial_out;
443 p->serial_in = mem_serial_in;
444 p->serial_out = mem_serial_out;
448 p->serial_in = mem16_serial_in;
449 p->serial_out = mem16_serial_out;
453 p->serial_in = mem32_serial_in;
454 p->serial_out = mem32_serial_out;
458 p->serial_in = mem32be_serial_in;
459 p->serial_out = mem32be_serial_out;
462 #ifdef CONFIG_SERIAL_8250_RT288X
464 p->serial_in = au_serial_in;
465 p->serial_out = au_serial_out;
466 up->dl_read = au_serial_dl_read;
467 up->dl_write = au_serial_dl_write;
472 p->serial_in = io_serial_in;
473 p->serial_out = io_serial_out;
476 /* Remember loaded iotype */
477 up->cur_iotype = p->iotype;
478 p->handle_irq = serial8250_default_handle_irq;
482 serial_port_out_sync(struct uart_port *p, int offset, int value)
490 p->serial_out(p, offset, value);
491 p->serial_in(p, UART_LCR); /* safe, no side-effects */
494 p->serial_out(p, offset, value);
501 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
503 serial_out(up, UART_SCR, offset);
504 serial_out(up, UART_ICR, value);
507 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
511 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
512 serial_out(up, UART_SCR, offset);
513 value = serial_in(up, UART_ICR);
514 serial_icr_write(up, UART_ACR, up->acr);
522 static void serial8250_clear_fifos(struct uart_8250_port *p)
524 if (p->capabilities & UART_CAP_FIFO) {
525 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
526 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
527 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
528 serial_out(p, UART_FCR, 0);
532 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
534 unsigned char mcr = serial8250_in_MCR(p);
536 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
539 mcr &= ~UART_MCR_RTS;
540 serial8250_out_MCR(p, mcr);
543 static void serial8250_em485_handle_start_tx(unsigned long arg);
544 static void serial8250_em485_handle_stop_tx(unsigned long arg);
546 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
548 serial8250_clear_fifos(p);
549 serial_out(p, UART_FCR, p->fcr);
551 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
553 void serial8250_rpm_get(struct uart_8250_port *p)
555 if (!(p->capabilities & UART_CAP_RPM))
557 pm_runtime_get_sync(p->port.dev);
559 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
561 void serial8250_rpm_put(struct uart_8250_port *p)
563 if (!(p->capabilities & UART_CAP_RPM))
565 pm_runtime_mark_last_busy(p->port.dev);
566 pm_runtime_put_autosuspend(p->port.dev);
568 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
571 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
572 * @p: uart_8250_port port instance
574 * The function is used to start rs485 software emulating on the
575 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
576 * transmission. The function is idempotent, so it is safe to call it
579 * The caller MUST enable interrupt on empty shift register before
580 * calling serial8250_em485_init(). This interrupt is not a part of
581 * 8250 standard, but implementation defined.
583 * The function is supposed to be called from .rs485_config callback
584 * or from any other callback protected with p->port.lock spinlock.
586 * See also serial8250_em485_destroy()
588 * Return 0 - success, -errno - otherwise
590 int serial8250_em485_init(struct uart_8250_port *p)
595 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
599 setup_timer(&p->em485->stop_tx_timer,
600 serial8250_em485_handle_stop_tx, (unsigned long)p);
601 setup_timer(&p->em485->start_tx_timer,
602 serial8250_em485_handle_start_tx, (unsigned long)p);
603 p->em485->active_timer = NULL;
605 serial8250_em485_rts_after_send(p);
609 EXPORT_SYMBOL_GPL(serial8250_em485_init);
612 * serial8250_em485_destroy() - put uart_8250_port into normal state
613 * @p: uart_8250_port port instance
615 * The function is used to stop rs485 software emulating on the
616 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
617 * call it multiple times.
619 * The function is supposed to be called from .rs485_config callback
620 * or from any other callback protected with p->port.lock spinlock.
622 * See also serial8250_em485_init()
624 void serial8250_em485_destroy(struct uart_8250_port *p)
629 del_timer(&p->em485->start_tx_timer);
630 del_timer(&p->em485->stop_tx_timer);
635 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
638 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
639 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
640 * empty and the HW can idle again.
642 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
644 unsigned char rpm_active;
646 if (!(p->capabilities & UART_CAP_RPM))
649 rpm_active = xchg(&p->rpm_tx_active, 1);
652 pm_runtime_get_sync(p->port.dev);
655 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
657 unsigned char rpm_active;
659 if (!(p->capabilities & UART_CAP_RPM))
662 rpm_active = xchg(&p->rpm_tx_active, 0);
665 pm_runtime_mark_last_busy(p->port.dev);
666 pm_runtime_put_autosuspend(p->port.dev);
670 * IER sleep support. UARTs which have EFRs need the "extended
671 * capability" bit enabled. Note that on XR16C850s, we need to
672 * reset LCR to write to IER.
674 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
676 unsigned char lcr = 0, efr = 0;
678 * Exar UARTs have a SLEEP register that enables or disables
679 * each UART to enter sleep mode separately. On the XR17V35x the
680 * register is accessible to each UART at the UART_EXAR_SLEEP
681 * offset but the UART channel may only write to the corresponding
684 serial8250_rpm_get(p);
685 if ((p->port.type == PORT_XR17V35X) ||
686 (p->port.type == PORT_XR17D15X)) {
687 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
691 if (p->capabilities & UART_CAP_SLEEP) {
692 if (p->capabilities & UART_CAP_EFR) {
693 lcr = serial_in(p, UART_LCR);
694 efr = serial_in(p, UART_EFR);
695 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
696 serial_out(p, UART_EFR, UART_EFR_ECB);
697 serial_out(p, UART_LCR, 0);
699 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
700 if (p->capabilities & UART_CAP_EFR) {
701 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
702 serial_out(p, UART_EFR, efr);
703 serial_out(p, UART_LCR, lcr);
707 serial8250_rpm_put(p);
710 #ifdef CONFIG_SERIAL_8250_RSA
712 * Attempts to turn on the RSA FIFO. Returns zero on failure.
713 * We set the port uart clock rate if we succeed.
715 static int __enable_rsa(struct uart_8250_port *up)
720 mode = serial_in(up, UART_RSA_MSR);
721 result = mode & UART_RSA_MSR_FIFO;
724 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
725 mode = serial_in(up, UART_RSA_MSR);
726 result = mode & UART_RSA_MSR_FIFO;
730 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
735 static void enable_rsa(struct uart_8250_port *up)
737 if (up->port.type == PORT_RSA) {
738 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
739 spin_lock_irq(&up->port.lock);
741 spin_unlock_irq(&up->port.lock);
743 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
744 serial_out(up, UART_RSA_FRR, 0);
749 * Attempts to turn off the RSA FIFO. Returns zero on failure.
750 * It is unknown why interrupts were disabled in here. However,
751 * the caller is expected to preserve this behaviour by grabbing
752 * the spinlock before calling this function.
754 static void disable_rsa(struct uart_8250_port *up)
759 if (up->port.type == PORT_RSA &&
760 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
761 spin_lock_irq(&up->port.lock);
763 mode = serial_in(up, UART_RSA_MSR);
764 result = !(mode & UART_RSA_MSR_FIFO);
767 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
768 mode = serial_in(up, UART_RSA_MSR);
769 result = !(mode & UART_RSA_MSR_FIFO);
773 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
774 spin_unlock_irq(&up->port.lock);
777 #endif /* CONFIG_SERIAL_8250_RSA */
780 * This is a quickie test to see how big the FIFO is.
781 * It doesn't work at all the time, more's the pity.
783 static int size_fifo(struct uart_8250_port *up)
785 unsigned char old_fcr, old_mcr, old_lcr;
786 unsigned short old_dl;
789 old_lcr = serial_in(up, UART_LCR);
790 serial_out(up, UART_LCR, 0);
791 old_fcr = serial_in(up, UART_FCR);
792 old_mcr = serial8250_in_MCR(up);
793 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
794 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
795 serial8250_out_MCR(up, UART_MCR_LOOP);
796 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
797 old_dl = serial_dl_read(up);
798 serial_dl_write(up, 0x0001);
799 serial_out(up, UART_LCR, 0x03);
800 for (count = 0; count < 256; count++)
801 serial_out(up, UART_TX, count);
802 mdelay(20);/* FIXME - schedule_timeout */
803 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
804 (count < 256); count++)
805 serial_in(up, UART_RX);
806 serial_out(up, UART_FCR, old_fcr);
807 serial8250_out_MCR(up, old_mcr);
808 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
809 serial_dl_write(up, old_dl);
810 serial_out(up, UART_LCR, old_lcr);
816 * Read UART ID using the divisor method - set DLL and DLM to zero
817 * and the revision will be in DLL and device type in DLM. We
818 * preserve the device state across this.
820 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
822 unsigned char old_lcr;
823 unsigned int id, old_dl;
825 old_lcr = serial_in(p, UART_LCR);
826 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
827 old_dl = serial_dl_read(p);
828 serial_dl_write(p, 0);
829 id = serial_dl_read(p);
830 serial_dl_write(p, old_dl);
832 serial_out(p, UART_LCR, old_lcr);
838 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
839 * When this function is called we know it is at least a StarTech
840 * 16650 V2, but it might be one of several StarTech UARTs, or one of
841 * its clones. (We treat the broken original StarTech 16650 V1 as a
842 * 16550, and why not? Startech doesn't seem to even acknowledge its
845 * What evil have men's minds wrought...
847 static void autoconfig_has_efr(struct uart_8250_port *up)
849 unsigned int id1, id2, id3, rev;
852 * Everything with an EFR has SLEEP
854 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
857 * First we check to see if it's an Oxford Semiconductor UART.
859 * If we have to do this here because some non-National
860 * Semiconductor clone chips lock up if you try writing to the
861 * LSR register (which serial_icr_read does)
865 * Check for Oxford Semiconductor 16C950.
867 * EFR [4] must be set else this test fails.
869 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
870 * claims that it's needed for 952 dual UART's (which are not
871 * recommended for new designs).
874 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
875 serial_out(up, UART_EFR, UART_EFR_ECB);
876 serial_out(up, UART_LCR, 0x00);
877 id1 = serial_icr_read(up, UART_ID1);
878 id2 = serial_icr_read(up, UART_ID2);
879 id3 = serial_icr_read(up, UART_ID3);
880 rev = serial_icr_read(up, UART_REV);
882 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
884 if (id1 == 0x16 && id2 == 0xC9 &&
885 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
886 up->port.type = PORT_16C950;
889 * Enable work around for the Oxford Semiconductor 952 rev B
890 * chip which causes it to seriously miscalculate baud rates
893 if (id3 == 0x52 && rev == 0x01)
894 up->bugs |= UART_BUG_QUOT;
899 * We check for a XR16C850 by setting DLL and DLM to 0, and then
900 * reading back DLL and DLM. The chip type depends on the DLM
902 * 0x10 - XR16C850 and the DLL contains the chip revision.
906 id1 = autoconfig_read_divisor_id(up);
907 DEBUG_AUTOCONF("850id=%04x ", id1);
910 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
911 up->port.type = PORT_16850;
916 * It wasn't an XR16C850.
918 * We distinguish between the '654 and the '650 by counting
919 * how many bytes are in the FIFO. I'm using this for now,
920 * since that's the technique that was sent to me in the
921 * serial driver update, but I'm not convinced this works.
922 * I've had problems doing this in the past. -TYT
924 if (size_fifo(up) == 64)
925 up->port.type = PORT_16654;
927 up->port.type = PORT_16650V2;
931 * We detected a chip without a FIFO. Only two fall into
932 * this category - the original 8250 and the 16450. The
933 * 16450 has a scratch register (accessible with LCR=0)
935 static void autoconfig_8250(struct uart_8250_port *up)
937 unsigned char scratch, status1, status2;
939 up->port.type = PORT_8250;
941 scratch = serial_in(up, UART_SCR);
942 serial_out(up, UART_SCR, 0xa5);
943 status1 = serial_in(up, UART_SCR);
944 serial_out(up, UART_SCR, 0x5a);
945 status2 = serial_in(up, UART_SCR);
946 serial_out(up, UART_SCR, scratch);
948 if (status1 == 0xa5 && status2 == 0x5a)
949 up->port.type = PORT_16450;
952 static int broken_efr(struct uart_8250_port *up)
955 * Exar ST16C2550 "A2" devices incorrectly detect as
956 * having an EFR, and report an ID of 0x0201. See
957 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
959 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
966 * We know that the chip has FIFOs. Does it have an EFR? The
967 * EFR is located in the same register position as the IIR and
968 * we know the top two bits of the IIR are currently set. The
969 * EFR should contain zero. Try to read the EFR.
971 static void autoconfig_16550a(struct uart_8250_port *up)
973 unsigned char status1, status2;
974 unsigned int iersave;
976 up->port.type = PORT_16550A;
977 up->capabilities |= UART_CAP_FIFO;
980 * XR17V35x UARTs have an extra divisor register, DLD
981 * that gets enabled with when DLAB is set which will
982 * cause the device to incorrectly match and assign
983 * port type to PORT_16650. The EFR for this UART is
984 * found at offset 0x09. Instead check the Deice ID (DVID)
985 * register for a 2, 4 or 8 port UART.
987 if (up->port.flags & UPF_EXAR_EFR) {
988 status1 = serial_in(up, UART_EXAR_DVID);
989 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
990 DEBUG_AUTOCONF("Exar XR17V35x ");
991 up->port.type = PORT_XR17V35X;
992 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1001 * Check for presence of the EFR when DLAB is set.
1002 * Only ST16C650V1 UARTs pass this test.
1004 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1005 if (serial_in(up, UART_EFR) == 0) {
1006 serial_out(up, UART_EFR, 0xA8);
1007 if (serial_in(up, UART_EFR) != 0) {
1008 DEBUG_AUTOCONF("EFRv1 ");
1009 up->port.type = PORT_16650;
1010 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1012 serial_out(up, UART_LCR, 0);
1013 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1015 status1 = serial_in(up, UART_IIR) >> 5;
1016 serial_out(up, UART_FCR, 0);
1017 serial_out(up, UART_LCR, 0);
1020 up->port.type = PORT_16550A_FSL64;
1022 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1024 serial_out(up, UART_EFR, 0);
1029 * Maybe it requires 0xbf to be written to the LCR.
1030 * (other ST16C650V2 UARTs, TI16C752A, etc)
1032 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1033 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1034 DEBUG_AUTOCONF("EFRv2 ");
1035 autoconfig_has_efr(up);
1040 * Check for a National Semiconductor SuperIO chip.
1041 * Attempt to switch to bank 2, read the value of the LOOP bit
1042 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1043 * switch back to bank 2, read it from EXCR1 again and check
1044 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1046 serial_out(up, UART_LCR, 0);
1047 status1 = serial8250_in_MCR(up);
1048 serial_out(up, UART_LCR, 0xE0);
1049 status2 = serial_in(up, 0x02); /* EXCR1 */
1051 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1052 serial_out(up, UART_LCR, 0);
1053 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1054 serial_out(up, UART_LCR, 0xE0);
1055 status2 = serial_in(up, 0x02); /* EXCR1 */
1056 serial_out(up, UART_LCR, 0);
1057 serial8250_out_MCR(up, status1);
1059 if ((status2 ^ status1) & UART_MCR_LOOP) {
1060 unsigned short quot;
1062 serial_out(up, UART_LCR, 0xE0);
1064 quot = serial_dl_read(up);
1067 if (ns16550a_goto_highspeed(up))
1068 serial_dl_write(up, quot);
1070 serial_out(up, UART_LCR, 0);
1072 up->port.uartclk = 921600*16;
1073 up->port.type = PORT_NS16550A;
1074 up->capabilities |= UART_NATSEMI;
1080 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1081 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1082 * Try setting it with and without DLAB set. Cheap clones
1083 * set bit 5 without DLAB set.
1085 serial_out(up, UART_LCR, 0);
1086 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1087 status1 = serial_in(up, UART_IIR) >> 5;
1088 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1089 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1090 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1091 status2 = serial_in(up, UART_IIR) >> 5;
1092 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1093 serial_out(up, UART_LCR, 0);
1095 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1097 if (status1 == 6 && status2 == 7) {
1098 up->port.type = PORT_16750;
1099 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1104 * Try writing and reading the UART_IER_UUE bit (b6).
1105 * If it works, this is probably one of the Xscale platform's
1107 * We're going to explicitly set the UUE bit to 0 before
1108 * trying to write and read a 1 just to make sure it's not
1109 * already a 1 and maybe locked there before we even start start.
1111 iersave = serial_in(up, UART_IER);
1112 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1113 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1115 * OK it's in a known zero state, try writing and reading
1116 * without disturbing the current state of the other bits.
1118 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1119 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1122 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1124 DEBUG_AUTOCONF("Xscale ");
1125 up->port.type = PORT_XSCALE;
1126 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1131 * If we got here we couldn't force the IER_UUE bit to 0.
1132 * Log it and continue.
1134 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1136 serial_out(up, UART_IER, iersave);
1139 * Exar uarts have EFR in a weird location
1141 if (up->port.flags & UPF_EXAR_EFR) {
1142 DEBUG_AUTOCONF("Exar XR17D15x ");
1143 up->port.type = PORT_XR17D15X;
1144 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1151 * We distinguish between 16550A and U6 16550A by counting
1152 * how many bytes are in the FIFO.
1154 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1155 up->port.type = PORT_U6_16550A;
1156 up->capabilities |= UART_CAP_AFE;
1161 * This routine is called by rs_init() to initialize a specific serial
1162 * port. It determines what type of UART chip this serial port is
1163 * using: 8250, 16450, 16550, 16550A. The important question is
1164 * whether or not this UART is a 16550A or not, since this will
1165 * determine whether or not we can use its FIFO features or not.
1167 static void autoconfig(struct uart_8250_port *up)
1169 unsigned char status1, scratch, scratch2, scratch3;
1170 unsigned char save_lcr, save_mcr;
1171 struct uart_port *port = &up->port;
1172 unsigned long flags;
1173 unsigned int old_capabilities;
1175 if (!port->iobase && !port->mapbase && !port->membase)
1178 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1179 serial_index(port), port->iobase, port->membase);
1182 * We really do need global IRQs disabled here - we're going to
1183 * be frobbing the chips IRQ enable register to see if it exists.
1185 spin_lock_irqsave(&port->lock, flags);
1187 up->capabilities = 0;
1190 if (!(port->flags & UPF_BUGGY_UART)) {
1192 * Do a simple existence test first; if we fail this,
1193 * there's no point trying anything else.
1195 * 0x80 is used as a nonsense port to prevent against
1196 * false positives due to ISA bus float. The
1197 * assumption is that 0x80 is a non-existent port;
1198 * which should be safe since include/asm/io.h also
1199 * makes this assumption.
1201 * Note: this is safe as long as MCR bit 4 is clear
1202 * and the device is in "PC" mode.
1204 scratch = serial_in(up, UART_IER);
1205 serial_out(up, UART_IER, 0);
1210 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1211 * 16C754B) allow only to modify them if an EFR bit is set.
1213 scratch2 = serial_in(up, UART_IER) & 0x0f;
1214 serial_out(up, UART_IER, 0x0F);
1218 scratch3 = serial_in(up, UART_IER) & 0x0f;
1219 serial_out(up, UART_IER, scratch);
1220 if (scratch2 != 0 || scratch3 != 0x0F) {
1222 * We failed; there's nothing here
1224 spin_unlock_irqrestore(&port->lock, flags);
1225 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1226 scratch2, scratch3);
1231 save_mcr = serial8250_in_MCR(up);
1232 save_lcr = serial_in(up, UART_LCR);
1235 * Check to see if a UART is really there. Certain broken
1236 * internal modems based on the Rockwell chipset fail this
1237 * test, because they apparently don't implement the loopback
1238 * test mode. So this test is skipped on the COM 1 through
1239 * COM 4 ports. This *should* be safe, since no board
1240 * manufacturer would be stupid enough to design a board
1241 * that conflicts with COM 1-4 --- we hope!
1243 if (!(port->flags & UPF_SKIP_TEST)) {
1244 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1245 status1 = serial_in(up, UART_MSR) & 0xF0;
1246 serial8250_out_MCR(up, save_mcr);
1247 if (status1 != 0x90) {
1248 spin_unlock_irqrestore(&port->lock, flags);
1249 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1256 * We're pretty sure there's a port here. Lets find out what
1257 * type of port it is. The IIR top two bits allows us to find
1258 * out if it's 8250 or 16450, 16550, 16550A or later. This
1259 * determines what we test for next.
1261 * We also initialise the EFR (if any) to zero for later. The
1262 * EFR occupies the same register location as the FCR and IIR.
1264 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1265 serial_out(up, UART_EFR, 0);
1266 serial_out(up, UART_LCR, 0);
1268 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1270 /* Assign this as it is to truncate any bits above 7. */
1271 scratch = serial_in(up, UART_IIR);
1273 switch (scratch >> 6) {
1275 autoconfig_8250(up);
1278 port->type = PORT_UNKNOWN;
1281 port->type = PORT_16550;
1284 autoconfig_16550a(up);
1288 #ifdef CONFIG_SERIAL_8250_RSA
1290 * Only probe for RSA ports if we got the region.
1292 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1294 port->type = PORT_RSA;
1297 serial_out(up, UART_LCR, save_lcr);
1299 port->fifosize = uart_config[up->port.type].fifo_size;
1300 old_capabilities = up->capabilities;
1301 up->capabilities = uart_config[port->type].flags;
1302 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1304 if (port->type == PORT_UNKNOWN)
1310 #ifdef CONFIG_SERIAL_8250_RSA
1311 if (port->type == PORT_RSA)
1312 serial_out(up, UART_RSA_FRR, 0);
1314 serial8250_out_MCR(up, save_mcr);
1315 serial8250_clear_fifos(up);
1316 serial_in(up, UART_RX);
1317 if (up->capabilities & UART_CAP_UUE)
1318 serial_out(up, UART_IER, UART_IER_UUE);
1320 serial_out(up, UART_IER, 0);
1323 spin_unlock_irqrestore(&port->lock, flags);
1326 * Check if the device is a Fintek F81216A
1328 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1329 fintek_8250_probe(up);
1331 if (up->capabilities != old_capabilities) {
1332 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1333 serial_index(port), old_capabilities,
1337 DEBUG_AUTOCONF("iir=%d ", scratch);
1338 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1341 static void autoconfig_irq(struct uart_8250_port *up)
1343 struct uart_port *port = &up->port;
1344 unsigned char save_mcr, save_ier;
1345 unsigned char save_ICP = 0;
1346 unsigned int ICP = 0;
1350 if (port->flags & UPF_FOURPORT) {
1351 ICP = (port->iobase & 0xfe0) | 0x1f;
1352 save_ICP = inb_p(ICP);
1357 if (uart_console(port))
1360 /* forget possible initially masked and pending IRQ */
1361 probe_irq_off(probe_irq_on());
1362 save_mcr = serial8250_in_MCR(up);
1363 save_ier = serial_in(up, UART_IER);
1364 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1366 irqs = probe_irq_on();
1367 serial8250_out_MCR(up, 0);
1369 if (port->flags & UPF_FOURPORT) {
1370 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1372 serial8250_out_MCR(up,
1373 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1375 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1376 serial_in(up, UART_LSR);
1377 serial_in(up, UART_RX);
1378 serial_in(up, UART_IIR);
1379 serial_in(up, UART_MSR);
1380 serial_out(up, UART_TX, 0xFF);
1382 irq = probe_irq_off(irqs);
1384 serial8250_out_MCR(up, save_mcr);
1385 serial_out(up, UART_IER, save_ier);
1387 if (port->flags & UPF_FOURPORT)
1388 outb_p(save_ICP, ICP);
1390 if (uart_console(port))
1393 port->irq = (irq > 0) ? irq : 0;
1396 static void serial8250_stop_rx(struct uart_port *port)
1398 struct uart_8250_port *up = up_to_u8250p(port);
1400 serial8250_rpm_get(up);
1402 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1403 up->port.read_status_mask &= ~UART_LSR_DR;
1404 serial_port_out(port, UART_IER, up->ier);
1406 serial8250_rpm_put(up);
1409 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1411 serial8250_em485_rts_after_send(p);
1414 * Empty the RX FIFO, we are not interested in anything
1415 * received during the half-duplex transmission.
1416 * Enable previously disabled RX interrupts.
1418 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1419 serial8250_clear_and_reinit_fifos(p);
1421 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1422 serial_port_out(&p->port, UART_IER, p->ier);
1426 static void serial8250_em485_handle_stop_tx(unsigned long arg)
1428 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1429 struct uart_8250_em485 *em485 = p->em485;
1430 unsigned long flags;
1432 serial8250_rpm_get(p);
1433 spin_lock_irqsave(&p->port.lock, flags);
1435 em485->active_timer == &em485->stop_tx_timer) {
1436 __do_stop_tx_rs485(p);
1437 em485->active_timer = NULL;
1439 spin_unlock_irqrestore(&p->port.lock, flags);
1440 serial8250_rpm_put(p);
1443 static void __stop_tx_rs485(struct uart_8250_port *p)
1445 struct uart_8250_em485 *em485 = p->em485;
1448 * __do_stop_tx_rs485 is going to set RTS according to config
1449 * AND flush RX FIFO if required.
1451 if (p->port.rs485.delay_rts_after_send > 0) {
1452 em485->active_timer = &em485->stop_tx_timer;
1453 mod_timer(&em485->stop_tx_timer, jiffies +
1454 p->port.rs485.delay_rts_after_send * HZ / 1000);
1456 __do_stop_tx_rs485(p);
1460 static inline void __do_stop_tx(struct uart_8250_port *p)
1462 if (p->ier & UART_IER_THRI) {
1463 p->ier &= ~UART_IER_THRI;
1464 serial_out(p, UART_IER, p->ier);
1465 serial8250_rpm_put_tx(p);
1469 static inline void __stop_tx(struct uart_8250_port *p)
1471 struct uart_8250_em485 *em485 = p->em485;
1474 unsigned char lsr = serial_in(p, UART_LSR);
1476 * To provide required timeing and allow FIFO transfer,
1477 * __stop_tx_rs485() must be called only when both FIFO and
1478 * shift register are empty. It is for device driver to enable
1479 * interrupt on TEMT.
1481 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1484 del_timer(&em485->start_tx_timer);
1485 em485->active_timer = NULL;
1492 static void serial8250_stop_tx(struct uart_port *port)
1494 struct uart_8250_port *up = up_to_u8250p(port);
1496 serial8250_rpm_get(up);
1500 * We really want to stop the transmitter from sending.
1502 if (port->type == PORT_16C950) {
1503 up->acr |= UART_ACR_TXDIS;
1504 serial_icr_write(up, UART_ACR, up->acr);
1506 serial8250_rpm_put(up);
1509 static inline void __start_tx(struct uart_port *port)
1511 struct uart_8250_port *up = up_to_u8250p(port);
1513 if (up->dma && !up->dma->tx_dma(up))
1516 if (!(up->ier & UART_IER_THRI)) {
1517 up->ier |= UART_IER_THRI;
1518 serial_port_out(port, UART_IER, up->ier);
1520 if (up->bugs & UART_BUG_TXEN) {
1523 lsr = serial_in(up, UART_LSR);
1524 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1525 if (lsr & UART_LSR_THRE)
1526 serial8250_tx_chars(up);
1531 * Re-enable the transmitter if we disabled it.
1533 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1534 up->acr &= ~UART_ACR_TXDIS;
1535 serial_icr_write(up, UART_ACR, up->acr);
1539 static inline void start_tx_rs485(struct uart_port *port)
1541 struct uart_8250_port *up = up_to_u8250p(port);
1542 struct uart_8250_em485 *em485 = up->em485;
1545 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1546 serial8250_stop_rx(&up->port);
1548 del_timer(&em485->stop_tx_timer);
1549 em485->active_timer = NULL;
1551 mcr = serial8250_in_MCR(up);
1552 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1553 !!(mcr & UART_MCR_RTS)) {
1554 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1555 mcr |= UART_MCR_RTS;
1557 mcr &= ~UART_MCR_RTS;
1558 serial8250_out_MCR(up, mcr);
1560 if (up->port.rs485.delay_rts_before_send > 0) {
1561 em485->active_timer = &em485->start_tx_timer;
1562 mod_timer(&em485->start_tx_timer, jiffies +
1563 up->port.rs485.delay_rts_before_send * HZ / 1000);
1571 static void serial8250_em485_handle_start_tx(unsigned long arg)
1573 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1574 struct uart_8250_em485 *em485 = p->em485;
1575 unsigned long flags;
1577 spin_lock_irqsave(&p->port.lock, flags);
1579 em485->active_timer == &em485->start_tx_timer) {
1580 __start_tx(&p->port);
1581 em485->active_timer = NULL;
1583 spin_unlock_irqrestore(&p->port.lock, flags);
1586 static void serial8250_start_tx(struct uart_port *port)
1588 struct uart_8250_port *up = up_to_u8250p(port);
1589 struct uart_8250_em485 *em485 = up->em485;
1591 serial8250_rpm_get_tx(up);
1594 em485->active_timer == &em485->start_tx_timer)
1598 start_tx_rs485(port);
1603 static void serial8250_throttle(struct uart_port *port)
1605 port->throttle(port);
1608 static void serial8250_unthrottle(struct uart_port *port)
1610 port->unthrottle(port);
1613 static void serial8250_disable_ms(struct uart_port *port)
1615 struct uart_8250_port *up = up_to_u8250p(port);
1617 /* no MSR capabilities */
1618 if (up->bugs & UART_BUG_NOMSR)
1621 up->ier &= ~UART_IER_MSI;
1622 serial_port_out(port, UART_IER, up->ier);
1625 static void serial8250_enable_ms(struct uart_port *port)
1627 struct uart_8250_port *up = up_to_u8250p(port);
1629 /* no MSR capabilities */
1630 if (up->bugs & UART_BUG_NOMSR)
1633 up->ier |= UART_IER_MSI;
1635 serial8250_rpm_get(up);
1636 serial_port_out(port, UART_IER, up->ier);
1637 serial8250_rpm_put(up);
1640 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1642 struct uart_port *port = &up->port;
1644 char flag = TTY_NORMAL;
1646 if (likely(lsr & UART_LSR_DR))
1647 ch = serial_in(up, UART_RX);
1650 * Intel 82571 has a Serial Over Lan device that will
1651 * set UART_LSR_BI without setting UART_LSR_DR when
1652 * it receives a break. To avoid reading from the
1653 * receive buffer without UART_LSR_DR bit set, we
1654 * just force the read character to be 0
1660 lsr |= up->lsr_saved_flags;
1661 up->lsr_saved_flags = 0;
1663 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1664 if (lsr & UART_LSR_BI) {
1665 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1668 * We do the SysRQ and SAK checking
1669 * here because otherwise the break
1670 * may get masked by ignore_status_mask
1671 * or read_status_mask.
1673 if (uart_handle_break(port))
1675 } else if (lsr & UART_LSR_PE)
1676 port->icount.parity++;
1677 else if (lsr & UART_LSR_FE)
1678 port->icount.frame++;
1679 if (lsr & UART_LSR_OE)
1680 port->icount.overrun++;
1683 * Mask off conditions which should be ignored.
1685 lsr &= port->read_status_mask;
1687 if (lsr & UART_LSR_BI) {
1688 pr_debug("%s: handling break\n", __func__);
1690 } else if (lsr & UART_LSR_PE)
1692 else if (lsr & UART_LSR_FE)
1695 if (uart_handle_sysrq_char(port, ch))
1698 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1702 * serial8250_rx_chars: processes according to the passed in LSR
1703 * value, and returns the remaining LSR bits not handled
1704 * by this Rx routine.
1706 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1708 struct uart_port *port = &up->port;
1709 int max_count = 256;
1712 serial8250_read_char(up, lsr);
1713 if (--max_count == 0)
1715 lsr = serial_in(up, UART_LSR);
1716 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1718 tty_flip_buffer_push(&port->state->port);
1721 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1723 void serial8250_tx_chars(struct uart_8250_port *up)
1725 struct uart_port *port = &up->port;
1726 struct circ_buf *xmit = &port->state->xmit;
1730 serial_out(up, UART_TX, port->x_char);
1735 if (uart_tx_stopped(port)) {
1736 serial8250_stop_tx(port);
1739 if (uart_circ_empty(xmit)) {
1744 count = up->tx_loadsz;
1746 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1747 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1749 if (uart_circ_empty(xmit))
1751 if ((up->capabilities & UART_CAP_HFIFO) &&
1752 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1754 } while (--count > 0);
1756 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1757 uart_write_wakeup(port);
1760 * With RPM enabled, we have to wait until the FIFO is empty before the
1761 * HW can go idle. So we get here once again with empty FIFO and disable
1762 * the interrupt and RPM in __stop_tx()
1764 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1767 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1769 /* Caller holds uart port lock */
1770 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1772 struct uart_port *port = &up->port;
1773 unsigned int status = serial_in(up, UART_MSR);
1775 status |= up->msr_saved_flags;
1776 up->msr_saved_flags = 0;
1777 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1778 port->state != NULL) {
1779 if (status & UART_MSR_TERI)
1781 if (status & UART_MSR_DDSR)
1783 if (status & UART_MSR_DDCD)
1784 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1785 if (status & UART_MSR_DCTS)
1786 uart_handle_cts_change(port, status & UART_MSR_CTS);
1788 wake_up_interruptible(&port->state->port.delta_msr_wait);
1793 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1795 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1797 switch (iir & 0x3f) {
1798 case UART_IIR_RX_TIMEOUT:
1799 serial8250_rx_dma_flush(up);
1804 return up->dma->rx_dma(up);
1808 * This handles the interrupt from one port.
1810 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1812 unsigned char status;
1813 unsigned long flags;
1814 struct uart_8250_port *up = up_to_u8250p(port);
1815 bool skip_rx = false;
1817 if (iir & UART_IIR_NO_INT)
1820 spin_lock_irqsave(&port->lock, flags);
1822 status = serial_port_in(port, UART_LSR);
1825 * If port is stopped and there are no error conditions in the
1826 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1827 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1828 * control when FIFO occupancy reaches preset threshold, thus
1829 * halting RX. This only works when auto HW flow control is
1832 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1833 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1834 !(port->read_status_mask & UART_LSR_DR))
1837 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1838 if (!up->dma || handle_rx_dma(up, iir))
1839 status = serial8250_rx_chars(up, status);
1841 serial8250_modem_status(up);
1842 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1843 (up->ier & UART_IER_THRI))
1844 serial8250_tx_chars(up);
1846 spin_unlock_irqrestore(&port->lock, flags);
1849 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1851 static int serial8250_default_handle_irq(struct uart_port *port)
1853 struct uart_8250_port *up = up_to_u8250p(port);
1857 serial8250_rpm_get(up);
1859 iir = serial_port_in(port, UART_IIR);
1860 ret = serial8250_handle_irq(port, iir);
1862 serial8250_rpm_put(up);
1867 * These Exar UARTs have an extra interrupt indicator that could
1868 * fire for a few unimplemented interrupts. One of which is a
1869 * wakeup event when coming out of sleep. Put this here just
1870 * to be on the safe side that these interrupts don't go unhandled.
1872 static int exar_handle_irq(struct uart_port *port)
1874 unsigned int iir = serial_port_in(port, UART_IIR);
1877 ret = serial8250_handle_irq(port, iir);
1879 if ((port->type == PORT_XR17V35X) ||
1880 (port->type == PORT_XR17D15X)) {
1881 serial_port_in(port, 0x80);
1882 serial_port_in(port, 0x81);
1883 serial_port_in(port, 0x82);
1884 serial_port_in(port, 0x83);
1891 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1892 * have a programmable TX threshold that triggers the THRE interrupt in
1893 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1894 * has space available. Load it up with tx_loadsz bytes.
1896 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1898 unsigned long flags;
1899 unsigned int iir = serial_port_in(port, UART_IIR);
1901 /* TX Threshold IRQ triggered so load up FIFO */
1902 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1903 struct uart_8250_port *up = up_to_u8250p(port);
1905 spin_lock_irqsave(&port->lock, flags);
1906 serial8250_tx_chars(up);
1907 spin_unlock_irqrestore(&port->lock, flags);
1910 iir = serial_port_in(port, UART_IIR);
1911 return serial8250_handle_irq(port, iir);
1914 static unsigned int serial8250_tx_empty(struct uart_port *port)
1916 struct uart_8250_port *up = up_to_u8250p(port);
1917 unsigned long flags;
1920 serial8250_rpm_get(up);
1922 spin_lock_irqsave(&port->lock, flags);
1923 lsr = serial_port_in(port, UART_LSR);
1924 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1925 spin_unlock_irqrestore(&port->lock, flags);
1927 serial8250_rpm_put(up);
1929 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1932 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1934 struct uart_8250_port *up = up_to_u8250p(port);
1935 unsigned int status;
1938 serial8250_rpm_get(up);
1939 status = serial8250_modem_status(up);
1940 serial8250_rpm_put(up);
1943 if (status & UART_MSR_DCD)
1945 if (status & UART_MSR_RI)
1947 if (status & UART_MSR_DSR)
1949 if (status & UART_MSR_CTS)
1953 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1955 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1957 if (port->get_mctrl)
1958 return port->get_mctrl(port);
1959 return serial8250_do_get_mctrl(port);
1962 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1964 struct uart_8250_port *up = up_to_u8250p(port);
1965 unsigned char mcr = 0;
1967 if (mctrl & TIOCM_RTS)
1968 mcr |= UART_MCR_RTS;
1969 if (mctrl & TIOCM_DTR)
1970 mcr |= UART_MCR_DTR;
1971 if (mctrl & TIOCM_OUT1)
1972 mcr |= UART_MCR_OUT1;
1973 if (mctrl & TIOCM_OUT2)
1974 mcr |= UART_MCR_OUT2;
1975 if (mctrl & TIOCM_LOOP)
1976 mcr |= UART_MCR_LOOP;
1978 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1980 serial8250_out_MCR(up, mcr);
1982 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1984 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1986 if (port->set_mctrl)
1987 port->set_mctrl(port, mctrl);
1989 serial8250_do_set_mctrl(port, mctrl);
1992 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1994 struct uart_8250_port *up = up_to_u8250p(port);
1995 unsigned long flags;
1997 serial8250_rpm_get(up);
1998 spin_lock_irqsave(&port->lock, flags);
1999 if (break_state == -1)
2000 up->lcr |= UART_LCR_SBC;
2002 up->lcr &= ~UART_LCR_SBC;
2003 serial_port_out(port, UART_LCR, up->lcr);
2004 spin_unlock_irqrestore(&port->lock, flags);
2005 serial8250_rpm_put(up);
2009 * Wait for transmitter & holding register to empty
2011 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2013 unsigned int status, tmout = 10000;
2015 /* Wait up to 10ms for the character(s) to be sent. */
2017 status = serial_in(up, UART_LSR);
2019 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2021 if ((status & bits) == bits)
2026 touch_nmi_watchdog();
2029 /* Wait up to 1s for flow control if necessary */
2030 if (up->port.flags & UPF_CONS_FLOW) {
2031 for (tmout = 1000000; tmout; tmout--) {
2032 unsigned int msr = serial_in(up, UART_MSR);
2033 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2034 if (msr & UART_MSR_CTS)
2037 touch_nmi_watchdog();
2042 #ifdef CONFIG_CONSOLE_POLL
2044 * Console polling routines for writing and reading from the uart while
2045 * in an interrupt or debug context.
2048 static int serial8250_get_poll_char(struct uart_port *port)
2050 struct uart_8250_port *up = up_to_u8250p(port);
2054 serial8250_rpm_get(up);
2056 lsr = serial_port_in(port, UART_LSR);
2058 if (!(lsr & UART_LSR_DR)) {
2059 status = NO_POLL_CHAR;
2063 status = serial_port_in(port, UART_RX);
2065 serial8250_rpm_put(up);
2070 static void serial8250_put_poll_char(struct uart_port *port,
2074 struct uart_8250_port *up = up_to_u8250p(port);
2076 serial8250_rpm_get(up);
2078 * First save the IER then disable the interrupts
2080 ier = serial_port_in(port, UART_IER);
2081 if (up->capabilities & UART_CAP_UUE)
2082 serial_port_out(port, UART_IER, UART_IER_UUE);
2084 serial_port_out(port, UART_IER, 0);
2086 wait_for_xmitr(up, BOTH_EMPTY);
2088 * Send the character out.
2090 serial_port_out(port, UART_TX, c);
2093 * Finally, wait for transmitter to become empty
2094 * and restore the IER
2096 wait_for_xmitr(up, BOTH_EMPTY);
2097 serial_port_out(port, UART_IER, ier);
2098 serial8250_rpm_put(up);
2101 #endif /* CONFIG_CONSOLE_POLL */
2103 int serial8250_do_startup(struct uart_port *port)
2105 struct uart_8250_port *up = up_to_u8250p(port);
2106 unsigned long flags;
2107 unsigned char lsr, iir;
2110 if (!port->fifosize)
2111 port->fifosize = uart_config[port->type].fifo_size;
2113 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2114 if (!up->capabilities)
2115 up->capabilities = uart_config[port->type].flags;
2118 if (port->iotype != up->cur_iotype)
2119 set_io_from_upio(port);
2121 serial8250_rpm_get(up);
2122 if (port->type == PORT_16C950) {
2123 /* Wake up and initialize UART */
2125 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2126 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2127 serial_port_out(port, UART_IER, 0);
2128 serial_port_out(port, UART_LCR, 0);
2129 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2130 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2131 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2132 serial_port_out(port, UART_LCR, 0);
2135 #ifdef CONFIG_SERIAL_8250_RSA
2137 * If this is an RSA port, see if we can kick it up to the
2138 * higher speed clock.
2143 if (port->type == PORT_XR17V35X) {
2145 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2146 * MCR [7:5] and MSR [7:0]
2148 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2151 * Make sure all interrups are masked until initialization is
2152 * complete and the FIFOs are cleared
2154 serial_port_out(port, UART_IER, 0);
2158 * Clear the FIFO buffers and disable them.
2159 * (they will be reenabled in set_termios())
2161 serial8250_clear_fifos(up);
2164 * Clear the interrupt registers.
2166 serial_port_in(port, UART_LSR);
2167 serial_port_in(port, UART_RX);
2168 serial_port_in(port, UART_IIR);
2169 serial_port_in(port, UART_MSR);
2172 * At this point, there's no way the LSR could still be 0xff;
2173 * if it is, then bail out, because there's likely no UART
2176 if (!(port->flags & UPF_BUGGY_UART) &&
2177 (serial_port_in(port, UART_LSR) == 0xff)) {
2178 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2179 serial_index(port));
2185 * For a XR16C850, we need to set the trigger levels
2187 if (port->type == PORT_16850) {
2190 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2192 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2193 serial_port_out(port, UART_FCTR,
2194 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2195 serial_port_out(port, UART_TRG, UART_TRG_96);
2196 serial_port_out(port, UART_FCTR,
2197 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2198 serial_port_out(port, UART_TRG, UART_TRG_96);
2200 serial_port_out(port, UART_LCR, 0);
2204 * For the Altera 16550 variants, set TX threshold trigger level.
2206 if (((port->type == PORT_ALTR_16550_F32) ||
2207 (port->type == PORT_ALTR_16550_F64) ||
2208 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2209 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2210 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2211 pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2212 serial_index(port));
2214 serial_port_out(port, UART_ALTR_AFR,
2215 UART_ALTR_EN_TXFIFO_LW);
2216 serial_port_out(port, UART_ALTR_TX_LOW,
2217 port->fifosize - up->tx_loadsz);
2218 port->handle_irq = serial8250_tx_threshold_handle_irq;
2222 /* Check if we need to have shared IRQs */
2223 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2224 up->port.irqflags |= IRQF_SHARED;
2229 if (port->irqflags & IRQF_SHARED)
2230 disable_irq_nosync(port->irq);
2233 * Test for UARTs that do not reassert THRE when the
2234 * transmitter is idle and the interrupt has already
2235 * been cleared. Real 16550s should always reassert
2236 * this interrupt whenever the transmitter is idle and
2237 * the interrupt is enabled. Delays are necessary to
2238 * allow register changes to become visible.
2240 spin_lock_irqsave(&port->lock, flags);
2242 wait_for_xmitr(up, UART_LSR_THRE);
2243 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2244 udelay(1); /* allow THRE to set */
2245 iir1 = serial_port_in(port, UART_IIR);
2246 serial_port_out(port, UART_IER, 0);
2247 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2248 udelay(1); /* allow a working UART time to re-assert THRE */
2249 iir = serial_port_in(port, UART_IIR);
2250 serial_port_out(port, UART_IER, 0);
2252 spin_unlock_irqrestore(&port->lock, flags);
2254 if (port->irqflags & IRQF_SHARED)
2255 enable_irq(port->irq);
2258 * If the interrupt is not reasserted, or we otherwise
2259 * don't trust the iir, setup a timer to kick the UART
2260 * on a regular basis.
2262 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2263 up->port.flags & UPF_BUG_THRE) {
2264 up->bugs |= UART_BUG_THRE;
2268 retval = up->ops->setup_irq(up);
2273 * Now, initialize the UART
2275 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2277 spin_lock_irqsave(&port->lock, flags);
2278 if (up->port.flags & UPF_FOURPORT) {
2280 up->port.mctrl |= TIOCM_OUT1;
2283 * Most PC uarts need OUT2 raised to enable interrupts.
2286 up->port.mctrl |= TIOCM_OUT2;
2288 serial8250_set_mctrl(port, port->mctrl);
2291 * Serial over Lan (SoL) hack:
2292 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2293 * used for Serial Over Lan. Those chips take a longer time than a
2294 * normal serial device to signalize that a transmission data was
2295 * queued. Due to that, the above test generally fails. One solution
2296 * would be to delay the reading of iir. However, this is not
2297 * reliable, since the timeout is variable. So, let's just don't
2298 * test if we receive TX irq. This way, we'll never enable
2301 if (up->port.flags & UPF_NO_TXEN_TEST)
2302 goto dont_test_tx_en;
2305 * Do a quick test to see if we receive an interrupt when we enable
2308 serial_port_out(port, UART_IER, UART_IER_THRI);
2309 lsr = serial_port_in(port, UART_LSR);
2310 iir = serial_port_in(port, UART_IIR);
2311 serial_port_out(port, UART_IER, 0);
2313 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2314 if (!(up->bugs & UART_BUG_TXEN)) {
2315 up->bugs |= UART_BUG_TXEN;
2316 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2317 serial_index(port));
2320 up->bugs &= ~UART_BUG_TXEN;
2324 spin_unlock_irqrestore(&port->lock, flags);
2327 * Clear the interrupt registers again for luck, and clear the
2328 * saved flags to avoid getting false values from polling
2329 * routines or the previous session.
2331 serial_port_in(port, UART_LSR);
2332 serial_port_in(port, UART_RX);
2333 serial_port_in(port, UART_IIR);
2334 serial_port_in(port, UART_MSR);
2335 up->lsr_saved_flags = 0;
2336 up->msr_saved_flags = 0;
2339 * Request DMA channels for both RX and TX.
2342 retval = serial8250_request_dma(up);
2344 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2345 serial_index(port));
2351 * Set the IER shadow for rx interrupts but defer actual interrupt
2352 * enable until after the FIFOs are enabled; otherwise, an already-
2353 * active sender can swamp the interrupt handler with "too much work".
2355 up->ier = UART_IER_RLSI | UART_IER_RDI;
2357 if (port->flags & UPF_FOURPORT) {
2360 * Enable interrupts on the AST Fourport board
2362 icp = (port->iobase & 0xfe0) | 0x01f;
2368 serial8250_rpm_put(up);
2371 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2373 static int serial8250_startup(struct uart_port *port)
2376 return port->startup(port);
2377 return serial8250_do_startup(port);
2380 void serial8250_do_shutdown(struct uart_port *port)
2382 struct uart_8250_port *up = up_to_u8250p(port);
2383 unsigned long flags;
2385 serial8250_rpm_get(up);
2387 * Disable interrupts from this port
2389 spin_lock_irqsave(&port->lock, flags);
2391 serial_port_out(port, UART_IER, 0);
2392 spin_unlock_irqrestore(&port->lock, flags);
2394 synchronize_irq(port->irq);
2397 serial8250_release_dma(up);
2399 spin_lock_irqsave(&port->lock, flags);
2400 if (port->flags & UPF_FOURPORT) {
2401 /* reset interrupts on the AST Fourport board */
2402 inb((port->iobase & 0xfe0) | 0x1f);
2403 port->mctrl |= TIOCM_OUT1;
2405 port->mctrl &= ~TIOCM_OUT2;
2407 serial8250_set_mctrl(port, port->mctrl);
2408 spin_unlock_irqrestore(&port->lock, flags);
2411 * Disable break condition and FIFOs
2413 serial_port_out(port, UART_LCR,
2414 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2415 serial8250_clear_fifos(up);
2417 #ifdef CONFIG_SERIAL_8250_RSA
2419 * Reset the RSA board back to 115kbps compat mode.
2425 * Read data port to reset things, and then unlink from
2428 serial_port_in(port, UART_RX);
2429 serial8250_rpm_put(up);
2431 up->ops->release_irq(up);
2433 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2435 static void serial8250_shutdown(struct uart_port *port)
2438 port->shutdown(port);
2440 serial8250_do_shutdown(port);
2444 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2445 * Calculate divisor with extra 4-bit fractional portion
2447 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2451 struct uart_port *port = &up->port;
2452 unsigned int quot_16;
2454 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2455 *frac = quot_16 & 0x0f;
2457 return quot_16 >> 4;
2460 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2464 struct uart_port *port = &up->port;
2468 * Handle magic divisors for baud rates above baud_base on
2469 * SMSC SuperIO chips.
2472 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2473 baud == (port->uartclk/4))
2475 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2476 baud == (port->uartclk/8))
2478 else if (up->port.type == PORT_XR17V35X)
2479 quot = xr17v35x_get_divisor(up, baud, frac);
2481 quot = uart_get_divisor(port, baud);
2484 * Oxford Semi 952 rev B workaround
2486 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2492 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2497 switch (c_cflag & CSIZE) {
2499 cval = UART_LCR_WLEN5;
2502 cval = UART_LCR_WLEN6;
2505 cval = UART_LCR_WLEN7;
2509 cval = UART_LCR_WLEN8;
2513 if (c_cflag & CSTOPB)
2514 cval |= UART_LCR_STOP;
2515 if (c_cflag & PARENB) {
2516 cval |= UART_LCR_PARITY;
2517 if (up->bugs & UART_BUG_PARITY)
2518 up->fifo_bug = true;
2520 if (!(c_cflag & PARODD))
2521 cval |= UART_LCR_EPAR;
2523 if (c_cflag & CMSPAR)
2524 cval |= UART_LCR_SPAR;
2530 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2531 unsigned int quot, unsigned int quot_frac)
2533 struct uart_8250_port *up = up_to_u8250p(port);
2535 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2536 if (is_omap1510_8250(up)) {
2537 if (baud == 115200) {
2539 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2541 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2545 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2546 * otherwise just set DLAB
2548 if (up->capabilities & UART_NATSEMI)
2549 serial_port_out(port, UART_LCR, 0xe0);
2551 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2553 serial_dl_write(up, quot);
2555 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2556 if (up->port.type == PORT_XR17V35X) {
2557 /* Preserve bits not related to baudrate; DLD[7:4]. */
2558 quot_frac |= serial_port_in(port, 0x2) & 0xf0;
2559 serial_port_out(port, 0x2, quot_frac);
2563 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2564 struct ktermios *termios,
2565 struct ktermios *old)
2568 * Ask the core to calculate the divisor for us.
2569 * Allow 1% tolerance at the upper limit so uart clks marginally
2570 * slower than nominal still match standard baud rates without
2571 * causing transmission errors.
2573 return uart_get_baud_rate(port, termios, old,
2574 port->uartclk / 16 / 0xffff,
2579 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2580 struct ktermios *old)
2582 struct uart_8250_port *up = up_to_u8250p(port);
2584 unsigned long flags;
2585 unsigned int baud, quot, frac = 0;
2587 cval = serial8250_compute_lcr(up, termios->c_cflag);
2589 baud = serial8250_get_baud_rate(port, termios, old);
2590 quot = serial8250_get_divisor(up, baud, &frac);
2593 * Ok, we're now changing the port state. Do it with
2594 * interrupts disabled.
2596 serial8250_rpm_get(up);
2597 spin_lock_irqsave(&port->lock, flags);
2599 up->lcr = cval; /* Save computed LCR */
2601 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2602 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2603 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2604 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2605 up->fcr |= UART_FCR_TRIGGER_1;
2610 * MCR-based auto flow control. When AFE is enabled, RTS will be
2611 * deasserted when the receive FIFO contains more characters than
2612 * the trigger, or the MCR RTS bit is cleared.
2614 if (up->capabilities & UART_CAP_AFE) {
2615 up->mcr &= ~UART_MCR_AFE;
2616 if (termios->c_cflag & CRTSCTS)
2617 up->mcr |= UART_MCR_AFE;
2621 * Update the per-port timeout.
2623 uart_update_timeout(port, termios->c_cflag, baud);
2625 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2626 if (termios->c_iflag & INPCK)
2627 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2628 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2629 port->read_status_mask |= UART_LSR_BI;
2632 * Characteres to ignore
2634 port->ignore_status_mask = 0;
2635 if (termios->c_iflag & IGNPAR)
2636 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2637 if (termios->c_iflag & IGNBRK) {
2638 port->ignore_status_mask |= UART_LSR_BI;
2640 * If we're ignoring parity and break indicators,
2641 * ignore overruns too (for real raw support).
2643 if (termios->c_iflag & IGNPAR)
2644 port->ignore_status_mask |= UART_LSR_OE;
2648 * ignore all characters if CREAD is not set
2650 if ((termios->c_cflag & CREAD) == 0)
2651 port->ignore_status_mask |= UART_LSR_DR;
2654 * CTS flow control flag and modem status interrupts
2656 up->ier &= ~UART_IER_MSI;
2657 if (!(up->bugs & UART_BUG_NOMSR) &&
2658 UART_ENABLE_MS(&up->port, termios->c_cflag))
2659 up->ier |= UART_IER_MSI;
2660 if (up->capabilities & UART_CAP_UUE)
2661 up->ier |= UART_IER_UUE;
2662 if (up->capabilities & UART_CAP_RTOIE)
2663 up->ier |= UART_IER_RTOIE;
2665 serial_port_out(port, UART_IER, up->ier);
2667 if (up->capabilities & UART_CAP_EFR) {
2668 unsigned char efr = 0;
2670 * TI16C752/Startech hardware flow control. FIXME:
2671 * - TI16C752 requires control thresholds to be set.
2672 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2674 if (termios->c_cflag & CRTSCTS)
2675 efr |= UART_EFR_CTS;
2677 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2678 if (port->flags & UPF_EXAR_EFR)
2679 serial_port_out(port, UART_XR_EFR, efr);
2681 serial_port_out(port, UART_EFR, efr);
2684 serial8250_set_divisor(port, baud, quot, frac);
2687 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2688 * is written without DLAB set, this mode will be disabled.
2690 if (port->type == PORT_16750)
2691 serial_port_out(port, UART_FCR, up->fcr);
2693 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2694 if (port->type != PORT_16750) {
2695 /* emulated UARTs (Lucent Venus 167x) need two steps */
2696 if (up->fcr & UART_FCR_ENABLE_FIFO)
2697 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2698 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2700 serial8250_set_mctrl(port, port->mctrl);
2701 spin_unlock_irqrestore(&port->lock, flags);
2702 serial8250_rpm_put(up);
2704 /* Don't rewrite B0 */
2705 if (tty_termios_baud_rate(termios))
2706 tty_termios_encode_baud_rate(termios, baud, baud);
2708 EXPORT_SYMBOL(serial8250_do_set_termios);
2711 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2712 struct ktermios *old)
2714 if (port->set_termios)
2715 port->set_termios(port, termios, old);
2717 serial8250_do_set_termios(port, termios, old);
2721 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2723 if (termios->c_line == N_PPS) {
2724 port->flags |= UPF_HARDPPS_CD;
2725 spin_lock_irq(&port->lock);
2726 serial8250_enable_ms(port);
2727 spin_unlock_irq(&port->lock);
2729 port->flags &= ~UPF_HARDPPS_CD;
2730 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2731 spin_lock_irq(&port->lock);
2732 serial8250_disable_ms(port);
2733 spin_unlock_irq(&port->lock);
2739 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2740 unsigned int oldstate)
2742 struct uart_8250_port *p = up_to_u8250p(port);
2744 serial8250_set_sleep(p, state != 0);
2746 EXPORT_SYMBOL(serial8250_do_pm);
2749 serial8250_pm(struct uart_port *port, unsigned int state,
2750 unsigned int oldstate)
2753 port->pm(port, state, oldstate);
2755 serial8250_do_pm(port, state, oldstate);
2758 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2760 if (pt->port.mapsize)
2761 return pt->port.mapsize;
2762 if (pt->port.iotype == UPIO_AU) {
2763 if (pt->port.type == PORT_RT2880)
2767 if (is_omap1_8250(pt))
2768 return 0x16 << pt->port.regshift;
2770 return 8 << pt->port.regshift;
2774 * Resource handling.
2776 static int serial8250_request_std_resource(struct uart_8250_port *up)
2778 unsigned int size = serial8250_port_size(up);
2779 struct uart_port *port = &up->port;
2782 switch (port->iotype) {
2792 if (!request_mem_region(port->mapbase, size, "serial")) {
2797 if (port->flags & UPF_IOREMAP) {
2798 port->membase = ioremap_nocache(port->mapbase, size);
2799 if (!port->membase) {
2800 release_mem_region(port->mapbase, size);
2808 if (!request_region(port->iobase, size, "serial"))
2815 static void serial8250_release_std_resource(struct uart_8250_port *up)
2817 unsigned int size = serial8250_port_size(up);
2818 struct uart_port *port = &up->port;
2820 switch (port->iotype) {
2830 if (port->flags & UPF_IOREMAP) {
2831 iounmap(port->membase);
2832 port->membase = NULL;
2835 release_mem_region(port->mapbase, size);
2840 release_region(port->iobase, size);
2845 static void serial8250_release_port(struct uart_port *port)
2847 struct uart_8250_port *up = up_to_u8250p(port);
2849 serial8250_release_std_resource(up);
2852 static int serial8250_request_port(struct uart_port *port)
2854 struct uart_8250_port *up = up_to_u8250p(port);
2856 return serial8250_request_std_resource(up);
2859 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2861 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2862 unsigned char bytes;
2864 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2866 return bytes ? bytes : -EOPNOTSUPP;
2869 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2871 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2874 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2877 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2878 if (bytes < conf_type->rxtrig_bytes[i])
2879 /* Use the nearest lower value */
2880 return (--i) << UART_FCR_R_TRIG_SHIFT;
2883 return UART_FCR_R_TRIG_11;
2886 static int do_get_rxtrig(struct tty_port *port)
2888 struct uart_state *state = container_of(port, struct uart_state, port);
2889 struct uart_port *uport = state->uart_port;
2890 struct uart_8250_port *up = up_to_u8250p(uport);
2892 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2895 return fcr_get_rxtrig_bytes(up);
2898 static int do_serial8250_get_rxtrig(struct tty_port *port)
2902 mutex_lock(&port->mutex);
2903 rxtrig_bytes = do_get_rxtrig(port);
2904 mutex_unlock(&port->mutex);
2906 return rxtrig_bytes;
2909 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2910 struct device_attribute *attr, char *buf)
2912 struct tty_port *port = dev_get_drvdata(dev);
2915 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2916 if (rxtrig_bytes < 0)
2917 return rxtrig_bytes;
2919 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2922 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2924 struct uart_state *state = container_of(port, struct uart_state, port);
2925 struct uart_port *uport = state->uart_port;
2926 struct uart_8250_port *up = up_to_u8250p(uport);
2929 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2933 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2937 serial8250_clear_fifos(up);
2938 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2939 up->fcr |= (unsigned char)rxtrig;
2940 serial_out(up, UART_FCR, up->fcr);
2944 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2948 mutex_lock(&port->mutex);
2949 ret = do_set_rxtrig(port, bytes);
2950 mutex_unlock(&port->mutex);
2955 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2956 struct device_attribute *attr, const char *buf, size_t count)
2958 struct tty_port *port = dev_get_drvdata(dev);
2959 unsigned char bytes;
2965 ret = kstrtou8(buf, 10, &bytes);
2969 ret = do_serial8250_set_rxtrig(port, bytes);
2976 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2977 serial8250_get_attr_rx_trig_bytes,
2978 serial8250_set_attr_rx_trig_bytes);
2980 static struct attribute *serial8250_dev_attrs[] = {
2981 &dev_attr_rx_trig_bytes.attr,
2985 static struct attribute_group serial8250_dev_attr_group = {
2986 .attrs = serial8250_dev_attrs,
2989 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2991 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2993 if (conf_type->rxtrig_bytes[0])
2994 up->port.attr_group = &serial8250_dev_attr_group;
2997 static void serial8250_config_port(struct uart_port *port, int flags)
2999 struct uart_8250_port *up = up_to_u8250p(port);
3003 * Find the region that we can probe for. This in turn
3004 * tells us whether we can probe for the type of port.
3006 ret = serial8250_request_std_resource(up);
3010 if (port->iotype != up->cur_iotype)
3011 set_io_from_upio(port);
3013 if (flags & UART_CONFIG_TYPE)
3016 /* if access method is AU, it is a 16550 with a quirk */
3017 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3018 up->bugs |= UART_BUG_NOMSR;
3020 /* HW bugs may trigger IRQ while IIR == NO_INT */
3021 if (port->type == PORT_TEGRA)
3022 up->bugs |= UART_BUG_NOMSR;
3024 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3027 if (port->type == PORT_UNKNOWN)
3028 serial8250_release_std_resource(up);
3030 /* Fixme: probably not the best place for this */
3031 if ((port->type == PORT_XR17V35X) ||
3032 (port->type == PORT_XR17D15X))
3033 port->handle_irq = exar_handle_irq;
3035 register_dev_spec_attr_grp(up);
3036 up->fcr = uart_config[up->port.type].fcr;
3040 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3042 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3043 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3044 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3045 ser->type == PORT_STARTECH)
3050 static const char *serial8250_type(struct uart_port *port)
3052 int type = port->type;
3054 if (type >= ARRAY_SIZE(uart_config))
3056 return uart_config[type].name;
3059 static const struct uart_ops serial8250_pops = {
3060 .tx_empty = serial8250_tx_empty,
3061 .set_mctrl = serial8250_set_mctrl,
3062 .get_mctrl = serial8250_get_mctrl,
3063 .stop_tx = serial8250_stop_tx,
3064 .start_tx = serial8250_start_tx,
3065 .throttle = serial8250_throttle,
3066 .unthrottle = serial8250_unthrottle,
3067 .stop_rx = serial8250_stop_rx,
3068 .enable_ms = serial8250_enable_ms,
3069 .break_ctl = serial8250_break_ctl,
3070 .startup = serial8250_startup,
3071 .shutdown = serial8250_shutdown,
3072 .set_termios = serial8250_set_termios,
3073 .set_ldisc = serial8250_set_ldisc,
3074 .pm = serial8250_pm,
3075 .type = serial8250_type,
3076 .release_port = serial8250_release_port,
3077 .request_port = serial8250_request_port,
3078 .config_port = serial8250_config_port,
3079 .verify_port = serial8250_verify_port,
3080 #ifdef CONFIG_CONSOLE_POLL
3081 .poll_get_char = serial8250_get_poll_char,
3082 .poll_put_char = serial8250_put_poll_char,
3086 void serial8250_init_port(struct uart_8250_port *up)
3088 struct uart_port *port = &up->port;
3090 spin_lock_init(&port->lock);
3091 port->ops = &serial8250_pops;
3093 up->cur_iotype = 0xFF;
3095 EXPORT_SYMBOL_GPL(serial8250_init_port);
3097 void serial8250_set_defaults(struct uart_8250_port *up)
3099 struct uart_port *port = &up->port;
3101 if (up->port.flags & UPF_FIXED_TYPE) {
3102 unsigned int type = up->port.type;
3104 if (!up->port.fifosize)
3105 up->port.fifosize = uart_config[type].fifo_size;
3107 up->tx_loadsz = uart_config[type].tx_loadsz;
3108 if (!up->capabilities)
3109 up->capabilities = uart_config[type].flags;
3112 set_io_from_upio(port);
3114 /* default dma handlers */
3116 if (!up->dma->tx_dma)
3117 up->dma->tx_dma = serial8250_tx_dma;
3118 if (!up->dma->rx_dma)
3119 up->dma->rx_dma = serial8250_rx_dma;
3122 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3124 #ifdef CONFIG_SERIAL_8250_CONSOLE
3126 static void serial8250_console_putchar(struct uart_port *port, int ch)
3128 struct uart_8250_port *up = up_to_u8250p(port);
3130 wait_for_xmitr(up, UART_LSR_THRE);
3131 serial_port_out(port, UART_TX, ch);
3135 * Restore serial console when h/w power-off detected
3137 static void serial8250_console_restore(struct uart_8250_port *up)
3139 struct uart_port *port = &up->port;
3140 struct ktermios termios;
3141 unsigned int baud, quot, frac = 0;
3143 termios.c_cflag = port->cons->cflag;
3144 if (port->state->port.tty && termios.c_cflag == 0)
3145 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3147 baud = serial8250_get_baud_rate(port, &termios, NULL);
3148 quot = serial8250_get_divisor(up, baud, &frac);
3150 serial8250_set_divisor(port, baud, quot, frac);
3151 serial_port_out(port, UART_LCR, up->lcr);
3152 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3156 * Print a string to the serial port trying not to disturb
3157 * any possible real use of the port...
3159 * The console_lock must be held when we get here.
3161 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3164 struct uart_port *port = &up->port;
3165 unsigned long flags;
3169 touch_nmi_watchdog();
3171 serial8250_rpm_get(up);
3175 else if (oops_in_progress)
3176 locked = spin_trylock_irqsave(&port->lock, flags);
3178 spin_lock_irqsave(&port->lock, flags);
3181 * First save the IER then disable the interrupts
3183 ier = serial_port_in(port, UART_IER);
3185 if (up->capabilities & UART_CAP_UUE)
3186 serial_port_out(port, UART_IER, UART_IER_UUE);
3188 serial_port_out(port, UART_IER, 0);
3190 /* check scratch reg to see if port powered off during system sleep */
3191 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3192 serial8250_console_restore(up);
3196 uart_console_write(port, s, count, serial8250_console_putchar);
3199 * Finally, wait for transmitter to become empty
3200 * and restore the IER
3202 wait_for_xmitr(up, BOTH_EMPTY);
3203 serial_port_out(port, UART_IER, ier);
3206 * The receive handling will happen properly because the
3207 * receive ready bit will still be set; it is not cleared
3208 * on read. However, modem control will not, we must
3209 * call it if we have saved something in the saved flags
3210 * while processing with interrupts off.
3212 if (up->msr_saved_flags)
3213 serial8250_modem_status(up);
3216 spin_unlock_irqrestore(&port->lock, flags);
3217 serial8250_rpm_put(up);
3220 static unsigned int probe_baud(struct uart_port *port)
3222 unsigned char lcr, dll, dlm;
3225 lcr = serial_port_in(port, UART_LCR);
3226 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3227 dll = serial_port_in(port, UART_DLL);
3228 dlm = serial_port_in(port, UART_DLM);
3229 serial_port_out(port, UART_LCR, lcr);
3231 quot = (dlm << 8) | dll;
3232 return (port->uartclk / 16) / quot;
3235 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3242 if (!port->iobase && !port->membase)
3246 uart_parse_options(options, &baud, &parity, &bits, &flow);
3248 baud = probe_baud(port);
3250 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3253 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3255 MODULE_LICENSE("GPL");