2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/timer.h>
51 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
53 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
56 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
59 * Here we define the default xmit fifo size used for each type of UART.
61 static const struct serial8250_config uart_config[] = {
86 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
87 .rxtrig_bytes = {1, 4, 8, 14},
88 .flags = UART_CAP_FIFO,
99 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
105 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
107 .rxtrig_bytes = {8, 16, 24, 28},
108 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
114 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
116 .rxtrig_bytes = {1, 16, 32, 56},
117 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
125 .name = "16C950/954",
128 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
129 .rxtrig_bytes = {16, 32, 112, 120},
130 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
131 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
137 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
139 .rxtrig_bytes = {8, 16, 56, 60},
140 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
146 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
147 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
153 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
154 .flags = UART_CAP_FIFO,
160 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
161 .flags = UART_CAP_FIFO | UART_NATSEMI,
167 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
168 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
174 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
175 .flags = UART_CAP_FIFO,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
182 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
188 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
189 .flags = UART_CAP_FIFO | UART_CAP_AFE,
195 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
197 .rxtrig_bytes = {1, 4, 8, 14},
198 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
204 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
205 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
212 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
214 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
221 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
222 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
223 .flags = UART_CAP_FIFO,
225 [PORT_BRCM_TRUMANAGE] = {
229 .flags = UART_CAP_HFIFO,
234 [PORT_ALTR_16550_F32] = {
235 .name = "Altera 16550 FIFO32",
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
239 .flags = UART_CAP_FIFO | UART_CAP_AFE,
241 [PORT_ALTR_16550_F64] = {
242 .name = "Altera 16550 FIFO64",
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_AFE,
248 [PORT_ALTR_16550_F128] = {
249 .name = "Altera 16550 FIFO128",
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_AFE,
256 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
257 * workaround of errata A-008006 which states that tx_loadsz should
258 * be configured less than Maximum supported fifo bytes.
260 [PORT_16550A_FSL64] = {
261 .name = "16550A_FSL64",
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
266 .flags = UART_CAP_FIFO,
269 .name = "Palmchip BK-3103",
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .rxtrig_bytes = {1, 4, 8, 14},
274 .flags = UART_CAP_FIFO,
278 /* Uart divisor latch read */
279 static int default_serial_dl_read(struct uart_8250_port *up)
281 /* Assign these in pieces to truncate any bits above 7. */
282 unsigned char dll = serial_in(up, UART_DLL);
283 unsigned char dlm = serial_in(up, UART_DLM);
285 return dll | dlm << 8;
288 /* Uart divisor latch write */
289 static void default_serial_dl_write(struct uart_8250_port *up, int value)
291 serial_out(up, UART_DLL, value & 0xff);
292 serial_out(up, UART_DLM, value >> 8 & 0xff);
295 #ifdef CONFIG_SERIAL_8250_RT288X
297 /* Au1x00/RT288x UART hardware has a weird register layout */
298 static const s8 au_io_in_map[8] = {
306 -1, /* UART_SCR (unmapped) */
309 static const s8 au_io_out_map[8] = {
315 -1, /* UART_LSR (unmapped) */
316 -1, /* UART_MSR (unmapped) */
317 -1, /* UART_SCR (unmapped) */
320 static unsigned int au_serial_in(struct uart_port *p, int offset)
322 if (offset >= ARRAY_SIZE(au_io_in_map))
324 offset = au_io_in_map[offset];
327 return __raw_readl(p->membase + (offset << p->regshift));
330 static void au_serial_out(struct uart_port *p, int offset, int value)
332 if (offset >= ARRAY_SIZE(au_io_out_map))
334 offset = au_io_out_map[offset];
337 __raw_writel(value, p->membase + (offset << p->regshift));
340 /* Au1x00 haven't got a standard divisor latch */
341 static int au_serial_dl_read(struct uart_8250_port *up)
343 return __raw_readl(up->port.membase + 0x28);
346 static void au_serial_dl_write(struct uart_8250_port *up, int value)
348 __raw_writel(value, up->port.membase + 0x28);
353 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
355 offset = offset << p->regshift;
356 outb(p->hub6 - 1 + offset, p->iobase);
357 return inb(p->iobase + 1);
360 static void hub6_serial_out(struct uart_port *p, int offset, int value)
362 offset = offset << p->regshift;
363 outb(p->hub6 - 1 + offset, p->iobase);
364 outb(value, p->iobase + 1);
367 static unsigned int mem_serial_in(struct uart_port *p, int offset)
369 offset = offset << p->regshift;
370 return readb(p->membase + offset);
373 static void mem_serial_out(struct uart_port *p, int offset, int value)
375 offset = offset << p->regshift;
376 writeb(value, p->membase + offset);
379 static void mem16_serial_out(struct uart_port *p, int offset, int value)
381 offset = offset << p->regshift;
382 writew(value, p->membase + offset);
385 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
387 offset = offset << p->regshift;
388 return readw(p->membase + offset);
391 static void mem32_serial_out(struct uart_port *p, int offset, int value)
393 offset = offset << p->regshift;
394 writel(value, p->membase + offset);
397 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
399 offset = offset << p->regshift;
400 return readl(p->membase + offset);
403 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
405 offset = offset << p->regshift;
406 iowrite32be(value, p->membase + offset);
409 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
411 offset = offset << p->regshift;
412 return ioread32be(p->membase + offset);
415 static unsigned int io_serial_in(struct uart_port *p, int offset)
417 offset = offset << p->regshift;
418 return inb(p->iobase + offset);
421 static void io_serial_out(struct uart_port *p, int offset, int value)
423 offset = offset << p->regshift;
424 outb(value, p->iobase + offset);
427 static int serial8250_default_handle_irq(struct uart_port *port);
428 static int exar_handle_irq(struct uart_port *port);
430 static void set_io_from_upio(struct uart_port *p)
432 struct uart_8250_port *up = up_to_u8250p(p);
434 up->dl_read = default_serial_dl_read;
435 up->dl_write = default_serial_dl_write;
439 p->serial_in = hub6_serial_in;
440 p->serial_out = hub6_serial_out;
444 p->serial_in = mem_serial_in;
445 p->serial_out = mem_serial_out;
449 p->serial_in = mem16_serial_in;
450 p->serial_out = mem16_serial_out;
454 p->serial_in = mem32_serial_in;
455 p->serial_out = mem32_serial_out;
459 p->serial_in = mem32be_serial_in;
460 p->serial_out = mem32be_serial_out;
463 #ifdef CONFIG_SERIAL_8250_RT288X
465 p->serial_in = au_serial_in;
466 p->serial_out = au_serial_out;
467 up->dl_read = au_serial_dl_read;
468 up->dl_write = au_serial_dl_write;
473 p->serial_in = io_serial_in;
474 p->serial_out = io_serial_out;
477 /* Remember loaded iotype */
478 up->cur_iotype = p->iotype;
479 p->handle_irq = serial8250_default_handle_irq;
483 serial_port_out_sync(struct uart_port *p, int offset, int value)
491 p->serial_out(p, offset, value);
492 p->serial_in(p, UART_LCR); /* safe, no side-effects */
495 p->serial_out(p, offset, value);
502 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
504 serial_out(up, UART_SCR, offset);
505 serial_out(up, UART_ICR, value);
508 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
512 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
513 serial_out(up, UART_SCR, offset);
514 value = serial_in(up, UART_ICR);
515 serial_icr_write(up, UART_ACR, up->acr);
523 static void serial8250_clear_fifos(struct uart_8250_port *p)
525 if (p->capabilities & UART_CAP_FIFO) {
526 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
527 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
528 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
529 serial_out(p, UART_FCR, 0);
533 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
535 unsigned char mcr = serial8250_in_MCR(p);
537 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
540 mcr &= ~UART_MCR_RTS;
541 serial8250_out_MCR(p, mcr);
544 static void serial8250_em485_handle_start_tx(unsigned long arg);
545 static void serial8250_em485_handle_stop_tx(unsigned long arg);
547 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
549 serial8250_clear_fifos(p);
550 serial_out(p, UART_FCR, p->fcr);
552 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
554 void serial8250_rpm_get(struct uart_8250_port *p)
556 if (!(p->capabilities & UART_CAP_RPM))
558 pm_runtime_get_sync(p->port.dev);
560 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
562 void serial8250_rpm_put(struct uart_8250_port *p)
564 if (!(p->capabilities & UART_CAP_RPM))
566 pm_runtime_mark_last_busy(p->port.dev);
567 pm_runtime_put_autosuspend(p->port.dev);
569 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
572 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
573 * @p: uart_8250_port port instance
575 * The function is used to start rs485 software emulating on the
576 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
577 * transmission. The function is idempotent, so it is safe to call it
580 * The caller MUST enable interrupt on empty shift register before
581 * calling serial8250_em485_init(). This interrupt is not a part of
582 * 8250 standard, but implementation defined.
584 * The function is supposed to be called from .rs485_config callback
585 * or from any other callback protected with p->port.lock spinlock.
587 * See also serial8250_em485_destroy()
589 * Return 0 - success, -errno - otherwise
591 int serial8250_em485_init(struct uart_8250_port *p)
596 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
600 setup_timer(&p->em485->stop_tx_timer,
601 serial8250_em485_handle_stop_tx, (unsigned long)p);
602 setup_timer(&p->em485->start_tx_timer,
603 serial8250_em485_handle_start_tx, (unsigned long)p);
604 p->em485->active_timer = NULL;
606 serial8250_em485_rts_after_send(p);
610 EXPORT_SYMBOL_GPL(serial8250_em485_init);
613 * serial8250_em485_destroy() - put uart_8250_port into normal state
614 * @p: uart_8250_port port instance
616 * The function is used to stop rs485 software emulating on the
617 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
618 * call it multiple times.
620 * The function is supposed to be called from .rs485_config callback
621 * or from any other callback protected with p->port.lock spinlock.
623 * See also serial8250_em485_init()
625 void serial8250_em485_destroy(struct uart_8250_port *p)
630 del_timer(&p->em485->start_tx_timer);
631 del_timer(&p->em485->stop_tx_timer);
636 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
639 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
640 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
641 * empty and the HW can idle again.
643 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
645 unsigned char rpm_active;
647 if (!(p->capabilities & UART_CAP_RPM))
650 rpm_active = xchg(&p->rpm_tx_active, 1);
653 pm_runtime_get_sync(p->port.dev);
656 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
658 unsigned char rpm_active;
660 if (!(p->capabilities & UART_CAP_RPM))
663 rpm_active = xchg(&p->rpm_tx_active, 0);
666 pm_runtime_mark_last_busy(p->port.dev);
667 pm_runtime_put_autosuspend(p->port.dev);
671 * IER sleep support. UARTs which have EFRs need the "extended
672 * capability" bit enabled. Note that on XR16C850s, we need to
673 * reset LCR to write to IER.
675 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
677 unsigned char lcr = 0, efr = 0;
679 * Exar UARTs have a SLEEP register that enables or disables
680 * each UART to enter sleep mode separately. On the XR17V35x the
681 * register is accessible to each UART at the UART_EXAR_SLEEP
682 * offset but the UART channel may only write to the corresponding
685 serial8250_rpm_get(p);
686 if ((p->port.type == PORT_XR17V35X) ||
687 (p->port.type == PORT_XR17D15X)) {
688 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
692 if (p->capabilities & UART_CAP_SLEEP) {
693 if (p->capabilities & UART_CAP_EFR) {
694 lcr = serial_in(p, UART_LCR);
695 efr = serial_in(p, UART_EFR);
696 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
697 serial_out(p, UART_EFR, UART_EFR_ECB);
698 serial_out(p, UART_LCR, 0);
700 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
701 if (p->capabilities & UART_CAP_EFR) {
702 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
703 serial_out(p, UART_EFR, efr);
704 serial_out(p, UART_LCR, lcr);
708 serial8250_rpm_put(p);
711 #ifdef CONFIG_SERIAL_8250_RSA
713 * Attempts to turn on the RSA FIFO. Returns zero on failure.
714 * We set the port uart clock rate if we succeed.
716 static int __enable_rsa(struct uart_8250_port *up)
721 mode = serial_in(up, UART_RSA_MSR);
722 result = mode & UART_RSA_MSR_FIFO;
725 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
726 mode = serial_in(up, UART_RSA_MSR);
727 result = mode & UART_RSA_MSR_FIFO;
731 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
736 static void enable_rsa(struct uart_8250_port *up)
738 if (up->port.type == PORT_RSA) {
739 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
740 spin_lock_irq(&up->port.lock);
742 spin_unlock_irq(&up->port.lock);
744 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
745 serial_out(up, UART_RSA_FRR, 0);
750 * Attempts to turn off the RSA FIFO. Returns zero on failure.
751 * It is unknown why interrupts were disabled in here. However,
752 * the caller is expected to preserve this behaviour by grabbing
753 * the spinlock before calling this function.
755 static void disable_rsa(struct uart_8250_port *up)
760 if (up->port.type == PORT_RSA &&
761 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
762 spin_lock_irq(&up->port.lock);
764 mode = serial_in(up, UART_RSA_MSR);
765 result = !(mode & UART_RSA_MSR_FIFO);
768 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
769 mode = serial_in(up, UART_RSA_MSR);
770 result = !(mode & UART_RSA_MSR_FIFO);
774 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
775 spin_unlock_irq(&up->port.lock);
778 #endif /* CONFIG_SERIAL_8250_RSA */
781 * This is a quickie test to see how big the FIFO is.
782 * It doesn't work at all the time, more's the pity.
784 static int size_fifo(struct uart_8250_port *up)
786 unsigned char old_fcr, old_mcr, old_lcr;
787 unsigned short old_dl;
790 old_lcr = serial_in(up, UART_LCR);
791 serial_out(up, UART_LCR, 0);
792 old_fcr = serial_in(up, UART_FCR);
793 old_mcr = serial8250_in_MCR(up);
794 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
795 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
796 serial8250_out_MCR(up, UART_MCR_LOOP);
797 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
798 old_dl = serial_dl_read(up);
799 serial_dl_write(up, 0x0001);
800 serial_out(up, UART_LCR, 0x03);
801 for (count = 0; count < 256; count++)
802 serial_out(up, UART_TX, count);
803 mdelay(20);/* FIXME - schedule_timeout */
804 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
805 (count < 256); count++)
806 serial_in(up, UART_RX);
807 serial_out(up, UART_FCR, old_fcr);
808 serial8250_out_MCR(up, old_mcr);
809 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
810 serial_dl_write(up, old_dl);
811 serial_out(up, UART_LCR, old_lcr);
817 * Read UART ID using the divisor method - set DLL and DLM to zero
818 * and the revision will be in DLL and device type in DLM. We
819 * preserve the device state across this.
821 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
823 unsigned char old_lcr;
824 unsigned int id, old_dl;
826 old_lcr = serial_in(p, UART_LCR);
827 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
828 old_dl = serial_dl_read(p);
829 serial_dl_write(p, 0);
830 id = serial_dl_read(p);
831 serial_dl_write(p, old_dl);
833 serial_out(p, UART_LCR, old_lcr);
839 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
840 * When this function is called we know it is at least a StarTech
841 * 16650 V2, but it might be one of several StarTech UARTs, or one of
842 * its clones. (We treat the broken original StarTech 16650 V1 as a
843 * 16550, and why not? Startech doesn't seem to even acknowledge its
846 * What evil have men's minds wrought...
848 static void autoconfig_has_efr(struct uart_8250_port *up)
850 unsigned int id1, id2, id3, rev;
853 * Everything with an EFR has SLEEP
855 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
858 * First we check to see if it's an Oxford Semiconductor UART.
860 * If we have to do this here because some non-National
861 * Semiconductor clone chips lock up if you try writing to the
862 * LSR register (which serial_icr_read does)
866 * Check for Oxford Semiconductor 16C950.
868 * EFR [4] must be set else this test fails.
870 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
871 * claims that it's needed for 952 dual UART's (which are not
872 * recommended for new designs).
875 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
876 serial_out(up, UART_EFR, UART_EFR_ECB);
877 serial_out(up, UART_LCR, 0x00);
878 id1 = serial_icr_read(up, UART_ID1);
879 id2 = serial_icr_read(up, UART_ID2);
880 id3 = serial_icr_read(up, UART_ID3);
881 rev = serial_icr_read(up, UART_REV);
883 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
885 if (id1 == 0x16 && id2 == 0xC9 &&
886 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
887 up->port.type = PORT_16C950;
890 * Enable work around for the Oxford Semiconductor 952 rev B
891 * chip which causes it to seriously miscalculate baud rates
894 if (id3 == 0x52 && rev == 0x01)
895 up->bugs |= UART_BUG_QUOT;
900 * We check for a XR16C850 by setting DLL and DLM to 0, and then
901 * reading back DLL and DLM. The chip type depends on the DLM
903 * 0x10 - XR16C850 and the DLL contains the chip revision.
907 id1 = autoconfig_read_divisor_id(up);
908 DEBUG_AUTOCONF("850id=%04x ", id1);
911 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
912 up->port.type = PORT_16850;
917 * It wasn't an XR16C850.
919 * We distinguish between the '654 and the '650 by counting
920 * how many bytes are in the FIFO. I'm using this for now,
921 * since that's the technique that was sent to me in the
922 * serial driver update, but I'm not convinced this works.
923 * I've had problems doing this in the past. -TYT
925 if (size_fifo(up) == 64)
926 up->port.type = PORT_16654;
928 up->port.type = PORT_16650V2;
932 * We detected a chip without a FIFO. Only two fall into
933 * this category - the original 8250 and the 16450. The
934 * 16450 has a scratch register (accessible with LCR=0)
936 static void autoconfig_8250(struct uart_8250_port *up)
938 unsigned char scratch, status1, status2;
940 up->port.type = PORT_8250;
942 scratch = serial_in(up, UART_SCR);
943 serial_out(up, UART_SCR, 0xa5);
944 status1 = serial_in(up, UART_SCR);
945 serial_out(up, UART_SCR, 0x5a);
946 status2 = serial_in(up, UART_SCR);
947 serial_out(up, UART_SCR, scratch);
949 if (status1 == 0xa5 && status2 == 0x5a)
950 up->port.type = PORT_16450;
953 static int broken_efr(struct uart_8250_port *up)
956 * Exar ST16C2550 "A2" devices incorrectly detect as
957 * having an EFR, and report an ID of 0x0201. See
958 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
960 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
967 * We know that the chip has FIFOs. Does it have an EFR? The
968 * EFR is located in the same register position as the IIR and
969 * we know the top two bits of the IIR are currently set. The
970 * EFR should contain zero. Try to read the EFR.
972 static void autoconfig_16550a(struct uart_8250_port *up)
974 unsigned char status1, status2;
975 unsigned int iersave;
977 up->port.type = PORT_16550A;
978 up->capabilities |= UART_CAP_FIFO;
981 * XR17V35x UARTs have an extra divisor register, DLD
982 * that gets enabled with when DLAB is set which will
983 * cause the device to incorrectly match and assign
984 * port type to PORT_16650. The EFR for this UART is
985 * found at offset 0x09. Instead check the Deice ID (DVID)
986 * register for a 2, 4 or 8 port UART.
988 if (up->port.flags & UPF_EXAR_EFR) {
989 status1 = serial_in(up, UART_EXAR_DVID);
990 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
991 DEBUG_AUTOCONF("Exar XR17V35x ");
992 up->port.type = PORT_XR17V35X;
993 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1002 * Check for presence of the EFR when DLAB is set.
1003 * Only ST16C650V1 UARTs pass this test.
1005 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1006 if (serial_in(up, UART_EFR) == 0) {
1007 serial_out(up, UART_EFR, 0xA8);
1008 if (serial_in(up, UART_EFR) != 0) {
1009 DEBUG_AUTOCONF("EFRv1 ");
1010 up->port.type = PORT_16650;
1011 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1013 serial_out(up, UART_LCR, 0);
1014 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1016 status1 = serial_in(up, UART_IIR) >> 5;
1017 serial_out(up, UART_FCR, 0);
1018 serial_out(up, UART_LCR, 0);
1021 up->port.type = PORT_16550A_FSL64;
1023 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1025 serial_out(up, UART_EFR, 0);
1030 * Maybe it requires 0xbf to be written to the LCR.
1031 * (other ST16C650V2 UARTs, TI16C752A, etc)
1033 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1034 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1035 DEBUG_AUTOCONF("EFRv2 ");
1036 autoconfig_has_efr(up);
1041 * Check for a National Semiconductor SuperIO chip.
1042 * Attempt to switch to bank 2, read the value of the LOOP bit
1043 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1044 * switch back to bank 2, read it from EXCR1 again and check
1045 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1047 serial_out(up, UART_LCR, 0);
1048 status1 = serial8250_in_MCR(up);
1049 serial_out(up, UART_LCR, 0xE0);
1050 status2 = serial_in(up, 0x02); /* EXCR1 */
1052 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1053 serial_out(up, UART_LCR, 0);
1054 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1055 serial_out(up, UART_LCR, 0xE0);
1056 status2 = serial_in(up, 0x02); /* EXCR1 */
1057 serial_out(up, UART_LCR, 0);
1058 serial8250_out_MCR(up, status1);
1060 if ((status2 ^ status1) & UART_MCR_LOOP) {
1061 unsigned short quot;
1063 serial_out(up, UART_LCR, 0xE0);
1065 quot = serial_dl_read(up);
1068 if (ns16550a_goto_highspeed(up))
1069 serial_dl_write(up, quot);
1071 serial_out(up, UART_LCR, 0);
1073 up->port.uartclk = 921600*16;
1074 up->port.type = PORT_NS16550A;
1075 up->capabilities |= UART_NATSEMI;
1081 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1082 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1083 * Try setting it with and without DLAB set. Cheap clones
1084 * set bit 5 without DLAB set.
1086 serial_out(up, UART_LCR, 0);
1087 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1088 status1 = serial_in(up, UART_IIR) >> 5;
1089 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1090 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1091 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1092 status2 = serial_in(up, UART_IIR) >> 5;
1093 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1094 serial_out(up, UART_LCR, 0);
1096 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1098 if (status1 == 6 && status2 == 7) {
1099 up->port.type = PORT_16750;
1100 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1105 * Try writing and reading the UART_IER_UUE bit (b6).
1106 * If it works, this is probably one of the Xscale platform's
1108 * We're going to explicitly set the UUE bit to 0 before
1109 * trying to write and read a 1 just to make sure it's not
1110 * already a 1 and maybe locked there before we even start start.
1112 iersave = serial_in(up, UART_IER);
1113 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1114 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1116 * OK it's in a known zero state, try writing and reading
1117 * without disturbing the current state of the other bits.
1119 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1120 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1123 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1125 DEBUG_AUTOCONF("Xscale ");
1126 up->port.type = PORT_XSCALE;
1127 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1132 * If we got here we couldn't force the IER_UUE bit to 0.
1133 * Log it and continue.
1135 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1137 serial_out(up, UART_IER, iersave);
1140 * Exar uarts have EFR in a weird location
1142 if (up->port.flags & UPF_EXAR_EFR) {
1143 DEBUG_AUTOCONF("Exar XR17D15x ");
1144 up->port.type = PORT_XR17D15X;
1145 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1152 * We distinguish between 16550A and U6 16550A by counting
1153 * how many bytes are in the FIFO.
1155 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1156 up->port.type = PORT_U6_16550A;
1157 up->capabilities |= UART_CAP_AFE;
1162 * This routine is called by rs_init() to initialize a specific serial
1163 * port. It determines what type of UART chip this serial port is
1164 * using: 8250, 16450, 16550, 16550A. The important question is
1165 * whether or not this UART is a 16550A or not, since this will
1166 * determine whether or not we can use its FIFO features or not.
1168 static void autoconfig(struct uart_8250_port *up)
1170 unsigned char status1, scratch, scratch2, scratch3;
1171 unsigned char save_lcr, save_mcr;
1172 struct uart_port *port = &up->port;
1173 unsigned long flags;
1174 unsigned int old_capabilities;
1176 if (!port->iobase && !port->mapbase && !port->membase)
1179 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1180 serial_index(port), port->iobase, port->membase);
1183 * We really do need global IRQs disabled here - we're going to
1184 * be frobbing the chips IRQ enable register to see if it exists.
1186 spin_lock_irqsave(&port->lock, flags);
1188 up->capabilities = 0;
1191 if (!(port->flags & UPF_BUGGY_UART)) {
1193 * Do a simple existence test first; if we fail this,
1194 * there's no point trying anything else.
1196 * 0x80 is used as a nonsense port to prevent against
1197 * false positives due to ISA bus float. The
1198 * assumption is that 0x80 is a non-existent port;
1199 * which should be safe since include/asm/io.h also
1200 * makes this assumption.
1202 * Note: this is safe as long as MCR bit 4 is clear
1203 * and the device is in "PC" mode.
1205 scratch = serial_in(up, UART_IER);
1206 serial_out(up, UART_IER, 0);
1211 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1212 * 16C754B) allow only to modify them if an EFR bit is set.
1214 scratch2 = serial_in(up, UART_IER) & 0x0f;
1215 serial_out(up, UART_IER, 0x0F);
1219 scratch3 = serial_in(up, UART_IER) & 0x0f;
1220 serial_out(up, UART_IER, scratch);
1221 if (scratch2 != 0 || scratch3 != 0x0F) {
1223 * We failed; there's nothing here
1225 spin_unlock_irqrestore(&port->lock, flags);
1226 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1227 scratch2, scratch3);
1232 save_mcr = serial8250_in_MCR(up);
1233 save_lcr = serial_in(up, UART_LCR);
1236 * Check to see if a UART is really there. Certain broken
1237 * internal modems based on the Rockwell chipset fail this
1238 * test, because they apparently don't implement the loopback
1239 * test mode. So this test is skipped on the COM 1 through
1240 * COM 4 ports. This *should* be safe, since no board
1241 * manufacturer would be stupid enough to design a board
1242 * that conflicts with COM 1-4 --- we hope!
1244 if (!(port->flags & UPF_SKIP_TEST)) {
1245 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1246 status1 = serial_in(up, UART_MSR) & 0xF0;
1247 serial8250_out_MCR(up, save_mcr);
1248 if (status1 != 0x90) {
1249 spin_unlock_irqrestore(&port->lock, flags);
1250 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1257 * We're pretty sure there's a port here. Lets find out what
1258 * type of port it is. The IIR top two bits allows us to find
1259 * out if it's 8250 or 16450, 16550, 16550A or later. This
1260 * determines what we test for next.
1262 * We also initialise the EFR (if any) to zero for later. The
1263 * EFR occupies the same register location as the FCR and IIR.
1265 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1266 serial_out(up, UART_EFR, 0);
1267 serial_out(up, UART_LCR, 0);
1269 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1271 /* Assign this as it is to truncate any bits above 7. */
1272 scratch = serial_in(up, UART_IIR);
1274 switch (scratch >> 6) {
1276 autoconfig_8250(up);
1279 port->type = PORT_UNKNOWN;
1282 port->type = PORT_16550;
1285 autoconfig_16550a(up);
1289 #ifdef CONFIG_SERIAL_8250_RSA
1291 * Only probe for RSA ports if we got the region.
1293 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1295 port->type = PORT_RSA;
1298 serial_out(up, UART_LCR, save_lcr);
1300 port->fifosize = uart_config[up->port.type].fifo_size;
1301 old_capabilities = up->capabilities;
1302 up->capabilities = uart_config[port->type].flags;
1303 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1305 if (port->type == PORT_UNKNOWN)
1311 #ifdef CONFIG_SERIAL_8250_RSA
1312 if (port->type == PORT_RSA)
1313 serial_out(up, UART_RSA_FRR, 0);
1315 serial8250_out_MCR(up, save_mcr);
1316 serial8250_clear_fifos(up);
1317 serial_in(up, UART_RX);
1318 if (up->capabilities & UART_CAP_UUE)
1319 serial_out(up, UART_IER, UART_IER_UUE);
1321 serial_out(up, UART_IER, 0);
1324 spin_unlock_irqrestore(&port->lock, flags);
1327 * Check if the device is a Fintek F81216A
1329 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1330 fintek_8250_probe(up);
1332 if (up->capabilities != old_capabilities) {
1333 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1334 serial_index(port), old_capabilities,
1338 DEBUG_AUTOCONF("iir=%d ", scratch);
1339 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1342 static void autoconfig_irq(struct uart_8250_port *up)
1344 struct uart_port *port = &up->port;
1345 unsigned char save_mcr, save_ier;
1346 unsigned char save_ICP = 0;
1347 unsigned int ICP = 0;
1351 if (port->flags & UPF_FOURPORT) {
1352 ICP = (port->iobase & 0xfe0) | 0x1f;
1353 save_ICP = inb_p(ICP);
1358 if (uart_console(port))
1361 /* forget possible initially masked and pending IRQ */
1362 probe_irq_off(probe_irq_on());
1363 save_mcr = serial8250_in_MCR(up);
1364 save_ier = serial_in(up, UART_IER);
1365 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1367 irqs = probe_irq_on();
1368 serial8250_out_MCR(up, 0);
1370 if (port->flags & UPF_FOURPORT) {
1371 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1373 serial8250_out_MCR(up,
1374 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1376 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1377 serial_in(up, UART_LSR);
1378 serial_in(up, UART_RX);
1379 serial_in(up, UART_IIR);
1380 serial_in(up, UART_MSR);
1381 serial_out(up, UART_TX, 0xFF);
1383 irq = probe_irq_off(irqs);
1385 serial8250_out_MCR(up, save_mcr);
1386 serial_out(up, UART_IER, save_ier);
1388 if (port->flags & UPF_FOURPORT)
1389 outb_p(save_ICP, ICP);
1391 if (uart_console(port))
1394 port->irq = (irq > 0) ? irq : 0;
1397 static void serial8250_stop_rx(struct uart_port *port)
1399 struct uart_8250_port *up = up_to_u8250p(port);
1401 serial8250_rpm_get(up);
1403 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1404 up->port.read_status_mask &= ~UART_LSR_DR;
1405 serial_port_out(port, UART_IER, up->ier);
1407 serial8250_rpm_put(up);
1410 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1412 serial8250_em485_rts_after_send(p);
1415 * Empty the RX FIFO, we are not interested in anything
1416 * received during the half-duplex transmission.
1417 * Enable previously disabled RX interrupts.
1419 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1420 serial8250_clear_and_reinit_fifos(p);
1422 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1423 serial_port_out(&p->port, UART_IER, p->ier);
1427 static void serial8250_em485_handle_stop_tx(unsigned long arg)
1429 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1430 struct uart_8250_em485 *em485 = p->em485;
1431 unsigned long flags;
1433 serial8250_rpm_get(p);
1434 spin_lock_irqsave(&p->port.lock, flags);
1436 em485->active_timer == &em485->stop_tx_timer) {
1437 __do_stop_tx_rs485(p);
1438 em485->active_timer = NULL;
1440 spin_unlock_irqrestore(&p->port.lock, flags);
1441 serial8250_rpm_put(p);
1444 static void __stop_tx_rs485(struct uart_8250_port *p)
1446 struct uart_8250_em485 *em485 = p->em485;
1449 * __do_stop_tx_rs485 is going to set RTS according to config
1450 * AND flush RX FIFO if required.
1452 if (p->port.rs485.delay_rts_after_send > 0) {
1453 em485->active_timer = &em485->stop_tx_timer;
1454 mod_timer(&em485->stop_tx_timer, jiffies +
1455 p->port.rs485.delay_rts_after_send * HZ / 1000);
1457 __do_stop_tx_rs485(p);
1461 static inline void __do_stop_tx(struct uart_8250_port *p)
1463 if (p->ier & UART_IER_THRI) {
1464 p->ier &= ~UART_IER_THRI;
1465 serial_out(p, UART_IER, p->ier);
1466 serial8250_rpm_put_tx(p);
1470 static inline void __stop_tx(struct uart_8250_port *p)
1472 struct uart_8250_em485 *em485 = p->em485;
1475 unsigned char lsr = serial_in(p, UART_LSR);
1477 * To provide required timeing and allow FIFO transfer,
1478 * __stop_tx_rs485() must be called only when both FIFO and
1479 * shift register are empty. It is for device driver to enable
1480 * interrupt on TEMT.
1482 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1485 del_timer(&em485->start_tx_timer);
1486 em485->active_timer = NULL;
1493 static void serial8250_stop_tx(struct uart_port *port)
1495 struct uart_8250_port *up = up_to_u8250p(port);
1497 serial8250_rpm_get(up);
1501 * We really want to stop the transmitter from sending.
1503 if (port->type == PORT_16C950) {
1504 up->acr |= UART_ACR_TXDIS;
1505 serial_icr_write(up, UART_ACR, up->acr);
1507 serial8250_rpm_put(up);
1510 static inline void __start_tx(struct uart_port *port)
1512 struct uart_8250_port *up = up_to_u8250p(port);
1514 if (up->dma && !up->dma->tx_dma(up))
1517 if (!(up->ier & UART_IER_THRI)) {
1518 up->ier |= UART_IER_THRI;
1519 serial_port_out(port, UART_IER, up->ier);
1521 if (up->bugs & UART_BUG_TXEN) {
1524 lsr = serial_in(up, UART_LSR);
1525 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1526 if (lsr & UART_LSR_THRE)
1527 serial8250_tx_chars(up);
1532 * Re-enable the transmitter if we disabled it.
1534 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1535 up->acr &= ~UART_ACR_TXDIS;
1536 serial_icr_write(up, UART_ACR, up->acr);
1540 static inline void start_tx_rs485(struct uart_port *port)
1542 struct uart_8250_port *up = up_to_u8250p(port);
1543 struct uart_8250_em485 *em485 = up->em485;
1546 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1547 serial8250_stop_rx(&up->port);
1549 del_timer(&em485->stop_tx_timer);
1550 em485->active_timer = NULL;
1552 mcr = serial8250_in_MCR(up);
1553 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1554 !!(mcr & UART_MCR_RTS)) {
1555 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1556 mcr |= UART_MCR_RTS;
1558 mcr &= ~UART_MCR_RTS;
1559 serial8250_out_MCR(up, mcr);
1561 if (up->port.rs485.delay_rts_before_send > 0) {
1562 em485->active_timer = &em485->start_tx_timer;
1563 mod_timer(&em485->start_tx_timer, jiffies +
1564 up->port.rs485.delay_rts_before_send * HZ / 1000);
1572 static void serial8250_em485_handle_start_tx(unsigned long arg)
1574 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1575 struct uart_8250_em485 *em485 = p->em485;
1576 unsigned long flags;
1578 spin_lock_irqsave(&p->port.lock, flags);
1580 em485->active_timer == &em485->start_tx_timer) {
1581 __start_tx(&p->port);
1582 em485->active_timer = NULL;
1584 spin_unlock_irqrestore(&p->port.lock, flags);
1587 static void serial8250_start_tx(struct uart_port *port)
1589 struct uart_8250_port *up = up_to_u8250p(port);
1590 struct uart_8250_em485 *em485 = up->em485;
1592 serial8250_rpm_get_tx(up);
1595 em485->active_timer == &em485->start_tx_timer)
1599 start_tx_rs485(port);
1604 static void serial8250_throttle(struct uart_port *port)
1606 port->throttle(port);
1609 static void serial8250_unthrottle(struct uart_port *port)
1611 port->unthrottle(port);
1614 static void serial8250_disable_ms(struct uart_port *port)
1616 struct uart_8250_port *up = up_to_u8250p(port);
1618 /* no MSR capabilities */
1619 if (up->bugs & UART_BUG_NOMSR)
1622 up->ier &= ~UART_IER_MSI;
1623 serial_port_out(port, UART_IER, up->ier);
1626 static void serial8250_enable_ms(struct uart_port *port)
1628 struct uart_8250_port *up = up_to_u8250p(port);
1630 /* no MSR capabilities */
1631 if (up->bugs & UART_BUG_NOMSR)
1634 up->ier |= UART_IER_MSI;
1636 serial8250_rpm_get(up);
1637 serial_port_out(port, UART_IER, up->ier);
1638 serial8250_rpm_put(up);
1641 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1643 struct uart_port *port = &up->port;
1645 char flag = TTY_NORMAL;
1647 if (likely(lsr & UART_LSR_DR))
1648 ch = serial_in(up, UART_RX);
1651 * Intel 82571 has a Serial Over Lan device that will
1652 * set UART_LSR_BI without setting UART_LSR_DR when
1653 * it receives a break. To avoid reading from the
1654 * receive buffer without UART_LSR_DR bit set, we
1655 * just force the read character to be 0
1661 lsr |= up->lsr_saved_flags;
1662 up->lsr_saved_flags = 0;
1664 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1665 if (lsr & UART_LSR_BI) {
1666 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1669 * We do the SysRQ and SAK checking
1670 * here because otherwise the break
1671 * may get masked by ignore_status_mask
1672 * or read_status_mask.
1674 if (uart_handle_break(port))
1676 } else if (lsr & UART_LSR_PE)
1677 port->icount.parity++;
1678 else if (lsr & UART_LSR_FE)
1679 port->icount.frame++;
1680 if (lsr & UART_LSR_OE)
1681 port->icount.overrun++;
1684 * Mask off conditions which should be ignored.
1686 lsr &= port->read_status_mask;
1688 if (lsr & UART_LSR_BI) {
1689 pr_debug("%s: handling break\n", __func__);
1691 } else if (lsr & UART_LSR_PE)
1693 else if (lsr & UART_LSR_FE)
1696 if (uart_handle_sysrq_char(port, ch))
1699 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1703 * serial8250_rx_chars: processes according to the passed in LSR
1704 * value, and returns the remaining LSR bits not handled
1705 * by this Rx routine.
1707 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1709 struct uart_port *port = &up->port;
1710 int max_count = 256;
1713 serial8250_read_char(up, lsr);
1714 if (--max_count == 0)
1716 lsr = serial_in(up, UART_LSR);
1717 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1719 tty_flip_buffer_push(&port->state->port);
1722 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1724 void serial8250_tx_chars(struct uart_8250_port *up)
1726 struct uart_port *port = &up->port;
1727 struct circ_buf *xmit = &port->state->xmit;
1731 serial_out(up, UART_TX, port->x_char);
1736 if (uart_tx_stopped(port)) {
1737 serial8250_stop_tx(port);
1740 if (uart_circ_empty(xmit)) {
1745 count = up->tx_loadsz;
1747 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1748 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1750 if (uart_circ_empty(xmit))
1752 if ((up->capabilities & UART_CAP_HFIFO) &&
1753 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1755 } while (--count > 0);
1757 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1758 uart_write_wakeup(port);
1761 * With RPM enabled, we have to wait until the FIFO is empty before the
1762 * HW can go idle. So we get here once again with empty FIFO and disable
1763 * the interrupt and RPM in __stop_tx()
1765 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1768 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1770 /* Caller holds uart port lock */
1771 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1773 struct uart_port *port = &up->port;
1774 unsigned int status = serial_in(up, UART_MSR);
1776 status |= up->msr_saved_flags;
1777 up->msr_saved_flags = 0;
1778 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1779 port->state != NULL) {
1780 if (status & UART_MSR_TERI)
1782 if (status & UART_MSR_DDSR)
1784 if (status & UART_MSR_DDCD)
1785 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1786 if (status & UART_MSR_DCTS)
1787 uart_handle_cts_change(port, status & UART_MSR_CTS);
1789 wake_up_interruptible(&port->state->port.delta_msr_wait);
1794 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1796 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1798 switch (iir & 0x3f) {
1799 case UART_IIR_RX_TIMEOUT:
1800 serial8250_rx_dma_flush(up);
1805 return up->dma->rx_dma(up);
1809 * This handles the interrupt from one port.
1811 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1813 unsigned char status;
1814 unsigned long flags;
1815 struct uart_8250_port *up = up_to_u8250p(port);
1816 bool skip_rx = false;
1818 if (iir & UART_IIR_NO_INT)
1821 spin_lock_irqsave(&port->lock, flags);
1823 status = serial_port_in(port, UART_LSR);
1826 * If port is stopped and there are no error conditions in the
1827 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1828 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1829 * control when FIFO occupancy reaches preset threshold, thus
1830 * halting RX. This only works when auto HW flow control is
1833 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1834 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1835 !(port->read_status_mask & UART_LSR_DR))
1838 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1839 if (!up->dma || handle_rx_dma(up, iir))
1840 status = serial8250_rx_chars(up, status);
1842 serial8250_modem_status(up);
1843 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1844 (up->ier & UART_IER_THRI))
1845 serial8250_tx_chars(up);
1847 spin_unlock_irqrestore(&port->lock, flags);
1850 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1852 static int serial8250_default_handle_irq(struct uart_port *port)
1854 struct uart_8250_port *up = up_to_u8250p(port);
1858 serial8250_rpm_get(up);
1860 iir = serial_port_in(port, UART_IIR);
1861 ret = serial8250_handle_irq(port, iir);
1863 serial8250_rpm_put(up);
1868 * These Exar UARTs have an extra interrupt indicator that could
1869 * fire for a few unimplemented interrupts. One of which is a
1870 * wakeup event when coming out of sleep. Put this here just
1871 * to be on the safe side that these interrupts don't go unhandled.
1873 static int exar_handle_irq(struct uart_port *port)
1875 unsigned int iir = serial_port_in(port, UART_IIR);
1878 ret = serial8250_handle_irq(port, iir);
1880 if ((port->type == PORT_XR17V35X) ||
1881 (port->type == PORT_XR17D15X)) {
1882 serial_port_in(port, 0x80);
1883 serial_port_in(port, 0x81);
1884 serial_port_in(port, 0x82);
1885 serial_port_in(port, 0x83);
1892 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1893 * have a programmable TX threshold that triggers the THRE interrupt in
1894 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1895 * has space available. Load it up with tx_loadsz bytes.
1897 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1899 unsigned long flags;
1900 unsigned int iir = serial_port_in(port, UART_IIR);
1902 /* TX Threshold IRQ triggered so load up FIFO */
1903 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1904 struct uart_8250_port *up = up_to_u8250p(port);
1906 spin_lock_irqsave(&port->lock, flags);
1907 serial8250_tx_chars(up);
1908 spin_unlock_irqrestore(&port->lock, flags);
1911 iir = serial_port_in(port, UART_IIR);
1912 return serial8250_handle_irq(port, iir);
1915 static unsigned int serial8250_tx_empty(struct uart_port *port)
1917 struct uart_8250_port *up = up_to_u8250p(port);
1918 unsigned long flags;
1921 serial8250_rpm_get(up);
1923 spin_lock_irqsave(&port->lock, flags);
1924 lsr = serial_port_in(port, UART_LSR);
1925 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1926 spin_unlock_irqrestore(&port->lock, flags);
1928 serial8250_rpm_put(up);
1930 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1933 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1935 struct uart_8250_port *up = up_to_u8250p(port);
1936 unsigned int status;
1939 serial8250_rpm_get(up);
1940 status = serial8250_modem_status(up);
1941 serial8250_rpm_put(up);
1944 if (status & UART_MSR_DCD)
1946 if (status & UART_MSR_RI)
1948 if (status & UART_MSR_DSR)
1950 if (status & UART_MSR_CTS)
1954 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1956 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1958 if (port->get_mctrl)
1959 return port->get_mctrl(port);
1960 return serial8250_do_get_mctrl(port);
1963 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1965 struct uart_8250_port *up = up_to_u8250p(port);
1966 unsigned char mcr = 0;
1968 if (mctrl & TIOCM_RTS)
1969 mcr |= UART_MCR_RTS;
1970 if (mctrl & TIOCM_DTR)
1971 mcr |= UART_MCR_DTR;
1972 if (mctrl & TIOCM_OUT1)
1973 mcr |= UART_MCR_OUT1;
1974 if (mctrl & TIOCM_OUT2)
1975 mcr |= UART_MCR_OUT2;
1976 if (mctrl & TIOCM_LOOP)
1977 mcr |= UART_MCR_LOOP;
1979 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1981 serial8250_out_MCR(up, mcr);
1983 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1985 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1987 if (port->set_mctrl)
1988 port->set_mctrl(port, mctrl);
1990 serial8250_do_set_mctrl(port, mctrl);
1993 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1995 struct uart_8250_port *up = up_to_u8250p(port);
1996 unsigned long flags;
1998 serial8250_rpm_get(up);
1999 spin_lock_irqsave(&port->lock, flags);
2000 if (break_state == -1)
2001 up->lcr |= UART_LCR_SBC;
2003 up->lcr &= ~UART_LCR_SBC;
2004 serial_port_out(port, UART_LCR, up->lcr);
2005 spin_unlock_irqrestore(&port->lock, flags);
2006 serial8250_rpm_put(up);
2010 * Wait for transmitter & holding register to empty
2012 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2014 unsigned int status, tmout = 10000;
2016 /* Wait up to 10ms for the character(s) to be sent. */
2018 status = serial_in(up, UART_LSR);
2020 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2022 if ((status & bits) == bits)
2027 touch_nmi_watchdog();
2030 /* Wait up to 1s for flow control if necessary */
2031 if (up->port.flags & UPF_CONS_FLOW) {
2032 for (tmout = 1000000; tmout; tmout--) {
2033 unsigned int msr = serial_in(up, UART_MSR);
2034 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2035 if (msr & UART_MSR_CTS)
2038 touch_nmi_watchdog();
2043 #ifdef CONFIG_CONSOLE_POLL
2045 * Console polling routines for writing and reading from the uart while
2046 * in an interrupt or debug context.
2049 static int serial8250_get_poll_char(struct uart_port *port)
2051 struct uart_8250_port *up = up_to_u8250p(port);
2055 serial8250_rpm_get(up);
2057 lsr = serial_port_in(port, UART_LSR);
2059 if (!(lsr & UART_LSR_DR)) {
2060 status = NO_POLL_CHAR;
2064 status = serial_port_in(port, UART_RX);
2066 serial8250_rpm_put(up);
2071 static void serial8250_put_poll_char(struct uart_port *port,
2075 struct uart_8250_port *up = up_to_u8250p(port);
2077 serial8250_rpm_get(up);
2079 * First save the IER then disable the interrupts
2081 ier = serial_port_in(port, UART_IER);
2082 if (up->capabilities & UART_CAP_UUE)
2083 serial_port_out(port, UART_IER, UART_IER_UUE);
2085 serial_port_out(port, UART_IER, 0);
2087 wait_for_xmitr(up, BOTH_EMPTY);
2089 * Send the character out.
2091 serial_port_out(port, UART_TX, c);
2094 * Finally, wait for transmitter to become empty
2095 * and restore the IER
2097 wait_for_xmitr(up, BOTH_EMPTY);
2098 serial_port_out(port, UART_IER, ier);
2099 serial8250_rpm_put(up);
2102 #endif /* CONFIG_CONSOLE_POLL */
2104 int serial8250_do_startup(struct uart_port *port)
2106 struct uart_8250_port *up = up_to_u8250p(port);
2107 unsigned long flags;
2108 unsigned char lsr, iir;
2111 if (!port->fifosize)
2112 port->fifosize = uart_config[port->type].fifo_size;
2114 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2115 if (!up->capabilities)
2116 up->capabilities = uart_config[port->type].flags;
2119 if (port->iotype != up->cur_iotype)
2120 set_io_from_upio(port);
2122 serial8250_rpm_get(up);
2123 if (port->type == PORT_16C950) {
2124 /* Wake up and initialize UART */
2126 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2127 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2128 serial_port_out(port, UART_IER, 0);
2129 serial_port_out(port, UART_LCR, 0);
2130 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2131 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2132 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2133 serial_port_out(port, UART_LCR, 0);
2136 #ifdef CONFIG_SERIAL_8250_RSA
2138 * If this is an RSA port, see if we can kick it up to the
2139 * higher speed clock.
2144 if (port->type == PORT_XR17V35X) {
2146 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2147 * MCR [7:5] and MSR [7:0]
2149 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2152 * Make sure all interrups are masked until initialization is
2153 * complete and the FIFOs are cleared
2155 serial_port_out(port, UART_IER, 0);
2159 * Clear the FIFO buffers and disable them.
2160 * (they will be reenabled in set_termios())
2162 serial8250_clear_fifos(up);
2165 * Clear the interrupt registers.
2167 serial_port_in(port, UART_LSR);
2168 serial_port_in(port, UART_RX);
2169 serial_port_in(port, UART_IIR);
2170 serial_port_in(port, UART_MSR);
2173 * At this point, there's no way the LSR could still be 0xff;
2174 * if it is, then bail out, because there's likely no UART
2177 if (!(port->flags & UPF_BUGGY_UART) &&
2178 (serial_port_in(port, UART_LSR) == 0xff)) {
2179 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2180 serial_index(port));
2186 * For a XR16C850, we need to set the trigger levels
2188 if (port->type == PORT_16850) {
2191 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2193 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2194 serial_port_out(port, UART_FCTR,
2195 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2196 serial_port_out(port, UART_TRG, UART_TRG_96);
2197 serial_port_out(port, UART_FCTR,
2198 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2199 serial_port_out(port, UART_TRG, UART_TRG_96);
2201 serial_port_out(port, UART_LCR, 0);
2205 * For the Altera 16550 variants, set TX threshold trigger level.
2207 if (((port->type == PORT_ALTR_16550_F32) ||
2208 (port->type == PORT_ALTR_16550_F64) ||
2209 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2210 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2211 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2212 pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2213 serial_index(port));
2215 serial_port_out(port, UART_ALTR_AFR,
2216 UART_ALTR_EN_TXFIFO_LW);
2217 serial_port_out(port, UART_ALTR_TX_LOW,
2218 port->fifosize - up->tx_loadsz);
2219 port->handle_irq = serial8250_tx_threshold_handle_irq;
2223 /* Check if we need to have shared IRQs */
2224 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2225 up->port.irqflags |= IRQF_SHARED;
2230 if (port->irqflags & IRQF_SHARED)
2231 disable_irq_nosync(port->irq);
2234 * Test for UARTs that do not reassert THRE when the
2235 * transmitter is idle and the interrupt has already
2236 * been cleared. Real 16550s should always reassert
2237 * this interrupt whenever the transmitter is idle and
2238 * the interrupt is enabled. Delays are necessary to
2239 * allow register changes to become visible.
2241 spin_lock_irqsave(&port->lock, flags);
2243 wait_for_xmitr(up, UART_LSR_THRE);
2244 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2245 udelay(1); /* allow THRE to set */
2246 iir1 = serial_port_in(port, UART_IIR);
2247 serial_port_out(port, UART_IER, 0);
2248 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2249 udelay(1); /* allow a working UART time to re-assert THRE */
2250 iir = serial_port_in(port, UART_IIR);
2251 serial_port_out(port, UART_IER, 0);
2253 spin_unlock_irqrestore(&port->lock, flags);
2255 if (port->irqflags & IRQF_SHARED)
2256 enable_irq(port->irq);
2259 * If the interrupt is not reasserted, or we otherwise
2260 * don't trust the iir, setup a timer to kick the UART
2261 * on a regular basis.
2263 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2264 up->port.flags & UPF_BUG_THRE) {
2265 up->bugs |= UART_BUG_THRE;
2269 retval = up->ops->setup_irq(up);
2274 * Now, initialize the UART
2276 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2278 spin_lock_irqsave(&port->lock, flags);
2279 if (up->port.flags & UPF_FOURPORT) {
2281 up->port.mctrl |= TIOCM_OUT1;
2284 * Most PC uarts need OUT2 raised to enable interrupts.
2287 up->port.mctrl |= TIOCM_OUT2;
2289 serial8250_set_mctrl(port, port->mctrl);
2292 * Serial over Lan (SoL) hack:
2293 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2294 * used for Serial Over Lan. Those chips take a longer time than a
2295 * normal serial device to signalize that a transmission data was
2296 * queued. Due to that, the above test generally fails. One solution
2297 * would be to delay the reading of iir. However, this is not
2298 * reliable, since the timeout is variable. So, let's just don't
2299 * test if we receive TX irq. This way, we'll never enable
2302 if (up->port.flags & UPF_NO_TXEN_TEST)
2303 goto dont_test_tx_en;
2306 * Do a quick test to see if we receive an interrupt when we enable
2309 serial_port_out(port, UART_IER, UART_IER_THRI);
2310 lsr = serial_port_in(port, UART_LSR);
2311 iir = serial_port_in(port, UART_IIR);
2312 serial_port_out(port, UART_IER, 0);
2314 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2315 if (!(up->bugs & UART_BUG_TXEN)) {
2316 up->bugs |= UART_BUG_TXEN;
2317 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2318 serial_index(port));
2321 up->bugs &= ~UART_BUG_TXEN;
2325 spin_unlock_irqrestore(&port->lock, flags);
2328 * Clear the interrupt registers again for luck, and clear the
2329 * saved flags to avoid getting false values from polling
2330 * routines or the previous session.
2332 serial_port_in(port, UART_LSR);
2333 serial_port_in(port, UART_RX);
2334 serial_port_in(port, UART_IIR);
2335 serial_port_in(port, UART_MSR);
2336 up->lsr_saved_flags = 0;
2337 up->msr_saved_flags = 0;
2340 * Request DMA channels for both RX and TX.
2343 retval = serial8250_request_dma(up);
2345 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2346 serial_index(port));
2352 * Set the IER shadow for rx interrupts but defer actual interrupt
2353 * enable until after the FIFOs are enabled; otherwise, an already-
2354 * active sender can swamp the interrupt handler with "too much work".
2356 up->ier = UART_IER_RLSI | UART_IER_RDI;
2358 if (port->flags & UPF_FOURPORT) {
2361 * Enable interrupts on the AST Fourport board
2363 icp = (port->iobase & 0xfe0) | 0x01f;
2369 serial8250_rpm_put(up);
2372 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2374 static int serial8250_startup(struct uart_port *port)
2377 return port->startup(port);
2378 return serial8250_do_startup(port);
2381 void serial8250_do_shutdown(struct uart_port *port)
2383 struct uart_8250_port *up = up_to_u8250p(port);
2384 unsigned long flags;
2386 serial8250_rpm_get(up);
2388 * Disable interrupts from this port
2390 spin_lock_irqsave(&port->lock, flags);
2392 serial_port_out(port, UART_IER, 0);
2393 spin_unlock_irqrestore(&port->lock, flags);
2395 synchronize_irq(port->irq);
2398 serial8250_release_dma(up);
2400 spin_lock_irqsave(&port->lock, flags);
2401 if (port->flags & UPF_FOURPORT) {
2402 /* reset interrupts on the AST Fourport board */
2403 inb((port->iobase & 0xfe0) | 0x1f);
2404 port->mctrl |= TIOCM_OUT1;
2406 port->mctrl &= ~TIOCM_OUT2;
2408 serial8250_set_mctrl(port, port->mctrl);
2409 spin_unlock_irqrestore(&port->lock, flags);
2412 * Disable break condition and FIFOs
2414 serial_port_out(port, UART_LCR,
2415 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2416 serial8250_clear_fifos(up);
2418 #ifdef CONFIG_SERIAL_8250_RSA
2420 * Reset the RSA board back to 115kbps compat mode.
2426 * Read data port to reset things, and then unlink from
2429 serial_port_in(port, UART_RX);
2430 serial8250_rpm_put(up);
2432 up->ops->release_irq(up);
2434 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2436 static void serial8250_shutdown(struct uart_port *port)
2439 port->shutdown(port);
2441 serial8250_do_shutdown(port);
2445 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2446 * Calculate divisor with extra 4-bit fractional portion
2448 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2452 struct uart_port *port = &up->port;
2453 unsigned int quot_16;
2455 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2456 *frac = quot_16 & 0x0f;
2458 return quot_16 >> 4;
2461 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2465 struct uart_port *port = &up->port;
2469 * Handle magic divisors for baud rates above baud_base on
2470 * SMSC SuperIO chips.
2473 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2474 baud == (port->uartclk/4))
2476 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2477 baud == (port->uartclk/8))
2479 else if (up->port.type == PORT_XR17V35X)
2480 quot = xr17v35x_get_divisor(up, baud, frac);
2482 quot = uart_get_divisor(port, baud);
2485 * Oxford Semi 952 rev B workaround
2487 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2493 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2498 switch (c_cflag & CSIZE) {
2500 cval = UART_LCR_WLEN5;
2503 cval = UART_LCR_WLEN6;
2506 cval = UART_LCR_WLEN7;
2510 cval = UART_LCR_WLEN8;
2514 if (c_cflag & CSTOPB)
2515 cval |= UART_LCR_STOP;
2516 if (c_cflag & PARENB) {
2517 cval |= UART_LCR_PARITY;
2518 if (up->bugs & UART_BUG_PARITY)
2519 up->fifo_bug = true;
2521 if (!(c_cflag & PARODD))
2522 cval |= UART_LCR_EPAR;
2524 if (c_cflag & CMSPAR)
2525 cval |= UART_LCR_SPAR;
2531 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2532 unsigned int quot, unsigned int quot_frac)
2534 struct uart_8250_port *up = up_to_u8250p(port);
2536 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2537 if (is_omap1510_8250(up)) {
2538 if (baud == 115200) {
2540 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2542 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2546 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2547 * otherwise just set DLAB
2549 if (up->capabilities & UART_NATSEMI)
2550 serial_port_out(port, UART_LCR, 0xe0);
2552 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2554 serial_dl_write(up, quot);
2556 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2557 if (up->port.type == PORT_XR17V35X) {
2558 /* Preserve bits not related to baudrate; DLD[7:4]. */
2559 quot_frac |= serial_port_in(port, 0x2) & 0xf0;
2560 serial_port_out(port, 0x2, quot_frac);
2564 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2565 struct ktermios *termios,
2566 struct ktermios *old)
2569 * Ask the core to calculate the divisor for us.
2570 * Allow 1% tolerance at the upper limit so uart clks marginally
2571 * slower than nominal still match standard baud rates without
2572 * causing transmission errors.
2574 return uart_get_baud_rate(port, termios, old,
2575 port->uartclk / 16 / 0xffff,
2580 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2581 struct ktermios *old)
2583 struct uart_8250_port *up = up_to_u8250p(port);
2585 unsigned long flags;
2586 unsigned int baud, quot, frac = 0;
2588 cval = serial8250_compute_lcr(up, termios->c_cflag);
2590 baud = serial8250_get_baud_rate(port, termios, old);
2591 quot = serial8250_get_divisor(up, baud, &frac);
2594 * Ok, we're now changing the port state. Do it with
2595 * interrupts disabled.
2597 serial8250_rpm_get(up);
2598 spin_lock_irqsave(&port->lock, flags);
2600 up->lcr = cval; /* Save computed LCR */
2602 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2603 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2604 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2605 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2606 up->fcr |= UART_FCR_TRIGGER_1;
2611 * MCR-based auto flow control. When AFE is enabled, RTS will be
2612 * deasserted when the receive FIFO contains more characters than
2613 * the trigger, or the MCR RTS bit is cleared.
2615 if (up->capabilities & UART_CAP_AFE) {
2616 up->mcr &= ~UART_MCR_AFE;
2617 if (termios->c_cflag & CRTSCTS)
2618 up->mcr |= UART_MCR_AFE;
2622 * Update the per-port timeout.
2624 uart_update_timeout(port, termios->c_cflag, baud);
2626 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2627 if (termios->c_iflag & INPCK)
2628 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2629 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2630 port->read_status_mask |= UART_LSR_BI;
2633 * Characteres to ignore
2635 port->ignore_status_mask = 0;
2636 if (termios->c_iflag & IGNPAR)
2637 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2638 if (termios->c_iflag & IGNBRK) {
2639 port->ignore_status_mask |= UART_LSR_BI;
2641 * If we're ignoring parity and break indicators,
2642 * ignore overruns too (for real raw support).
2644 if (termios->c_iflag & IGNPAR)
2645 port->ignore_status_mask |= UART_LSR_OE;
2649 * ignore all characters if CREAD is not set
2651 if ((termios->c_cflag & CREAD) == 0)
2652 port->ignore_status_mask |= UART_LSR_DR;
2655 * CTS flow control flag and modem status interrupts
2657 up->ier &= ~UART_IER_MSI;
2658 if (!(up->bugs & UART_BUG_NOMSR) &&
2659 UART_ENABLE_MS(&up->port, termios->c_cflag))
2660 up->ier |= UART_IER_MSI;
2661 if (up->capabilities & UART_CAP_UUE)
2662 up->ier |= UART_IER_UUE;
2663 if (up->capabilities & UART_CAP_RTOIE)
2664 up->ier |= UART_IER_RTOIE;
2666 serial_port_out(port, UART_IER, up->ier);
2668 if (up->capabilities & UART_CAP_EFR) {
2669 unsigned char efr = 0;
2671 * TI16C752/Startech hardware flow control. FIXME:
2672 * - TI16C752 requires control thresholds to be set.
2673 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2675 if (termios->c_cflag & CRTSCTS)
2676 efr |= UART_EFR_CTS;
2678 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2679 if (port->flags & UPF_EXAR_EFR)
2680 serial_port_out(port, UART_XR_EFR, efr);
2682 serial_port_out(port, UART_EFR, efr);
2685 serial8250_set_divisor(port, baud, quot, frac);
2688 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2689 * is written without DLAB set, this mode will be disabled.
2691 if (port->type == PORT_16750)
2692 serial_port_out(port, UART_FCR, up->fcr);
2694 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2695 if (port->type != PORT_16750) {
2696 /* emulated UARTs (Lucent Venus 167x) need two steps */
2697 if (up->fcr & UART_FCR_ENABLE_FIFO)
2698 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2699 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2701 serial8250_set_mctrl(port, port->mctrl);
2702 spin_unlock_irqrestore(&port->lock, flags);
2703 serial8250_rpm_put(up);
2705 /* Don't rewrite B0 */
2706 if (tty_termios_baud_rate(termios))
2707 tty_termios_encode_baud_rate(termios, baud, baud);
2709 EXPORT_SYMBOL(serial8250_do_set_termios);
2712 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2713 struct ktermios *old)
2715 if (port->set_termios)
2716 port->set_termios(port, termios, old);
2718 serial8250_do_set_termios(port, termios, old);
2722 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2724 if (termios->c_line == N_PPS) {
2725 port->flags |= UPF_HARDPPS_CD;
2726 spin_lock_irq(&port->lock);
2727 serial8250_enable_ms(port);
2728 spin_unlock_irq(&port->lock);
2730 port->flags &= ~UPF_HARDPPS_CD;
2731 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2732 spin_lock_irq(&port->lock);
2733 serial8250_disable_ms(port);
2734 spin_unlock_irq(&port->lock);
2740 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2741 unsigned int oldstate)
2743 struct uart_8250_port *p = up_to_u8250p(port);
2745 serial8250_set_sleep(p, state != 0);
2747 EXPORT_SYMBOL(serial8250_do_pm);
2750 serial8250_pm(struct uart_port *port, unsigned int state,
2751 unsigned int oldstate)
2754 port->pm(port, state, oldstate);
2756 serial8250_do_pm(port, state, oldstate);
2759 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2761 if (pt->port.mapsize)
2762 return pt->port.mapsize;
2763 if (pt->port.iotype == UPIO_AU) {
2764 if (pt->port.type == PORT_RT2880)
2768 if (is_omap1_8250(pt))
2769 return 0x16 << pt->port.regshift;
2771 return 8 << pt->port.regshift;
2775 * Resource handling.
2777 static int serial8250_request_std_resource(struct uart_8250_port *up)
2779 unsigned int size = serial8250_port_size(up);
2780 struct uart_port *port = &up->port;
2783 switch (port->iotype) {
2793 if (!request_mem_region(port->mapbase, size, "serial")) {
2798 if (port->flags & UPF_IOREMAP) {
2799 port->membase = ioremap_nocache(port->mapbase, size);
2800 if (!port->membase) {
2801 release_mem_region(port->mapbase, size);
2809 if (!request_region(port->iobase, size, "serial"))
2816 static void serial8250_release_std_resource(struct uart_8250_port *up)
2818 unsigned int size = serial8250_port_size(up);
2819 struct uart_port *port = &up->port;
2821 switch (port->iotype) {
2831 if (port->flags & UPF_IOREMAP) {
2832 iounmap(port->membase);
2833 port->membase = NULL;
2836 release_mem_region(port->mapbase, size);
2841 release_region(port->iobase, size);
2846 static void serial8250_release_port(struct uart_port *port)
2848 struct uart_8250_port *up = up_to_u8250p(port);
2850 serial8250_release_std_resource(up);
2853 static int serial8250_request_port(struct uart_port *port)
2855 struct uart_8250_port *up = up_to_u8250p(port);
2857 return serial8250_request_std_resource(up);
2860 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2862 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2863 unsigned char bytes;
2865 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2867 return bytes ? bytes : -EOPNOTSUPP;
2870 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2872 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2875 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2878 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2879 if (bytes < conf_type->rxtrig_bytes[i])
2880 /* Use the nearest lower value */
2881 return (--i) << UART_FCR_R_TRIG_SHIFT;
2884 return UART_FCR_R_TRIG_11;
2887 static int do_get_rxtrig(struct tty_port *port)
2889 struct uart_state *state = container_of(port, struct uart_state, port);
2890 struct uart_port *uport = state->uart_port;
2891 struct uart_8250_port *up = up_to_u8250p(uport);
2893 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2896 return fcr_get_rxtrig_bytes(up);
2899 static int do_serial8250_get_rxtrig(struct tty_port *port)
2903 mutex_lock(&port->mutex);
2904 rxtrig_bytes = do_get_rxtrig(port);
2905 mutex_unlock(&port->mutex);
2907 return rxtrig_bytes;
2910 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2911 struct device_attribute *attr, char *buf)
2913 struct tty_port *port = dev_get_drvdata(dev);
2916 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2917 if (rxtrig_bytes < 0)
2918 return rxtrig_bytes;
2920 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2923 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2925 struct uart_state *state = container_of(port, struct uart_state, port);
2926 struct uart_port *uport = state->uart_port;
2927 struct uart_8250_port *up = up_to_u8250p(uport);
2930 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2934 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2938 serial8250_clear_fifos(up);
2939 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2940 up->fcr |= (unsigned char)rxtrig;
2941 serial_out(up, UART_FCR, up->fcr);
2945 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2949 mutex_lock(&port->mutex);
2950 ret = do_set_rxtrig(port, bytes);
2951 mutex_unlock(&port->mutex);
2956 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2957 struct device_attribute *attr, const char *buf, size_t count)
2959 struct tty_port *port = dev_get_drvdata(dev);
2960 unsigned char bytes;
2966 ret = kstrtou8(buf, 10, &bytes);
2970 ret = do_serial8250_set_rxtrig(port, bytes);
2977 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2978 serial8250_get_attr_rx_trig_bytes,
2979 serial8250_set_attr_rx_trig_bytes);
2981 static struct attribute *serial8250_dev_attrs[] = {
2982 &dev_attr_rx_trig_bytes.attr,
2986 static struct attribute_group serial8250_dev_attr_group = {
2987 .attrs = serial8250_dev_attrs,
2990 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2992 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2994 if (conf_type->rxtrig_bytes[0])
2995 up->port.attr_group = &serial8250_dev_attr_group;
2998 static void serial8250_config_port(struct uart_port *port, int flags)
3000 struct uart_8250_port *up = up_to_u8250p(port);
3004 * Find the region that we can probe for. This in turn
3005 * tells us whether we can probe for the type of port.
3007 ret = serial8250_request_std_resource(up);
3011 if (port->iotype != up->cur_iotype)
3012 set_io_from_upio(port);
3014 if (flags & UART_CONFIG_TYPE)
3017 /* if access method is AU, it is a 16550 with a quirk */
3018 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3019 up->bugs |= UART_BUG_NOMSR;
3021 /* HW bugs may trigger IRQ while IIR == NO_INT */
3022 if (port->type == PORT_TEGRA)
3023 up->bugs |= UART_BUG_NOMSR;
3025 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3028 if (port->type == PORT_UNKNOWN)
3029 serial8250_release_std_resource(up);
3031 /* Fixme: probably not the best place for this */
3032 if ((port->type == PORT_XR17V35X) ||
3033 (port->type == PORT_XR17D15X))
3034 port->handle_irq = exar_handle_irq;
3036 register_dev_spec_attr_grp(up);
3037 up->fcr = uart_config[up->port.type].fcr;
3041 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3043 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3044 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3045 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3046 ser->type == PORT_STARTECH)
3051 static const char *serial8250_type(struct uart_port *port)
3053 int type = port->type;
3055 if (type >= ARRAY_SIZE(uart_config))
3057 return uart_config[type].name;
3060 static const struct uart_ops serial8250_pops = {
3061 .tx_empty = serial8250_tx_empty,
3062 .set_mctrl = serial8250_set_mctrl,
3063 .get_mctrl = serial8250_get_mctrl,
3064 .stop_tx = serial8250_stop_tx,
3065 .start_tx = serial8250_start_tx,
3066 .throttle = serial8250_throttle,
3067 .unthrottle = serial8250_unthrottle,
3068 .stop_rx = serial8250_stop_rx,
3069 .enable_ms = serial8250_enable_ms,
3070 .break_ctl = serial8250_break_ctl,
3071 .startup = serial8250_startup,
3072 .shutdown = serial8250_shutdown,
3073 .set_termios = serial8250_set_termios,
3074 .set_ldisc = serial8250_set_ldisc,
3075 .pm = serial8250_pm,
3076 .type = serial8250_type,
3077 .release_port = serial8250_release_port,
3078 .request_port = serial8250_request_port,
3079 .config_port = serial8250_config_port,
3080 .verify_port = serial8250_verify_port,
3081 #ifdef CONFIG_CONSOLE_POLL
3082 .poll_get_char = serial8250_get_poll_char,
3083 .poll_put_char = serial8250_put_poll_char,
3087 void serial8250_init_port(struct uart_8250_port *up)
3089 struct uart_port *port = &up->port;
3091 spin_lock_init(&port->lock);
3092 port->ops = &serial8250_pops;
3094 up->cur_iotype = 0xFF;
3096 EXPORT_SYMBOL_GPL(serial8250_init_port);
3098 void serial8250_set_defaults(struct uart_8250_port *up)
3100 struct uart_port *port = &up->port;
3102 if (up->port.flags & UPF_FIXED_TYPE) {
3103 unsigned int type = up->port.type;
3105 if (!up->port.fifosize)
3106 up->port.fifosize = uart_config[type].fifo_size;
3108 up->tx_loadsz = uart_config[type].tx_loadsz;
3109 if (!up->capabilities)
3110 up->capabilities = uart_config[type].flags;
3113 set_io_from_upio(port);
3115 /* default dma handlers */
3117 if (!up->dma->tx_dma)
3118 up->dma->tx_dma = serial8250_tx_dma;
3119 if (!up->dma->rx_dma)
3120 up->dma->rx_dma = serial8250_rx_dma;
3123 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3125 #ifdef CONFIG_SERIAL_8250_CONSOLE
3127 static void serial8250_console_putchar(struct uart_port *port, int ch)
3129 struct uart_8250_port *up = up_to_u8250p(port);
3131 wait_for_xmitr(up, UART_LSR_THRE);
3132 serial_port_out(port, UART_TX, ch);
3136 * Restore serial console when h/w power-off detected
3138 static void serial8250_console_restore(struct uart_8250_port *up)
3140 struct uart_port *port = &up->port;
3141 struct ktermios termios;
3142 unsigned int baud, quot, frac = 0;
3144 termios.c_cflag = port->cons->cflag;
3145 if (port->state->port.tty && termios.c_cflag == 0)
3146 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3148 baud = serial8250_get_baud_rate(port, &termios, NULL);
3149 quot = serial8250_get_divisor(up, baud, &frac);
3151 serial8250_set_divisor(port, baud, quot, frac);
3152 serial_port_out(port, UART_LCR, up->lcr);
3153 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3157 * Print a string to the serial port trying not to disturb
3158 * any possible real use of the port...
3160 * The console_lock must be held when we get here.
3162 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3165 struct uart_port *port = &up->port;
3166 unsigned long flags;
3170 touch_nmi_watchdog();
3172 serial8250_rpm_get(up);
3176 else if (oops_in_progress)
3177 locked = spin_trylock_irqsave(&port->lock, flags);
3179 spin_lock_irqsave(&port->lock, flags);
3182 * First save the IER then disable the interrupts
3184 ier = serial_port_in(port, UART_IER);
3186 if (up->capabilities & UART_CAP_UUE)
3187 serial_port_out(port, UART_IER, UART_IER_UUE);
3189 serial_port_out(port, UART_IER, 0);
3191 /* check scratch reg to see if port powered off during system sleep */
3192 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3193 serial8250_console_restore(up);
3197 uart_console_write(port, s, count, serial8250_console_putchar);
3200 * Finally, wait for transmitter to become empty
3201 * and restore the IER
3203 wait_for_xmitr(up, BOTH_EMPTY);
3204 serial_port_out(port, UART_IER, ier);
3207 * The receive handling will happen properly because the
3208 * receive ready bit will still be set; it is not cleared
3209 * on read. However, modem control will not, we must
3210 * call it if we have saved something in the saved flags
3211 * while processing with interrupts off.
3213 if (up->msr_saved_flags)
3214 serial8250_modem_status(up);
3217 spin_unlock_irqrestore(&port->lock, flags);
3218 serial8250_rpm_put(up);
3221 static unsigned int probe_baud(struct uart_port *port)
3223 unsigned char lcr, dll, dlm;
3226 lcr = serial_port_in(port, UART_LCR);
3227 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3228 dll = serial_port_in(port, UART_DLL);
3229 dlm = serial_port_in(port, UART_DLM);
3230 serial_port_out(port, UART_LCR, lcr);
3232 quot = (dlm << 8) | dll;
3233 return (port->uartclk / 16) / quot;
3236 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3243 if (!port->iobase && !port->membase)
3247 uart_parse_options(options, &baud, &parity, &bits, &flow);
3249 baud = probe_baud(port);
3251 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3254 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3256 MODULE_LICENSE("GPL");