2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
50 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
52 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
55 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
58 * Here we define the default xmit fifo size used for each type of UART.
60 static const struct serial8250_config uart_config[] = {
85 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
86 .rxtrig_bytes = {1, 4, 8, 14},
87 .flags = UART_CAP_FIFO,
98 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
104 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
106 .rxtrig_bytes = {8, 16, 24, 28},
107 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
113 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
115 .rxtrig_bytes = {1, 16, 32, 56},
116 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
124 .name = "16C950/954",
127 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
128 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
129 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
135 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
137 .rxtrig_bytes = {8, 16, 56, 60},
138 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
144 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
145 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
151 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
152 .flags = UART_CAP_FIFO,
158 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
159 .flags = UART_CAP_FIFO | UART_NATSEMI,
165 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
166 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
172 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
173 .flags = UART_CAP_FIFO,
179 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
180 .flags = UART_CAP_FIFO | UART_CAP_AFE,
186 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
187 .flags = UART_CAP_FIFO | UART_CAP_AFE,
193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 .rxtrig_bytes = {1, 4, 8, 14},
196 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
212 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
219 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
220 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
221 .flags = UART_CAP_FIFO,
223 [PORT_BRCM_TRUMANAGE] = {
227 .flags = UART_CAP_HFIFO,
232 [PORT_ALTR_16550_F32] = {
233 .name = "Altera 16550 FIFO32",
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 [PORT_ALTR_16550_F64] = {
240 .name = "Altera 16550 FIFO64",
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 [PORT_ALTR_16550_F128] = {
247 .name = "Altera 16550 FIFO128",
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 /* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
254 workaround of errata A-008006 which states that tx_loadsz should be
255 configured less than Maximum supported fifo bytes */
256 [PORT_16550A_FSL64] = {
257 .name = "16550A_FSL64",
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
262 .flags = UART_CAP_FIFO,
265 .name = "Palmchip BK-3103",
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
269 .rxtrig_bytes = {1, 4, 8, 14},
270 .flags = UART_CAP_FIFO,
274 /* Uart divisor latch read */
275 static int default_serial_dl_read(struct uart_8250_port *up)
277 /* Assign these in pieces to truncate any bits above 7. */
278 unsigned char dll = serial_in(up, UART_DLL);
279 unsigned char dlm = serial_in(up, UART_DLM);
281 return dll | dlm << 8;
284 /* Uart divisor latch write */
285 static void default_serial_dl_write(struct uart_8250_port *up, int value)
287 serial_out(up, UART_DLL, value & 0xff);
288 serial_out(up, UART_DLM, value >> 8 & 0xff);
291 #ifdef CONFIG_SERIAL_8250_RT288X
293 /* Au1x00/RT288x UART hardware has a weird register layout */
294 static const s8 au_io_in_map[8] = {
302 -1, /* UART_SCR (unmapped) */
305 static const s8 au_io_out_map[8] = {
311 -1, /* UART_LSR (unmapped) */
312 -1, /* UART_MSR (unmapped) */
313 -1, /* UART_SCR (unmapped) */
316 static unsigned int au_serial_in(struct uart_port *p, int offset)
318 if (offset >= ARRAY_SIZE(au_io_in_map))
320 offset = au_io_in_map[offset];
323 return __raw_readl(p->membase + (offset << p->regshift));
326 static void au_serial_out(struct uart_port *p, int offset, int value)
328 if (offset >= ARRAY_SIZE(au_io_out_map))
330 offset = au_io_out_map[offset];
333 __raw_writel(value, p->membase + (offset << p->regshift));
336 /* Au1x00 haven't got a standard divisor latch */
337 static int au_serial_dl_read(struct uart_8250_port *up)
339 return __raw_readl(up->port.membase + 0x28);
342 static void au_serial_dl_write(struct uart_8250_port *up, int value)
344 __raw_writel(value, up->port.membase + 0x28);
349 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
351 offset = offset << p->regshift;
352 outb(p->hub6 - 1 + offset, p->iobase);
353 return inb(p->iobase + 1);
356 static void hub6_serial_out(struct uart_port *p, int offset, int value)
358 offset = offset << p->regshift;
359 outb(p->hub6 - 1 + offset, p->iobase);
360 outb(value, p->iobase + 1);
363 static unsigned int mem_serial_in(struct uart_port *p, int offset)
365 offset = offset << p->regshift;
366 return readb(p->membase + offset);
369 static void mem_serial_out(struct uart_port *p, int offset, int value)
371 offset = offset << p->regshift;
372 writeb(value, p->membase + offset);
375 static void mem32_serial_out(struct uart_port *p, int offset, int value)
377 offset = offset << p->regshift;
378 writel(value, p->membase + offset);
381 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
383 offset = offset << p->regshift;
384 return readl(p->membase + offset);
387 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
389 offset = offset << p->regshift;
390 iowrite32be(value, p->membase + offset);
393 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
395 offset = offset << p->regshift;
396 return ioread32be(p->membase + offset);
399 static unsigned int io_serial_in(struct uart_port *p, int offset)
401 offset = offset << p->regshift;
402 return inb(p->iobase + offset);
405 static void io_serial_out(struct uart_port *p, int offset, int value)
407 offset = offset << p->regshift;
408 outb(value, p->iobase + offset);
411 static int serial8250_default_handle_irq(struct uart_port *port);
412 static int exar_handle_irq(struct uart_port *port);
414 static void set_io_from_upio(struct uart_port *p)
416 struct uart_8250_port *up = up_to_u8250p(p);
418 up->dl_read = default_serial_dl_read;
419 up->dl_write = default_serial_dl_write;
423 p->serial_in = hub6_serial_in;
424 p->serial_out = hub6_serial_out;
428 p->serial_in = mem_serial_in;
429 p->serial_out = mem_serial_out;
433 p->serial_in = mem32_serial_in;
434 p->serial_out = mem32_serial_out;
438 p->serial_in = mem32be_serial_in;
439 p->serial_out = mem32be_serial_out;
442 #ifdef CONFIG_SERIAL_8250_RT288X
444 p->serial_in = au_serial_in;
445 p->serial_out = au_serial_out;
446 up->dl_read = au_serial_dl_read;
447 up->dl_write = au_serial_dl_write;
452 p->serial_in = io_serial_in;
453 p->serial_out = io_serial_out;
456 /* Remember loaded iotype */
457 up->cur_iotype = p->iotype;
458 p->handle_irq = serial8250_default_handle_irq;
462 serial_port_out_sync(struct uart_port *p, int offset, int value)
469 p->serial_out(p, offset, value);
470 p->serial_in(p, UART_LCR); /* safe, no side-effects */
473 p->serial_out(p, offset, value);
480 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
482 serial_out(up, UART_SCR, offset);
483 serial_out(up, UART_ICR, value);
486 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
490 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
491 serial_out(up, UART_SCR, offset);
492 value = serial_in(up, UART_ICR);
493 serial_icr_write(up, UART_ACR, up->acr);
501 static void serial8250_clear_fifos(struct uart_8250_port *p)
503 if (p->capabilities & UART_CAP_FIFO) {
504 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
505 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
506 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
507 serial_out(p, UART_FCR, 0);
511 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
513 serial8250_clear_fifos(p);
514 serial_out(p, UART_FCR, p->fcr);
516 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
518 void serial8250_rpm_get(struct uart_8250_port *p)
520 if (!(p->capabilities & UART_CAP_RPM))
522 pm_runtime_get_sync(p->port.dev);
524 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
526 void serial8250_rpm_put(struct uart_8250_port *p)
528 if (!(p->capabilities & UART_CAP_RPM))
530 pm_runtime_mark_last_busy(p->port.dev);
531 pm_runtime_put_autosuspend(p->port.dev);
533 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
536 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
537 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
538 * empty and the HW can idle again.
540 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
542 unsigned char rpm_active;
544 if (!(p->capabilities & UART_CAP_RPM))
547 rpm_active = xchg(&p->rpm_tx_active, 1);
550 pm_runtime_get_sync(p->port.dev);
553 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
555 unsigned char rpm_active;
557 if (!(p->capabilities & UART_CAP_RPM))
560 rpm_active = xchg(&p->rpm_tx_active, 0);
563 pm_runtime_mark_last_busy(p->port.dev);
564 pm_runtime_put_autosuspend(p->port.dev);
568 * IER sleep support. UARTs which have EFRs need the "extended
569 * capability" bit enabled. Note that on XR16C850s, we need to
570 * reset LCR to write to IER.
572 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
574 unsigned char lcr = 0, efr = 0;
576 * Exar UARTs have a SLEEP register that enables or disables
577 * each UART to enter sleep mode separately. On the XR17V35x the
578 * register is accessible to each UART at the UART_EXAR_SLEEP
579 * offset but the UART channel may only write to the corresponding
582 serial8250_rpm_get(p);
583 if ((p->port.type == PORT_XR17V35X) ||
584 (p->port.type == PORT_XR17D15X)) {
585 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
589 if (p->capabilities & UART_CAP_SLEEP) {
590 if (p->capabilities & UART_CAP_EFR) {
591 lcr = serial_in(p, UART_LCR);
592 efr = serial_in(p, UART_EFR);
593 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
594 serial_out(p, UART_EFR, UART_EFR_ECB);
595 serial_out(p, UART_LCR, 0);
597 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
598 if (p->capabilities & UART_CAP_EFR) {
599 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
600 serial_out(p, UART_EFR, efr);
601 serial_out(p, UART_LCR, lcr);
605 serial8250_rpm_put(p);
608 #ifdef CONFIG_SERIAL_8250_RSA
610 * Attempts to turn on the RSA FIFO. Returns zero on failure.
611 * We set the port uart clock rate if we succeed.
613 static int __enable_rsa(struct uart_8250_port *up)
618 mode = serial_in(up, UART_RSA_MSR);
619 result = mode & UART_RSA_MSR_FIFO;
622 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
623 mode = serial_in(up, UART_RSA_MSR);
624 result = mode & UART_RSA_MSR_FIFO;
628 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
633 static void enable_rsa(struct uart_8250_port *up)
635 if (up->port.type == PORT_RSA) {
636 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
637 spin_lock_irq(&up->port.lock);
639 spin_unlock_irq(&up->port.lock);
641 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
642 serial_out(up, UART_RSA_FRR, 0);
647 * Attempts to turn off the RSA FIFO. Returns zero on failure.
648 * It is unknown why interrupts were disabled in here. However,
649 * the caller is expected to preserve this behaviour by grabbing
650 * the spinlock before calling this function.
652 static void disable_rsa(struct uart_8250_port *up)
657 if (up->port.type == PORT_RSA &&
658 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
659 spin_lock_irq(&up->port.lock);
661 mode = serial_in(up, UART_RSA_MSR);
662 result = !(mode & UART_RSA_MSR_FIFO);
665 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
666 mode = serial_in(up, UART_RSA_MSR);
667 result = !(mode & UART_RSA_MSR_FIFO);
671 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
672 spin_unlock_irq(&up->port.lock);
675 #endif /* CONFIG_SERIAL_8250_RSA */
678 * This is a quickie test to see how big the FIFO is.
679 * It doesn't work at all the time, more's the pity.
681 static int size_fifo(struct uart_8250_port *up)
683 unsigned char old_fcr, old_mcr, old_lcr;
684 unsigned short old_dl;
687 old_lcr = serial_in(up, UART_LCR);
688 serial_out(up, UART_LCR, 0);
689 old_fcr = serial_in(up, UART_FCR);
690 old_mcr = serial_in(up, UART_MCR);
691 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
692 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
693 serial_out(up, UART_MCR, UART_MCR_LOOP);
694 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
695 old_dl = serial_dl_read(up);
696 serial_dl_write(up, 0x0001);
697 serial_out(up, UART_LCR, 0x03);
698 for (count = 0; count < 256; count++)
699 serial_out(up, UART_TX, count);
700 mdelay(20);/* FIXME - schedule_timeout */
701 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
702 (count < 256); count++)
703 serial_in(up, UART_RX);
704 serial_out(up, UART_FCR, old_fcr);
705 serial_out(up, UART_MCR, old_mcr);
706 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
707 serial_dl_write(up, old_dl);
708 serial_out(up, UART_LCR, old_lcr);
714 * Read UART ID using the divisor method - set DLL and DLM to zero
715 * and the revision will be in DLL and device type in DLM. We
716 * preserve the device state across this.
718 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
720 unsigned char old_lcr;
721 unsigned int id, old_dl;
723 old_lcr = serial_in(p, UART_LCR);
724 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
725 old_dl = serial_dl_read(p);
726 serial_dl_write(p, 0);
727 id = serial_dl_read(p);
728 serial_dl_write(p, old_dl);
730 serial_out(p, UART_LCR, old_lcr);
736 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
737 * When this function is called we know it is at least a StarTech
738 * 16650 V2, but it might be one of several StarTech UARTs, or one of
739 * its clones. (We treat the broken original StarTech 16650 V1 as a
740 * 16550, and why not? Startech doesn't seem to even acknowledge its
743 * What evil have men's minds wrought...
745 static void autoconfig_has_efr(struct uart_8250_port *up)
747 unsigned int id1, id2, id3, rev;
750 * Everything with an EFR has SLEEP
752 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
755 * First we check to see if it's an Oxford Semiconductor UART.
757 * If we have to do this here because some non-National
758 * Semiconductor clone chips lock up if you try writing to the
759 * LSR register (which serial_icr_read does)
763 * Check for Oxford Semiconductor 16C950.
765 * EFR [4] must be set else this test fails.
767 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
768 * claims that it's needed for 952 dual UART's (which are not
769 * recommended for new designs).
772 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
773 serial_out(up, UART_EFR, UART_EFR_ECB);
774 serial_out(up, UART_LCR, 0x00);
775 id1 = serial_icr_read(up, UART_ID1);
776 id2 = serial_icr_read(up, UART_ID2);
777 id3 = serial_icr_read(up, UART_ID3);
778 rev = serial_icr_read(up, UART_REV);
780 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
782 if (id1 == 0x16 && id2 == 0xC9 &&
783 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
784 up->port.type = PORT_16C950;
787 * Enable work around for the Oxford Semiconductor 952 rev B
788 * chip which causes it to seriously miscalculate baud rates
791 if (id3 == 0x52 && rev == 0x01)
792 up->bugs |= UART_BUG_QUOT;
797 * We check for a XR16C850 by setting DLL and DLM to 0, and then
798 * reading back DLL and DLM. The chip type depends on the DLM
800 * 0x10 - XR16C850 and the DLL contains the chip revision.
804 id1 = autoconfig_read_divisor_id(up);
805 DEBUG_AUTOCONF("850id=%04x ", id1);
808 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
809 up->port.type = PORT_16850;
814 * It wasn't an XR16C850.
816 * We distinguish between the '654 and the '650 by counting
817 * how many bytes are in the FIFO. I'm using this for now,
818 * since that's the technique that was sent to me in the
819 * serial driver update, but I'm not convinced this works.
820 * I've had problems doing this in the past. -TYT
822 if (size_fifo(up) == 64)
823 up->port.type = PORT_16654;
825 up->port.type = PORT_16650V2;
829 * We detected a chip without a FIFO. Only two fall into
830 * this category - the original 8250 and the 16450. The
831 * 16450 has a scratch register (accessible with LCR=0)
833 static void autoconfig_8250(struct uart_8250_port *up)
835 unsigned char scratch, status1, status2;
837 up->port.type = PORT_8250;
839 scratch = serial_in(up, UART_SCR);
840 serial_out(up, UART_SCR, 0xa5);
841 status1 = serial_in(up, UART_SCR);
842 serial_out(up, UART_SCR, 0x5a);
843 status2 = serial_in(up, UART_SCR);
844 serial_out(up, UART_SCR, scratch);
846 if (status1 == 0xa5 && status2 == 0x5a)
847 up->port.type = PORT_16450;
850 static int broken_efr(struct uart_8250_port *up)
853 * Exar ST16C2550 "A2" devices incorrectly detect as
854 * having an EFR, and report an ID of 0x0201. See
855 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
857 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
864 * We know that the chip has FIFOs. Does it have an EFR? The
865 * EFR is located in the same register position as the IIR and
866 * we know the top two bits of the IIR are currently set. The
867 * EFR should contain zero. Try to read the EFR.
869 static void autoconfig_16550a(struct uart_8250_port *up)
871 unsigned char status1, status2;
872 unsigned int iersave;
874 up->port.type = PORT_16550A;
875 up->capabilities |= UART_CAP_FIFO;
878 * XR17V35x UARTs have an extra divisor register, DLD
879 * that gets enabled with when DLAB is set which will
880 * cause the device to incorrectly match and assign
881 * port type to PORT_16650. The EFR for this UART is
882 * found at offset 0x09. Instead check the Deice ID (DVID)
883 * register for a 2, 4 or 8 port UART.
885 if (up->port.flags & UPF_EXAR_EFR) {
886 status1 = serial_in(up, UART_EXAR_DVID);
887 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
888 DEBUG_AUTOCONF("Exar XR17V35x ");
889 up->port.type = PORT_XR17V35X;
890 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
899 * Check for presence of the EFR when DLAB is set.
900 * Only ST16C650V1 UARTs pass this test.
902 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
903 if (serial_in(up, UART_EFR) == 0) {
904 serial_out(up, UART_EFR, 0xA8);
905 if (serial_in(up, UART_EFR) != 0) {
906 DEBUG_AUTOCONF("EFRv1 ");
907 up->port.type = PORT_16650;
908 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
910 serial_out(up, UART_LCR, 0);
911 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
913 status1 = serial_in(up, UART_IIR) >> 5;
914 serial_out(up, UART_FCR, 0);
915 serial_out(up, UART_LCR, 0);
918 up->port.type = PORT_16550A_FSL64;
920 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
922 serial_out(up, UART_EFR, 0);
927 * Maybe it requires 0xbf to be written to the LCR.
928 * (other ST16C650V2 UARTs, TI16C752A, etc)
930 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
931 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
932 DEBUG_AUTOCONF("EFRv2 ");
933 autoconfig_has_efr(up);
938 * Check for a National Semiconductor SuperIO chip.
939 * Attempt to switch to bank 2, read the value of the LOOP bit
940 * from EXCR1. Switch back to bank 0, change it in MCR. Then
941 * switch back to bank 2, read it from EXCR1 again and check
942 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
944 serial_out(up, UART_LCR, 0);
945 status1 = serial_in(up, UART_MCR);
946 serial_out(up, UART_LCR, 0xE0);
947 status2 = serial_in(up, 0x02); /* EXCR1 */
949 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
950 serial_out(up, UART_LCR, 0);
951 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
952 serial_out(up, UART_LCR, 0xE0);
953 status2 = serial_in(up, 0x02); /* EXCR1 */
954 serial_out(up, UART_LCR, 0);
955 serial_out(up, UART_MCR, status1);
957 if ((status2 ^ status1) & UART_MCR_LOOP) {
960 serial_out(up, UART_LCR, 0xE0);
962 quot = serial_dl_read(up);
965 if (ns16550a_goto_highspeed(up))
966 serial_dl_write(up, quot);
968 serial_out(up, UART_LCR, 0);
970 up->port.uartclk = 921600*16;
971 up->port.type = PORT_NS16550A;
972 up->capabilities |= UART_NATSEMI;
978 * No EFR. Try to detect a TI16750, which only sets bit 5 of
979 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
980 * Try setting it with and without DLAB set. Cheap clones
981 * set bit 5 without DLAB set.
983 serial_out(up, UART_LCR, 0);
984 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
985 status1 = serial_in(up, UART_IIR) >> 5;
986 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
987 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
988 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
989 status2 = serial_in(up, UART_IIR) >> 5;
990 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
991 serial_out(up, UART_LCR, 0);
993 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
995 if (status1 == 6 && status2 == 7) {
996 up->port.type = PORT_16750;
997 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1002 * Try writing and reading the UART_IER_UUE bit (b6).
1003 * If it works, this is probably one of the Xscale platform's
1005 * We're going to explicitly set the UUE bit to 0 before
1006 * trying to write and read a 1 just to make sure it's not
1007 * already a 1 and maybe locked there before we even start start.
1009 iersave = serial_in(up, UART_IER);
1010 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1011 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1013 * OK it's in a known zero state, try writing and reading
1014 * without disturbing the current state of the other bits.
1016 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1017 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1020 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1022 DEBUG_AUTOCONF("Xscale ");
1023 up->port.type = PORT_XSCALE;
1024 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1029 * If we got here we couldn't force the IER_UUE bit to 0.
1030 * Log it and continue.
1032 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1034 serial_out(up, UART_IER, iersave);
1037 * Exar uarts have EFR in a weird location
1039 if (up->port.flags & UPF_EXAR_EFR) {
1040 DEBUG_AUTOCONF("Exar XR17D15x ");
1041 up->port.type = PORT_XR17D15X;
1042 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1049 * We distinguish between 16550A and U6 16550A by counting
1050 * how many bytes are in the FIFO.
1052 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1053 up->port.type = PORT_U6_16550A;
1054 up->capabilities |= UART_CAP_AFE;
1059 * This routine is called by rs_init() to initialize a specific serial
1060 * port. It determines what type of UART chip this serial port is
1061 * using: 8250, 16450, 16550, 16550A. The important question is
1062 * whether or not this UART is a 16550A or not, since this will
1063 * determine whether or not we can use its FIFO features or not.
1065 static void autoconfig(struct uart_8250_port *up)
1067 unsigned char status1, scratch, scratch2, scratch3;
1068 unsigned char save_lcr, save_mcr;
1069 struct uart_port *port = &up->port;
1070 unsigned long flags;
1071 unsigned int old_capabilities;
1073 if (!port->iobase && !port->mapbase && !port->membase)
1076 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1077 serial_index(port), port->iobase, port->membase);
1080 * We really do need global IRQs disabled here - we're going to
1081 * be frobbing the chips IRQ enable register to see if it exists.
1083 spin_lock_irqsave(&port->lock, flags);
1085 up->capabilities = 0;
1088 if (!(port->flags & UPF_BUGGY_UART)) {
1090 * Do a simple existence test first; if we fail this,
1091 * there's no point trying anything else.
1093 * 0x80 is used as a nonsense port to prevent against
1094 * false positives due to ISA bus float. The
1095 * assumption is that 0x80 is a non-existent port;
1096 * which should be safe since include/asm/io.h also
1097 * makes this assumption.
1099 * Note: this is safe as long as MCR bit 4 is clear
1100 * and the device is in "PC" mode.
1102 scratch = serial_in(up, UART_IER);
1103 serial_out(up, UART_IER, 0);
1108 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1109 * 16C754B) allow only to modify them if an EFR bit is set.
1111 scratch2 = serial_in(up, UART_IER) & 0x0f;
1112 serial_out(up, UART_IER, 0x0F);
1116 scratch3 = serial_in(up, UART_IER) & 0x0f;
1117 serial_out(up, UART_IER, scratch);
1118 if (scratch2 != 0 || scratch3 != 0x0F) {
1120 * We failed; there's nothing here
1122 spin_unlock_irqrestore(&port->lock, flags);
1123 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1124 scratch2, scratch3);
1129 save_mcr = serial_in(up, UART_MCR);
1130 save_lcr = serial_in(up, UART_LCR);
1133 * Check to see if a UART is really there. Certain broken
1134 * internal modems based on the Rockwell chipset fail this
1135 * test, because they apparently don't implement the loopback
1136 * test mode. So this test is skipped on the COM 1 through
1137 * COM 4 ports. This *should* be safe, since no board
1138 * manufacturer would be stupid enough to design a board
1139 * that conflicts with COM 1-4 --- we hope!
1141 if (!(port->flags & UPF_SKIP_TEST)) {
1142 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1143 status1 = serial_in(up, UART_MSR) & 0xF0;
1144 serial_out(up, UART_MCR, save_mcr);
1145 if (status1 != 0x90) {
1146 spin_unlock_irqrestore(&port->lock, flags);
1147 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1154 * We're pretty sure there's a port here. Lets find out what
1155 * type of port it is. The IIR top two bits allows us to find
1156 * out if it's 8250 or 16450, 16550, 16550A or later. This
1157 * determines what we test for next.
1159 * We also initialise the EFR (if any) to zero for later. The
1160 * EFR occupies the same register location as the FCR and IIR.
1162 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1163 serial_out(up, UART_EFR, 0);
1164 serial_out(up, UART_LCR, 0);
1166 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1168 /* Assign this as it is to truncate any bits above 7. */
1169 scratch = serial_in(up, UART_IIR);
1171 switch (scratch >> 6) {
1173 autoconfig_8250(up);
1176 port->type = PORT_UNKNOWN;
1179 port->type = PORT_16550;
1182 autoconfig_16550a(up);
1186 #ifdef CONFIG_SERIAL_8250_RSA
1188 * Only probe for RSA ports if we got the region.
1190 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1192 port->type = PORT_RSA;
1195 serial_out(up, UART_LCR, save_lcr);
1197 port->fifosize = uart_config[up->port.type].fifo_size;
1198 old_capabilities = up->capabilities;
1199 up->capabilities = uart_config[port->type].flags;
1200 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1202 if (port->type == PORT_UNKNOWN)
1208 #ifdef CONFIG_SERIAL_8250_RSA
1209 if (port->type == PORT_RSA)
1210 serial_out(up, UART_RSA_FRR, 0);
1212 serial_out(up, UART_MCR, save_mcr);
1213 serial8250_clear_fifos(up);
1214 serial_in(up, UART_RX);
1215 if (up->capabilities & UART_CAP_UUE)
1216 serial_out(up, UART_IER, UART_IER_UUE);
1218 serial_out(up, UART_IER, 0);
1221 spin_unlock_irqrestore(&port->lock, flags);
1222 if (up->capabilities != old_capabilities) {
1224 "ttyS%d: detected caps %08x should be %08x\n",
1225 serial_index(port), old_capabilities,
1229 DEBUG_AUTOCONF("iir=%d ", scratch);
1230 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1233 static void autoconfig_irq(struct uart_8250_port *up)
1235 struct uart_port *port = &up->port;
1236 unsigned char save_mcr, save_ier;
1237 unsigned char save_ICP = 0;
1238 unsigned int ICP = 0;
1242 if (port->flags & UPF_FOURPORT) {
1243 ICP = (port->iobase & 0xfe0) | 0x1f;
1244 save_ICP = inb_p(ICP);
1249 if (uart_console(port))
1252 /* forget possible initially masked and pending IRQ */
1253 probe_irq_off(probe_irq_on());
1254 save_mcr = serial_in(up, UART_MCR);
1255 save_ier = serial_in(up, UART_IER);
1256 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1258 irqs = probe_irq_on();
1259 serial_out(up, UART_MCR, 0);
1261 if (port->flags & UPF_FOURPORT) {
1262 serial_out(up, UART_MCR,
1263 UART_MCR_DTR | UART_MCR_RTS);
1265 serial_out(up, UART_MCR,
1266 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1268 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1269 serial_in(up, UART_LSR);
1270 serial_in(up, UART_RX);
1271 serial_in(up, UART_IIR);
1272 serial_in(up, UART_MSR);
1273 serial_out(up, UART_TX, 0xFF);
1275 irq = probe_irq_off(irqs);
1277 serial_out(up, UART_MCR, save_mcr);
1278 serial_out(up, UART_IER, save_ier);
1280 if (port->flags & UPF_FOURPORT)
1281 outb_p(save_ICP, ICP);
1283 if (uart_console(port))
1286 port->irq = (irq > 0) ? irq : 0;
1289 static inline void __stop_tx(struct uart_8250_port *p)
1291 if (p->ier & UART_IER_THRI) {
1292 p->ier &= ~UART_IER_THRI;
1293 serial_out(p, UART_IER, p->ier);
1294 serial8250_rpm_put_tx(p);
1298 static void serial8250_stop_tx(struct uart_port *port)
1300 struct uart_8250_port *up = up_to_u8250p(port);
1302 serial8250_rpm_get(up);
1306 * We really want to stop the transmitter from sending.
1308 if (port->type == PORT_16C950) {
1309 up->acr |= UART_ACR_TXDIS;
1310 serial_icr_write(up, UART_ACR, up->acr);
1312 serial8250_rpm_put(up);
1315 static void serial8250_start_tx(struct uart_port *port)
1317 struct uart_8250_port *up = up_to_u8250p(port);
1319 serial8250_rpm_get_tx(up);
1321 if (up->dma && !up->dma->tx_dma(up))
1324 if (!(up->ier & UART_IER_THRI)) {
1325 up->ier |= UART_IER_THRI;
1326 serial_port_out(port, UART_IER, up->ier);
1328 if (up->bugs & UART_BUG_TXEN) {
1330 lsr = serial_in(up, UART_LSR);
1331 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1332 if (lsr & UART_LSR_THRE)
1333 serial8250_tx_chars(up);
1338 * Re-enable the transmitter if we disabled it.
1340 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1341 up->acr &= ~UART_ACR_TXDIS;
1342 serial_icr_write(up, UART_ACR, up->acr);
1346 static void serial8250_throttle(struct uart_port *port)
1348 port->throttle(port);
1351 static void serial8250_unthrottle(struct uart_port *port)
1353 port->unthrottle(port);
1356 static void serial8250_stop_rx(struct uart_port *port)
1358 struct uart_8250_port *up = up_to_u8250p(port);
1360 serial8250_rpm_get(up);
1362 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1363 up->port.read_status_mask &= ~UART_LSR_DR;
1364 serial_port_out(port, UART_IER, up->ier);
1366 serial8250_rpm_put(up);
1369 static void serial8250_disable_ms(struct uart_port *port)
1371 struct uart_8250_port *up =
1372 container_of(port, struct uart_8250_port, port);
1374 /* no MSR capabilities */
1375 if (up->bugs & UART_BUG_NOMSR)
1378 up->ier &= ~UART_IER_MSI;
1379 serial_port_out(port, UART_IER, up->ier);
1382 static void serial8250_enable_ms(struct uart_port *port)
1384 struct uart_8250_port *up = up_to_u8250p(port);
1386 /* no MSR capabilities */
1387 if (up->bugs & UART_BUG_NOMSR)
1390 up->ier |= UART_IER_MSI;
1392 serial8250_rpm_get(up);
1393 serial_port_out(port, UART_IER, up->ier);
1394 serial8250_rpm_put(up);
1398 * serial8250_rx_chars: processes according to the passed in LSR
1399 * value, and returns the remaining LSR bits not handled
1400 * by this Rx routine.
1403 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1405 struct uart_port *port = &up->port;
1407 int max_count = 256;
1411 if (likely(lsr & UART_LSR_DR))
1412 ch = serial_in(up, UART_RX);
1415 * Intel 82571 has a Serial Over Lan device that will
1416 * set UART_LSR_BI without setting UART_LSR_DR when
1417 * it receives a break. To avoid reading from the
1418 * receive buffer without UART_LSR_DR bit set, we
1419 * just force the read character to be 0
1426 lsr |= up->lsr_saved_flags;
1427 up->lsr_saved_flags = 0;
1429 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1430 if (lsr & UART_LSR_BI) {
1431 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1434 * We do the SysRQ and SAK checking
1435 * here because otherwise the break
1436 * may get masked by ignore_status_mask
1437 * or read_status_mask.
1439 if (uart_handle_break(port))
1441 } else if (lsr & UART_LSR_PE)
1442 port->icount.parity++;
1443 else if (lsr & UART_LSR_FE)
1444 port->icount.frame++;
1445 if (lsr & UART_LSR_OE)
1446 port->icount.overrun++;
1449 * Mask off conditions which should be ignored.
1451 lsr &= port->read_status_mask;
1453 if (lsr & UART_LSR_BI) {
1454 DEBUG_INTR("handling break....");
1456 } else if (lsr & UART_LSR_PE)
1458 else if (lsr & UART_LSR_FE)
1461 if (uart_handle_sysrq_char(port, ch))
1464 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1467 lsr = serial_in(up, UART_LSR);
1468 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0));
1469 spin_unlock(&port->lock);
1470 tty_flip_buffer_push(&port->state->port);
1471 spin_lock(&port->lock);
1474 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1476 void serial8250_tx_chars(struct uart_8250_port *up)
1478 struct uart_port *port = &up->port;
1479 struct circ_buf *xmit = &port->state->xmit;
1483 serial_out(up, UART_TX, port->x_char);
1488 if (uart_tx_stopped(port)) {
1489 serial8250_stop_tx(port);
1492 if (uart_circ_empty(xmit)) {
1497 count = up->tx_loadsz;
1499 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1500 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1502 if (uart_circ_empty(xmit))
1504 if (up->capabilities & UART_CAP_HFIFO) {
1505 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1509 } while (--count > 0);
1511 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1512 uart_write_wakeup(port);
1514 DEBUG_INTR("THRE...");
1517 * With RPM enabled, we have to wait until the FIFO is empty before the
1518 * HW can go idle. So we get here once again with empty FIFO and disable
1519 * the interrupt and RPM in __stop_tx()
1521 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1524 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1526 /* Caller holds uart port lock */
1527 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1529 struct uart_port *port = &up->port;
1530 unsigned int status = serial_in(up, UART_MSR);
1532 status |= up->msr_saved_flags;
1533 up->msr_saved_flags = 0;
1534 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1535 port->state != NULL) {
1536 if (status & UART_MSR_TERI)
1538 if (status & UART_MSR_DDSR)
1540 if (status & UART_MSR_DDCD)
1541 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1542 if (status & UART_MSR_DCTS)
1543 uart_handle_cts_change(port, status & UART_MSR_CTS);
1545 wake_up_interruptible(&port->state->port.delta_msr_wait);
1550 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1553 * This handles the interrupt from one port.
1555 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1557 unsigned char status;
1558 unsigned long flags;
1559 struct uart_8250_port *up = up_to_u8250p(port);
1562 if (iir & UART_IIR_NO_INT)
1565 spin_lock_irqsave(&port->lock, flags);
1567 status = serial_port_in(port, UART_LSR);
1569 DEBUG_INTR("status = %x...", status);
1571 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1573 dma_err = up->dma->rx_dma(up, iir);
1575 if (!up->dma || dma_err)
1576 status = serial8250_rx_chars(up, status);
1578 serial8250_modem_status(up);
1579 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1580 (status & UART_LSR_THRE))
1581 serial8250_tx_chars(up);
1583 spin_unlock_irqrestore(&port->lock, flags);
1586 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1588 static int serial8250_default_handle_irq(struct uart_port *port)
1590 struct uart_8250_port *up = up_to_u8250p(port);
1594 serial8250_rpm_get(up);
1596 iir = serial_port_in(port, UART_IIR);
1597 ret = serial8250_handle_irq(port, iir);
1599 serial8250_rpm_put(up);
1604 * These Exar UARTs have an extra interrupt indicator that could
1605 * fire for a few unimplemented interrupts. One of which is a
1606 * wakeup event when coming out of sleep. Put this here just
1607 * to be on the safe side that these interrupts don't go unhandled.
1609 static int exar_handle_irq(struct uart_port *port)
1611 unsigned char int0, int1, int2, int3;
1612 unsigned int iir = serial_port_in(port, UART_IIR);
1615 ret = serial8250_handle_irq(port, iir);
1617 if ((port->type == PORT_XR17V35X) ||
1618 (port->type == PORT_XR17D15X)) {
1619 int0 = serial_port_in(port, 0x80);
1620 int1 = serial_port_in(port, 0x81);
1621 int2 = serial_port_in(port, 0x82);
1622 int3 = serial_port_in(port, 0x83);
1628 static unsigned int serial8250_tx_empty(struct uart_port *port)
1630 struct uart_8250_port *up = up_to_u8250p(port);
1631 unsigned long flags;
1634 serial8250_rpm_get(up);
1636 spin_lock_irqsave(&port->lock, flags);
1637 lsr = serial_port_in(port, UART_LSR);
1638 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1639 spin_unlock_irqrestore(&port->lock, flags);
1641 serial8250_rpm_put(up);
1643 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1646 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1648 struct uart_8250_port *up = up_to_u8250p(port);
1649 unsigned int status;
1652 serial8250_rpm_get(up);
1653 status = serial8250_modem_status(up);
1654 serial8250_rpm_put(up);
1657 if (status & UART_MSR_DCD)
1659 if (status & UART_MSR_RI)
1661 if (status & UART_MSR_DSR)
1663 if (status & UART_MSR_CTS)
1668 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1670 struct uart_8250_port *up = up_to_u8250p(port);
1671 unsigned char mcr = 0;
1673 if (mctrl & TIOCM_RTS)
1674 mcr |= UART_MCR_RTS;
1675 if (mctrl & TIOCM_DTR)
1676 mcr |= UART_MCR_DTR;
1677 if (mctrl & TIOCM_OUT1)
1678 mcr |= UART_MCR_OUT1;
1679 if (mctrl & TIOCM_OUT2)
1680 mcr |= UART_MCR_OUT2;
1681 if (mctrl & TIOCM_LOOP)
1682 mcr |= UART_MCR_LOOP;
1684 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1686 serial_port_out(port, UART_MCR, mcr);
1688 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1690 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1692 if (port->set_mctrl)
1693 port->set_mctrl(port, mctrl);
1695 serial8250_do_set_mctrl(port, mctrl);
1698 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1700 struct uart_8250_port *up = up_to_u8250p(port);
1701 unsigned long flags;
1703 serial8250_rpm_get(up);
1704 spin_lock_irqsave(&port->lock, flags);
1705 if (break_state == -1)
1706 up->lcr |= UART_LCR_SBC;
1708 up->lcr &= ~UART_LCR_SBC;
1709 serial_port_out(port, UART_LCR, up->lcr);
1710 spin_unlock_irqrestore(&port->lock, flags);
1711 serial8250_rpm_put(up);
1715 * Wait for transmitter & holding register to empty
1717 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1719 unsigned int status, tmout = 10000;
1721 /* Wait up to 10ms for the character(s) to be sent. */
1723 status = serial_in(up, UART_LSR);
1725 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1727 if ((status & bits) == bits)
1734 /* Wait up to 1s for flow control if necessary */
1735 if (up->port.flags & UPF_CONS_FLOW) {
1737 for (tmout = 1000000; tmout; tmout--) {
1738 unsigned int msr = serial_in(up, UART_MSR);
1739 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1740 if (msr & UART_MSR_CTS)
1743 touch_nmi_watchdog();
1748 #ifdef CONFIG_CONSOLE_POLL
1750 * Console polling routines for writing and reading from the uart while
1751 * in an interrupt or debug context.
1754 static int serial8250_get_poll_char(struct uart_port *port)
1756 struct uart_8250_port *up = up_to_u8250p(port);
1760 serial8250_rpm_get(up);
1762 lsr = serial_port_in(port, UART_LSR);
1764 if (!(lsr & UART_LSR_DR)) {
1765 status = NO_POLL_CHAR;
1769 status = serial_port_in(port, UART_RX);
1771 serial8250_rpm_put(up);
1776 static void serial8250_put_poll_char(struct uart_port *port,
1780 struct uart_8250_port *up = up_to_u8250p(port);
1782 serial8250_rpm_get(up);
1784 * First save the IER then disable the interrupts
1786 ier = serial_port_in(port, UART_IER);
1787 if (up->capabilities & UART_CAP_UUE)
1788 serial_port_out(port, UART_IER, UART_IER_UUE);
1790 serial_port_out(port, UART_IER, 0);
1792 wait_for_xmitr(up, BOTH_EMPTY);
1794 * Send the character out.
1796 serial_port_out(port, UART_TX, c);
1799 * Finally, wait for transmitter to become empty
1800 * and restore the IER
1802 wait_for_xmitr(up, BOTH_EMPTY);
1803 serial_port_out(port, UART_IER, ier);
1804 serial8250_rpm_put(up);
1807 #endif /* CONFIG_CONSOLE_POLL */
1809 int serial8250_do_startup(struct uart_port *port)
1811 struct uart_8250_port *up = up_to_u8250p(port);
1812 unsigned long flags;
1813 unsigned char lsr, iir;
1816 if (!port->fifosize)
1817 port->fifosize = uart_config[port->type].fifo_size;
1819 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1820 if (!up->capabilities)
1821 up->capabilities = uart_config[port->type].flags;
1824 if (port->iotype != up->cur_iotype)
1825 set_io_from_upio(port);
1827 serial8250_rpm_get(up);
1828 if (port->type == PORT_16C950) {
1829 /* Wake up and initialize UART */
1831 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1832 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1833 serial_port_out(port, UART_IER, 0);
1834 serial_port_out(port, UART_LCR, 0);
1835 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1836 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1837 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1838 serial_port_out(port, UART_LCR, 0);
1841 #ifdef CONFIG_SERIAL_8250_RSA
1843 * If this is an RSA port, see if we can kick it up to the
1844 * higher speed clock.
1849 if (port->type == PORT_XR17V35X) {
1851 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
1852 * MCR [7:5] and MSR [7:0]
1854 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
1857 * Make sure all interrups are masked until initialization is
1858 * complete and the FIFOs are cleared
1860 serial_port_out(port, UART_IER, 0);
1864 * Clear the FIFO buffers and disable them.
1865 * (they will be reenabled in set_termios())
1867 serial8250_clear_fifos(up);
1870 * Clear the interrupt registers.
1872 serial_port_in(port, UART_LSR);
1873 serial_port_in(port, UART_RX);
1874 serial_port_in(port, UART_IIR);
1875 serial_port_in(port, UART_MSR);
1878 * At this point, there's no way the LSR could still be 0xff;
1879 * if it is, then bail out, because there's likely no UART
1882 if (!(port->flags & UPF_BUGGY_UART) &&
1883 (serial_port_in(port, UART_LSR) == 0xff)) {
1884 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1885 serial_index(port));
1891 * For a XR16C850, we need to set the trigger levels
1893 if (port->type == PORT_16850) {
1896 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1898 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1899 serial_port_out(port, UART_FCTR,
1900 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1901 serial_port_out(port, UART_TRG, UART_TRG_96);
1902 serial_port_out(port, UART_FCTR,
1903 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1904 serial_port_out(port, UART_TRG, UART_TRG_96);
1906 serial_port_out(port, UART_LCR, 0);
1912 if (port->irqflags & IRQF_SHARED)
1913 disable_irq_nosync(port->irq);
1916 * Test for UARTs that do not reassert THRE when the
1917 * transmitter is idle and the interrupt has already
1918 * been cleared. Real 16550s should always reassert
1919 * this interrupt whenever the transmitter is idle and
1920 * the interrupt is enabled. Delays are necessary to
1921 * allow register changes to become visible.
1923 spin_lock_irqsave(&port->lock, flags);
1925 wait_for_xmitr(up, UART_LSR_THRE);
1926 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1927 udelay(1); /* allow THRE to set */
1928 iir1 = serial_port_in(port, UART_IIR);
1929 serial_port_out(port, UART_IER, 0);
1930 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1931 udelay(1); /* allow a working UART time to re-assert THRE */
1932 iir = serial_port_in(port, UART_IIR);
1933 serial_port_out(port, UART_IER, 0);
1935 spin_unlock_irqrestore(&port->lock, flags);
1937 if (port->irqflags & IRQF_SHARED)
1938 enable_irq(port->irq);
1941 * If the interrupt is not reasserted, or we otherwise
1942 * don't trust the iir, setup a timer to kick the UART
1943 * on a regular basis.
1945 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
1946 up->port.flags & UPF_BUG_THRE) {
1947 up->bugs |= UART_BUG_THRE;
1951 retval = up->ops->setup_irq(up);
1956 * Now, initialize the UART
1958 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1960 spin_lock_irqsave(&port->lock, flags);
1961 if (up->port.flags & UPF_FOURPORT) {
1963 up->port.mctrl |= TIOCM_OUT1;
1966 * Most PC uarts need OUT2 raised to enable interrupts.
1969 up->port.mctrl |= TIOCM_OUT2;
1971 serial8250_set_mctrl(port, port->mctrl);
1973 /* Serial over Lan (SoL) hack:
1974 Intel 8257x Gigabit ethernet chips have a
1975 16550 emulation, to be used for Serial Over Lan.
1976 Those chips take a longer time than a normal
1977 serial device to signalize that a transmission
1978 data was queued. Due to that, the above test generally
1979 fails. One solution would be to delay the reading of
1980 iir. However, this is not reliable, since the timeout
1981 is variable. So, let's just don't test if we receive
1982 TX irq. This way, we'll never enable UART_BUG_TXEN.
1984 if (up->port.flags & UPF_NO_TXEN_TEST)
1985 goto dont_test_tx_en;
1988 * Do a quick test to see if we receive an
1989 * interrupt when we enable the TX irq.
1991 serial_port_out(port, UART_IER, UART_IER_THRI);
1992 lsr = serial_port_in(port, UART_LSR);
1993 iir = serial_port_in(port, UART_IIR);
1994 serial_port_out(port, UART_IER, 0);
1996 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1997 if (!(up->bugs & UART_BUG_TXEN)) {
1998 up->bugs |= UART_BUG_TXEN;
1999 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2000 serial_index(port));
2003 up->bugs &= ~UART_BUG_TXEN;
2007 spin_unlock_irqrestore(&port->lock, flags);
2010 * Clear the interrupt registers again for luck, and clear the
2011 * saved flags to avoid getting false values from polling
2012 * routines or the previous session.
2014 serial_port_in(port, UART_LSR);
2015 serial_port_in(port, UART_RX);
2016 serial_port_in(port, UART_IIR);
2017 serial_port_in(port, UART_MSR);
2018 up->lsr_saved_flags = 0;
2019 up->msr_saved_flags = 0;
2022 * Request DMA channels for both RX and TX.
2025 retval = serial8250_request_dma(up);
2027 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2028 serial_index(port));
2034 * Set the IER shadow for rx interrupts but defer actual interrupt
2035 * enable until after the FIFOs are enabled; otherwise, an already-
2036 * active sender can swamp the interrupt handler with "too much work".
2038 up->ier = UART_IER_RLSI | UART_IER_RDI;
2040 if (port->flags & UPF_FOURPORT) {
2043 * Enable interrupts on the AST Fourport board
2045 icp = (port->iobase & 0xfe0) | 0x01f;
2051 serial8250_rpm_put(up);
2054 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2056 static int serial8250_startup(struct uart_port *port)
2059 return port->startup(port);
2060 return serial8250_do_startup(port);
2063 void serial8250_do_shutdown(struct uart_port *port)
2065 struct uart_8250_port *up = up_to_u8250p(port);
2066 unsigned long flags;
2068 serial8250_rpm_get(up);
2070 * Disable interrupts from this port
2073 serial_port_out(port, UART_IER, 0);
2076 serial8250_release_dma(up);
2078 spin_lock_irqsave(&port->lock, flags);
2079 if (port->flags & UPF_FOURPORT) {
2080 /* reset interrupts on the AST Fourport board */
2081 inb((port->iobase & 0xfe0) | 0x1f);
2082 port->mctrl |= TIOCM_OUT1;
2084 port->mctrl &= ~TIOCM_OUT2;
2086 serial8250_set_mctrl(port, port->mctrl);
2087 spin_unlock_irqrestore(&port->lock, flags);
2090 * Disable break condition and FIFOs
2092 serial_port_out(port, UART_LCR,
2093 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2094 serial8250_clear_fifos(up);
2096 #ifdef CONFIG_SERIAL_8250_RSA
2098 * Reset the RSA board back to 115kbps compat mode.
2104 * Read data port to reset things, and then unlink from
2107 serial_port_in(port, UART_RX);
2108 serial8250_rpm_put(up);
2110 up->ops->release_irq(up);
2112 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2114 static void serial8250_shutdown(struct uart_port *port)
2117 port->shutdown(port);
2119 serial8250_do_shutdown(port);
2123 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2124 * Calculate divisor with extra 4-bit fractional portion
2126 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2130 struct uart_port *port = &up->port;
2131 unsigned int quot_16;
2133 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2134 *frac = quot_16 & 0x0f;
2136 return quot_16 >> 4;
2139 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2143 struct uart_port *port = &up->port;
2147 * Handle magic divisors for baud rates above baud_base on
2148 * SMSC SuperIO chips.
2151 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2152 baud == (port->uartclk/4))
2154 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2155 baud == (port->uartclk/8))
2157 else if (up->port.type == PORT_XR17V35X)
2158 quot = xr17v35x_get_divisor(up, baud, frac);
2160 quot = uart_get_divisor(port, baud);
2163 * Oxford Semi 952 rev B workaround
2165 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2171 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2176 switch (c_cflag & CSIZE) {
2178 cval = UART_LCR_WLEN5;
2181 cval = UART_LCR_WLEN6;
2184 cval = UART_LCR_WLEN7;
2188 cval = UART_LCR_WLEN8;
2192 if (c_cflag & CSTOPB)
2193 cval |= UART_LCR_STOP;
2194 if (c_cflag & PARENB) {
2195 cval |= UART_LCR_PARITY;
2196 if (up->bugs & UART_BUG_PARITY)
2197 up->fifo_bug = true;
2199 if (!(c_cflag & PARODD))
2200 cval |= UART_LCR_EPAR;
2202 if (c_cflag & CMSPAR)
2203 cval |= UART_LCR_SPAR;
2209 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2210 unsigned int quot, unsigned int quot_frac)
2212 struct uart_8250_port *up = up_to_u8250p(port);
2214 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2215 if (is_omap1510_8250(up)) {
2216 if (baud == 115200) {
2218 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2220 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2224 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2225 * otherwise just set DLAB
2227 if (up->capabilities & UART_NATSEMI)
2228 serial_port_out(port, UART_LCR, 0xe0);
2230 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2232 serial_dl_write(up, quot);
2234 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2235 if (up->port.type == PORT_XR17V35X) {
2236 /* Preserve bits not related to baudrate; DLD[7:4]. */
2237 quot_frac |= serial_port_in(port, 0x2) & 0xf0;
2238 serial_port_out(port, 0x2, quot_frac);
2243 serial8250_get_baud_rate(struct uart_port *port, struct ktermios *termios,
2244 struct ktermios *old)
2246 unsigned int tolerance = port->uartclk / 100;
2249 * Ask the core to calculate the divisor for us.
2250 * Allow 1% tolerance at the upper limit so uart clks marginally
2251 * slower than nominal still match standard baud rates without
2252 * causing transmission errors.
2254 return uart_get_baud_rate(port, termios, old,
2255 port->uartclk / 16 / 0xffff,
2256 (port->uartclk + tolerance) / 16);
2260 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2261 struct ktermios *old)
2263 struct uart_8250_port *up = up_to_u8250p(port);
2265 unsigned long flags;
2266 unsigned int baud, quot, frac = 0;
2268 cval = serial8250_compute_lcr(up, termios->c_cflag);
2270 baud = serial8250_get_baud_rate(port, termios, old);
2271 quot = serial8250_get_divisor(up, baud, &frac);
2274 * Ok, we're now changing the port state. Do it with
2275 * interrupts disabled.
2277 serial8250_rpm_get(up);
2278 spin_lock_irqsave(&port->lock, flags);
2280 up->lcr = cval; /* Save computed LCR */
2282 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2283 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2284 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2285 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2286 up->fcr |= UART_FCR_TRIGGER_1;
2291 * MCR-based auto flow control. When AFE is enabled, RTS will be
2292 * deasserted when the receive FIFO contains more characters than
2293 * the trigger, or the MCR RTS bit is cleared. In the case where
2294 * the remote UART is not using CTS auto flow control, we must
2295 * have sufficient FIFO entries for the latency of the remote
2296 * UART to respond. IOW, at least 32 bytes of FIFO.
2298 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2299 up->mcr &= ~UART_MCR_AFE;
2300 if (termios->c_cflag & CRTSCTS)
2301 up->mcr |= UART_MCR_AFE;
2305 * Update the per-port timeout.
2307 uart_update_timeout(port, termios->c_cflag, baud);
2309 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2310 if (termios->c_iflag & INPCK)
2311 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2312 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2313 port->read_status_mask |= UART_LSR_BI;
2316 * Characteres to ignore
2318 port->ignore_status_mask = 0;
2319 if (termios->c_iflag & IGNPAR)
2320 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2321 if (termios->c_iflag & IGNBRK) {
2322 port->ignore_status_mask |= UART_LSR_BI;
2324 * If we're ignoring parity and break indicators,
2325 * ignore overruns too (for real raw support).
2327 if (termios->c_iflag & IGNPAR)
2328 port->ignore_status_mask |= UART_LSR_OE;
2332 * ignore all characters if CREAD is not set
2334 if ((termios->c_cflag & CREAD) == 0)
2335 port->ignore_status_mask |= UART_LSR_DR;
2338 * CTS flow control flag and modem status interrupts
2340 up->ier &= ~UART_IER_MSI;
2341 if (!(up->bugs & UART_BUG_NOMSR) &&
2342 UART_ENABLE_MS(&up->port, termios->c_cflag))
2343 up->ier |= UART_IER_MSI;
2344 if (up->capabilities & UART_CAP_UUE)
2345 up->ier |= UART_IER_UUE;
2346 if (up->capabilities & UART_CAP_RTOIE)
2347 up->ier |= UART_IER_RTOIE;
2349 serial_port_out(port, UART_IER, up->ier);
2351 if (up->capabilities & UART_CAP_EFR) {
2352 unsigned char efr = 0;
2354 * TI16C752/Startech hardware flow control. FIXME:
2355 * - TI16C752 requires control thresholds to be set.
2356 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2358 if (termios->c_cflag & CRTSCTS)
2359 efr |= UART_EFR_CTS;
2361 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2362 if (port->flags & UPF_EXAR_EFR)
2363 serial_port_out(port, UART_XR_EFR, efr);
2365 serial_port_out(port, UART_EFR, efr);
2368 serial8250_set_divisor(port, baud, quot, frac);
2371 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2372 * is written without DLAB set, this mode will be disabled.
2374 if (port->type == PORT_16750)
2375 serial_port_out(port, UART_FCR, up->fcr);
2377 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2378 if (port->type != PORT_16750) {
2379 /* emulated UARTs (Lucent Venus 167x) need two steps */
2380 if (up->fcr & UART_FCR_ENABLE_FIFO)
2381 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2382 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2384 serial8250_set_mctrl(port, port->mctrl);
2385 spin_unlock_irqrestore(&port->lock, flags);
2386 serial8250_rpm_put(up);
2388 /* Don't rewrite B0 */
2389 if (tty_termios_baud_rate(termios))
2390 tty_termios_encode_baud_rate(termios, baud, baud);
2392 EXPORT_SYMBOL(serial8250_do_set_termios);
2395 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2396 struct ktermios *old)
2398 if (port->set_termios)
2399 port->set_termios(port, termios, old);
2401 serial8250_do_set_termios(port, termios, old);
2405 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2407 if (termios->c_line == N_PPS) {
2408 port->flags |= UPF_HARDPPS_CD;
2409 spin_lock_irq(&port->lock);
2410 serial8250_enable_ms(port);
2411 spin_unlock_irq(&port->lock);
2413 port->flags &= ~UPF_HARDPPS_CD;
2414 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2415 spin_lock_irq(&port->lock);
2416 serial8250_disable_ms(port);
2417 spin_unlock_irq(&port->lock);
2423 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2424 unsigned int oldstate)
2426 struct uart_8250_port *p = up_to_u8250p(port);
2428 serial8250_set_sleep(p, state != 0);
2430 EXPORT_SYMBOL(serial8250_do_pm);
2433 serial8250_pm(struct uart_port *port, unsigned int state,
2434 unsigned int oldstate)
2437 port->pm(port, state, oldstate);
2439 serial8250_do_pm(port, state, oldstate);
2442 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2444 if (pt->port.mapsize)
2445 return pt->port.mapsize;
2446 if (pt->port.iotype == UPIO_AU) {
2447 if (pt->port.type == PORT_RT2880)
2451 if (is_omap1_8250(pt))
2452 return 0x16 << pt->port.regshift;
2454 return 8 << pt->port.regshift;
2458 * Resource handling.
2460 static int serial8250_request_std_resource(struct uart_8250_port *up)
2462 unsigned int size = serial8250_port_size(up);
2463 struct uart_port *port = &up->port;
2466 switch (port->iotype) {
2475 if (!request_mem_region(port->mapbase, size, "serial")) {
2480 if (port->flags & UPF_IOREMAP) {
2481 port->membase = ioremap_nocache(port->mapbase, size);
2482 if (!port->membase) {
2483 release_mem_region(port->mapbase, size);
2491 if (!request_region(port->iobase, size, "serial"))
2498 static void serial8250_release_std_resource(struct uart_8250_port *up)
2500 unsigned int size = serial8250_port_size(up);
2501 struct uart_port *port = &up->port;
2503 switch (port->iotype) {
2512 if (port->flags & UPF_IOREMAP) {
2513 iounmap(port->membase);
2514 port->membase = NULL;
2517 release_mem_region(port->mapbase, size);
2522 release_region(port->iobase, size);
2527 static void serial8250_release_port(struct uart_port *port)
2529 struct uart_8250_port *up = up_to_u8250p(port);
2531 serial8250_release_std_resource(up);
2534 static int serial8250_request_port(struct uart_port *port)
2536 struct uart_8250_port *up = up_to_u8250p(port);
2538 return serial8250_request_std_resource(up);
2541 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2543 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2544 unsigned char bytes;
2546 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2548 return bytes ? bytes : -EOPNOTSUPP;
2551 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2553 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2556 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2559 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2560 if (bytes < conf_type->rxtrig_bytes[i])
2561 /* Use the nearest lower value */
2562 return (--i) << UART_FCR_R_TRIG_SHIFT;
2565 return UART_FCR_R_TRIG_11;
2568 static int do_get_rxtrig(struct tty_port *port)
2570 struct uart_state *state = container_of(port, struct uart_state, port);
2571 struct uart_port *uport = state->uart_port;
2572 struct uart_8250_port *up =
2573 container_of(uport, struct uart_8250_port, port);
2575 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2578 return fcr_get_rxtrig_bytes(up);
2581 static int do_serial8250_get_rxtrig(struct tty_port *port)
2585 mutex_lock(&port->mutex);
2586 rxtrig_bytes = do_get_rxtrig(port);
2587 mutex_unlock(&port->mutex);
2589 return rxtrig_bytes;
2592 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2593 struct device_attribute *attr, char *buf)
2595 struct tty_port *port = dev_get_drvdata(dev);
2598 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2599 if (rxtrig_bytes < 0)
2600 return rxtrig_bytes;
2602 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2605 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2607 struct uart_state *state = container_of(port, struct uart_state, port);
2608 struct uart_port *uport = state->uart_port;
2609 struct uart_8250_port *up =
2610 container_of(uport, struct uart_8250_port, port);
2613 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2617 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2621 serial8250_clear_fifos(up);
2622 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2623 up->fcr |= (unsigned char)rxtrig;
2624 serial_out(up, UART_FCR, up->fcr);
2628 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2632 mutex_lock(&port->mutex);
2633 ret = do_set_rxtrig(port, bytes);
2634 mutex_unlock(&port->mutex);
2639 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2640 struct device_attribute *attr, const char *buf, size_t count)
2642 struct tty_port *port = dev_get_drvdata(dev);
2643 unsigned char bytes;
2649 ret = kstrtou8(buf, 10, &bytes);
2653 ret = do_serial8250_set_rxtrig(port, bytes);
2660 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2661 serial8250_get_attr_rx_trig_bytes,
2662 serial8250_set_attr_rx_trig_bytes);
2664 static struct attribute *serial8250_dev_attrs[] = {
2665 &dev_attr_rx_trig_bytes.attr,
2669 static struct attribute_group serial8250_dev_attr_group = {
2670 .attrs = serial8250_dev_attrs,
2673 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2675 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2677 if (conf_type->rxtrig_bytes[0])
2678 up->port.attr_group = &serial8250_dev_attr_group;
2681 static void serial8250_config_port(struct uart_port *port, int flags)
2683 struct uart_8250_port *up = up_to_u8250p(port);
2687 * Find the region that we can probe for. This in turn
2688 * tells us whether we can probe for the type of port.
2690 ret = serial8250_request_std_resource(up);
2694 if (port->iotype != up->cur_iotype)
2695 set_io_from_upio(port);
2697 if (flags & UART_CONFIG_TYPE)
2700 /* if access method is AU, it is a 16550 with a quirk */
2701 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2702 up->bugs |= UART_BUG_NOMSR;
2704 /* HW bugs may trigger IRQ while IIR == NO_INT */
2705 if (port->type == PORT_TEGRA)
2706 up->bugs |= UART_BUG_NOMSR;
2708 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2711 if (port->type == PORT_UNKNOWN)
2712 serial8250_release_std_resource(up);
2714 /* Fixme: probably not the best place for this */
2715 if ((port->type == PORT_XR17V35X) ||
2716 (port->type == PORT_XR17D15X))
2717 port->handle_irq = exar_handle_irq;
2719 register_dev_spec_attr_grp(up);
2720 up->fcr = uart_config[up->port.type].fcr;
2724 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2726 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2727 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2728 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2729 ser->type == PORT_STARTECH)
2735 serial8250_type(struct uart_port *port)
2737 int type = port->type;
2739 if (type >= ARRAY_SIZE(uart_config))
2741 return uart_config[type].name;
2744 static const struct uart_ops serial8250_pops = {
2745 .tx_empty = serial8250_tx_empty,
2746 .set_mctrl = serial8250_set_mctrl,
2747 .get_mctrl = serial8250_get_mctrl,
2748 .stop_tx = serial8250_stop_tx,
2749 .start_tx = serial8250_start_tx,
2750 .throttle = serial8250_throttle,
2751 .unthrottle = serial8250_unthrottle,
2752 .stop_rx = serial8250_stop_rx,
2753 .enable_ms = serial8250_enable_ms,
2754 .break_ctl = serial8250_break_ctl,
2755 .startup = serial8250_startup,
2756 .shutdown = serial8250_shutdown,
2757 .set_termios = serial8250_set_termios,
2758 .set_ldisc = serial8250_set_ldisc,
2759 .pm = serial8250_pm,
2760 .type = serial8250_type,
2761 .release_port = serial8250_release_port,
2762 .request_port = serial8250_request_port,
2763 .config_port = serial8250_config_port,
2764 .verify_port = serial8250_verify_port,
2765 #ifdef CONFIG_CONSOLE_POLL
2766 .poll_get_char = serial8250_get_poll_char,
2767 .poll_put_char = serial8250_put_poll_char,
2771 void serial8250_init_port(struct uart_8250_port *up)
2773 struct uart_port *port = &up->port;
2775 spin_lock_init(&port->lock);
2776 port->ops = &serial8250_pops;
2778 up->cur_iotype = 0xFF;
2780 EXPORT_SYMBOL_GPL(serial8250_init_port);
2782 void serial8250_set_defaults(struct uart_8250_port *up)
2784 struct uart_port *port = &up->port;
2786 if (up->port.flags & UPF_FIXED_TYPE) {
2787 unsigned int type = up->port.type;
2789 if (!up->port.fifosize)
2790 up->port.fifosize = uart_config[type].fifo_size;
2792 up->tx_loadsz = uart_config[type].tx_loadsz;
2793 if (!up->capabilities)
2794 up->capabilities = uart_config[type].flags;
2797 set_io_from_upio(port);
2799 /* default dma handlers */
2801 if (!up->dma->tx_dma)
2802 up->dma->tx_dma = serial8250_tx_dma;
2803 if (!up->dma->rx_dma)
2804 up->dma->rx_dma = serial8250_rx_dma;
2807 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
2809 #ifdef CONFIG_SERIAL_8250_CONSOLE
2811 static void serial8250_console_putchar(struct uart_port *port, int ch)
2813 struct uart_8250_port *up = up_to_u8250p(port);
2815 wait_for_xmitr(up, UART_LSR_THRE);
2816 serial_port_out(port, UART_TX, ch);
2820 * Restore serial console when h/w power-off detected
2822 static void serial8250_console_restore(struct uart_8250_port *up)
2824 struct uart_port *port = &up->port;
2825 struct ktermios termios;
2826 unsigned int baud, quot, frac = 0;
2828 termios.c_cflag = port->cons->cflag;
2829 if (port->state->port.tty && termios.c_cflag == 0)
2830 termios.c_cflag = port->state->port.tty->termios.c_cflag;
2832 baud = serial8250_get_baud_rate(port, &termios, NULL);
2833 quot = serial8250_get_divisor(up, baud, &frac);
2835 serial8250_set_divisor(port, baud, quot, frac);
2836 serial_port_out(port, UART_LCR, up->lcr);
2837 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
2841 * Print a string to the serial port trying not to disturb
2842 * any possible real use of the port...
2844 * The console_lock must be held when we get here.
2846 void serial8250_console_write(struct uart_8250_port *up, const char *s,
2849 struct uart_port *port = &up->port;
2850 unsigned long flags;
2854 touch_nmi_watchdog();
2856 serial8250_rpm_get(up);
2860 else if (oops_in_progress)
2861 locked = spin_trylock_irqsave(&port->lock, flags);
2863 spin_lock_irqsave(&port->lock, flags);
2866 * First save the IER then disable the interrupts
2868 ier = serial_port_in(port, UART_IER);
2870 if (up->capabilities & UART_CAP_UUE)
2871 serial_port_out(port, UART_IER, UART_IER_UUE);
2873 serial_port_out(port, UART_IER, 0);
2875 /* check scratch reg to see if port powered off during system sleep */
2876 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
2877 serial8250_console_restore(up);
2881 uart_console_write(port, s, count, serial8250_console_putchar);
2884 * Finally, wait for transmitter to become empty
2885 * and restore the IER
2887 wait_for_xmitr(up, BOTH_EMPTY);
2888 serial_port_out(port, UART_IER, ier);
2891 * The receive handling will happen properly because the
2892 * receive ready bit will still be set; it is not cleared
2893 * on read. However, modem control will not, we must
2894 * call it if we have saved something in the saved flags
2895 * while processing with interrupts off.
2897 if (up->msr_saved_flags)
2898 serial8250_modem_status(up);
2901 spin_unlock_irqrestore(&port->lock, flags);
2902 serial8250_rpm_put(up);
2905 static unsigned int probe_baud(struct uart_port *port)
2907 unsigned char lcr, dll, dlm;
2910 lcr = serial_port_in(port, UART_LCR);
2911 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
2912 dll = serial_port_in(port, UART_DLL);
2913 dlm = serial_port_in(port, UART_DLM);
2914 serial_port_out(port, UART_LCR, lcr);
2916 quot = (dlm << 8) | dll;
2917 return (port->uartclk / 16) / quot;
2920 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
2927 if (!port->iobase && !port->membase)
2931 uart_parse_options(options, &baud, &parity, &bits, &flow);
2933 baud = probe_baud(port);
2935 return uart_set_options(port, port->cons, baud, parity, bits, flow);
2938 #endif /* CONFIG_SERIAL_8250_CONSOLE */
2940 MODULE_LICENSE("GPL");