2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
25 #include <asm/byteorder.h>
31 * init function returns:
32 * > 0 - number of ports
33 * = 0 - use board->num_ports
36 struct pci_serial_quirk {
41 int (*probe)(struct pci_dev *dev);
42 int (*init)(struct pci_dev *dev);
43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
45 struct uart_8250_port *, int);
46 void (*exit)(struct pci_dev *dev);
49 #define PCI_NUM_BAR_RESOURCES 6
51 struct serial_private {
54 struct pci_serial_quirk *quirk;
55 const struct pciserial_board *board;
59 static int pci_default_setup(struct serial_private*,
60 const struct pciserial_board*, struct uart_8250_port *, int);
62 static void moan_device(const char *str, struct pci_dev *dev)
66 "Please send the output of lspci -vv, this\n"
67 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 "manufacturer and name of serial board or\n"
69 "modem board to <linux-serial@vger.kernel.org>.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
75 setup_port(struct serial_private *priv, struct uart_8250_port *port,
76 u8 bar, unsigned int offset, int regshift)
78 struct pci_dev *dev = priv->dev;
80 if (bar >= PCI_NUM_BAR_RESOURCES)
83 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
84 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
87 port->port.iotype = UPIO_MEM;
88 port->port.iobase = 0;
89 port->port.mapbase = pci_resource_start(dev, bar) + offset;
90 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
91 port->port.regshift = regshift;
93 port->port.iotype = UPIO_PORT;
94 port->port.iobase = pci_resource_start(dev, bar) + offset;
95 port->port.mapbase = 0;
96 port->port.membase = NULL;
97 port->port.regshift = 0;
103 * ADDI-DATA GmbH communication cards <info@addi-data.com>
105 static int addidata_apci7800_setup(struct serial_private *priv,
106 const struct pciserial_board *board,
107 struct uart_8250_port *port, int idx)
109 unsigned int bar = 0, offset = board->first_offset;
110 bar = FL_GET_BASE(board->flags);
113 offset += idx * board->uart_offset;
114 } else if ((idx >= 2) && (idx < 4)) {
116 offset += ((idx - 2) * board->uart_offset);
117 } else if ((idx >= 4) && (idx < 6)) {
119 offset += ((idx - 4) * board->uart_offset);
120 } else if (idx >= 6) {
122 offset += ((idx - 6) * board->uart_offset);
125 return setup_port(priv, port, bar, offset, board->reg_shift);
129 * AFAVLAB uses a different mixture of BARs and offsets
130 * Not that ugly ;) -- HW
133 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
134 struct uart_8250_port *port, int idx)
136 unsigned int bar, offset = board->first_offset;
138 bar = FL_GET_BASE(board->flags);
143 offset += (idx - 4) * board->uart_offset;
146 return setup_port(priv, port, bar, offset, board->reg_shift);
150 * HP's Remote Management Console. The Diva chip came in several
151 * different versions. N-class, L2000 and A500 have two Diva chips, each
152 * with 3 UARTs (the third UART on the second chip is unused). Superdome
153 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
154 * one Diva chip, but it has been expanded to 5 UARTs.
156 static int pci_hp_diva_init(struct pci_dev *dev)
160 switch (dev->subsystem_device) {
161 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
162 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
163 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
164 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
170 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
173 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
174 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
183 * HP's Diva chip puts the 4th/5th serial port further out, and
184 * some serial ports are supposed to be hidden on certain models.
187 pci_hp_diva_setup(struct serial_private *priv,
188 const struct pciserial_board *board,
189 struct uart_8250_port *port, int idx)
191 unsigned int offset = board->first_offset;
192 unsigned int bar = FL_GET_BASE(board->flags);
194 switch (priv->dev->subsystem_device) {
195 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
199 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 offset += idx * board->uart_offset;
211 return setup_port(priv, port, bar, offset, board->reg_shift);
215 * Added for EKF Intel i960 serial boards
217 static int pci_inteli960ni_init(struct pci_dev *dev)
221 if (!(dev->subsystem_device & 0x1000))
224 /* is firmware started? */
225 pci_read_config_dword(dev, 0x44, &oldval);
226 if (oldval == 0x00001000L) { /* RESET value */
227 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
234 * Some PCI serial cards using the PLX 9050 PCI interface chip require
235 * that the card interrupt be explicitly enabled or disabled. This
236 * seems to be mainly needed on card using the PLX which also use I/O
239 static int pci_plx9050_init(struct pci_dev *dev)
244 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
245 moan_device("no memory in bar 0", dev);
250 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
251 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
254 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
255 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
257 * As the megawolf cards have the int pins active
258 * high, and have 2 UART chips, both ints must be
259 * enabled on the 9050. Also, the UARTS are set in
260 * 16450 mode by default, so we have to enable the
261 * 16C950 'enhanced' mode so that we can use the
266 * enable/disable interrupts
268 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
271 writel(irq_config, p + 0x4c);
274 * Read the register back to ensure that it took effect.
282 static void pci_plx9050_exit(struct pci_dev *dev)
286 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
297 * Read the register back to ensure that it took effect.
304 #define NI8420_INT_ENABLE_REG 0x38
305 #define NI8420_INT_ENABLE_BIT 0x2000
307 static void pci_ni8420_exit(struct pci_dev *dev)
310 unsigned int bar = 0;
312 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
313 moan_device("no memory in bar", dev);
317 p = pci_ioremap_bar(dev, bar);
321 /* Disable the CPU Interrupt */
322 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
323 p + NI8420_INT_ENABLE_REG);
329 #define MITE_IOWBSR1 0xc4
330 #define MITE_IOWCR1 0xf4
331 #define MITE_LCIMR1 0x08
332 #define MITE_LCIMR2 0x10
334 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
336 static void pci_ni8430_exit(struct pci_dev *dev)
339 unsigned int bar = 0;
341 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
342 moan_device("no memory in bar", dev);
346 p = pci_ioremap_bar(dev, bar);
350 /* Disable the CPU Interrupt */
351 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
355 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
357 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
358 struct uart_8250_port *port, int idx)
360 unsigned int bar, offset = board->first_offset;
365 /* first four channels map to 0, 0x100, 0x200, 0x300 */
366 offset += idx * board->uart_offset;
367 } else if (idx < 8) {
368 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
369 offset += idx * board->uart_offset + 0xC00;
370 } else /* we have only 8 ports on PMC-OCTALPRO */
373 return setup_port(priv, port, bar, offset, board->reg_shift);
377 * This does initialization for PMC OCTALPRO cards:
378 * maps the device memory, resets the UARTs (needed, bc
379 * if the module is removed and inserted again, the card
380 * is in the sleep mode) and enables global interrupt.
383 /* global control register offset for SBS PMC-OctalPro */
384 #define OCT_REG_CR_OFF 0x500
386 static int sbs_init(struct pci_dev *dev)
390 p = pci_ioremap_bar(dev, 0);
394 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
395 writeb(0x10, p + OCT_REG_CR_OFF);
397 writeb(0x0, p + OCT_REG_CR_OFF);
399 /* Set bit-2 (INTENABLE) of Control Register */
400 writeb(0x4, p + OCT_REG_CR_OFF);
407 * Disables the global interrupt of PMC-OctalPro
410 static void sbs_exit(struct pci_dev *dev)
414 p = pci_ioremap_bar(dev, 0);
415 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
417 writeb(0, p + OCT_REG_CR_OFF);
422 * SIIG serial cards have an PCI interface chip which also controls
423 * the UART clocking frequency. Each UART can be clocked independently
424 * (except cards equipped with 4 UARTs) and initial clocking settings
425 * are stored in the EEPROM chip. It can cause problems because this
426 * version of serial driver doesn't support differently clocked UART's
427 * on single PCI card. To prevent this, initialization functions set
428 * high frequency clocking for all UART's on given card. It is safe (I
429 * hope) because it doesn't touch EEPROM settings to prevent conflicts
430 * with other OSes (like M$ DOS).
432 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
434 * There is two family of SIIG serial cards with different PCI
435 * interface chip and different configuration methods:
436 * - 10x cards have control registers in IO and/or memory space;
437 * - 20x cards have control registers in standard PCI configuration space.
439 * Note: all 10x cards have PCI device ids 0x10..
440 * all 20x cards have PCI device ids 0x20..
442 * There are also Quartet Serial cards which use Oxford Semiconductor
443 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
445 * Note: some SIIG cards are probed by the parport_serial object.
448 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
449 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
451 static int pci_siig10x_init(struct pci_dev *dev)
456 switch (dev->device & 0xfff8) {
457 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
460 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
463 default: /* 1S1P, 4S */
468 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
472 writew(readw(p + 0x28) & data, p + 0x28);
478 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
479 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
481 static int pci_siig20x_init(struct pci_dev *dev)
485 /* Change clock frequency for the first UART. */
486 pci_read_config_byte(dev, 0x6f, &data);
487 pci_write_config_byte(dev, 0x6f, data & 0xef);
489 /* If this card has 2 UART, we have to do the same with second UART. */
490 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
491 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
492 pci_read_config_byte(dev, 0x73, &data);
493 pci_write_config_byte(dev, 0x73, data & 0xef);
498 static int pci_siig_init(struct pci_dev *dev)
500 unsigned int type = dev->device & 0xff00;
503 return pci_siig10x_init(dev);
504 else if (type == 0x2000)
505 return pci_siig20x_init(dev);
507 moan_device("Unknown SIIG card", dev);
511 static int pci_siig_setup(struct serial_private *priv,
512 const struct pciserial_board *board,
513 struct uart_8250_port *port, int idx)
515 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
519 offset = (idx - 4) * 8;
522 return setup_port(priv, port, bar, offset, 0);
526 * Timedia has an explosion of boards, and to avoid the PCI table from
527 * growing *huge*, we use this function to collapse some 70 entries
528 * in the PCI table into one, for sanity's and compactness's sake.
530 static const unsigned short timedia_single_port[] = {
531 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
534 static const unsigned short timedia_dual_port[] = {
535 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
536 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
537 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
538 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
542 static const unsigned short timedia_quad_port[] = {
543 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
544 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
545 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
549 static const unsigned short timedia_eight_port[] = {
550 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
551 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
554 static const struct timedia_struct {
556 const unsigned short *ids;
558 { 1, timedia_single_port },
559 { 2, timedia_dual_port },
560 { 4, timedia_quad_port },
561 { 8, timedia_eight_port }
565 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
566 * listing them individually, this driver merely grabs them all with
567 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
568 * and should be left free to be claimed by parport_serial instead.
570 static int pci_timedia_probe(struct pci_dev *dev)
573 * Check the third digit of the subdevice ID
574 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
576 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
578 "ignoring Timedia subdevice %04x for parport_serial\n",
579 dev->subsystem_device);
586 static int pci_timedia_init(struct pci_dev *dev)
588 const unsigned short *ids;
591 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
592 ids = timedia_data[i].ids;
593 for (j = 0; ids[j]; j++)
594 if (dev->subsystem_device == ids[j])
595 return timedia_data[i].num;
601 * Timedia/SUNIX uses a mixture of BARs and offsets
602 * Ugh, this is ugly as all hell --- TYT
605 pci_timedia_setup(struct serial_private *priv,
606 const struct pciserial_board *board,
607 struct uart_8250_port *port, int idx)
609 unsigned int bar = 0, offset = board->first_offset;
616 offset = board->uart_offset;
623 offset = board->uart_offset;
632 return setup_port(priv, port, bar, offset, board->reg_shift);
636 * Some Titan cards are also a little weird
639 titan_400l_800l_setup(struct serial_private *priv,
640 const struct pciserial_board *board,
641 struct uart_8250_port *port, int idx)
643 unsigned int bar, offset = board->first_offset;
654 offset = (idx - 2) * board->uart_offset;
657 return setup_port(priv, port, bar, offset, board->reg_shift);
660 static int pci_xircom_init(struct pci_dev *dev)
666 static int pci_ni8420_init(struct pci_dev *dev)
669 unsigned int bar = 0;
671 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
672 moan_device("no memory in bar", dev);
676 p = pci_ioremap_bar(dev, bar);
680 /* Enable CPU Interrupt */
681 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
682 p + NI8420_INT_ENABLE_REG);
688 #define MITE_IOWBSR1_WSIZE 0xa
689 #define MITE_IOWBSR1_WIN_OFFSET 0x800
690 #define MITE_IOWBSR1_WENAB (1 << 7)
691 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
692 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
693 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
695 static int pci_ni8430_init(struct pci_dev *dev)
698 struct pci_bus_region region;
700 unsigned int bar = 0;
702 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
703 moan_device("no memory in bar", dev);
707 p = pci_ioremap_bar(dev, bar);
712 * Set device window address and size in BAR0, while acknowledging that
713 * the resource structure may contain a translated address that differs
714 * from the address the device responds to.
716 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
717 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
718 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
719 writel(device_window, p + MITE_IOWBSR1);
721 /* Set window access to go to RAMSEL IO address space */
722 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
725 /* Enable IO Bus Interrupt 0 */
726 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
728 /* Enable CPU Interrupt */
729 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
735 /* UART Port Control Register */
736 #define NI8430_PORTCON 0x0f
737 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
740 pci_ni8430_setup(struct serial_private *priv,
741 const struct pciserial_board *board,
742 struct uart_8250_port *port, int idx)
744 struct pci_dev *dev = priv->dev;
746 unsigned int bar, offset = board->first_offset;
748 if (idx >= board->num_ports)
751 bar = FL_GET_BASE(board->flags);
752 offset += idx * board->uart_offset;
754 p = pci_ioremap_bar(dev, bar);
758 /* enable the transceiver */
759 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
760 p + offset + NI8430_PORTCON);
764 return setup_port(priv, port, bar, offset, board->reg_shift);
767 static int pci_netmos_9900_setup(struct serial_private *priv,
768 const struct pciserial_board *board,
769 struct uart_8250_port *port, int idx)
773 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
774 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
775 /* netmos apparently orders BARs by datasheet layout, so serial
776 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
780 return setup_port(priv, port, bar, 0, board->reg_shift);
782 return pci_default_setup(priv, board, port, idx);
786 /* the 99xx series comes with a range of device IDs and a variety
789 * 9900 has varying capabilities and can cascade to sub-controllers
790 * (cascading should be purely internal)
791 * 9904 is hardwired with 4 serial ports
792 * 9912 and 9922 are hardwired with 2 serial ports
794 static int pci_netmos_9900_numports(struct pci_dev *dev)
796 unsigned int c = dev->class;
798 unsigned short sub_serports;
805 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
806 /* two possibilities: 0x30ps encodes number of parallel and
807 * serial ports, or 0x1000 indicates *something*. This is not
808 * immediately obvious, since the 2s1p+4s configuration seems
809 * to offer all functionality on functions 0..2, while still
810 * advertising the same function 3 as the 4s+2s1p config.
812 sub_serports = dev->subsystem_device & 0xf;
813 if (sub_serports > 0)
817 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
821 moan_device("unknown NetMos/Mostech program interface", dev);
825 static int pci_netmos_init(struct pci_dev *dev)
827 /* subdevice 0x00PS means <P> parallel, <S> serial */
828 unsigned int num_serial = dev->subsystem_device & 0xf;
830 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
831 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
834 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
835 dev->subsystem_device == 0x0299)
838 switch (dev->device) { /* FALLTHROUGH on all */
839 case PCI_DEVICE_ID_NETMOS_9904:
840 case PCI_DEVICE_ID_NETMOS_9912:
841 case PCI_DEVICE_ID_NETMOS_9922:
842 case PCI_DEVICE_ID_NETMOS_9900:
843 num_serial = pci_netmos_9900_numports(dev);
850 if (num_serial == 0) {
851 moan_device("unknown NetMos/Mostech device", dev);
859 * These chips are available with optionally one parallel port and up to
860 * two serial ports. Unfortunately they all have the same product id.
862 * Basic configuration is done over a region of 32 I/O ports. The base
863 * ioport is called INTA or INTC, depending on docs/other drivers.
865 * The region of the 32 I/O ports is configured in POSIO0R...
869 #define ITE_887x_MISCR 0x9c
870 #define ITE_887x_INTCBAR 0x78
871 #define ITE_887x_UARTBAR 0x7c
872 #define ITE_887x_PS0BAR 0x10
873 #define ITE_887x_POSIO0 0x60
876 #define ITE_887x_IOSIZE 32
877 /* I/O space size (bits 26-24; 8 bytes = 011b) */
878 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
879 /* I/O space size (bits 26-24; 32 bytes = 101b) */
880 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
881 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
882 #define ITE_887x_POSIO_SPEED (3 << 29)
883 /* enable IO_Space bit */
884 #define ITE_887x_POSIO_ENABLE (1 << 31)
886 static int pci_ite887x_init(struct pci_dev *dev)
888 /* inta_addr are the configuration addresses of the ITE */
889 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
892 struct resource *iobase = NULL;
893 u32 miscr, uartbar, ioport;
895 /* search for the base-ioport */
897 while (inta_addr[i] && iobase == NULL) {
898 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
900 if (iobase != NULL) {
901 /* write POSIO0R - speed | size | ioport */
902 pci_write_config_dword(dev, ITE_887x_POSIO0,
903 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
904 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
905 /* write INTCBAR - ioport */
906 pci_write_config_dword(dev, ITE_887x_INTCBAR,
908 ret = inb(inta_addr[i]);
910 /* ioport connected */
913 release_region(iobase->start, ITE_887x_IOSIZE);
920 dev_err(&dev->dev, "ite887x: could not find iobase\n");
924 /* start of undocumented type checking (see parport_pc.c) */
925 type = inb(iobase->start + 0x18) & 0x0f;
928 case 0x2: /* ITE8871 (1P) */
929 case 0xa: /* ITE8875 (1P) */
932 case 0xe: /* ITE8872 (2S1P) */
935 case 0x6: /* ITE8873 (1S) */
938 case 0x8: /* ITE8874 (2S) */
942 moan_device("Unknown ITE887x", dev);
946 /* configure all serial ports */
947 for (i = 0; i < ret; i++) {
948 /* read the I/O port from the device */
949 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
951 ioport &= 0x0000FF00; /* the actual base address */
952 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
953 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
954 ITE_887x_POSIO_IOSIZE_8 | ioport);
956 /* write the ioport to the UARTBAR */
957 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
958 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
959 uartbar |= (ioport << (16 * i)); /* set the ioport */
960 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
962 /* get current config */
963 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
964 /* disable interrupts (UARTx_Routing[3:0]) */
965 miscr &= ~(0xf << (12 - 4 * i));
966 /* activate the UART (UARTx_En) */
967 miscr |= 1 << (23 - i);
968 /* write new config with activated UART */
969 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
973 /* the device has no UARTs if we get here */
974 release_region(iobase->start, ITE_887x_IOSIZE);
980 static void pci_ite887x_exit(struct pci_dev *dev)
983 /* the ioport is bit 0-15 in POSIO0R */
984 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
986 release_region(ioport, ITE_887x_IOSIZE);
990 * EndRun Technologies.
991 * Determine the number of ports available on the device.
993 #define PCI_VENDOR_ID_ENDRUN 0x7401
994 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
996 static int pci_endrun_init(struct pci_dev *dev)
999 unsigned long deviceID;
1000 unsigned int number_uarts = 0;
1002 /* EndRun device is all 0xexxx */
1003 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1004 (dev->device & 0xf000) != 0xe000)
1007 p = pci_iomap(dev, 0, 5);
1011 deviceID = ioread32(p);
1013 if (deviceID == 0x07000200) {
1014 number_uarts = ioread8(p + 4);
1016 "%d ports detected on EndRun PCI Express device\n",
1019 pci_iounmap(dev, p);
1020 return number_uarts;
1024 * Oxford Semiconductor Inc.
1025 * Check that device is part of the Tornado range of devices, then determine
1026 * the number of ports available on the device.
1028 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1031 unsigned long deviceID;
1032 unsigned int number_uarts = 0;
1034 /* OxSemi Tornado devices are all 0xCxxx */
1035 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1036 (dev->device & 0xF000) != 0xC000)
1039 p = pci_iomap(dev, 0, 5);
1043 deviceID = ioread32(p);
1044 /* Tornado device */
1045 if (deviceID == 0x07000200) {
1046 number_uarts = ioread8(p + 4);
1048 "%d ports detected on Oxford PCI Express device\n",
1051 pci_iounmap(dev, p);
1052 return number_uarts;
1055 static int pci_asix_setup(struct serial_private *priv,
1056 const struct pciserial_board *board,
1057 struct uart_8250_port *port, int idx)
1059 port->bugs |= UART_BUG_PARITY;
1060 return pci_default_setup(priv, board, port, idx);
1063 /* Quatech devices have their own extra interface features */
1065 struct quatech_feature {
1070 #define QPCR_TEST_FOR1 0x3F
1071 #define QPCR_TEST_GET1 0x00
1072 #define QPCR_TEST_FOR2 0x40
1073 #define QPCR_TEST_GET2 0x40
1074 #define QPCR_TEST_FOR3 0x80
1075 #define QPCR_TEST_GET3 0x40
1076 #define QPCR_TEST_FOR4 0xC0
1077 #define QPCR_TEST_GET4 0x80
1079 #define QOPR_CLOCK_X1 0x0000
1080 #define QOPR_CLOCK_X2 0x0001
1081 #define QOPR_CLOCK_X4 0x0002
1082 #define QOPR_CLOCK_X8 0x0003
1083 #define QOPR_CLOCK_RATE_MASK 0x0003
1086 static struct quatech_feature quatech_cards[] = {
1087 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1088 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1089 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1090 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1091 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1092 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1093 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1094 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1096 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1097 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1098 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1099 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1100 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1101 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1102 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1103 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1104 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1105 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1109 static int pci_quatech_amcc(u16 devid)
1111 struct quatech_feature *qf = &quatech_cards[0];
1113 if (qf->devid == devid)
1117 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1121 static int pci_quatech_rqopr(struct uart_8250_port *port)
1123 unsigned long base = port->port.iobase;
1126 LCR = inb(base + UART_LCR);
1127 outb(0xBF, base + UART_LCR);
1128 val = inb(base + UART_SCR);
1129 outb(LCR, base + UART_LCR);
1133 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1135 unsigned long base = port->port.iobase;
1138 LCR = inb(base + UART_LCR);
1139 outb(0xBF, base + UART_LCR);
1140 inb(base + UART_SCR);
1141 outb(qopr, base + UART_SCR);
1142 outb(LCR, base + UART_LCR);
1145 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1147 unsigned long base = port->port.iobase;
1150 LCR = inb(base + UART_LCR);
1151 outb(0xBF, base + UART_LCR);
1152 val = inb(base + UART_SCR);
1153 outb(val | 0x10, base + UART_SCR);
1154 qmcr = inb(base + UART_MCR);
1155 outb(val, base + UART_SCR);
1156 outb(LCR, base + UART_LCR);
1161 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1163 unsigned long base = port->port.iobase;
1166 LCR = inb(base + UART_LCR);
1167 outb(0xBF, base + UART_LCR);
1168 val = inb(base + UART_SCR);
1169 outb(val | 0x10, base + UART_SCR);
1170 outb(qmcr, base + UART_MCR);
1171 outb(val, base + UART_SCR);
1172 outb(LCR, base + UART_LCR);
1175 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1177 unsigned long base = port->port.iobase;
1180 LCR = inb(base + UART_LCR);
1181 outb(0xBF, base + UART_LCR);
1182 val = inb(base + UART_SCR);
1184 outb(0x80, UART_LCR);
1185 if (!(inb(UART_SCR) & 0x20)) {
1186 outb(LCR, base + UART_LCR);
1193 static int pci_quatech_test(struct uart_8250_port *port)
1197 qopr = pci_quatech_rqopr(port);
1198 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1199 reg = pci_quatech_rqopr(port) & 0xC0;
1200 if (reg != QPCR_TEST_GET1)
1202 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1203 reg = pci_quatech_rqopr(port) & 0xC0;
1204 if (reg != QPCR_TEST_GET2)
1206 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1207 reg = pci_quatech_rqopr(port) & 0xC0;
1208 if (reg != QPCR_TEST_GET3)
1210 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1211 reg = pci_quatech_rqopr(port) & 0xC0;
1212 if (reg != QPCR_TEST_GET4)
1215 pci_quatech_wqopr(port, qopr);
1219 static int pci_quatech_clock(struct uart_8250_port *port)
1222 unsigned long clock;
1224 if (pci_quatech_test(port) < 0)
1227 qopr = pci_quatech_rqopr(port);
1229 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1230 reg = pci_quatech_rqopr(port);
1231 if (reg & QOPR_CLOCK_X8) {
1235 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1236 reg = pci_quatech_rqopr(port);
1237 if (!(reg & QOPR_CLOCK_X8)) {
1241 reg &= QOPR_CLOCK_X8;
1242 if (reg == QOPR_CLOCK_X2) {
1244 set = QOPR_CLOCK_X2;
1245 } else if (reg == QOPR_CLOCK_X4) {
1247 set = QOPR_CLOCK_X4;
1248 } else if (reg == QOPR_CLOCK_X8) {
1250 set = QOPR_CLOCK_X8;
1253 set = QOPR_CLOCK_X1;
1255 qopr &= ~QOPR_CLOCK_RATE_MASK;
1259 pci_quatech_wqopr(port, qopr);
1263 static int pci_quatech_rs422(struct uart_8250_port *port)
1268 if (!pci_quatech_has_qmcr(port))
1270 qmcr = pci_quatech_rqmcr(port);
1271 pci_quatech_wqmcr(port, 0xFF);
1272 if (pci_quatech_rqmcr(port))
1274 pci_quatech_wqmcr(port, qmcr);
1278 static int pci_quatech_init(struct pci_dev *dev)
1280 if (pci_quatech_amcc(dev->device)) {
1281 unsigned long base = pci_resource_start(dev, 0);
1285 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1286 tmp = inl(base + 0x3c);
1287 outl(tmp | 0x01000000, base + 0x3c);
1288 outl(tmp &= ~0x01000000, base + 0x3c);
1294 static int pci_quatech_setup(struct serial_private *priv,
1295 const struct pciserial_board *board,
1296 struct uart_8250_port *port, int idx)
1298 /* Needed by pci_quatech calls below */
1299 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1300 /* Set up the clocking */
1301 port->port.uartclk = pci_quatech_clock(port);
1302 /* For now just warn about RS422 */
1303 if (pci_quatech_rs422(port))
1304 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1305 return pci_default_setup(priv, board, port, idx);
1308 static void pci_quatech_exit(struct pci_dev *dev)
1312 static int pci_default_setup(struct serial_private *priv,
1313 const struct pciserial_board *board,
1314 struct uart_8250_port *port, int idx)
1316 unsigned int bar, offset = board->first_offset, maxnr;
1318 bar = FL_GET_BASE(board->flags);
1319 if (board->flags & FL_BASE_BARS)
1322 offset += idx * board->uart_offset;
1324 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1325 (board->reg_shift + 3);
1327 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1330 return setup_port(priv, port, bar, offset, board->reg_shift);
1333 static int pci_pericom_setup(struct serial_private *priv,
1334 const struct pciserial_board *board,
1335 struct uart_8250_port *port, int idx)
1337 unsigned int bar, offset = board->first_offset, maxnr;
1339 bar = FL_GET_BASE(board->flags);
1340 if (board->flags & FL_BASE_BARS)
1343 offset += idx * board->uart_offset;
1348 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1349 (board->reg_shift + 3);
1351 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354 return setup_port(priv, port, bar, offset, board->reg_shift);
1358 ce4100_serial_setup(struct serial_private *priv,
1359 const struct pciserial_board *board,
1360 struct uart_8250_port *port, int idx)
1364 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1365 port->port.iotype = UPIO_MEM32;
1366 port->port.type = PORT_XSCALE;
1367 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1368 port->port.regshift = 2;
1374 pci_omegapci_setup(struct serial_private *priv,
1375 const struct pciserial_board *board,
1376 struct uart_8250_port *port, int idx)
1378 return setup_port(priv, port, 2, idx * 8, 0);
1382 pci_brcm_trumanage_setup(struct serial_private *priv,
1383 const struct pciserial_board *board,
1384 struct uart_8250_port *port, int idx)
1386 int ret = pci_default_setup(priv, board, port, idx);
1388 port->port.type = PORT_BRCM_TRUMANAGE;
1389 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1393 /* RTS will control by MCR if this bit is 0 */
1394 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1395 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1396 #define FINTEK_RTS_INVERT BIT(5)
1398 /* We should do proper H/W transceiver setting before change to RS485 mode */
1399 static int pci_fintek_rs485_config(struct uart_port *port,
1400 struct serial_rs485 *rs485)
1402 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1404 u8 *index = (u8 *) port->private_data;
1406 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1409 rs485 = &port->rs485;
1410 else if (rs485->flags & SER_RS485_ENABLED)
1411 memset(rs485->padding, 0, sizeof(rs485->padding));
1413 memset(rs485, 0, sizeof(*rs485));
1415 /* F81504/508/512 not support RTS delay before or after send */
1416 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1418 if (rs485->flags & SER_RS485_ENABLED) {
1419 /* Enable RTS H/W control mode */
1420 setting |= FINTEK_RTS_CONTROL_BY_HW;
1422 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1423 /* RTS driving high on TX */
1424 setting &= ~FINTEK_RTS_INVERT;
1426 /* RTS driving low on TX */
1427 setting |= FINTEK_RTS_INVERT;
1430 rs485->delay_rts_after_send = 0;
1431 rs485->delay_rts_before_send = 0;
1433 /* Disable RTS H/W control mode */
1434 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1437 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1439 if (rs485 != &port->rs485)
1440 port->rs485 = *rs485;
1445 static int pci_fintek_setup(struct serial_private *priv,
1446 const struct pciserial_board *board,
1447 struct uart_8250_port *port, int idx)
1449 struct pci_dev *pdev = priv->dev;
1454 config_base = 0x40 + 0x08 * idx;
1456 /* Get the io address from configuration space */
1457 pci_read_config_word(pdev, config_base + 4, &iobase);
1459 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1461 port->port.iotype = UPIO_PORT;
1462 port->port.iobase = iobase;
1463 port->port.rs485_config = pci_fintek_rs485_config;
1465 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1469 /* preserve index in PCI configuration space */
1471 port->port.private_data = data;
1476 static int pci_fintek_init(struct pci_dev *dev)
1478 unsigned long iobase;
1482 struct serial_private *priv = pci_get_drvdata(dev);
1483 struct uart_8250_port *port;
1485 switch (dev->device) {
1486 case 0x1104: /* 4 ports */
1487 case 0x1108: /* 8 ports */
1488 max_port = dev->device & 0xff;
1490 case 0x1112: /* 12 ports */
1497 /* Get the io address dispatch from the BIOS */
1498 pci_read_config_dword(dev, 0x24, &bar_data[0]);
1499 pci_read_config_dword(dev, 0x20, &bar_data[1]);
1500 pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1502 for (i = 0; i < max_port; ++i) {
1503 /* UART0 configuration offset start from 0x40 */
1504 config_base = 0x40 + 0x08 * i;
1506 /* Calculate Real IO Port */
1507 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1509 /* Enable UART I/O port */
1510 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1512 /* Select 128-byte FIFO and 8x FIFO threshold */
1513 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1516 pci_write_config_byte(dev, config_base + 0x04,
1517 (u8)(iobase & 0xff));
1520 pci_write_config_byte(dev, config_base + 0x05,
1521 (u8)((iobase & 0xff00) >> 8));
1523 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1526 /* re-apply RS232/485 mode when
1527 * pciserial_resume_ports()
1529 port = serial8250_get_port(priv->line[i]);
1530 pci_fintek_rs485_config(&port->port, NULL);
1532 /* First init without port data
1533 * force init to RS232 Mode
1535 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1542 static int skip_tx_en_setup(struct serial_private *priv,
1543 const struct pciserial_board *board,
1544 struct uart_8250_port *port, int idx)
1546 port->port.flags |= UPF_NO_TXEN_TEST;
1547 dev_dbg(&priv->dev->dev,
1548 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1549 priv->dev->vendor, priv->dev->device,
1550 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1552 return pci_default_setup(priv, board, port, idx);
1555 static void kt_handle_break(struct uart_port *p)
1557 struct uart_8250_port *up = up_to_u8250p(p);
1559 * On receipt of a BI, serial device in Intel ME (Intel
1560 * management engine) needs to have its fifos cleared for sane
1561 * SOL (Serial Over Lan) output.
1563 serial8250_clear_and_reinit_fifos(up);
1566 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1568 struct uart_8250_port *up = up_to_u8250p(p);
1572 * When the Intel ME (management engine) gets reset its serial
1573 * port registers could return 0 momentarily. Functions like
1574 * serial8250_console_write, read and save the IER, perform
1575 * some operation and then restore it. In order to avoid
1576 * setting IER register inadvertently to 0, if the value read
1577 * is 0, double check with ier value in uart_8250_port and use
1578 * that instead. up->ier should be the same value as what is
1579 * currently configured.
1581 val = inb(p->iobase + offset);
1582 if (offset == UART_IER) {
1589 static int kt_serial_setup(struct serial_private *priv,
1590 const struct pciserial_board *board,
1591 struct uart_8250_port *port, int idx)
1593 port->port.flags |= UPF_BUG_THRE;
1594 port->port.serial_in = kt_serial_in;
1595 port->port.handle_break = kt_handle_break;
1596 return skip_tx_en_setup(priv, board, port, idx);
1599 static int pci_eg20t_init(struct pci_dev *dev)
1601 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1608 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1609 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1611 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
1612 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
1613 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
1614 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
1615 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
1616 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
1617 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
1618 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
1619 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
1620 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
1621 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
1622 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
1625 pci_xr17c154_setup(struct serial_private *priv,
1626 const struct pciserial_board *board,
1627 struct uart_8250_port *port, int idx)
1629 port->port.flags |= UPF_EXAR_EFR;
1630 return pci_default_setup(priv, board, port, idx);
1634 xr17v35x_has_slave(struct serial_private *priv)
1636 const int dev_id = priv->dev->device;
1638 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1639 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1643 pci_xr17v35x_setup(struct serial_private *priv,
1644 const struct pciserial_board *board,
1645 struct uart_8250_port *port, int idx)
1649 p = pci_ioremap_bar(priv->dev, 0);
1653 port->port.flags |= UPF_EXAR_EFR;
1656 * Setup the uart clock for the devices on expansion slot to
1657 * half the clock speed of the main chip (which is 125MHz)
1659 if (xr17v35x_has_slave(priv) && idx >= 8)
1660 port->port.uartclk = (7812500 * 16 / 2);
1663 * Setup Multipurpose Input/Output pins.
1666 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
1667 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
1668 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
1669 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
1670 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
1671 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
1672 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
1673 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
1674 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
1675 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
1676 writeb(0x00, p + UART_EXAR_MPIOSEL_15_8);
1677 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
1679 writeb(0x00, p + UART_EXAR_8XMODE);
1680 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1681 writeb(128, p + UART_EXAR_TXTRG);
1682 writeb(128, p + UART_EXAR_RXTRG);
1685 return pci_default_setup(priv, board, port, idx);
1688 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1689 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1690 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1691 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1694 pci_fastcom335_setup(struct serial_private *priv,
1695 const struct pciserial_board *board,
1696 struct uart_8250_port *port, int idx)
1700 p = pci_ioremap_bar(priv->dev, 0);
1704 port->port.flags |= UPF_EXAR_EFR;
1707 * Setup Multipurpose Input/Output pins.
1710 switch (priv->dev->device) {
1711 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1712 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1713 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
1714 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
1715 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
1717 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1718 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1719 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
1720 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
1721 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
1724 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
1725 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
1726 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
1728 writeb(0x00, p + UART_EXAR_8XMODE);
1729 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1730 writeb(32, p + UART_EXAR_TXTRG);
1731 writeb(32, p + UART_EXAR_RXTRG);
1734 return pci_default_setup(priv, board, port, idx);
1738 pci_wch_ch353_setup(struct serial_private *priv,
1739 const struct pciserial_board *board,
1740 struct uart_8250_port *port, int idx)
1742 port->port.flags |= UPF_FIXED_TYPE;
1743 port->port.type = PORT_16550A;
1744 return pci_default_setup(priv, board, port, idx);
1748 pci_wch_ch355_setup(struct serial_private *priv,
1749 const struct pciserial_board *board,
1750 struct uart_8250_port *port, int idx)
1752 port->port.flags |= UPF_FIXED_TYPE;
1753 port->port.type = PORT_16550A;
1754 return pci_default_setup(priv, board, port, idx);
1758 pci_wch_ch38x_setup(struct serial_private *priv,
1759 const struct pciserial_board *board,
1760 struct uart_8250_port *port, int idx)
1762 port->port.flags |= UPF_FIXED_TYPE;
1763 port->port.type = PORT_16850;
1764 return pci_default_setup(priv, board, port, idx);
1767 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1768 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1769 #define PCI_DEVICE_ID_OCTPRO 0x0001
1770 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1771 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1772 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1773 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1774 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1775 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1776 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1777 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1778 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1779 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1780 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1781 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1782 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1783 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1784 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1785 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1786 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1787 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1788 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1789 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1790 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1791 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1792 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1793 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1794 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1795 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1796 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1797 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1798 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1799 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1800 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1801 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1802 #define PCI_VENDOR_ID_WCH 0x4348
1803 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1804 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1805 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1806 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1807 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1808 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1809 #define PCI_VENDOR_ID_AGESTAR 0x5372
1810 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1811 #define PCI_VENDOR_ID_ASIX 0x9710
1812 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1813 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1814 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1815 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1816 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1818 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1819 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1821 #define PCIE_VENDOR_ID_WCH 0x1c00
1822 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1823 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1824 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1826 #define PCI_VENDOR_ID_PERICOM 0x12D8
1827 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1828 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1829 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1830 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1832 #define PCI_VENDOR_ID_ACCESIO 0x494f
1833 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1834 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1835 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1836 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1837 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1838 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1839 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1840 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1841 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1842 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1843 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1844 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1845 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1846 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1847 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1848 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1849 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1850 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1851 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1852 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1853 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1854 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1855 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1856 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1857 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1858 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1859 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1860 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1861 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1862 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1863 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1864 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1865 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1869 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1870 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1871 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1874 * Master list of serial port init/setup/exit quirks.
1875 * This does not describe the general nature of the port.
1876 * (ie, baud base, number and location of ports, etc)
1878 * This list is ordered alphabetically by vendor then device.
1879 * Specific entries must come before more generic entries.
1881 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1883 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1886 .vendor = PCI_VENDOR_ID_AMCC,
1887 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1888 .subvendor = PCI_ANY_ID,
1889 .subdevice = PCI_ANY_ID,
1890 .setup = addidata_apci7800_setup,
1893 * AFAVLAB cards - these may be called via parport_serial
1894 * It is not clear whether this applies to all products.
1897 .vendor = PCI_VENDOR_ID_AFAVLAB,
1898 .device = PCI_ANY_ID,
1899 .subvendor = PCI_ANY_ID,
1900 .subdevice = PCI_ANY_ID,
1901 .setup = afavlab_setup,
1907 .vendor = PCI_VENDOR_ID_HP,
1908 .device = PCI_DEVICE_ID_HP_DIVA,
1909 .subvendor = PCI_ANY_ID,
1910 .subdevice = PCI_ANY_ID,
1911 .init = pci_hp_diva_init,
1912 .setup = pci_hp_diva_setup,
1918 .vendor = PCI_VENDOR_ID_INTEL,
1919 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1920 .subvendor = 0xe4bf,
1921 .subdevice = PCI_ANY_ID,
1922 .init = pci_inteli960ni_init,
1923 .setup = pci_default_setup,
1926 .vendor = PCI_VENDOR_ID_INTEL,
1927 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1928 .subvendor = PCI_ANY_ID,
1929 .subdevice = PCI_ANY_ID,
1930 .setup = skip_tx_en_setup,
1933 .vendor = PCI_VENDOR_ID_INTEL,
1934 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1935 .subvendor = PCI_ANY_ID,
1936 .subdevice = PCI_ANY_ID,
1937 .setup = skip_tx_en_setup,
1940 .vendor = PCI_VENDOR_ID_INTEL,
1941 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1942 .subvendor = PCI_ANY_ID,
1943 .subdevice = PCI_ANY_ID,
1944 .setup = skip_tx_en_setup,
1947 .vendor = PCI_VENDOR_ID_INTEL,
1948 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1949 .subvendor = PCI_ANY_ID,
1950 .subdevice = PCI_ANY_ID,
1951 .setup = ce4100_serial_setup,
1954 .vendor = PCI_VENDOR_ID_INTEL,
1955 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1956 .subvendor = PCI_ANY_ID,
1957 .subdevice = PCI_ANY_ID,
1958 .setup = kt_serial_setup,
1964 .vendor = PCI_VENDOR_ID_ITE,
1965 .device = PCI_DEVICE_ID_ITE_8872,
1966 .subvendor = PCI_ANY_ID,
1967 .subdevice = PCI_ANY_ID,
1968 .init = pci_ite887x_init,
1969 .setup = pci_default_setup,
1970 .exit = pci_ite887x_exit,
1973 * National Instruments
1976 .vendor = PCI_VENDOR_ID_NI,
1977 .device = PCI_DEVICE_ID_NI_PCI23216,
1978 .subvendor = PCI_ANY_ID,
1979 .subdevice = PCI_ANY_ID,
1980 .init = pci_ni8420_init,
1981 .setup = pci_default_setup,
1982 .exit = pci_ni8420_exit,
1985 .vendor = PCI_VENDOR_ID_NI,
1986 .device = PCI_DEVICE_ID_NI_PCI2328,
1987 .subvendor = PCI_ANY_ID,
1988 .subdevice = PCI_ANY_ID,
1989 .init = pci_ni8420_init,
1990 .setup = pci_default_setup,
1991 .exit = pci_ni8420_exit,
1994 .vendor = PCI_VENDOR_ID_NI,
1995 .device = PCI_DEVICE_ID_NI_PCI2324,
1996 .subvendor = PCI_ANY_ID,
1997 .subdevice = PCI_ANY_ID,
1998 .init = pci_ni8420_init,
1999 .setup = pci_default_setup,
2000 .exit = pci_ni8420_exit,
2003 .vendor = PCI_VENDOR_ID_NI,
2004 .device = PCI_DEVICE_ID_NI_PCI2322,
2005 .subvendor = PCI_ANY_ID,
2006 .subdevice = PCI_ANY_ID,
2007 .init = pci_ni8420_init,
2008 .setup = pci_default_setup,
2009 .exit = pci_ni8420_exit,
2012 .vendor = PCI_VENDOR_ID_NI,
2013 .device = PCI_DEVICE_ID_NI_PCI2324I,
2014 .subvendor = PCI_ANY_ID,
2015 .subdevice = PCI_ANY_ID,
2016 .init = pci_ni8420_init,
2017 .setup = pci_default_setup,
2018 .exit = pci_ni8420_exit,
2021 .vendor = PCI_VENDOR_ID_NI,
2022 .device = PCI_DEVICE_ID_NI_PCI2322I,
2023 .subvendor = PCI_ANY_ID,
2024 .subdevice = PCI_ANY_ID,
2025 .init = pci_ni8420_init,
2026 .setup = pci_default_setup,
2027 .exit = pci_ni8420_exit,
2030 .vendor = PCI_VENDOR_ID_NI,
2031 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2032 .subvendor = PCI_ANY_ID,
2033 .subdevice = PCI_ANY_ID,
2034 .init = pci_ni8420_init,
2035 .setup = pci_default_setup,
2036 .exit = pci_ni8420_exit,
2039 .vendor = PCI_VENDOR_ID_NI,
2040 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2041 .subvendor = PCI_ANY_ID,
2042 .subdevice = PCI_ANY_ID,
2043 .init = pci_ni8420_init,
2044 .setup = pci_default_setup,
2045 .exit = pci_ni8420_exit,
2048 .vendor = PCI_VENDOR_ID_NI,
2049 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2050 .subvendor = PCI_ANY_ID,
2051 .subdevice = PCI_ANY_ID,
2052 .init = pci_ni8420_init,
2053 .setup = pci_default_setup,
2054 .exit = pci_ni8420_exit,
2057 .vendor = PCI_VENDOR_ID_NI,
2058 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2059 .subvendor = PCI_ANY_ID,
2060 .subdevice = PCI_ANY_ID,
2061 .init = pci_ni8420_init,
2062 .setup = pci_default_setup,
2063 .exit = pci_ni8420_exit,
2066 .vendor = PCI_VENDOR_ID_NI,
2067 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2068 .subvendor = PCI_ANY_ID,
2069 .subdevice = PCI_ANY_ID,
2070 .init = pci_ni8420_init,
2071 .setup = pci_default_setup,
2072 .exit = pci_ni8420_exit,
2075 .vendor = PCI_VENDOR_ID_NI,
2076 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2077 .subvendor = PCI_ANY_ID,
2078 .subdevice = PCI_ANY_ID,
2079 .init = pci_ni8420_init,
2080 .setup = pci_default_setup,
2081 .exit = pci_ni8420_exit,
2084 .vendor = PCI_VENDOR_ID_NI,
2085 .device = PCI_ANY_ID,
2086 .subvendor = PCI_ANY_ID,
2087 .subdevice = PCI_ANY_ID,
2088 .init = pci_ni8430_init,
2089 .setup = pci_ni8430_setup,
2090 .exit = pci_ni8430_exit,
2094 .vendor = PCI_VENDOR_ID_QUATECH,
2095 .device = PCI_ANY_ID,
2096 .subvendor = PCI_ANY_ID,
2097 .subdevice = PCI_ANY_ID,
2098 .init = pci_quatech_init,
2099 .setup = pci_quatech_setup,
2100 .exit = pci_quatech_exit,
2106 .vendor = PCI_VENDOR_ID_PANACOM,
2107 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2108 .subvendor = PCI_ANY_ID,
2109 .subdevice = PCI_ANY_ID,
2110 .init = pci_plx9050_init,
2111 .setup = pci_default_setup,
2112 .exit = pci_plx9050_exit,
2115 .vendor = PCI_VENDOR_ID_PANACOM,
2116 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2117 .subvendor = PCI_ANY_ID,
2118 .subdevice = PCI_ANY_ID,
2119 .init = pci_plx9050_init,
2120 .setup = pci_default_setup,
2121 .exit = pci_plx9050_exit,
2124 * Pericom (Only 7954 - It have a offset jump for port 4)
2127 .vendor = PCI_VENDOR_ID_PERICOM,
2128 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2129 .subvendor = PCI_ANY_ID,
2130 .subdevice = PCI_ANY_ID,
2131 .setup = pci_pericom_setup,
2137 .vendor = PCI_VENDOR_ID_PLX,
2138 .device = PCI_DEVICE_ID_PLX_9050,
2139 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2140 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2141 .init = pci_plx9050_init,
2142 .setup = pci_default_setup,
2143 .exit = pci_plx9050_exit,
2146 .vendor = PCI_VENDOR_ID_PLX,
2147 .device = PCI_DEVICE_ID_PLX_9050,
2148 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2149 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2150 .init = pci_plx9050_init,
2151 .setup = pci_default_setup,
2152 .exit = pci_plx9050_exit,
2155 .vendor = PCI_VENDOR_ID_PLX,
2156 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2157 .subvendor = PCI_VENDOR_ID_PLX,
2158 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2159 .init = pci_plx9050_init,
2160 .setup = pci_default_setup,
2161 .exit = pci_plx9050_exit,
2164 .vendor = PCI_VENDOR_ID_ACCESIO,
2165 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2166 .subvendor = PCI_ANY_ID,
2167 .subdevice = PCI_ANY_ID,
2168 .setup = pci_pericom_setup,
2171 .vendor = PCI_VENDOR_ID_ACCESIO,
2172 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2173 .subvendor = PCI_ANY_ID,
2174 .subdevice = PCI_ANY_ID,
2175 .setup = pci_pericom_setup,
2178 .vendor = PCI_VENDOR_ID_ACCESIO,
2179 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2180 .subvendor = PCI_ANY_ID,
2181 .subdevice = PCI_ANY_ID,
2182 .setup = pci_pericom_setup,
2185 .vendor = PCI_VENDOR_ID_ACCESIO,
2186 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2187 .subvendor = PCI_ANY_ID,
2188 .subdevice = PCI_ANY_ID,
2189 .setup = pci_pericom_setup,
2192 .vendor = PCI_VENDOR_ID_ACCESIO,
2193 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .setup = pci_pericom_setup,
2199 .vendor = PCI_VENDOR_ID_ACCESIO,
2200 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .setup = pci_pericom_setup,
2206 .vendor = PCI_VENDOR_ID_ACCESIO,
2207 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2208 .subvendor = PCI_ANY_ID,
2209 .subdevice = PCI_ANY_ID,
2210 .setup = pci_pericom_setup,
2213 .vendor = PCI_VENDOR_ID_ACCESIO,
2214 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2215 .subvendor = PCI_ANY_ID,
2216 .subdevice = PCI_ANY_ID,
2217 .setup = pci_pericom_setup,
2220 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2221 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2222 .subvendor = PCI_ANY_ID,
2223 .subdevice = PCI_ANY_ID,
2224 .setup = pci_pericom_setup,
2227 .vendor = PCI_VENDOR_ID_ACCESIO,
2228 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2229 .subvendor = PCI_ANY_ID,
2230 .subdevice = PCI_ANY_ID,
2231 .setup = pci_pericom_setup,
2234 .vendor = PCI_VENDOR_ID_ACCESIO,
2235 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2236 .subvendor = PCI_ANY_ID,
2237 .subdevice = PCI_ANY_ID,
2238 .setup = pci_pericom_setup,
2241 .vendor = PCI_VENDOR_ID_ACCESIO,
2242 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2243 .subvendor = PCI_ANY_ID,
2244 .subdevice = PCI_ANY_ID,
2245 .setup = pci_pericom_setup,
2248 .vendor = PCI_VENDOR_ID_ACCESIO,
2249 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2250 .subvendor = PCI_ANY_ID,
2251 .subdevice = PCI_ANY_ID,
2252 .setup = pci_pericom_setup,
2255 .vendor = PCI_VENDOR_ID_ACCESIO,
2256 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2257 .subvendor = PCI_ANY_ID,
2258 .subdevice = PCI_ANY_ID,
2259 .setup = pci_pericom_setup,
2262 .vendor = PCI_VENDOR_ID_ACCESIO,
2263 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2264 .subvendor = PCI_ANY_ID,
2265 .subdevice = PCI_ANY_ID,
2266 .setup = pci_pericom_setup,
2269 * SBS Technologies, Inc., PMC-OCTALPRO 232
2272 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2273 .device = PCI_DEVICE_ID_OCTPRO,
2274 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2275 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2281 * SBS Technologies, Inc., PMC-OCTALPRO 422
2284 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2285 .device = PCI_DEVICE_ID_OCTPRO,
2286 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2287 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2293 * SBS Technologies, Inc., P-Octal 232
2296 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2297 .device = PCI_DEVICE_ID_OCTPRO,
2298 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2299 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2305 * SBS Technologies, Inc., P-Octal 422
2308 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2309 .device = PCI_DEVICE_ID_OCTPRO,
2310 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2311 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2317 * SIIG cards - these may be called via parport_serial
2320 .vendor = PCI_VENDOR_ID_SIIG,
2321 .device = PCI_ANY_ID,
2322 .subvendor = PCI_ANY_ID,
2323 .subdevice = PCI_ANY_ID,
2324 .init = pci_siig_init,
2325 .setup = pci_siig_setup,
2331 .vendor = PCI_VENDOR_ID_TITAN,
2332 .device = PCI_DEVICE_ID_TITAN_400L,
2333 .subvendor = PCI_ANY_ID,
2334 .subdevice = PCI_ANY_ID,
2335 .setup = titan_400l_800l_setup,
2338 .vendor = PCI_VENDOR_ID_TITAN,
2339 .device = PCI_DEVICE_ID_TITAN_800L,
2340 .subvendor = PCI_ANY_ID,
2341 .subdevice = PCI_ANY_ID,
2342 .setup = titan_400l_800l_setup,
2348 .vendor = PCI_VENDOR_ID_TIMEDIA,
2349 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2350 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2351 .subdevice = PCI_ANY_ID,
2352 .probe = pci_timedia_probe,
2353 .init = pci_timedia_init,
2354 .setup = pci_timedia_setup,
2357 .vendor = PCI_VENDOR_ID_TIMEDIA,
2358 .device = PCI_ANY_ID,
2359 .subvendor = PCI_ANY_ID,
2360 .subdevice = PCI_ANY_ID,
2361 .setup = pci_timedia_setup,
2364 * SUNIX (Timedia) cards
2365 * Do not "probe" for these cards as there is at least one combination
2366 * card that should be handled by parport_pc that doesn't match the
2367 * rule in pci_timedia_probe.
2368 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2369 * There are some boards with part number SER5037AL that report
2370 * subdevice ID 0x0002.
2373 .vendor = PCI_VENDOR_ID_SUNIX,
2374 .device = PCI_DEVICE_ID_SUNIX_1999,
2375 .subvendor = PCI_VENDOR_ID_SUNIX,
2376 .subdevice = PCI_ANY_ID,
2377 .init = pci_timedia_init,
2378 .setup = pci_timedia_setup,
2384 .vendor = PCI_VENDOR_ID_EXAR,
2385 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2386 .subvendor = PCI_ANY_ID,
2387 .subdevice = PCI_ANY_ID,
2388 .setup = pci_xr17c154_setup,
2391 .vendor = PCI_VENDOR_ID_EXAR,
2392 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2393 .subvendor = PCI_ANY_ID,
2394 .subdevice = PCI_ANY_ID,
2395 .setup = pci_xr17c154_setup,
2398 .vendor = PCI_VENDOR_ID_EXAR,
2399 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2400 .subvendor = PCI_ANY_ID,
2401 .subdevice = PCI_ANY_ID,
2402 .setup = pci_xr17c154_setup,
2405 .vendor = PCI_VENDOR_ID_EXAR,
2406 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2407 .subvendor = PCI_ANY_ID,
2408 .subdevice = PCI_ANY_ID,
2409 .setup = pci_xr17v35x_setup,
2412 .vendor = PCI_VENDOR_ID_EXAR,
2413 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2414 .subvendor = PCI_ANY_ID,
2415 .subdevice = PCI_ANY_ID,
2416 .setup = pci_xr17v35x_setup,
2419 .vendor = PCI_VENDOR_ID_EXAR,
2420 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2421 .subvendor = PCI_ANY_ID,
2422 .subdevice = PCI_ANY_ID,
2423 .setup = pci_xr17v35x_setup,
2426 .vendor = PCI_VENDOR_ID_EXAR,
2427 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2428 .subvendor = PCI_ANY_ID,
2429 .subdevice = PCI_ANY_ID,
2430 .setup = pci_xr17v35x_setup,
2433 .vendor = PCI_VENDOR_ID_EXAR,
2434 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2435 .subvendor = PCI_ANY_ID,
2436 .subdevice = PCI_ANY_ID,
2437 .setup = pci_xr17v35x_setup,
2443 .vendor = PCI_VENDOR_ID_XIRCOM,
2444 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2445 .subvendor = PCI_ANY_ID,
2446 .subdevice = PCI_ANY_ID,
2447 .init = pci_xircom_init,
2448 .setup = pci_default_setup,
2451 * Netmos cards - these may be called via parport_serial
2454 .vendor = PCI_VENDOR_ID_NETMOS,
2455 .device = PCI_ANY_ID,
2456 .subvendor = PCI_ANY_ID,
2457 .subdevice = PCI_ANY_ID,
2458 .init = pci_netmos_init,
2459 .setup = pci_netmos_9900_setup,
2462 * EndRun Technologies
2465 .vendor = PCI_VENDOR_ID_ENDRUN,
2466 .device = PCI_ANY_ID,
2467 .subvendor = PCI_ANY_ID,
2468 .subdevice = PCI_ANY_ID,
2469 .init = pci_endrun_init,
2470 .setup = pci_default_setup,
2473 * For Oxford Semiconductor Tornado based devices
2476 .vendor = PCI_VENDOR_ID_OXSEMI,
2477 .device = PCI_ANY_ID,
2478 .subvendor = PCI_ANY_ID,
2479 .subdevice = PCI_ANY_ID,
2480 .init = pci_oxsemi_tornado_init,
2481 .setup = pci_default_setup,
2484 .vendor = PCI_VENDOR_ID_MAINPINE,
2485 .device = PCI_ANY_ID,
2486 .subvendor = PCI_ANY_ID,
2487 .subdevice = PCI_ANY_ID,
2488 .init = pci_oxsemi_tornado_init,
2489 .setup = pci_default_setup,
2492 .vendor = PCI_VENDOR_ID_DIGI,
2493 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2494 .subvendor = PCI_SUBVENDOR_ID_IBM,
2495 .subdevice = PCI_ANY_ID,
2496 .init = pci_oxsemi_tornado_init,
2497 .setup = pci_default_setup,
2500 .vendor = PCI_VENDOR_ID_INTEL,
2502 .subvendor = PCI_ANY_ID,
2503 .subdevice = PCI_ANY_ID,
2504 .init = pci_eg20t_init,
2505 .setup = pci_default_setup,
2508 .vendor = PCI_VENDOR_ID_INTEL,
2510 .subvendor = PCI_ANY_ID,
2511 .subdevice = PCI_ANY_ID,
2512 .init = pci_eg20t_init,
2513 .setup = pci_default_setup,
2516 .vendor = PCI_VENDOR_ID_INTEL,
2518 .subvendor = PCI_ANY_ID,
2519 .subdevice = PCI_ANY_ID,
2520 .init = pci_eg20t_init,
2521 .setup = pci_default_setup,
2524 .vendor = PCI_VENDOR_ID_INTEL,
2526 .subvendor = PCI_ANY_ID,
2527 .subdevice = PCI_ANY_ID,
2528 .init = pci_eg20t_init,
2529 .setup = pci_default_setup,
2534 .subvendor = PCI_ANY_ID,
2535 .subdevice = PCI_ANY_ID,
2536 .init = pci_eg20t_init,
2537 .setup = pci_default_setup,
2542 .subvendor = PCI_ANY_ID,
2543 .subdevice = PCI_ANY_ID,
2544 .init = pci_eg20t_init,
2545 .setup = pci_default_setup,
2550 .subvendor = PCI_ANY_ID,
2551 .subdevice = PCI_ANY_ID,
2552 .init = pci_eg20t_init,
2553 .setup = pci_default_setup,
2558 .subvendor = PCI_ANY_ID,
2559 .subdevice = PCI_ANY_ID,
2560 .init = pci_eg20t_init,
2561 .setup = pci_default_setup,
2566 .subvendor = PCI_ANY_ID,
2567 .subdevice = PCI_ANY_ID,
2568 .init = pci_eg20t_init,
2569 .setup = pci_default_setup,
2572 * Cronyx Omega PCI (PLX-chip based)
2575 .vendor = PCI_VENDOR_ID_PLX,
2576 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2577 .subvendor = PCI_ANY_ID,
2578 .subdevice = PCI_ANY_ID,
2579 .setup = pci_omegapci_setup,
2581 /* WCH CH353 1S1P card (16550 clone) */
2583 .vendor = PCI_VENDOR_ID_WCH,
2584 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2585 .subvendor = PCI_ANY_ID,
2586 .subdevice = PCI_ANY_ID,
2587 .setup = pci_wch_ch353_setup,
2589 /* WCH CH353 2S1P card (16550 clone) */
2591 .vendor = PCI_VENDOR_ID_WCH,
2592 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2593 .subvendor = PCI_ANY_ID,
2594 .subdevice = PCI_ANY_ID,
2595 .setup = pci_wch_ch353_setup,
2597 /* WCH CH353 4S card (16550 clone) */
2599 .vendor = PCI_VENDOR_ID_WCH,
2600 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2601 .subvendor = PCI_ANY_ID,
2602 .subdevice = PCI_ANY_ID,
2603 .setup = pci_wch_ch353_setup,
2605 /* WCH CH353 2S1PF card (16550 clone) */
2607 .vendor = PCI_VENDOR_ID_WCH,
2608 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2609 .subvendor = PCI_ANY_ID,
2610 .subdevice = PCI_ANY_ID,
2611 .setup = pci_wch_ch353_setup,
2613 /* WCH CH352 2S card (16550 clone) */
2615 .vendor = PCI_VENDOR_ID_WCH,
2616 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2617 .subvendor = PCI_ANY_ID,
2618 .subdevice = PCI_ANY_ID,
2619 .setup = pci_wch_ch353_setup,
2621 /* WCH CH355 4S card (16550 clone) */
2623 .vendor = PCI_VENDOR_ID_WCH,
2624 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2625 .subvendor = PCI_ANY_ID,
2626 .subdevice = PCI_ANY_ID,
2627 .setup = pci_wch_ch355_setup,
2629 /* WCH CH382 2S card (16850 clone) */
2631 .vendor = PCIE_VENDOR_ID_WCH,
2632 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2633 .subvendor = PCI_ANY_ID,
2634 .subdevice = PCI_ANY_ID,
2635 .setup = pci_wch_ch38x_setup,
2637 /* WCH CH382 2S1P card (16850 clone) */
2639 .vendor = PCIE_VENDOR_ID_WCH,
2640 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2641 .subvendor = PCI_ANY_ID,
2642 .subdevice = PCI_ANY_ID,
2643 .setup = pci_wch_ch38x_setup,
2645 /* WCH CH384 4S card (16850 clone) */
2647 .vendor = PCIE_VENDOR_ID_WCH,
2648 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2649 .subvendor = PCI_ANY_ID,
2650 .subdevice = PCI_ANY_ID,
2651 .setup = pci_wch_ch38x_setup,
2654 * ASIX devices with FIFO bug
2657 .vendor = PCI_VENDOR_ID_ASIX,
2658 .device = PCI_ANY_ID,
2659 .subvendor = PCI_ANY_ID,
2660 .subdevice = PCI_ANY_ID,
2661 .setup = pci_asix_setup,
2664 * Commtech, Inc. Fastcom adapters
2668 .vendor = PCI_VENDOR_ID_COMMTECH,
2669 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2670 .subvendor = PCI_ANY_ID,
2671 .subdevice = PCI_ANY_ID,
2672 .setup = pci_fastcom335_setup,
2675 .vendor = PCI_VENDOR_ID_COMMTECH,
2676 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2677 .subvendor = PCI_ANY_ID,
2678 .subdevice = PCI_ANY_ID,
2679 .setup = pci_fastcom335_setup,
2682 .vendor = PCI_VENDOR_ID_COMMTECH,
2683 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2684 .subvendor = PCI_ANY_ID,
2685 .subdevice = PCI_ANY_ID,
2686 .setup = pci_fastcom335_setup,
2689 .vendor = PCI_VENDOR_ID_COMMTECH,
2690 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2691 .subvendor = PCI_ANY_ID,
2692 .subdevice = PCI_ANY_ID,
2693 .setup = pci_fastcom335_setup,
2696 .vendor = PCI_VENDOR_ID_COMMTECH,
2697 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2698 .subvendor = PCI_ANY_ID,
2699 .subdevice = PCI_ANY_ID,
2700 .setup = pci_xr17v35x_setup,
2703 .vendor = PCI_VENDOR_ID_COMMTECH,
2704 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2705 .subvendor = PCI_ANY_ID,
2706 .subdevice = PCI_ANY_ID,
2707 .setup = pci_xr17v35x_setup,
2710 .vendor = PCI_VENDOR_ID_COMMTECH,
2711 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2712 .subvendor = PCI_ANY_ID,
2713 .subdevice = PCI_ANY_ID,
2714 .setup = pci_xr17v35x_setup,
2717 * Broadcom TruManage (NetXtreme)
2720 .vendor = PCI_VENDOR_ID_BROADCOM,
2721 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2722 .subvendor = PCI_ANY_ID,
2723 .subdevice = PCI_ANY_ID,
2724 .setup = pci_brcm_trumanage_setup,
2729 .subvendor = PCI_ANY_ID,
2730 .subdevice = PCI_ANY_ID,
2731 .setup = pci_fintek_setup,
2732 .init = pci_fintek_init,
2737 .subvendor = PCI_ANY_ID,
2738 .subdevice = PCI_ANY_ID,
2739 .setup = pci_fintek_setup,
2740 .init = pci_fintek_init,
2745 .subvendor = PCI_ANY_ID,
2746 .subdevice = PCI_ANY_ID,
2747 .setup = pci_fintek_setup,
2748 .init = pci_fintek_init,
2752 * Default "match everything" terminator entry
2755 .vendor = PCI_ANY_ID,
2756 .device = PCI_ANY_ID,
2757 .subvendor = PCI_ANY_ID,
2758 .subdevice = PCI_ANY_ID,
2759 .setup = pci_default_setup,
2763 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2765 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2768 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2770 struct pci_serial_quirk *quirk;
2772 for (quirk = pci_serial_quirks; ; quirk++)
2773 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2774 quirk_id_matches(quirk->device, dev->device) &&
2775 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2776 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2781 static inline int get_pci_irq(struct pci_dev *dev,
2782 const struct pciserial_board *board)
2784 if (board->flags & FL_NOIRQ)
2791 * This is the configuration table for all of the PCI serial boards
2792 * which we support. It is directly indexed by the pci_board_num_t enum
2793 * value, which is encoded in the pci_device_id PCI probe table's
2794 * driver_data member.
2796 * The makeup of these names are:
2797 * pbn_bn{_bt}_n_baud{_offsetinhex}
2799 * bn = PCI BAR number
2800 * bt = Index using PCI BARs
2801 * n = number of serial ports
2803 * offsetinhex = offset for each sequential port (in hex)
2805 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2807 * Please note: in theory if n = 1, _bt infix should make no difference.
2808 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2810 enum pci_board_num_t {
2827 pbn_b0_2_1152000_200,
2828 pbn_b0_4_1152000_200,
2829 pbn_b0_8_1152000_200,
2836 pbn_b0_2_1843200_200,
2837 pbn_b0_4_1843200_200,
2838 pbn_b0_8_1843200_200,
2912 * Board-specific versions.
2918 pbn_endrun_2_3906250,
2920 pbn_oxsemi_1_4000000,
2921 pbn_oxsemi_2_4000000,
2922 pbn_oxsemi_4_4000000,
2923 pbn_oxsemi_8_4000000,
2938 pbn_exar_ibm_saturn,
2944 pbn_ADDIDATA_PCIe_1_3906250,
2945 pbn_ADDIDATA_PCIe_2_3906250,
2946 pbn_ADDIDATA_PCIe_4_3906250,
2947 pbn_ADDIDATA_PCIe_8_3906250,
2948 pbn_ce4100_1_115200,
2950 pbn_NETMOS9900_2s_115200,
2957 pbn_pericom_PI7C9X7951,
2958 pbn_pericom_PI7C9X7952,
2959 pbn_pericom_PI7C9X7954,
2960 pbn_pericom_PI7C9X7958,
2964 * uart_offset - the space between channels
2965 * reg_shift - describes how the UART registers are mapped
2966 * to PCI memory by the card.
2967 * For example IER register on SBS, Inc. PMC-OctPro is located at
2968 * offset 0x10 from the UART base, while UART_IER is defined as 1
2969 * in include/linux/serial_reg.h,
2970 * see first lines of serial_in() and serial_out() in 8250.c
2973 static struct pciserial_board pci_boards[] = {
2977 .base_baud = 115200,
2980 [pbn_b0_1_115200] = {
2983 .base_baud = 115200,
2986 [pbn_b0_2_115200] = {
2989 .base_baud = 115200,
2992 [pbn_b0_4_115200] = {
2995 .base_baud = 115200,
2998 [pbn_b0_5_115200] = {
3001 .base_baud = 115200,
3004 [pbn_b0_8_115200] = {
3007 .base_baud = 115200,
3010 [pbn_b0_1_921600] = {
3013 .base_baud = 921600,
3016 [pbn_b0_2_921600] = {
3019 .base_baud = 921600,
3022 [pbn_b0_4_921600] = {
3025 .base_baud = 921600,
3029 [pbn_b0_2_1130000] = {
3032 .base_baud = 1130000,
3036 [pbn_b0_4_1152000] = {
3039 .base_baud = 1152000,
3043 [pbn_b0_2_1152000_200] = {
3046 .base_baud = 1152000,
3047 .uart_offset = 0x200,
3050 [pbn_b0_4_1152000_200] = {
3053 .base_baud = 1152000,
3054 .uart_offset = 0x200,
3057 [pbn_b0_8_1152000_200] = {
3060 .base_baud = 1152000,
3061 .uart_offset = 0x200,
3064 [pbn_b0_4_1250000] = {
3067 .base_baud = 1250000,
3071 [pbn_b0_2_1843200] = {
3074 .base_baud = 1843200,
3077 [pbn_b0_4_1843200] = {
3080 .base_baud = 1843200,
3084 [pbn_b0_2_1843200_200] = {
3087 .base_baud = 1843200,
3088 .uart_offset = 0x200,
3090 [pbn_b0_4_1843200_200] = {
3093 .base_baud = 1843200,
3094 .uart_offset = 0x200,
3096 [pbn_b0_8_1843200_200] = {
3099 .base_baud = 1843200,
3100 .uart_offset = 0x200,
3102 [pbn_b0_1_4000000] = {
3105 .base_baud = 4000000,
3109 [pbn_b0_bt_1_115200] = {
3110 .flags = FL_BASE0|FL_BASE_BARS,
3112 .base_baud = 115200,
3115 [pbn_b0_bt_2_115200] = {
3116 .flags = FL_BASE0|FL_BASE_BARS,
3118 .base_baud = 115200,
3121 [pbn_b0_bt_4_115200] = {
3122 .flags = FL_BASE0|FL_BASE_BARS,
3124 .base_baud = 115200,
3127 [pbn_b0_bt_8_115200] = {
3128 .flags = FL_BASE0|FL_BASE_BARS,
3130 .base_baud = 115200,
3134 [pbn_b0_bt_1_460800] = {
3135 .flags = FL_BASE0|FL_BASE_BARS,
3137 .base_baud = 460800,
3140 [pbn_b0_bt_2_460800] = {
3141 .flags = FL_BASE0|FL_BASE_BARS,
3143 .base_baud = 460800,
3146 [pbn_b0_bt_4_460800] = {
3147 .flags = FL_BASE0|FL_BASE_BARS,
3149 .base_baud = 460800,
3153 [pbn_b0_bt_1_921600] = {
3154 .flags = FL_BASE0|FL_BASE_BARS,
3156 .base_baud = 921600,
3159 [pbn_b0_bt_2_921600] = {
3160 .flags = FL_BASE0|FL_BASE_BARS,
3162 .base_baud = 921600,
3165 [pbn_b0_bt_4_921600] = {
3166 .flags = FL_BASE0|FL_BASE_BARS,
3168 .base_baud = 921600,
3171 [pbn_b0_bt_8_921600] = {
3172 .flags = FL_BASE0|FL_BASE_BARS,
3174 .base_baud = 921600,
3178 [pbn_b1_1_115200] = {
3181 .base_baud = 115200,
3184 [pbn_b1_2_115200] = {
3187 .base_baud = 115200,
3190 [pbn_b1_4_115200] = {
3193 .base_baud = 115200,
3196 [pbn_b1_8_115200] = {
3199 .base_baud = 115200,
3202 [pbn_b1_16_115200] = {
3205 .base_baud = 115200,
3209 [pbn_b1_1_921600] = {
3212 .base_baud = 921600,
3215 [pbn_b1_2_921600] = {
3218 .base_baud = 921600,
3221 [pbn_b1_4_921600] = {
3224 .base_baud = 921600,
3227 [pbn_b1_8_921600] = {
3230 .base_baud = 921600,
3233 [pbn_b1_2_1250000] = {
3236 .base_baud = 1250000,
3240 [pbn_b1_bt_1_115200] = {
3241 .flags = FL_BASE1|FL_BASE_BARS,
3243 .base_baud = 115200,
3246 [pbn_b1_bt_2_115200] = {
3247 .flags = FL_BASE1|FL_BASE_BARS,
3249 .base_baud = 115200,
3252 [pbn_b1_bt_4_115200] = {
3253 .flags = FL_BASE1|FL_BASE_BARS,
3255 .base_baud = 115200,
3259 [pbn_b1_bt_2_921600] = {
3260 .flags = FL_BASE1|FL_BASE_BARS,
3262 .base_baud = 921600,
3266 [pbn_b1_1_1382400] = {
3269 .base_baud = 1382400,
3272 [pbn_b1_2_1382400] = {
3275 .base_baud = 1382400,
3278 [pbn_b1_4_1382400] = {
3281 .base_baud = 1382400,
3284 [pbn_b1_8_1382400] = {
3287 .base_baud = 1382400,
3291 [pbn_b2_1_115200] = {
3294 .base_baud = 115200,
3297 [pbn_b2_2_115200] = {
3300 .base_baud = 115200,
3303 [pbn_b2_4_115200] = {
3306 .base_baud = 115200,
3309 [pbn_b2_8_115200] = {
3312 .base_baud = 115200,
3316 [pbn_b2_1_460800] = {
3319 .base_baud = 460800,
3322 [pbn_b2_4_460800] = {
3325 .base_baud = 460800,
3328 [pbn_b2_8_460800] = {
3331 .base_baud = 460800,
3334 [pbn_b2_16_460800] = {
3337 .base_baud = 460800,
3341 [pbn_b2_1_921600] = {
3344 .base_baud = 921600,
3347 [pbn_b2_4_921600] = {
3350 .base_baud = 921600,
3353 [pbn_b2_8_921600] = {
3356 .base_baud = 921600,
3360 [pbn_b2_8_1152000] = {
3363 .base_baud = 1152000,
3367 [pbn_b2_bt_1_115200] = {
3368 .flags = FL_BASE2|FL_BASE_BARS,
3370 .base_baud = 115200,
3373 [pbn_b2_bt_2_115200] = {
3374 .flags = FL_BASE2|FL_BASE_BARS,
3376 .base_baud = 115200,
3379 [pbn_b2_bt_4_115200] = {
3380 .flags = FL_BASE2|FL_BASE_BARS,
3382 .base_baud = 115200,
3386 [pbn_b2_bt_2_921600] = {
3387 .flags = FL_BASE2|FL_BASE_BARS,
3389 .base_baud = 921600,
3392 [pbn_b2_bt_4_921600] = {
3393 .flags = FL_BASE2|FL_BASE_BARS,
3395 .base_baud = 921600,
3399 [pbn_b3_2_115200] = {
3402 .base_baud = 115200,
3405 [pbn_b3_4_115200] = {
3408 .base_baud = 115200,
3411 [pbn_b3_8_115200] = {
3414 .base_baud = 115200,
3418 [pbn_b4_bt_2_921600] = {
3421 .base_baud = 921600,
3424 [pbn_b4_bt_4_921600] = {
3427 .base_baud = 921600,
3430 [pbn_b4_bt_8_921600] = {
3433 .base_baud = 921600,
3438 * Entries following this are board-specific.
3447 .base_baud = 921600,
3448 .uart_offset = 0x400,
3452 .flags = FL_BASE2|FL_BASE_BARS,
3454 .base_baud = 921600,
3455 .uart_offset = 0x400,
3459 .flags = FL_BASE2|FL_BASE_BARS,
3461 .base_baud = 921600,
3462 .uart_offset = 0x400,
3466 /* I think this entry is broken - the first_offset looks wrong --rmk */
3467 [pbn_plx_romulus] = {
3470 .base_baud = 921600,
3471 .uart_offset = 8 << 2,
3473 .first_offset = 0x03,
3477 * EndRun Technologies
3478 * Uses the size of PCI Base region 0 to
3479 * signal now many ports are available
3480 * 2 port 952 Uart support
3482 [pbn_endrun_2_3906250] = {
3485 .base_baud = 3906250,
3486 .uart_offset = 0x200,
3487 .first_offset = 0x1000,
3491 * This board uses the size of PCI Base region 0 to
3492 * signal now many ports are available
3495 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3497 .base_baud = 115200,
3500 [pbn_oxsemi_1_4000000] = {
3503 .base_baud = 4000000,
3504 .uart_offset = 0x200,
3505 .first_offset = 0x1000,
3507 [pbn_oxsemi_2_4000000] = {
3510 .base_baud = 4000000,
3511 .uart_offset = 0x200,
3512 .first_offset = 0x1000,
3514 [pbn_oxsemi_4_4000000] = {
3517 .base_baud = 4000000,
3518 .uart_offset = 0x200,
3519 .first_offset = 0x1000,
3521 [pbn_oxsemi_8_4000000] = {
3524 .base_baud = 4000000,
3525 .uart_offset = 0x200,
3526 .first_offset = 0x1000,
3531 * EKF addition for i960 Boards form EKF with serial port.
3534 [pbn_intel_i960] = {
3537 .base_baud = 921600,
3538 .uart_offset = 8 << 2,
3540 .first_offset = 0x10000,
3543 .flags = FL_BASE0|FL_NOIRQ,
3545 .base_baud = 458333,
3548 .first_offset = 0x20178,
3552 * Computone - uses IOMEM.
3554 [pbn_computone_4] = {
3557 .base_baud = 921600,
3558 .uart_offset = 0x40,
3560 .first_offset = 0x200,
3562 [pbn_computone_6] = {
3565 .base_baud = 921600,
3566 .uart_offset = 0x40,
3568 .first_offset = 0x200,
3570 [pbn_computone_8] = {
3573 .base_baud = 921600,
3574 .uart_offset = 0x40,
3576 .first_offset = 0x200,
3581 .base_baud = 460800,
3586 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3587 * Only basic 16550A support.
3588 * XR17C15[24] are not tested, but they should work.
3590 [pbn_exar_XR17C152] = {
3593 .base_baud = 921600,
3594 .uart_offset = 0x200,
3596 [pbn_exar_XR17C154] = {
3599 .base_baud = 921600,
3600 .uart_offset = 0x200,
3602 [pbn_exar_XR17C158] = {
3605 .base_baud = 921600,
3606 .uart_offset = 0x200,
3608 [pbn_exar_XR17V352] = {
3611 .base_baud = 7812500,
3612 .uart_offset = 0x400,
3616 [pbn_exar_XR17V354] = {
3619 .base_baud = 7812500,
3620 .uart_offset = 0x400,
3624 [pbn_exar_XR17V358] = {
3627 .base_baud = 7812500,
3628 .uart_offset = 0x400,
3632 [pbn_exar_XR17V4358] = {
3635 .base_baud = 7812500,
3636 .uart_offset = 0x400,
3640 [pbn_exar_XR17V8358] = {
3643 .base_baud = 7812500,
3644 .uart_offset = 0x400,
3648 [pbn_exar_ibm_saturn] = {
3651 .base_baud = 921600,
3652 .uart_offset = 0x200,
3656 * PA Semi PWRficient PA6T-1682M on-chip UART
3658 [pbn_pasemi_1682M] = {
3661 .base_baud = 8333333,
3664 * National Instruments 843x
3669 .base_baud = 3686400,
3670 .uart_offset = 0x10,
3671 .first_offset = 0x800,
3676 .base_baud = 3686400,
3677 .uart_offset = 0x10,
3678 .first_offset = 0x800,
3683 .base_baud = 3686400,
3684 .uart_offset = 0x10,
3685 .first_offset = 0x800,
3690 .base_baud = 3686400,
3691 .uart_offset = 0x10,
3692 .first_offset = 0x800,
3695 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3697 [pbn_ADDIDATA_PCIe_1_3906250] = {
3700 .base_baud = 3906250,
3701 .uart_offset = 0x200,
3702 .first_offset = 0x1000,
3704 [pbn_ADDIDATA_PCIe_2_3906250] = {
3707 .base_baud = 3906250,
3708 .uart_offset = 0x200,
3709 .first_offset = 0x1000,
3711 [pbn_ADDIDATA_PCIe_4_3906250] = {
3714 .base_baud = 3906250,
3715 .uart_offset = 0x200,
3716 .first_offset = 0x1000,
3718 [pbn_ADDIDATA_PCIe_8_3906250] = {
3721 .base_baud = 3906250,
3722 .uart_offset = 0x200,
3723 .first_offset = 0x1000,
3725 [pbn_ce4100_1_115200] = {
3726 .flags = FL_BASE_BARS,
3728 .base_baud = 921600,
3734 .base_baud = 115200,
3735 .uart_offset = 0x200,
3737 [pbn_NETMOS9900_2s_115200] = {
3740 .base_baud = 115200,
3742 [pbn_brcm_trumanage] = {
3746 .base_baud = 115200,
3751 .base_baud = 115200,
3752 .first_offset = 0x40,
3757 .base_baud = 115200,
3758 .first_offset = 0x40,
3763 .base_baud = 115200,
3764 .first_offset = 0x40,
3769 .base_baud = 115200,
3771 .first_offset = 0xC0,
3776 .base_baud = 115200,
3778 .first_offset = 0xC0,
3781 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3783 [pbn_pericom_PI7C9X7951] = {
3786 .base_baud = 921600,
3789 [pbn_pericom_PI7C9X7952] = {
3792 .base_baud = 921600,
3795 [pbn_pericom_PI7C9X7954] = {
3798 .base_baud = 921600,
3801 [pbn_pericom_PI7C9X7958] = {
3804 .base_baud = 921600,
3809 static const struct pci_device_id blacklist[] = {
3811 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3812 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3813 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3815 /* multi-io cards handled by parport_serial */
3816 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3817 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3818 { PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */
3819 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3820 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3822 /* Moxa Smartio MUE boards handled by 8250_moxa */
3823 { PCI_VDEVICE(MOXA, 0x1024), },
3824 { PCI_VDEVICE(MOXA, 0x1025), },
3825 { PCI_VDEVICE(MOXA, 0x1045), },
3826 { PCI_VDEVICE(MOXA, 0x1144), },
3827 { PCI_VDEVICE(MOXA, 0x1160), },
3828 { PCI_VDEVICE(MOXA, 0x1161), },
3829 { PCI_VDEVICE(MOXA, 0x1182), },
3830 { PCI_VDEVICE(MOXA, 0x1183), },
3831 { PCI_VDEVICE(MOXA, 0x1322), },
3832 { PCI_VDEVICE(MOXA, 0x1342), },
3833 { PCI_VDEVICE(MOXA, 0x1381), },
3834 { PCI_VDEVICE(MOXA, 0x1683), },
3836 /* Intel platforms with MID UART */
3837 { PCI_VDEVICE(INTEL, 0x081b), },
3838 { PCI_VDEVICE(INTEL, 0x081c), },
3839 { PCI_VDEVICE(INTEL, 0x081d), },
3840 { PCI_VDEVICE(INTEL, 0x1191), },
3841 { PCI_VDEVICE(INTEL, 0x19d8), },
3843 /* Intel platforms with DesignWare UART */
3844 { PCI_VDEVICE(INTEL, 0x0936), },
3845 { PCI_VDEVICE(INTEL, 0x0f0a), },
3846 { PCI_VDEVICE(INTEL, 0x0f0c), },
3847 { PCI_VDEVICE(INTEL, 0x228a), },
3848 { PCI_VDEVICE(INTEL, 0x228c), },
3849 { PCI_VDEVICE(INTEL, 0x9ce3), },
3850 { PCI_VDEVICE(INTEL, 0x9ce4), },
3854 * Given a complete unknown PCI device, try to use some heuristics to
3855 * guess what the configuration might be, based on the pitiful PCI
3856 * serial specs. Returns 0 on success, 1 on failure.
3859 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3861 const struct pci_device_id *bldev;
3862 int num_iomem, num_port, first_port = -1, i;
3865 * If it is not a communications device or the programming
3866 * interface is greater than 6, give up.
3868 * (Should we try to make guesses for multiport serial devices
3871 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3872 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3873 (dev->class & 0xff) > 6)
3877 * Do not access blacklisted devices that are known not to
3878 * feature serial ports or are handled by other modules.
3880 for (bldev = blacklist;
3881 bldev < blacklist + ARRAY_SIZE(blacklist);
3883 if (dev->vendor == bldev->vendor &&
3884 dev->device == bldev->device)
3888 num_iomem = num_port = 0;
3889 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3890 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3892 if (first_port == -1)
3895 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3900 * If there is 1 or 0 iomem regions, and exactly one port,
3901 * use it. We guess the number of ports based on the IO
3904 if (num_iomem <= 1 && num_port == 1) {
3905 board->flags = first_port;
3906 board->num_ports = pci_resource_len(dev, first_port) / 8;
3911 * Now guess if we've got a board which indexes by BARs.
3912 * Each IO BAR should be 8 bytes, and they should follow
3917 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3918 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3919 pci_resource_len(dev, i) == 8 &&
3920 (first_port == -1 || (first_port + num_port) == i)) {
3922 if (first_port == -1)
3928 board->flags = first_port | FL_BASE_BARS;
3929 board->num_ports = num_port;
3937 serial_pci_matches(const struct pciserial_board *board,
3938 const struct pciserial_board *guessed)
3941 board->num_ports == guessed->num_ports &&
3942 board->base_baud == guessed->base_baud &&
3943 board->uart_offset == guessed->uart_offset &&
3944 board->reg_shift == guessed->reg_shift &&
3945 board->first_offset == guessed->first_offset;
3948 struct serial_private *
3949 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3951 struct uart_8250_port uart;
3952 struct serial_private *priv;
3953 struct pci_serial_quirk *quirk;
3954 int rc, nr_ports, i;
3956 nr_ports = board->num_ports;
3959 * Find an init and setup quirks.
3961 quirk = find_quirk(dev);
3964 * Run the new-style initialization function.
3965 * The initialization function returns:
3967 * 0 - use board->num_ports
3968 * >0 - number of ports
3971 rc = quirk->init(dev);
3980 priv = kzalloc(sizeof(struct serial_private) +
3981 sizeof(unsigned int) * nr_ports,
3984 priv = ERR_PTR(-ENOMEM);
3989 priv->quirk = quirk;
3991 memset(&uart, 0, sizeof(uart));
3992 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3993 uart.port.uartclk = board->base_baud * 16;
3994 uart.port.irq = get_pci_irq(dev, board);
3995 uart.port.dev = &dev->dev;
3997 for (i = 0; i < nr_ports; i++) {
3998 if (quirk->setup(priv, board, &uart, i))
4001 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4002 uart.port.iobase, uart.port.irq, uart.port.iotype);
4004 priv->line[i] = serial8250_register_8250_port(&uart);
4005 if (priv->line[i] < 0) {
4007 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4008 uart.port.iobase, uart.port.irq,
4009 uart.port.iotype, priv->line[i]);
4014 priv->board = board;
4023 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4025 void pciserial_detach_ports(struct serial_private *priv)
4027 struct pci_serial_quirk *quirk;
4030 for (i = 0; i < priv->nr; i++)
4031 serial8250_unregister_port(priv->line[i]);
4034 * Find the exit quirks.
4036 quirk = find_quirk(priv->dev);
4038 quirk->exit(priv->dev);
4041 void pciserial_remove_ports(struct serial_private *priv)
4043 pciserial_detach_ports(priv);
4046 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4048 void pciserial_suspend_ports(struct serial_private *priv)
4052 for (i = 0; i < priv->nr; i++)
4053 if (priv->line[i] >= 0)
4054 serial8250_suspend_port(priv->line[i]);
4057 * Ensure that every init quirk is properly torn down
4059 if (priv->quirk->exit)
4060 priv->quirk->exit(priv->dev);
4062 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4064 void pciserial_resume_ports(struct serial_private *priv)
4069 * Ensure that the board is correctly configured.
4071 if (priv->quirk->init)
4072 priv->quirk->init(priv->dev);
4074 for (i = 0; i < priv->nr; i++)
4075 if (priv->line[i] >= 0)
4076 serial8250_resume_port(priv->line[i]);
4078 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4081 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4082 * to the arrangement of serial ports on a PCI card.
4085 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4087 struct pci_serial_quirk *quirk;
4088 struct serial_private *priv;
4089 const struct pciserial_board *board;
4090 struct pciserial_board tmp;
4093 quirk = find_quirk(dev);
4095 rc = quirk->probe(dev);
4100 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4101 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4106 board = &pci_boards[ent->driver_data];
4108 rc = pcim_enable_device(dev);
4109 pci_save_state(dev);
4113 if (ent->driver_data == pbn_default) {
4115 * Use a copy of the pci_board entry for this;
4116 * avoid changing entries in the table.
4118 memcpy(&tmp, board, sizeof(struct pciserial_board));
4122 * We matched one of our class entries. Try to
4123 * determine the parameters of this board.
4125 rc = serial_pci_guess_board(dev, &tmp);
4130 * We matched an explicit entry. If we are able to
4131 * detect this boards settings with our heuristic,
4132 * then we no longer need this entry.
4134 memcpy(&tmp, &pci_boards[pbn_default],
4135 sizeof(struct pciserial_board));
4136 rc = serial_pci_guess_board(dev, &tmp);
4137 if (rc == 0 && serial_pci_matches(board, &tmp))
4138 moan_device("Redundant entry in serial pci_table.",
4142 priv = pciserial_init_ports(dev, board);
4144 return PTR_ERR(priv);
4146 pci_set_drvdata(dev, priv);
4150 static void pciserial_remove_one(struct pci_dev *dev)
4152 struct serial_private *priv = pci_get_drvdata(dev);
4154 pciserial_remove_ports(priv);
4157 #ifdef CONFIG_PM_SLEEP
4158 static int pciserial_suspend_one(struct device *dev)
4160 struct pci_dev *pdev = to_pci_dev(dev);
4161 struct serial_private *priv = pci_get_drvdata(pdev);
4164 pciserial_suspend_ports(priv);
4169 static int pciserial_resume_one(struct device *dev)
4171 struct pci_dev *pdev = to_pci_dev(dev);
4172 struct serial_private *priv = pci_get_drvdata(pdev);
4177 * The device may have been disabled. Re-enable it.
4179 err = pci_enable_device(pdev);
4180 /* FIXME: We cannot simply error out here */
4182 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4183 pciserial_resume_ports(priv);
4189 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4190 pciserial_resume_one);
4192 static struct pci_device_id serial_pci_tbl[] = {
4193 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4194 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4195 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4197 /* Advantech also use 0x3618 and 0xf618 */
4198 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4199 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4201 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4202 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4204 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4205 PCI_SUBVENDOR_ID_CONNECT_TECH,
4206 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4208 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4209 PCI_SUBVENDOR_ID_CONNECT_TECH,
4210 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4212 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4213 PCI_SUBVENDOR_ID_CONNECT_TECH,
4214 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4216 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4217 PCI_SUBVENDOR_ID_CONNECT_TECH,
4218 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4220 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4221 PCI_SUBVENDOR_ID_CONNECT_TECH,
4222 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4224 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4225 PCI_SUBVENDOR_ID_CONNECT_TECH,
4226 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4228 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4229 PCI_SUBVENDOR_ID_CONNECT_TECH,
4230 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4232 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4233 PCI_SUBVENDOR_ID_CONNECT_TECH,
4234 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4236 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4237 PCI_SUBVENDOR_ID_CONNECT_TECH,
4238 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4240 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4241 PCI_SUBVENDOR_ID_CONNECT_TECH,
4242 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4244 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4245 PCI_SUBVENDOR_ID_CONNECT_TECH,
4246 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4248 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4249 PCI_SUBVENDOR_ID_CONNECT_TECH,
4250 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4252 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4253 PCI_SUBVENDOR_ID_CONNECT_TECH,
4254 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4256 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4257 PCI_SUBVENDOR_ID_CONNECT_TECH,
4258 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4260 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4261 PCI_SUBVENDOR_ID_CONNECT_TECH,
4262 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4264 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4265 PCI_SUBVENDOR_ID_CONNECT_TECH,
4266 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4268 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4269 PCI_SUBVENDOR_ID_CONNECT_TECH,
4270 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4272 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4273 PCI_VENDOR_ID_AFAVLAB,
4274 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4276 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4277 PCI_SUBVENDOR_ID_CONNECT_TECH,
4278 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4279 pbn_b0_2_1843200_200 },
4280 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4281 PCI_SUBVENDOR_ID_CONNECT_TECH,
4282 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4283 pbn_b0_4_1843200_200 },
4284 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4285 PCI_SUBVENDOR_ID_CONNECT_TECH,
4286 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4287 pbn_b0_8_1843200_200 },
4288 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4289 PCI_SUBVENDOR_ID_CONNECT_TECH,
4290 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4291 pbn_b0_2_1843200_200 },
4292 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4293 PCI_SUBVENDOR_ID_CONNECT_TECH,
4294 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4295 pbn_b0_4_1843200_200 },
4296 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4297 PCI_SUBVENDOR_ID_CONNECT_TECH,
4298 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4299 pbn_b0_8_1843200_200 },
4300 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4301 PCI_SUBVENDOR_ID_CONNECT_TECH,
4302 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4303 pbn_b0_2_1843200_200 },
4304 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4305 PCI_SUBVENDOR_ID_CONNECT_TECH,
4306 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4307 pbn_b0_4_1843200_200 },
4308 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4309 PCI_SUBVENDOR_ID_CONNECT_TECH,
4310 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4311 pbn_b0_8_1843200_200 },
4312 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4313 PCI_SUBVENDOR_ID_CONNECT_TECH,
4314 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4315 pbn_b0_2_1843200_200 },
4316 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4317 PCI_SUBVENDOR_ID_CONNECT_TECH,
4318 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4319 pbn_b0_4_1843200_200 },
4320 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4321 PCI_SUBVENDOR_ID_CONNECT_TECH,
4322 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4323 pbn_b0_8_1843200_200 },
4324 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4325 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4326 0, 0, pbn_exar_ibm_saturn },
4328 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 pbn_b2_bt_1_115200 },
4331 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 pbn_b2_bt_2_115200 },
4334 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_b2_bt_4_115200 },
4337 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_b2_bt_2_115200 },
4340 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b2_bt_4_115200 },
4343 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4346 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4349 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4353 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4355 pbn_b2_bt_2_115200 },
4356 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4358 pbn_b2_bt_2_921600 },
4360 * VScom SPCOM800, from sl@s.pl
4362 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4365 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4368 /* Unknown card - subdevice 0x1584 */
4369 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4371 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4373 /* Unknown card - subdevice 0x1588 */
4374 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4376 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4378 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4379 PCI_SUBVENDOR_ID_KEYSPAN,
4380 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4382 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4385 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4388 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4389 PCI_VENDOR_ID_ESDGMBH,
4390 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4392 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4393 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4394 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4396 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4397 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4398 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4400 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4401 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4402 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4404 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4405 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4406 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4408 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4409 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4410 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4412 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4413 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4414 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4416 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4417 PCI_SUBVENDOR_ID_EXSYS,
4418 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4421 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4424 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4425 0x10b5, 0x106a, 0, 0,
4428 * EndRun Technologies. PCI express device range.
4429 * EndRun PTP/1588 has 2 Native UARTs.
4431 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 pbn_endrun_2_3906250 },
4435 * Quatech cards. These actually have configurable clocks but for
4436 * now we just use the default.
4438 * 100 series are RS232, 200 series RS422,
4440 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4458 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4461 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4467 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4470 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4473 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4476 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4488 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4499 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4502 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4503 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4506 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_b0_bt_2_921600 },
4511 * The below card is a little controversial since it is the
4512 * subject of a PCI vendor/device ID clash. (See
4513 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4514 * For now just used the hex ID 0x950a.
4516 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4517 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4518 0, 0, pbn_b0_2_115200 },
4519 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4520 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4521 0, 0, pbn_b0_2_115200 },
4522 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4526 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4528 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_b0_bt_2_921600 },
4534 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 * Oxford Semiconductor Inc. Tornado PCI express device range.
4541 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 pbn_oxsemi_1_4000000 },
4550 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552 pbn_oxsemi_1_4000000 },
4553 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4557 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4560 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4561 pbn_oxsemi_1_4000000 },
4562 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4564 pbn_oxsemi_1_4000000 },
4565 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4579 pbn_oxsemi_2_4000000 },
4580 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582 pbn_oxsemi_2_4000000 },
4583 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585 pbn_oxsemi_4_4000000 },
4586 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4588 pbn_oxsemi_4_4000000 },
4589 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591 pbn_oxsemi_8_4000000 },
4592 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594 pbn_oxsemi_8_4000000 },
4595 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597 pbn_oxsemi_1_4000000 },
4598 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600 pbn_oxsemi_1_4000000 },
4601 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603 pbn_oxsemi_1_4000000 },
4604 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606 pbn_oxsemi_1_4000000 },
4607 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609 pbn_oxsemi_1_4000000 },
4610 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612 pbn_oxsemi_1_4000000 },
4613 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 pbn_oxsemi_1_4000000 },
4616 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 pbn_oxsemi_1_4000000 },
4619 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_oxsemi_1_4000000 },
4622 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_oxsemi_1_4000000 },
4625 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_oxsemi_1_4000000 },
4628 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_oxsemi_1_4000000 },
4631 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_oxsemi_1_4000000 },
4634 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_oxsemi_1_4000000 },
4637 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_oxsemi_1_4000000 },
4640 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_oxsemi_1_4000000 },
4643 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 pbn_oxsemi_1_4000000 },
4646 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_oxsemi_1_4000000 },
4649 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 pbn_oxsemi_1_4000000 },
4652 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 pbn_oxsemi_1_4000000 },
4655 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_oxsemi_1_4000000 },
4658 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 pbn_oxsemi_1_4000000 },
4661 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663 pbn_oxsemi_1_4000000 },
4664 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_oxsemi_1_4000000 },
4667 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_oxsemi_1_4000000 },
4670 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_oxsemi_1_4000000 },
4674 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4676 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4677 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4678 pbn_oxsemi_1_4000000 },
4679 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4680 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4681 pbn_oxsemi_2_4000000 },
4682 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4683 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4684 pbn_oxsemi_4_4000000 },
4685 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4686 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4687 pbn_oxsemi_8_4000000 },
4690 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4692 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4693 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4694 pbn_oxsemi_2_4000000 },
4697 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4698 * from skokodyn@yahoo.com
4700 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4701 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4703 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4704 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4706 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4707 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4709 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4710 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4714 * Digitan DS560-558, from jimd@esoft.com
4716 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721 * Titan Electronic cards
4722 * The 400L and 800L have a custom setup quirk.
4724 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 pbn_b1_bt_2_921600 },
4742 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744 pbn_b0_bt_4_921600 },
4745 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747 pbn_b0_bt_8_921600 },
4748 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 pbn_b4_bt_2_921600 },
4751 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753 pbn_b4_bt_4_921600 },
4754 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 pbn_b4_bt_8_921600 },
4757 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 pbn_oxsemi_1_4000000 },
4769 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 pbn_oxsemi_2_4000000 },
4772 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774 pbn_oxsemi_4_4000000 },
4775 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777 pbn_oxsemi_8_4000000 },
4778 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 pbn_oxsemi_2_4000000 },
4781 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 pbn_oxsemi_2_4000000 },
4784 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 pbn_b0_bt_2_921600 },
4787 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4809 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_b2_bt_2_921600 },
4812 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 pbn_b2_bt_2_921600 },
4815 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817 pbn_b2_bt_2_921600 },
4818 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820 pbn_b2_bt_4_921600 },
4821 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823 pbn_b2_bt_4_921600 },
4824 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826 pbn_b2_bt_4_921600 },
4827 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4830 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4833 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4836 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838 pbn_b0_bt_2_921600 },
4839 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841 pbn_b0_bt_2_921600 },
4842 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4844 pbn_b0_bt_2_921600 },
4845 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847 pbn_b0_bt_4_921600 },
4848 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4850 pbn_b0_bt_4_921600 },
4851 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853 pbn_b0_bt_4_921600 },
4854 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4856 pbn_b0_bt_8_921600 },
4857 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859 pbn_b0_bt_8_921600 },
4860 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862 pbn_b0_bt_8_921600 },
4865 * Computone devices submitted by Doug McNash dmcnash@computone.com
4867 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4868 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4869 0, 0, pbn_computone_4 },
4870 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4871 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4872 0, 0, pbn_computone_8 },
4873 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4874 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4875 0, 0, pbn_computone_6 },
4877 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4880 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4881 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4882 pbn_b0_bt_1_921600 },
4887 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4888 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4889 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4890 pbn_b0_bt_1_921600 },
4892 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4893 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4894 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4895 pbn_b0_bt_1_921600 },
4898 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4900 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 pbn_b0_bt_8_115200 },
4903 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_b0_bt_8_115200 },
4907 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909 pbn_b0_bt_2_115200 },
4910 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912 pbn_b0_bt_2_115200 },
4913 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915 pbn_b0_bt_2_115200 },
4916 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918 pbn_b0_bt_2_115200 },
4919 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921 pbn_b0_bt_2_115200 },
4922 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4924 pbn_b0_bt_4_460800 },
4925 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927 pbn_b0_bt_4_460800 },
4928 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930 pbn_b0_bt_2_460800 },
4931 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4933 pbn_b0_bt_2_460800 },
4934 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4936 pbn_b0_bt_2_460800 },
4937 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939 pbn_b0_bt_1_115200 },
4940 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4942 pbn_b0_bt_1_460800 },
4945 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4946 * Cards are identified by their subsystem vendor IDs, which
4947 * (in hex) match the model number.
4949 * Note that JC140x are RS422/485 cards which require ox950
4950 * ACR = 0x10, and as such are not currently fully supported.
4952 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4953 0x1204, 0x0004, 0, 0,
4955 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4956 0x1208, 0x0004, 0, 0,
4958 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4959 0x1402, 0x0002, 0, 0,
4960 pbn_b0_2_921600 }, */
4961 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4962 0x1404, 0x0004, 0, 0,
4963 pbn_b0_4_921600 }, */
4964 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4965 0x1208, 0x0004, 0, 0,
4968 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4969 0x1204, 0x0004, 0, 0,
4971 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4972 0x1208, 0x0004, 0, 0,
4974 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4975 0x1208, 0x0004, 0, 0,
4978 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4980 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4987 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992 * RAStel 2 port modem, gerg@moreton.com.au
4994 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 pbn_b2_bt_2_115200 },
4999 * EKF addition for i960 Boards form EKF with serial port
5001 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5002 0xE4BF, PCI_ANY_ID, 0, 0,
5006 * Xircom Cardbus/Ethernet combos
5008 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5012 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5014 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5019 * Untested PCI modems, sent in from various folks...
5023 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5025 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5026 0x1048, 0x1500, 0, 0,
5029 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5036 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5037 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5039 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5042 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5046 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5049 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5052 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5057 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5059 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5060 PCI_ANY_ID, PCI_ANY_ID,
5062 0, pbn_exar_XR17C152 },
5063 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5064 PCI_ANY_ID, PCI_ANY_ID,
5066 0, pbn_exar_XR17C154 },
5067 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5068 PCI_ANY_ID, PCI_ANY_ID,
5070 0, pbn_exar_XR17C158 },
5072 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5074 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5075 PCI_ANY_ID, PCI_ANY_ID,
5077 0, pbn_exar_XR17V352 },
5078 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5079 PCI_ANY_ID, PCI_ANY_ID,
5081 0, pbn_exar_XR17V354 },
5082 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5083 PCI_ANY_ID, PCI_ANY_ID,
5085 0, pbn_exar_XR17V358 },
5086 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5087 PCI_ANY_ID, PCI_ANY_ID,
5089 0, pbn_exar_XR17V4358 },
5090 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5091 PCI_ANY_ID, PCI_ANY_ID,
5093 0, pbn_exar_XR17V8358 },
5095 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5097 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5098 PCI_ANY_ID, PCI_ANY_ID,
5100 0, pbn_pericom_PI7C9X7951 },
5101 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5102 PCI_ANY_ID, PCI_ANY_ID,
5104 0, pbn_pericom_PI7C9X7952 },
5105 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5106 PCI_ANY_ID, PCI_ANY_ID,
5108 0, pbn_pericom_PI7C9X7954 },
5109 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5110 PCI_ANY_ID, PCI_ANY_ID,
5112 0, pbn_pericom_PI7C9X7958 },
5114 * ACCES I/O Products quad
5116 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5118 pbn_pericom_PI7C9X7952 },
5119 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5121 pbn_pericom_PI7C9X7952 },
5122 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5124 pbn_pericom_PI7C9X7954 },
5125 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5127 pbn_pericom_PI7C9X7954 },
5128 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5130 pbn_pericom_PI7C9X7952 },
5131 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5133 pbn_pericom_PI7C9X7952 },
5134 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5136 pbn_pericom_PI7C9X7954 },
5137 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5139 pbn_pericom_PI7C9X7954 },
5140 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5142 pbn_pericom_PI7C9X7952 },
5143 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5145 pbn_pericom_PI7C9X7952 },
5146 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5148 pbn_pericom_PI7C9X7954 },
5149 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5151 pbn_pericom_PI7C9X7954 },
5152 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5154 pbn_pericom_PI7C9X7951 },
5155 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5157 pbn_pericom_PI7C9X7952 },
5158 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5160 pbn_pericom_PI7C9X7952 },
5161 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5163 pbn_pericom_PI7C9X7954 },
5164 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5166 pbn_pericom_PI7C9X7954 },
5167 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5169 pbn_pericom_PI7C9X7952 },
5170 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5172 pbn_pericom_PI7C9X7954 },
5173 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5175 pbn_pericom_PI7C9X7952 },
5176 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5178 pbn_pericom_PI7C9X7952 },
5179 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5181 pbn_pericom_PI7C9X7954 },
5182 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5184 pbn_pericom_PI7C9X7954 },
5185 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5187 pbn_pericom_PI7C9X7952 },
5188 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5190 pbn_pericom_PI7C9X7954 },
5191 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5193 pbn_pericom_PI7C9X7954 },
5194 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5196 pbn_pericom_PI7C9X7958 },
5197 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5199 pbn_pericom_PI7C9X7958 },
5200 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5202 pbn_pericom_PI7C9X7954 },
5203 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5205 pbn_pericom_PI7C9X7958 },
5206 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5208 pbn_pericom_PI7C9X7954 },
5209 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5211 pbn_pericom_PI7C9X7958 },
5212 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5214 pbn_pericom_PI7C9X7954 },
5216 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5218 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5224 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5225 PCI_ANY_ID, PCI_ANY_ID,
5227 pbn_b1_bt_1_115200 },
5232 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5238 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5241 /* Brainboxes Devices */
5245 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5246 PCI_ANY_ID, PCI_ANY_ID,
5250 * Brainboxes UC-235/246
5252 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5253 PCI_ANY_ID, PCI_ANY_ID,
5259 { PCI_VENDOR_ID_INTASHIELD, 0x0861,
5260 PCI_ANY_ID, PCI_ANY_ID,
5264 * Brainboxes UC-260/271/701/756
5266 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5267 PCI_ANY_ID, PCI_ANY_ID,
5268 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5270 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5271 PCI_ANY_ID, PCI_ANY_ID,
5272 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5277 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5278 PCI_ANY_ID, PCI_ANY_ID,
5282 * Brainboxes UC-275/279
5284 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5285 PCI_ANY_ID, PCI_ANY_ID,
5291 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5292 PCI_ANY_ID, PCI_ANY_ID,
5298 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5299 PCI_ANY_ID, PCI_ANY_ID,
5305 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5306 PCI_ANY_ID, PCI_ANY_ID,
5310 * Brainboxes UC-320/324
5312 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5313 PCI_ANY_ID, PCI_ANY_ID,
5319 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5320 PCI_ANY_ID, PCI_ANY_ID,
5326 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5327 PCI_ANY_ID, PCI_ANY_ID,
5330 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5331 PCI_ANY_ID, PCI_ANY_ID,
5337 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5338 PCI_ANY_ID, PCI_ANY_ID,
5342 * Brainboxes UC-420/431
5344 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5345 PCI_ANY_ID, PCI_ANY_ID,
5349 * Perle PCI-RAS cards
5351 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5352 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5353 0, 0, pbn_b2_4_921600 },
5354 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5355 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5356 0, 0, pbn_b2_8_921600 },
5359 * Mainpine series cards: Fairly standard layout but fools
5360 * parts of the autodetect in some cases and uses otherwise
5361 * unmatched communications subclasses in the PCI Express case
5364 { /* RockForceDUO */
5365 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5366 PCI_VENDOR_ID_MAINPINE, 0x0200,
5367 0, 0, pbn_b0_2_115200 },
5368 { /* RockForceQUATRO */
5369 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5370 PCI_VENDOR_ID_MAINPINE, 0x0300,
5371 0, 0, pbn_b0_4_115200 },
5372 { /* RockForceDUO+ */
5373 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5374 PCI_VENDOR_ID_MAINPINE, 0x0400,
5375 0, 0, pbn_b0_2_115200 },
5376 { /* RockForceQUATRO+ */
5377 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5378 PCI_VENDOR_ID_MAINPINE, 0x0500,
5379 0, 0, pbn_b0_4_115200 },
5381 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5382 PCI_VENDOR_ID_MAINPINE, 0x0600,
5383 0, 0, pbn_b0_2_115200 },
5385 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5386 PCI_VENDOR_ID_MAINPINE, 0x0700,
5387 0, 0, pbn_b0_4_115200 },
5388 { /* RockForceOCTO+ */
5389 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5390 PCI_VENDOR_ID_MAINPINE, 0x0800,
5391 0, 0, pbn_b0_8_115200 },
5392 { /* RockForceDUO+ */
5393 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5394 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5395 0, 0, pbn_b0_2_115200 },
5396 { /* RockForceQUARTRO+ */
5397 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5398 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5399 0, 0, pbn_b0_4_115200 },
5400 { /* RockForceOCTO+ */
5401 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5402 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5403 0, 0, pbn_b0_8_115200 },
5405 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5406 PCI_VENDOR_ID_MAINPINE, 0x2000,
5407 0, 0, pbn_b0_1_115200 },
5409 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5410 PCI_VENDOR_ID_MAINPINE, 0x2100,
5411 0, 0, pbn_b0_1_115200 },
5413 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5414 PCI_VENDOR_ID_MAINPINE, 0x2200,
5415 0, 0, pbn_b0_2_115200 },
5417 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5418 PCI_VENDOR_ID_MAINPINE, 0x2300,
5419 0, 0, pbn_b0_2_115200 },
5421 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5422 PCI_VENDOR_ID_MAINPINE, 0x2400,
5423 0, 0, pbn_b0_4_115200 },
5425 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5426 PCI_VENDOR_ID_MAINPINE, 0x2500,
5427 0, 0, pbn_b0_4_115200 },
5429 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5430 PCI_VENDOR_ID_MAINPINE, 0x2600,
5431 0, 0, pbn_b0_8_115200 },
5433 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5434 PCI_VENDOR_ID_MAINPINE, 0x2700,
5435 0, 0, pbn_b0_8_115200 },
5436 { /* IQ Express D1 */
5437 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5438 PCI_VENDOR_ID_MAINPINE, 0x3000,
5439 0, 0, pbn_b0_1_115200 },
5440 { /* IQ Express F1 */
5441 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5442 PCI_VENDOR_ID_MAINPINE, 0x3100,
5443 0, 0, pbn_b0_1_115200 },
5444 { /* IQ Express D2 */
5445 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5446 PCI_VENDOR_ID_MAINPINE, 0x3200,
5447 0, 0, pbn_b0_2_115200 },
5448 { /* IQ Express F2 */
5449 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5450 PCI_VENDOR_ID_MAINPINE, 0x3300,
5451 0, 0, pbn_b0_2_115200 },
5452 { /* IQ Express D4 */
5453 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5454 PCI_VENDOR_ID_MAINPINE, 0x3400,
5455 0, 0, pbn_b0_4_115200 },
5456 { /* IQ Express F4 */
5457 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5458 PCI_VENDOR_ID_MAINPINE, 0x3500,
5459 0, 0, pbn_b0_4_115200 },
5460 { /* IQ Express D8 */
5461 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5462 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5463 0, 0, pbn_b0_8_115200 },
5464 { /* IQ Express F8 */
5465 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5466 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5467 0, 0, pbn_b0_8_115200 },
5471 * PA Semi PA6T-1682M on-chip UART
5473 { PCI_VENDOR_ID_PASEMI, 0xa004,
5474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5478 * National Instruments
5480 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5483 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5486 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5488 pbn_b1_bt_4_115200 },
5489 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5491 pbn_b1_bt_2_115200 },
5492 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5494 pbn_b1_bt_4_115200 },
5495 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5497 pbn_b1_bt_2_115200 },
5498 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5501 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5504 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5506 pbn_b1_bt_4_115200 },
5507 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5509 pbn_b1_bt_2_115200 },
5510 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5512 pbn_b1_bt_4_115200 },
5513 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5515 pbn_b1_bt_2_115200 },
5516 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5519 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5522 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5525 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5528 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5531 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5534 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5537 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5540 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5543 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5546 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5549 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5554 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5556 { PCI_VENDOR_ID_ADDIDATA,
5557 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5564 { PCI_VENDOR_ID_ADDIDATA,
5565 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5572 { PCI_VENDOR_ID_ADDIDATA,
5573 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5580 { PCI_VENDOR_ID_AMCC,
5581 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5588 { PCI_VENDOR_ID_ADDIDATA,
5589 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5596 { PCI_VENDOR_ID_ADDIDATA,
5597 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5604 { PCI_VENDOR_ID_ADDIDATA,
5605 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5612 { PCI_VENDOR_ID_ADDIDATA,
5613 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5620 { PCI_VENDOR_ID_ADDIDATA,
5621 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5628 { PCI_VENDOR_ID_ADDIDATA,
5629 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5636 { PCI_VENDOR_ID_ADDIDATA,
5637 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5644 { PCI_VENDOR_ID_ADDIDATA,
5645 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5650 pbn_ADDIDATA_PCIe_4_3906250 },
5652 { PCI_VENDOR_ID_ADDIDATA,
5653 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5658 pbn_ADDIDATA_PCIe_2_3906250 },
5660 { PCI_VENDOR_ID_ADDIDATA,
5661 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5666 pbn_ADDIDATA_PCIe_1_3906250 },
5668 { PCI_VENDOR_ID_ADDIDATA,
5669 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5674 pbn_ADDIDATA_PCIe_8_3906250 },
5676 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5677 PCI_VENDOR_ID_IBM, 0x0299,
5678 0, 0, pbn_b0_bt_2_115200 },
5681 * other NetMos 9835 devices are most likely handled by the
5682 * parport_serial driver, check drivers/parport/parport_serial.c
5683 * before adding them here.
5686 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5688 0, 0, pbn_b0_1_115200 },
5690 /* the 9901 is a rebranded 9912 */
5691 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5693 0, 0, pbn_b0_1_115200 },
5695 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5697 0, 0, pbn_b0_1_115200 },
5699 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5701 0, 0, pbn_b0_1_115200 },
5703 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5705 0, 0, pbn_b0_1_115200 },
5707 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5709 0, 0, pbn_NETMOS9900_2s_115200 },
5712 * Best Connectivity and Rosewill PCI Multi I/O cards
5715 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5717 0, 0, pbn_b0_1_115200 },
5719 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5721 0, 0, pbn_b0_bt_2_115200 },
5723 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5725 0, 0, pbn_b0_bt_4_115200 },
5727 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5729 pbn_ce4100_1_115200 },
5734 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5739 * Broadcom TruManage
5741 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5743 pbn_brcm_trumanage },
5746 * AgeStar as-prs2-009
5748 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5749 PCI_ANY_ID, PCI_ANY_ID,
5750 0, 0, pbn_b0_bt_2_115200 },
5753 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5754 * so not listed here.
5756 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5757 PCI_ANY_ID, PCI_ANY_ID,
5758 0, 0, pbn_b0_bt_4_115200 },
5760 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5761 PCI_ANY_ID, PCI_ANY_ID,
5762 0, 0, pbn_b0_bt_2_115200 },
5764 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5765 PCI_ANY_ID, PCI_ANY_ID,
5766 0, 0, pbn_b0_bt_4_115200 },
5768 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5769 PCI_ANY_ID, PCI_ANY_ID,
5770 0, 0, pbn_wch382_2 },
5772 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5773 PCI_ANY_ID, PCI_ANY_ID,
5774 0, 0, pbn_wch384_4 },
5777 * Commtech, Inc. Fastcom adapters
5779 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5780 PCI_ANY_ID, PCI_ANY_ID,
5782 0, pbn_b0_2_1152000_200 },
5783 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5784 PCI_ANY_ID, PCI_ANY_ID,
5786 0, pbn_b0_4_1152000_200 },
5787 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5788 PCI_ANY_ID, PCI_ANY_ID,
5790 0, pbn_b0_4_1152000_200 },
5791 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5792 PCI_ANY_ID, PCI_ANY_ID,
5794 0, pbn_b0_8_1152000_200 },
5795 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5796 PCI_ANY_ID, PCI_ANY_ID,
5798 0, pbn_exar_XR17V352 },
5799 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5800 PCI_ANY_ID, PCI_ANY_ID,
5802 0, pbn_exar_XR17V354 },
5803 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5804 PCI_ANY_ID, PCI_ANY_ID,
5806 0, pbn_exar_XR17V358 },
5809 * Realtek RealManage
5811 { PCI_VENDOR_ID_REALTEK, 0x816a,
5812 PCI_ANY_ID, PCI_ANY_ID,
5813 0, 0, pbn_b0_1_115200 },
5815 { PCI_VENDOR_ID_REALTEK, 0x816b,
5816 PCI_ANY_ID, PCI_ANY_ID,
5817 0, 0, pbn_b0_1_115200 },
5819 /* Fintek PCI serial cards */
5820 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5821 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5822 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5824 /* MKS Tenta SCOM-080x serial cards */
5825 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5826 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5828 /* Amazon PCI serial device */
5829 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5832 * These entries match devices with class COMMUNICATION_SERIAL,
5833 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5835 { PCI_ANY_ID, PCI_ANY_ID,
5836 PCI_ANY_ID, PCI_ANY_ID,
5837 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5838 0xffff00, pbn_default },
5839 { PCI_ANY_ID, PCI_ANY_ID,
5840 PCI_ANY_ID, PCI_ANY_ID,
5841 PCI_CLASS_COMMUNICATION_MODEM << 8,
5842 0xffff00, pbn_default },
5843 { PCI_ANY_ID, PCI_ANY_ID,
5844 PCI_ANY_ID, PCI_ANY_ID,
5845 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5846 0xffff00, pbn_default },
5850 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5851 pci_channel_state_t state)
5853 struct serial_private *priv = pci_get_drvdata(dev);
5855 if (state == pci_channel_io_perm_failure)
5856 return PCI_ERS_RESULT_DISCONNECT;
5859 pciserial_detach_ports(priv);
5861 pci_disable_device(dev);
5863 return PCI_ERS_RESULT_NEED_RESET;
5866 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5870 rc = pci_enable_device(dev);
5873 return PCI_ERS_RESULT_DISCONNECT;
5875 pci_restore_state(dev);
5876 pci_save_state(dev);
5878 return PCI_ERS_RESULT_RECOVERED;
5881 static void serial8250_io_resume(struct pci_dev *dev)
5883 struct serial_private *priv = pci_get_drvdata(dev);
5884 struct serial_private *new;
5889 new = pciserial_init_ports(dev, priv->board);
5891 pci_set_drvdata(dev, new);
5896 static const struct pci_error_handlers serial8250_err_handler = {
5897 .error_detected = serial8250_io_error_detected,
5898 .slot_reset = serial8250_io_slot_reset,
5899 .resume = serial8250_io_resume,
5902 static struct pci_driver serial_pci_driver = {
5904 .probe = pciserial_init_one,
5905 .remove = pciserial_remove_one,
5907 .pm = &pciserial_pm_ops,
5909 .id_table = serial_pci_tbl,
5910 .err_handler = &serial8250_err_handler,
5913 module_pci_driver(serial_pci_driver);
5915 MODULE_LICENSE("GPL");
5916 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5917 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);