drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #undef DEBUG
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24 #include <linux/rational.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include <linux/dmaengine.h>
  30 #include <linux/platform_data/dma-dw.h>
  31
  32 #include "8250.h"
  33
  34 /*
  35  * init function returns:
  36  *  > 0 - number of ports
  37  *  = 0 - use board->num_ports
  38  *  < 0 - error
  39  */
  40 struct pci_serial_quirk {
  41         u32     vendor;
  42         u32     device;
  43         u32     subvendor;
  44         u32     subdevice;
  45         int     (*probe)(struct pci_dev *dev);
  46         int     (*init)(struct pci_dev *dev);
  47         int     (*setup)(struct serial_private *,
  48                          const struct pciserial_board *,
  49                          struct uart_8250_port *, int);
  50         void    (*exit)(struct pci_dev *dev);
  51 };
  52
  53 #define PCI_NUM_BAR_RESOURCES   6
  54
  55 struct serial_private {
  56         struct pci_dev          *dev;
  57         unsigned int            nr;
  58         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  59         struct pci_serial_quirk *quirk;
  60         const struct pciserial_board *board;
  61         int                     line[0];
  62 };
  63
  64 static int pci_default_setup(struct serial_private*,
  65           const struct pciserial_board*, struct uart_8250_port *, int);
  66
  67 static void moan_device(const char *str, struct pci_dev *dev)
  68 {
  69         dev_err(&dev->dev,
  70                "%s: %s\n"
  71                "Please send the output of lspci -vv, this\n"
  72                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  73                "manufacturer and name of serial board or\n"
  74                "modem board to <linux-serial@vger.kernel.org>.\n",
  75                pci_name(dev), str, dev->vendor, dev->device,
  76                dev->subsystem_vendor, dev->subsystem_device);
  77 }
  78
  79 static int
  80 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  81            u8 bar, unsigned int offset, int regshift)
  82 {
  83         struct pci_dev *dev = priv->dev;
  84
  85         if (bar >= PCI_NUM_BAR_RESOURCES)
  86                 return -EINVAL;
  87
  88         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->port.iotype = UPIO_MEM;
  95                 port->port.iobase = 0;
  96                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
  97                 port->port.membase = priv->remapped_bar[bar] + offset;
  98                 port->port.regshift = regshift;
  99         } else {
 100                 port->port.iotype = UPIO_PORT;
 101                 port->port.iobase = pci_resource_start(dev, bar) + offset;
 102                 port->port.mapbase = 0;
 103                 port->port.membase = NULL;
 104                 port->port.regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 111  */
 112 static int addidata_apci7800_setup(struct serial_private *priv,
 113                                 const struct pciserial_board *board,
 114                                 struct uart_8250_port *port, int idx)
 115 {
 116         unsigned int bar = 0, offset = board->first_offset;
 117         bar = FL_GET_BASE(board->flags);
 118
 119         if (idx < 2) {
 120                 offset += idx * board->uart_offset;
 121         } else if ((idx >= 2) && (idx < 4)) {
 122                 bar += 1;
 123                 offset += ((idx - 2) * board->uart_offset);
 124         } else if ((idx >= 4) && (idx < 6)) {
 125                 bar += 2;
 126                 offset += ((idx - 4) * board->uart_offset);
 127         } else if (idx >= 6) {
 128                 bar += 3;
 129                 offset += ((idx - 6) * board->uart_offset);
 130         }
 131
 132         return setup_port(priv, port, bar, offset, board->reg_shift);
 133 }
 134
 135 /*
 136  * AFAVLAB uses a different mixture of BARs and offsets
 137  * Not that ugly ;) -- HW
 138  */
 139 static int
 140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 141               struct uart_8250_port *port, int idx)
 142 {
 143         unsigned int bar, offset = board->first_offset;
 144
 145         bar = FL_GET_BASE(board->flags);
 146         if (idx < 4)
 147                 bar += idx;
 148         else {
 149                 bar = 4;
 150                 offset += (idx - 4) * board->uart_offset;
 151         }
 152
 153         return setup_port(priv, port, bar, offset, board->reg_shift);
 154 }
 155
 156 /*
 157  * HP's Remote Management Console.  The Diva chip came in several
 158  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 159  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 160  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 161  * one Diva chip, but it has been expanded to 5 UARTs.
 162  */
 163 static int pci_hp_diva_init(struct pci_dev *dev)
 164 {
 165         int rc = 0;
 166
 167         switch (dev->subsystem_device) {
 168         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 169         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 170         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 171         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 172                 rc = 3;
 173                 break;
 174         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 175                 rc = 2;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 178                 rc = 4;
 179                 break;
 180         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 181         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 182                 rc = 1;
 183                 break;
 184         }
 185
 186         return rc;
 187 }
 188
 189 /*
 190  * HP's Diva chip puts the 4th/5th serial port further out, and
 191  * some serial ports are supposed to be hidden on certain models.
 192  */
 193 static int
 194 pci_hp_diva_setup(struct serial_private *priv,
 195                 const struct pciserial_board *board,
 196                 struct uart_8250_port *port, int idx)
 197 {
 198         unsigned int offset = board->first_offset;
 199         unsigned int bar = FL_GET_BASE(board->flags);
 200
 201         switch (priv->dev->subsystem_device) {
 202         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 203                 if (idx == 3)
 204                         idx++;
 205                 break;
 206         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 207                 if (idx > 0)
 208                         idx++;
 209                 if (idx > 2)
 210                         idx++;
 211                 break;
 212         }
 213         if (idx > 2)
 214                 offset = 0x18;
 215
 216         offset += idx * board->uart_offset;
 217
 218         return setup_port(priv, port, bar, offset, board->reg_shift);
 219 }
 220
 221 /*
 222  * Added for EKF Intel i960 serial boards
 223  */
 224 static int pci_inteli960ni_init(struct pci_dev *dev)
 225 {
 226         u32 oldval;
 227
 228         if (!(dev->subsystem_device & 0x1000))
 229                 return -ENODEV;
 230
 231         /* is firmware started? */
 232         pci_read_config_dword(dev, 0x44, &oldval);
 233         if (oldval == 0x00001000L) { /* RESET value */
 234                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 235                 return -ENODEV;
 236         }
 237         return 0;
 238 }
 239
 240 /*
 241  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 242  * that the card interrupt be explicitly enabled or disabled.  This
 243  * seems to be mainly needed on card using the PLX which also use I/O
 244  * mapped memory.
 245  */
 246 static int pci_plx9050_init(struct pci_dev *dev)
 247 {
 248         u8 irq_config;
 249         void __iomem *p;
 250
 251         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 252                 moan_device("no memory in bar 0", dev);
 253                 return 0;
 254         }
 255
 256         irq_config = 0x41;
 257         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 258             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 259                 irq_config = 0x43;
 260
 261         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 262             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 263                 /*
 264                  * As the megawolf cards have the int pins active
 265                  * high, and have 2 UART chips, both ints must be
 266                  * enabled on the 9050. Also, the UARTS are set in
 267                  * 16450 mode by default, so we have to enable the
 268                  * 16C950 'enhanced' mode so that we can use the
 269                  * deep FIFOs
 270                  */
 271                 irq_config = 0x5b;
 272         /*
 273          * enable/disable interrupts
 274          */
 275         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 276         if (p == NULL)
 277                 return -ENOMEM;
 278         writel(irq_config, p + 0x4c);
 279
 280         /*
 281          * Read the register back to ensure that it took effect.
 282          */
 283         readl(p + 0x4c);
 284         iounmap(p);
 285
 286         return 0;
 287 }
 288
 289 static void pci_plx9050_exit(struct pci_dev *dev)
 290 {
 291         u8 __iomem *p;
 292
 293         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 294                 return;
 295
 296         /*
 297          * disable interrupts
 298          */
 299         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 300         if (p != NULL) {
 301                 writel(0, p + 0x4c);
 302
 303                 /*
 304                  * Read the register back to ensure that it took effect.
 305                  */
 306                 readl(p + 0x4c);
 307                 iounmap(p);
 308         }
 309 }
 310
 311 #define NI8420_INT_ENABLE_REG   0x38
 312 #define NI8420_INT_ENABLE_BIT   0x2000
 313
 314 static void pci_ni8420_exit(struct pci_dev *dev)
 315 {
 316         void __iomem *p;
 317         unsigned int bar = 0;
 318
 319         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 320                 moan_device("no memory in bar", dev);
 321                 return;
 322         }
 323
 324         p = pci_ioremap_bar(dev, bar);
 325         if (p == NULL)
 326                 return;
 327
 328         /* Disable the CPU Interrupt */
 329         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 330                p + NI8420_INT_ENABLE_REG);
 331         iounmap(p);
 332 }
 333
 334
 335 /* MITE registers */
 336 #define MITE_IOWBSR1    0xc4
 337 #define MITE_IOWCR1     0xf4
 338 #define MITE_LCIMR1     0x08
 339 #define MITE_LCIMR2     0x10
 340
 341 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 342
 343 static void pci_ni8430_exit(struct pci_dev *dev)
 344 {
 345         void __iomem *p;
 346         unsigned int bar = 0;
 347
 348         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 349                 moan_device("no memory in bar", dev);
 350                 return;
 351         }
 352
 353         p = pci_ioremap_bar(dev, bar);
 354         if (p == NULL)
 355                 return;
 356
 357         /* Disable the CPU Interrupt */
 358         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 359         iounmap(p);
 360 }
 361
 362 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 363 static int
 364 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 365                 struct uart_8250_port *port, int idx)
 366 {
 367         unsigned int bar, offset = board->first_offset;
 368
 369         bar = 0;
 370
 371         if (idx < 4) {
 372                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 373                 offset += idx * board->uart_offset;
 374         } else if (idx < 8) {
 375                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 376                 offset += idx * board->uart_offset + 0xC00;
 377         } else /* we have only 8 ports on PMC-OCTALPRO */
 378                 return 1;
 379
 380         return setup_port(priv, port, bar, offset, board->reg_shift);
 381 }
 382
 383 /*
 384 * This does initialization for PMC OCTALPRO cards:
 385 * maps the device memory, resets the UARTs (needed, bc
 386 * if the module is removed and inserted again, the card
 387 * is in the sleep mode) and enables global interrupt.
 388 */
 389
 390 /* global control register offset for SBS PMC-OctalPro */
 391 #define OCT_REG_CR_OFF          0x500
 392
 393 static int sbs_init(struct pci_dev *dev)
 394 {
 395         u8 __iomem *p;
 396
 397         p = pci_ioremap_bar(dev, 0);
 398
 399         if (p == NULL)
 400                 return -ENOMEM;
 401         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 402         writeb(0x10, p + OCT_REG_CR_OFF);
 403         udelay(50);
 404         writeb(0x0, p + OCT_REG_CR_OFF);
 405
 406         /* Set bit-2 (INTENABLE) of Control Register */
 407         writeb(0x4, p + OCT_REG_CR_OFF);
 408         iounmap(p);
 409
 410         return 0;
 411 }
 412
 413 /*
 414  * Disables the global interrupt of PMC-OctalPro
 415  */
 416
 417 static void sbs_exit(struct pci_dev *dev)
 418 {
 419         u8 __iomem *p;
 420
 421         p = pci_ioremap_bar(dev, 0);
 422         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 423         if (p != NULL)
 424                 writeb(0, p + OCT_REG_CR_OFF);
 425         iounmap(p);
 426 }
 427
 428 /*
 429  * SIIG serial cards have an PCI interface chip which also controls
 430  * the UART clocking frequency. Each UART can be clocked independently
 431  * (except cards equipped with 4 UARTs) and initial clocking settings
 432  * are stored in the EEPROM chip. It can cause problems because this
 433  * version of serial driver doesn't support differently clocked UART's
 434  * on single PCI card. To prevent this, initialization functions set
 435  * high frequency clocking for all UART's on given card. It is safe (I
 436  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 437  * with other OSes (like M$ DOS).
 438  *
 439  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 440  *
 441  * There is two family of SIIG serial cards with different PCI
 442  * interface chip and different configuration methods:
 443  *     - 10x cards have control registers in IO and/or memory space;
 444  *     - 20x cards have control registers in standard PCI configuration space.
 445  *
 446  * Note: all 10x cards have PCI device ids 0x10..
 447  *       all 20x cards have PCI device ids 0x20..
 448  *
 449  * There are also Quartet Serial cards which use Oxford Semiconductor
 450  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 451  *
 452  * Note: some SIIG cards are probed by the parport_serial object.
 453  */
 454
 455 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 456 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 457
 458 static int pci_siig10x_init(struct pci_dev *dev)
 459 {
 460         u16 data;
 461         void __iomem *p;
 462
 463         switch (dev->device & 0xfff8) {
 464         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 465                 data = 0xffdf;
 466                 break;
 467         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 468                 data = 0xf7ff;
 469                 break;
 470         default:                        /* 1S1P, 4S */
 471                 data = 0xfffb;
 472                 break;
 473         }
 474
 475         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 476         if (p == NULL)
 477                 return -ENOMEM;
 478
 479         writew(readw(p + 0x28) & data, p + 0x28);
 480         readw(p + 0x28);
 481         iounmap(p);
 482         return 0;
 483 }
 484
 485 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 486 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 487
 488 static int pci_siig20x_init(struct pci_dev *dev)
 489 {
 490         u8 data;
 491
 492         /* Change clock frequency for the first UART. */
 493         pci_read_config_byte(dev, 0x6f, &data);
 494         pci_write_config_byte(dev, 0x6f, data & 0xef);
 495
 496         /* If this card has 2 UART, we have to do the same with second UART. */
 497         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 498             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 499                 pci_read_config_byte(dev, 0x73, &data);
 500                 pci_write_config_byte(dev, 0x73, data & 0xef);
 501         }
 502         return 0;
 503 }
 504
 505 static int pci_siig_init(struct pci_dev *dev)
 506 {
 507         unsigned int type = dev->device & 0xff00;
 508
 509         if (type == 0x1000)
 510                 return pci_siig10x_init(dev);
 511         else if (type == 0x2000)
 512                 return pci_siig20x_init(dev);
 513
 514         moan_device("Unknown SIIG card", dev);
 515         return -ENODEV;
 516 }
 517
 518 static int pci_siig_setup(struct serial_private *priv,
 519                           const struct pciserial_board *board,
 520                           struct uart_8250_port *port, int idx)
 521 {
 522         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 523
 524         if (idx > 3) {
 525                 bar = 4;
 526                 offset = (idx - 4) * 8;
 527         }
 528
 529         return setup_port(priv, port, bar, offset, 0);
 530 }
 531
 532 /*
 533  * Timedia has an explosion of boards, and to avoid the PCI table from
 534  * growing *huge*, we use this function to collapse some 70 entries
 535  * in the PCI table into one, for sanity's and compactness's sake.
 536  */
 537 static const unsigned short timedia_single_port[] = {
 538         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 539 };
 540
 541 static const unsigned short timedia_dual_port[] = {
 542         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 543         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 544         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 545         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 546         0xD079, 0
 547 };
 548
 549 static const unsigned short timedia_quad_port[] = {
 550         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 551         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 552         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 553         0xB157, 0
 554 };
 555
 556 static const unsigned short timedia_eight_port[] = {
 557         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 558         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 559 };
 560
 561 static const struct timedia_struct {
 562         int num;
 563         const unsigned short *ids;
 564 } timedia_data[] = {
 565         { 1, timedia_single_port },
 566         { 2, timedia_dual_port },
 567         { 4, timedia_quad_port },
 568         { 8, timedia_eight_port }
 569 };
 570
 571 /*
 572  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 573  * listing them individually, this driver merely grabs them all with
 574  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 575  * and should be left free to be claimed by parport_serial instead.
 576  */
 577 static int pci_timedia_probe(struct pci_dev *dev)
 578 {
 579         /*
 580          * Check the third digit of the subdevice ID
 581          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 582          */
 583         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 584                 dev_info(&dev->dev,
 585                         "ignoring Timedia subdevice %04x for parport_serial\n",
 586                         dev->subsystem_device);
 587                 return -ENODEV;
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int pci_timedia_init(struct pci_dev *dev)
 594 {
 595         const unsigned short *ids;
 596         int i, j;
 597
 598         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 599                 ids = timedia_data[i].ids;
 600                 for (j = 0; ids[j]; j++)
 601                         if (dev->subsystem_device == ids[j])
 602                                 return timedia_data[i].num;
 603         }
 604         return 0;
 605 }
 606
 607 /*
 608  * Timedia/SUNIX uses a mixture of BARs and offsets
 609  * Ugh, this is ugly as all hell --- TYT
 610  */
 611 static int
 612 pci_timedia_setup(struct serial_private *priv,
 613                   const struct pciserial_board *board,
 614                   struct uart_8250_port *port, int idx)
 615 {
 616         unsigned int bar = 0, offset = board->first_offset;
 617
 618         switch (idx) {
 619         case 0:
 620                 bar = 0;
 621                 break;
 622         case 1:
 623                 offset = board->uart_offset;
 624                 bar = 0;
 625                 break;
 626         case 2:
 627                 bar = 1;
 628                 break;
 629         case 3:
 630                 offset = board->uart_offset;
 631                 /* FALLTHROUGH */
 632         case 4: /* BAR 2 */
 633         case 5: /* BAR 3 */
 634         case 6: /* BAR 4 */
 635         case 7: /* BAR 5 */
 636                 bar = idx - 2;
 637         }
 638
 639         return setup_port(priv, port, bar, offset, board->reg_shift);
 640 }
 641
 642 /*
 643  * Some Titan cards are also a little weird
 644  */
 645 static int
 646 titan_400l_800l_setup(struct serial_private *priv,
 647                       const struct pciserial_board *board,
 648                       struct uart_8250_port *port, int idx)
 649 {
 650         unsigned int bar, offset = board->first_offset;
 651
 652         switch (idx) {
 653         case 0:
 654                 bar = 1;
 655                 break;
 656         case 1:
 657                 bar = 2;
 658                 break;
 659         default:
 660                 bar = 4;
 661                 offset = (idx - 2) * board->uart_offset;
 662         }
 663
 664         return setup_port(priv, port, bar, offset, board->reg_shift);
 665 }
 666
 667 static int pci_xircom_init(struct pci_dev *dev)
 668 {
 669         msleep(100);
 670         return 0;
 671 }
 672
 673 static int pci_ni8420_init(struct pci_dev *dev)
 674 {
 675         void __iomem *p;
 676         unsigned int bar = 0;
 677
 678         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 679                 moan_device("no memory in bar", dev);
 680                 return 0;
 681         }
 682
 683         p = pci_ioremap_bar(dev, bar);
 684         if (p == NULL)
 685                 return -ENOMEM;
 686
 687         /* Enable CPU Interrupt */
 688         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 689                p + NI8420_INT_ENABLE_REG);
 690
 691         iounmap(p);
 692         return 0;
 693 }
 694
 695 #define MITE_IOWBSR1_WSIZE      0xa
 696 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 697 #define MITE_IOWBSR1_WENAB      (1 << 7)
 698 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 699 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 700 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 701
 702 static int pci_ni8430_init(struct pci_dev *dev)
 703 {
 704         void __iomem *p;
 705         struct pci_bus_region region;
 706         u32 device_window;
 707         unsigned int bar = 0;
 708
 709         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 710                 moan_device("no memory in bar", dev);
 711                 return 0;
 712         }
 713
 714         p = pci_ioremap_bar(dev, bar);
 715         if (p == NULL)
 716                 return -ENOMEM;
 717
 718         /*
 719          * Set device window address and size in BAR0, while acknowledging that
 720          * the resource structure may contain a translated address that differs
 721          * from the address the device responds to.
 722          */
 723         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
 724         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 725                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 726         writel(device_window, p + MITE_IOWBSR1);
 727
 728         /* Set window access to go to RAMSEL IO address space */
 729         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 730                p + MITE_IOWCR1);
 731
 732         /* Enable IO Bus Interrupt 0 */
 733         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 734
 735         /* Enable CPU Interrupt */
 736         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 737
 738         iounmap(p);
 739         return 0;
 740 }
 741
 742 /* UART Port Control Register */
 743 #define NI8430_PORTCON  0x0f
 744 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 745
 746 static int
 747 pci_ni8430_setup(struct serial_private *priv,
 748                  const struct pciserial_board *board,
 749                  struct uart_8250_port *port, int idx)
 750 {
 751         struct pci_dev *dev = priv->dev;
 752         void __iomem *p;
 753         unsigned int bar, offset = board->first_offset;
 754
 755         if (idx >= board->num_ports)
 756                 return 1;
 757
 758         bar = FL_GET_BASE(board->flags);
 759         offset += idx * board->uart_offset;
 760
 761         p = pci_ioremap_bar(dev, bar);
 762         if (!p)
 763                 return -ENOMEM;
 764
 765         /* enable the transceiver */
 766         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 767                p + offset + NI8430_PORTCON);
 768
 769         iounmap(p);
 770
 771         return setup_port(priv, port, bar, offset, board->reg_shift);
 772 }
 773
 774 static int pci_netmos_9900_setup(struct serial_private *priv,
 775                                 const struct pciserial_board *board,
 776                                 struct uart_8250_port *port, int idx)
 777 {
 778         unsigned int bar;
 779
 780         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 781             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 782                 /* netmos apparently orders BARs by datasheet layout, so serial
 783                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 784                  */
 785                 bar = 3 * idx;
 786
 787                 return setup_port(priv, port, bar, 0, board->reg_shift);
 788         } else {
 789                 return pci_default_setup(priv, board, port, idx);
 790         }
 791 }
 792
 793 /* the 99xx series comes with a range of device IDs and a variety
 794  * of capabilities:
 795  *
 796  * 9900 has varying capabilities and can cascade to sub-controllers
 797  *   (cascading should be purely internal)
 798  * 9904 is hardwired with 4 serial ports
 799  * 9912 and 9922 are hardwired with 2 serial ports
 800  */
 801 static int pci_netmos_9900_numports(struct pci_dev *dev)
 802 {
 803         unsigned int c = dev->class;
 804         unsigned int pi;
 805         unsigned short sub_serports;
 806
 807         pi = (c & 0xff);
 808
 809         if (pi == 2) {
 810                 return 1;
 811         } else if ((pi == 0) &&
 812                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 813                 /* two possibilities: 0x30ps encodes number of parallel and
 814                  * serial ports, or 0x1000 indicates *something*. This is not
 815                  * immediately obvious, since the 2s1p+4s configuration seems
 816                  * to offer all functionality on functions 0..2, while still
 817                  * advertising the same function 3 as the 4s+2s1p config.
 818                  */
 819                 sub_serports = dev->subsystem_device & 0xf;
 820                 if (sub_serports > 0) {
 821                         return sub_serports;
 822                 } else {
 823                         dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 824                         return 0;
 825                 }
 826         }
 827
 828         moan_device("unknown NetMos/Mostech program interface", dev);
 829         return 0;
 830 }
 831
 832 static int pci_netmos_init(struct pci_dev *dev)
 833 {
 834         /* subdevice 0x00PS means <P> parallel, <S> serial */
 835         unsigned int num_serial = dev->subsystem_device & 0xf;
 836
 837         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 838                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 839                 return 0;
 840
 841         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 842                         dev->subsystem_device == 0x0299)
 843                 return 0;
 844
 845         switch (dev->device) { /* FALLTHROUGH on all */
 846                 case PCI_DEVICE_ID_NETMOS_9904:
 847                 case PCI_DEVICE_ID_NETMOS_9912:
 848                 case PCI_DEVICE_ID_NETMOS_9922:
 849                 case PCI_DEVICE_ID_NETMOS_9900:
 850                         num_serial = pci_netmos_9900_numports(dev);
 851                         break;
 852
 853                 default:
 854                         if (num_serial == 0 ) {
 855                                 moan_device("unknown NetMos/Mostech device", dev);
 856                         }
 857         }
 858
 859         if (num_serial == 0)
 860                 return -ENODEV;
 861
 862         return num_serial;
 863 }
 864
 865 /*
 866  * These chips are available with optionally one parallel port and up to
 867  * two serial ports. Unfortunately they all have the same product id.
 868  *
 869  * Basic configuration is done over a region of 32 I/O ports. The base
 870  * ioport is called INTA or INTC, depending on docs/other drivers.
 871  *
 872  * The region of the 32 I/O ports is configured in POSIO0R...
 873  */
 874
 875 /* registers */
 876 #define ITE_887x_MISCR          0x9c
 877 #define ITE_887x_INTCBAR        0x78
 878 #define ITE_887x_UARTBAR        0x7c
 879 #define ITE_887x_PS0BAR         0x10
 880 #define ITE_887x_POSIO0         0x60
 881
 882 /* I/O space size */
 883 #define ITE_887x_IOSIZE         32
 884 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 885 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 886 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 887 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 888 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 889 #define ITE_887x_POSIO_SPEED            (3 << 29)
 890 /* enable IO_Space bit */
 891 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 892
 893 static int pci_ite887x_init(struct pci_dev *dev)
 894 {
 895         /* inta_addr are the configuration addresses of the ITE */
 896         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 897                                                         0x200, 0x280, 0 };
 898         int ret, i, type;
 899         struct resource *iobase = NULL;
 900         u32 miscr, uartbar, ioport;
 901
 902         /* search for the base-ioport */
 903         i = 0;
 904         while (inta_addr[i] && iobase == NULL) {
 905                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 906                                                                 "ite887x");
 907                 if (iobase != NULL) {
 908                         /* write POSIO0R - speed | size | ioport */
 909                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 910                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 911                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 912                         /* write INTCBAR - ioport */
 913                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 914                                                                 inta_addr[i]);
 915                         ret = inb(inta_addr[i]);
 916                         if (ret != 0xff) {
 917                                 /* ioport connected */
 918                                 break;
 919                         }
 920                         release_region(iobase->start, ITE_887x_IOSIZE);
 921                         iobase = NULL;
 922                 }
 923                 i++;
 924         }
 925
 926         if (!inta_addr[i]) {
 927                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 928                 return -ENODEV;
 929         }
 930
 931         /* start of undocumented type checking (see parport_pc.c) */
 932         type = inb(iobase->start + 0x18) & 0x0f;
 933
 934         switch (type) {
 935         case 0x2:       /* ITE8871 (1P) */
 936         case 0xa:       /* ITE8875 (1P) */
 937                 ret = 0;
 938                 break;
 939         case 0xe:       /* ITE8872 (2S1P) */
 940                 ret = 2;
 941                 break;
 942         case 0x6:       /* ITE8873 (1S) */
 943                 ret = 1;
 944                 break;
 945         case 0x8:       /* ITE8874 (2S) */
 946                 ret = 2;
 947                 break;
 948         default:
 949                 moan_device("Unknown ITE887x", dev);
 950                 ret = -ENODEV;
 951         }
 952
 953         /* configure all serial ports */
 954         for (i = 0; i < ret; i++) {
 955                 /* read the I/O port from the device */
 956                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 957                                                                 &ioport);
 958                 ioport &= 0x0000FF00;   /* the actual base address */
 959                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 960                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 961                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 962
 963                 /* write the ioport to the UARTBAR */
 964                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 965                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 966                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 967                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 968
 969                 /* get current config */
 970                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 971                 /* disable interrupts (UARTx_Routing[3:0]) */
 972                 miscr &= ~(0xf << (12 - 4 * i));
 973                 /* activate the UART (UARTx_En) */
 974                 miscr |= 1 << (23 - i);
 975                 /* write new config with activated UART */
 976                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 977         }
 978
 979         if (ret <= 0) {
 980                 /* the device has no UARTs if we get here */
 981                 release_region(iobase->start, ITE_887x_IOSIZE);
 982         }
 983
 984         return ret;
 985 }
 986
 987 static void pci_ite887x_exit(struct pci_dev *dev)
 988 {
 989         u32 ioport;
 990         /* the ioport is bit 0-15 in POSIO0R */
 991         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 992         ioport &= 0xffff;
 993         release_region(ioport, ITE_887x_IOSIZE);
 994 }
 995
 996 /*
 997  * EndRun Technologies.
 998  * Determine the number of ports available on the device.
 999  */
1000 #define PCI_VENDOR_ID_ENDRUN                    0x7401
1001 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
1002
1003 static int pci_endrun_init(struct pci_dev *dev)
1004 {
1005         u8 __iomem *p;
1006         unsigned long deviceID;
1007         unsigned int  number_uarts = 0;
1008
1009         /* EndRun device is all 0xexxx */
1010         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011                 (dev->device & 0xf000) != 0xe000)
1012                 return 0;
1013
1014         p = pci_iomap(dev, 0, 5);
1015         if (p == NULL)
1016                 return -ENOMEM;
1017
1018         deviceID = ioread32(p);
1019         /* EndRun device */
1020         if (deviceID == 0x07000200) {
1021                 number_uarts = ioread8(p + 4);
1022                 dev_dbg(&dev->dev,
1023                         "%d ports detected on EndRun PCI Express device\n",
1024                         number_uarts);
1025         }
1026         pci_iounmap(dev, p);
1027         return number_uarts;
1028 }
1029
1030 /*
1031  * Oxford Semiconductor Inc.
1032  * Check that device is part of the Tornado range of devices, then determine
1033  * the number of ports available on the device.
1034  */
1035 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036 {
1037         u8 __iomem *p;
1038         unsigned long deviceID;
1039         unsigned int  number_uarts = 0;
1040
1041         /* OxSemi Tornado devices are all 0xCxxx */
1042         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1043             (dev->device & 0xF000) != 0xC000)
1044                 return 0;
1045
1046         p = pci_iomap(dev, 0, 5);
1047         if (p == NULL)
1048                 return -ENOMEM;
1049
1050         deviceID = ioread32(p);
1051         /* Tornado device */
1052         if (deviceID == 0x07000200) {
1053                 number_uarts = ioread8(p + 4);
1054                 dev_dbg(&dev->dev,
1055                         "%d ports detected on Oxford PCI Express device\n",
1056                         number_uarts);
1057         }
1058         pci_iounmap(dev, p);
1059         return number_uarts;
1060 }
1061
1062 static int pci_asix_setup(struct serial_private *priv,
1063                   const struct pciserial_board *board,
1064                   struct uart_8250_port *port, int idx)
1065 {
1066         port->bugs |= UART_BUG_PARITY;
1067         return pci_default_setup(priv, board, port, idx);
1068 }
1069
1070 /* Quatech devices have their own extra interface features */
1071
1072 struct quatech_feature {
1073         u16 devid;
1074         bool amcc;
1075 };
1076
1077 #define QPCR_TEST_FOR1          0x3F
1078 #define QPCR_TEST_GET1          0x00
1079 #define QPCR_TEST_FOR2          0x40
1080 #define QPCR_TEST_GET2          0x40
1081 #define QPCR_TEST_FOR3          0x80
1082 #define QPCR_TEST_GET3          0x40
1083 #define QPCR_TEST_FOR4          0xC0
1084 #define QPCR_TEST_GET4          0x80
1085
1086 #define QOPR_CLOCK_X1           0x0000
1087 #define QOPR_CLOCK_X2           0x0001
1088 #define QOPR_CLOCK_X4           0x0002
1089 #define QOPR_CLOCK_X8           0x0003
1090 #define QOPR_CLOCK_RATE_MASK    0x0003
1091
1092
1093 static struct quatech_feature quatech_cards[] = {
1094         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1095         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1096         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1097         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1098         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1099         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1100         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1101         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1102         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1103         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1104         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1105         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1106         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1107         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1108         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1109         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1110         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1111         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1112         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1113         { 0, }
1114 };
1115
1116 static int pci_quatech_amcc(u16 devid)
1117 {
1118         struct quatech_feature *qf = &quatech_cards[0];
1119         while (qf->devid) {
1120                 if (qf->devid == devid)
1121                         return qf->amcc;
1122                 qf++;
1123         }
1124         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1125         return 0;
1126 };
1127
1128 static int pci_quatech_rqopr(struct uart_8250_port *port)
1129 {
1130         unsigned long base = port->port.iobase;
1131         u8 LCR, val;
1132
1133         LCR = inb(base + UART_LCR);
1134         outb(0xBF, base + UART_LCR);
1135         val = inb(base + UART_SCR);
1136         outb(LCR, base + UART_LCR);
1137         return val;
1138 }
1139
1140 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141 {
1142         unsigned long base = port->port.iobase;
1143         u8 LCR, val;
1144
1145         LCR = inb(base + UART_LCR);
1146         outb(0xBF, base + UART_LCR);
1147         val = inb(base + UART_SCR);
1148         outb(qopr, base + UART_SCR);
1149         outb(LCR, base + UART_LCR);
1150 }
1151
1152 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153 {
1154         unsigned long base = port->port.iobase;
1155         u8 LCR, val, qmcr;
1156
1157         LCR = inb(base + UART_LCR);
1158         outb(0xBF, base + UART_LCR);
1159         val = inb(base + UART_SCR);
1160         outb(val | 0x10, base + UART_SCR);
1161         qmcr = inb(base + UART_MCR);
1162         outb(val, base + UART_SCR);
1163         outb(LCR, base + UART_LCR);
1164
1165         return qmcr;
1166 }
1167
1168 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169 {
1170         unsigned long base = port->port.iobase;
1171         u8 LCR, val;
1172
1173         LCR = inb(base + UART_LCR);
1174         outb(0xBF, base + UART_LCR);
1175         val = inb(base + UART_SCR);
1176         outb(val | 0x10, base + UART_SCR);
1177         outb(qmcr, base + UART_MCR);
1178         outb(val, base + UART_SCR);
1179         outb(LCR, base + UART_LCR);
1180 }
1181
1182 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183 {
1184         unsigned long base = port->port.iobase;
1185         u8 LCR, val;
1186
1187         LCR = inb(base + UART_LCR);
1188         outb(0xBF, base + UART_LCR);
1189         val = inb(base + UART_SCR);
1190         if (val & 0x20) {
1191                 outb(0x80, UART_LCR);
1192                 if (!(inb(UART_SCR) & 0x20)) {
1193                         outb(LCR, base + UART_LCR);
1194                         return 1;
1195                 }
1196         }
1197         return 0;
1198 }
1199
1200 static int pci_quatech_test(struct uart_8250_port *port)
1201 {
1202         u8 reg;
1203         u8 qopr = pci_quatech_rqopr(port);
1204         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205         reg = pci_quatech_rqopr(port) & 0xC0;
1206         if (reg != QPCR_TEST_GET1)
1207                 return -EINVAL;
1208         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209         reg = pci_quatech_rqopr(port) & 0xC0;
1210         if (reg != QPCR_TEST_GET2)
1211                 return -EINVAL;
1212         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213         reg = pci_quatech_rqopr(port) & 0xC0;
1214         if (reg != QPCR_TEST_GET3)
1215                 return -EINVAL;
1216         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217         reg = pci_quatech_rqopr(port) & 0xC0;
1218         if (reg != QPCR_TEST_GET4)
1219                 return -EINVAL;
1220
1221         pci_quatech_wqopr(port, qopr);
1222         return 0;
1223 }
1224
1225 static int pci_quatech_clock(struct uart_8250_port *port)
1226 {
1227         u8 qopr, reg, set;
1228         unsigned long clock;
1229
1230         if (pci_quatech_test(port) < 0)
1231                 return 1843200;
1232
1233         qopr = pci_quatech_rqopr(port);
1234
1235         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236         reg = pci_quatech_rqopr(port);
1237         if (reg & QOPR_CLOCK_X8) {
1238                 clock = 1843200;
1239                 goto out;
1240         }
1241         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242         reg = pci_quatech_rqopr(port);
1243         if (!(reg & QOPR_CLOCK_X8)) {
1244                 clock = 1843200;
1245                 goto out;
1246         }
1247         reg &= QOPR_CLOCK_X8;
1248         if (reg == QOPR_CLOCK_X2) {
1249                 clock =  3685400;
1250                 set = QOPR_CLOCK_X2;
1251         } else if (reg == QOPR_CLOCK_X4) {
1252                 clock = 7372800;
1253                 set = QOPR_CLOCK_X4;
1254         } else if (reg == QOPR_CLOCK_X8) {
1255                 clock = 14745600;
1256                 set = QOPR_CLOCK_X8;
1257         } else {
1258                 clock = 1843200;
1259                 set = QOPR_CLOCK_X1;
1260         }
1261         qopr &= ~QOPR_CLOCK_RATE_MASK;
1262         qopr |= set;
1263
1264 out:
1265         pci_quatech_wqopr(port, qopr);
1266         return clock;
1267 }
1268
1269 static int pci_quatech_rs422(struct uart_8250_port *port)
1270 {
1271         u8 qmcr;
1272         int rs422 = 0;
1273
1274         if (!pci_quatech_has_qmcr(port))
1275                 return 0;
1276         qmcr = pci_quatech_rqmcr(port);
1277         pci_quatech_wqmcr(port, 0xFF);
1278         if (pci_quatech_rqmcr(port))
1279                 rs422 = 1;
1280         pci_quatech_wqmcr(port, qmcr);
1281         return rs422;
1282 }
1283
1284 static int pci_quatech_init(struct pci_dev *dev)
1285 {
1286         if (pci_quatech_amcc(dev->device)) {
1287                 unsigned long base = pci_resource_start(dev, 0);
1288                 if (base) {
1289                         u32 tmp;
1290                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1291                         tmp = inl(base + 0x3c);
1292                         outl(tmp | 0x01000000, base + 0x3c);
1293                         outl(tmp &= ~0x01000000, base + 0x3c);
1294                 }
1295         }
1296         return 0;
1297 }
1298
1299 static int pci_quatech_setup(struct serial_private *priv,
1300                   const struct pciserial_board *board,
1301                   struct uart_8250_port *port, int idx)
1302 {
1303         /* Needed by pci_quatech calls below */
1304         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1305         /* Set up the clocking */
1306         port->port.uartclk = pci_quatech_clock(port);
1307         /* For now just warn about RS422 */
1308         if (pci_quatech_rs422(port))
1309                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1310         return pci_default_setup(priv, board, port, idx);
1311 }
1312
1313 static void pci_quatech_exit(struct pci_dev *dev)
1314 {
1315 }
1316
1317 static int pci_default_setup(struct serial_private *priv,
1318                   const struct pciserial_board *board,
1319                   struct uart_8250_port *port, int idx)
1320 {
1321         unsigned int bar, offset = board->first_offset, maxnr;
1322
1323         bar = FL_GET_BASE(board->flags);
1324         if (board->flags & FL_BASE_BARS)
1325                 bar += idx;
1326         else
1327                 offset += idx * board->uart_offset;
1328
1329         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1330                 (board->reg_shift + 3);
1331
1332         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333                 return 1;
1334
1335         return setup_port(priv, port, bar, offset, board->reg_shift);
1336 }
1337
1338 static int pci_pericom_setup(struct serial_private *priv,
1339                   const struct pciserial_board *board,
1340                   struct uart_8250_port *port, int idx)
1341 {
1342         unsigned int bar, offset = board->first_offset, maxnr;
1343
1344         bar = FL_GET_BASE(board->flags);
1345         if (board->flags & FL_BASE_BARS)
1346                 bar += idx;
1347         else
1348                 offset += idx * board->uart_offset;
1349
1350         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1351                 (board->reg_shift + 3);
1352
1353         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354                 return 1;
1355
1356         port->port.uartclk = 14745600;
1357
1358         return setup_port(priv, port, bar, offset, board->reg_shift);
1359 }
1360
1361 static int
1362 ce4100_serial_setup(struct serial_private *priv,
1363                   const struct pciserial_board *board,
1364                   struct uart_8250_port *port, int idx)
1365 {
1366         int ret;
1367
1368         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1369         port->port.iotype = UPIO_MEM32;
1370         port->port.type = PORT_XSCALE;
1371         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1372         port->port.regshift = 2;
1373
1374         return ret;
1375 }
1376
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART1   0x0f0a
1378 #define PCI_DEVICE_ID_INTEL_BYT_UART2   0x0f0c
1379
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART1   0x228a
1381 #define PCI_DEVICE_ID_INTEL_BSW_UART2   0x228c
1382
1383 #define PCI_DEVICE_ID_INTEL_BDW_UART1   0x9ce3
1384 #define PCI_DEVICE_ID_INTEL_BDW_UART2   0x9ce4
1385
1386 #define BYT_PRV_CLK                     0x800
1387 #define BYT_PRV_CLK_EN                  (1 << 0)
1388 #define BYT_PRV_CLK_M_VAL_SHIFT         1
1389 #define BYT_PRV_CLK_N_VAL_SHIFT         16
1390 #define BYT_PRV_CLK_UPDATE              (1 << 31)
1391
1392 #define BYT_TX_OVF_INT                  0x820
1393 #define BYT_TX_OVF_INT_MASK             (1 << 1)
1394
1395 static void
1396 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1397                 struct ktermios *old)
1398 {
1399         unsigned int baud = tty_termios_baud_rate(termios);
1400         unsigned long fref = 100000000, fuart = baud * 16;
1401         unsigned long w = BIT(15) - 1;
1402         unsigned long m, n;
1403         u32 reg;
1404
1405         /* Gracefully handle the B0 case: fall back to B9600 */
1406         fuart = fuart ? fuart : 9600 * 16;
1407
1408         /* Get Fuart closer to Fref */
1409         fuart *= rounddown_pow_of_two(fref / fuart);
1410
1411         /*
1412          * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1413          * dividers must be adjusted.
1414          *
1415          * uartclk = (m / n) * 100 MHz, where m <= n
1416          */
1417         rational_best_approximation(fuart, fref, w, w, &m, &n);
1418         p->uartclk = fuart;
1419
1420         /* Reset the clock */
1421         reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1422         writel(reg, p->membase + BYT_PRV_CLK);
1423         reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1424         writel(reg, p->membase + BYT_PRV_CLK);
1425
1426         p->status &= ~UPSTAT_AUTOCTS;
1427         if (termios->c_cflag & CRTSCTS)
1428                 p->status |= UPSTAT_AUTOCTS;
1429
1430         serial8250_do_set_termios(p, termios, old);
1431 }
1432
1433 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1434 {
1435         struct dw_dma_slave *dws = param;
1436
1437         if (dws->dma_dev != chan->device->dev)
1438                 return false;
1439
1440         chan->private = dws;
1441         return true;
1442 }
1443
1444 static int
1445 byt_serial_setup(struct serial_private *priv,
1446                  const struct pciserial_board *board,
1447                  struct uart_8250_port *port, int idx)
1448 {
1449         struct pci_dev *pdev = priv->dev;
1450         struct device *dev = port->port.dev;
1451         struct uart_8250_dma *dma;
1452         struct dw_dma_slave *tx_param, *rx_param;
1453         struct pci_dev *dma_dev;
1454         int ret;
1455
1456         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1457         if (!dma)
1458                 return -ENOMEM;
1459
1460         tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1461         if (!tx_param)
1462                 return -ENOMEM;
1463
1464         rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1465         if (!rx_param)
1466                 return -ENOMEM;
1467
1468         switch (pdev->device) {
1469         case PCI_DEVICE_ID_INTEL_BYT_UART1:
1470         case PCI_DEVICE_ID_INTEL_BSW_UART1:
1471         case PCI_DEVICE_ID_INTEL_BDW_UART1:
1472                 rx_param->src_id = 3;
1473                 tx_param->dst_id = 2;
1474                 break;
1475         case PCI_DEVICE_ID_INTEL_BYT_UART2:
1476         case PCI_DEVICE_ID_INTEL_BSW_UART2:
1477         case PCI_DEVICE_ID_INTEL_BDW_UART2:
1478                 rx_param->src_id = 5;
1479                 tx_param->dst_id = 4;
1480                 break;
1481         default:
1482                 return -EINVAL;
1483         }
1484
1485         rx_param->src_master = 1;
1486         rx_param->dst_master = 0;
1487
1488         dma->rxconf.src_maxburst = 16;
1489
1490         tx_param->src_master = 1;
1491         tx_param->dst_master = 0;
1492
1493         dma->txconf.dst_maxburst = 16;
1494
1495         dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1496         rx_param->dma_dev = &dma_dev->dev;
1497         tx_param->dma_dev = &dma_dev->dev;
1498
1499         dma->fn = byt_dma_filter;
1500         dma->rx_param = rx_param;
1501         dma->tx_param = tx_param;
1502
1503         ret = pci_default_setup(priv, board, port, idx);
1504         port->port.iotype = UPIO_MEM;
1505         port->port.type = PORT_16550A;
1506         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1507         port->port.set_termios = byt_set_termios;
1508         port->port.fifosize = 64;
1509         port->tx_loadsz = 64;
1510         port->dma = dma;
1511         port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1512
1513         /* Disable Tx counter interrupts */
1514         writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1515
1516         return ret;
1517 }
1518
1519 static int
1520 pci_omegapci_setup(struct serial_private *priv,
1521                       const struct pciserial_board *board,
1522                       struct uart_8250_port *port, int idx)
1523 {
1524         return setup_port(priv, port, 2, idx * 8, 0);
1525 }
1526
1527 static int
1528 pci_brcm_trumanage_setup(struct serial_private *priv,
1529                          const struct pciserial_board *board,
1530                          struct uart_8250_port *port, int idx)
1531 {
1532         int ret = pci_default_setup(priv, board, port, idx);
1533
1534         port->port.type = PORT_BRCM_TRUMANAGE;
1535         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1536         return ret;
1537 }
1538
1539 /* RTS will control by MCR if this bit is 0 */
1540 #define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1541 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1542 #define FINTEK_RTS_INVERT               BIT(5)
1543
1544 /* We should do proper H/W transceiver setting before change to RS485 mode */
1545 static int pci_fintek_rs485_config(struct uart_port *port,
1546                                struct serial_rs485 *rs485)
1547 {
1548         u8 setting;
1549         u8 *index = (u8 *) port->private_data;
1550         struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev,
1551                                                 dev);
1552
1553         pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1554
1555         if (!rs485)
1556                 rs485 = &port->rs485;
1557         else if (rs485->flags & SER_RS485_ENABLED)
1558                 memset(rs485->padding, 0, sizeof(rs485->padding));
1559         else
1560                 memset(rs485, 0, sizeof(*rs485));
1561
1562         /* F81504/508/512 not support RTS delay before or after send */
1563         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1564
1565         if (rs485->flags & SER_RS485_ENABLED) {
1566                 /* Enable RTS H/W control mode */
1567                 setting |= FINTEK_RTS_CONTROL_BY_HW;
1568
1569                 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1570                         /* RTS driving high on TX */
1571                         setting &= ~FINTEK_RTS_INVERT;
1572                 } else {
1573                         /* RTS driving low on TX */
1574                         setting |= FINTEK_RTS_INVERT;
1575                 }
1576
1577                 rs485->delay_rts_after_send = 0;
1578                 rs485->delay_rts_before_send = 0;
1579         } else {
1580                 /* Disable RTS H/W control mode */
1581                 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1582         }
1583
1584         pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1585
1586         if (rs485 != &port->rs485)
1587                 port->rs485 = *rs485;
1588
1589         return 0;
1590 }
1591
1592 static int pci_fintek_setup(struct serial_private *priv,
1593                             const struct pciserial_board *board,
1594                             struct uart_8250_port *port, int idx)
1595 {
1596         struct pci_dev *pdev = priv->dev;
1597         u8 *data;
1598         u8 config_base;
1599         u16 iobase;
1600
1601         config_base = 0x40 + 0x08 * idx;
1602
1603         /* Get the io address from configuration space */
1604         pci_read_config_word(pdev, config_base + 4, &iobase);
1605
1606         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1607
1608         port->port.iotype = UPIO_PORT;
1609         port->port.iobase = iobase;
1610         port->port.rs485_config = pci_fintek_rs485_config;
1611
1612         data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1613         if (!data)
1614                 return -ENOMEM;
1615
1616         /* preserve index in PCI configuration space */
1617         *data = idx;
1618         port->port.private_data = data;
1619
1620         return 0;
1621 }
1622
1623 static int pci_fintek_init(struct pci_dev *dev)
1624 {
1625         unsigned long iobase;
1626         u32 max_port, i;
1627         u32 bar_data[3];
1628         u8 config_base;
1629         struct serial_private *priv = pci_get_drvdata(dev);
1630         struct uart_8250_port *port;
1631
1632         switch (dev->device) {
1633         case 0x1104: /* 4 ports */
1634         case 0x1108: /* 8 ports */
1635                 max_port = dev->device & 0xff;
1636                 break;
1637         case 0x1112: /* 12 ports */
1638                 max_port = 12;
1639                 break;
1640         default:
1641                 return -EINVAL;
1642         }
1643
1644         /* Get the io address dispatch from the BIOS */
1645         pci_read_config_dword(dev, 0x24, &bar_data[0]);
1646         pci_read_config_dword(dev, 0x20, &bar_data[1]);
1647         pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1648
1649         for (i = 0; i < max_port; ++i) {
1650                 /* UART0 configuration offset start from 0x40 */
1651                 config_base = 0x40 + 0x08 * i;
1652
1653                 /* Calculate Real IO Port */
1654                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1655
1656                 /* Enable UART I/O port */
1657                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1658
1659                 /* Select 128-byte FIFO and 8x FIFO threshold */
1660                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1661
1662                 /* LSB UART */
1663                 pci_write_config_byte(dev, config_base + 0x04,
1664                                 (u8)(iobase & 0xff));
1665
1666                 /* MSB UART */
1667                 pci_write_config_byte(dev, config_base + 0x05,
1668                                 (u8)((iobase & 0xff00) >> 8));
1669
1670                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1671
1672                 if (priv) {
1673                         /* re-apply RS232/485 mode when
1674                          * pciserial_resume_ports()
1675                          */
1676                         port = serial8250_get_port(priv->line[i]);
1677                         pci_fintek_rs485_config(&port->port, NULL);
1678                 } else {
1679                         /* First init without port data
1680                          * force init to RS232 Mode
1681                          */
1682                         pci_write_config_byte(dev, config_base + 0x07, 0x01);
1683                 }
1684         }
1685
1686         return max_port;
1687 }
1688
1689 static int skip_tx_en_setup(struct serial_private *priv,
1690                         const struct pciserial_board *board,
1691                         struct uart_8250_port *port, int idx)
1692 {
1693         port->port.flags |= UPF_NO_TXEN_TEST;
1694         dev_dbg(&priv->dev->dev,
1695                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1696                 priv->dev->vendor, priv->dev->device,
1697                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1698
1699         return pci_default_setup(priv, board, port, idx);
1700 }
1701
1702 static void kt_handle_break(struct uart_port *p)
1703 {
1704         struct uart_8250_port *up = up_to_u8250p(p);
1705         /*
1706          * On receipt of a BI, serial device in Intel ME (Intel
1707          * management engine) needs to have its fifos cleared for sane
1708          * SOL (Serial Over Lan) output.
1709          */
1710         serial8250_clear_and_reinit_fifos(up);
1711 }
1712
1713 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1714 {
1715         struct uart_8250_port *up = up_to_u8250p(p);
1716         unsigned int val;
1717
1718         /*
1719          * When the Intel ME (management engine) gets reset its serial
1720          * port registers could return 0 momentarily.  Functions like
1721          * serial8250_console_write, read and save the IER, perform
1722          * some operation and then restore it.  In order to avoid
1723          * setting IER register inadvertently to 0, if the value read
1724          * is 0, double check with ier value in uart_8250_port and use
1725          * that instead.  up->ier should be the same value as what is
1726          * currently configured.
1727          */
1728         val = inb(p->iobase + offset);
1729         if (offset == UART_IER) {
1730                 if (val == 0)
1731                         val = up->ier;
1732         }
1733         return val;
1734 }
1735
1736 static int kt_serial_setup(struct serial_private *priv,
1737                            const struct pciserial_board *board,
1738                            struct uart_8250_port *port, int idx)
1739 {
1740         port->port.flags |= UPF_BUG_THRE;
1741         port->port.serial_in = kt_serial_in;
1742         port->port.handle_break = kt_handle_break;
1743         return skip_tx_en_setup(priv, board, port, idx);
1744 }
1745
1746 static int pci_eg20t_init(struct pci_dev *dev)
1747 {
1748 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1749         return -ENODEV;
1750 #else
1751         return 0;
1752 #endif
1753 }
1754
1755 #define PCI_DEVICE_ID_EXAR_XR17V4358    0x4358
1756 #define PCI_DEVICE_ID_EXAR_XR17V8358    0x8358
1757
1758 static int
1759 pci_xr17c154_setup(struct serial_private *priv,
1760                   const struct pciserial_board *board,
1761                   struct uart_8250_port *port, int idx)
1762 {
1763         port->port.flags |= UPF_EXAR_EFR;
1764         return pci_default_setup(priv, board, port, idx);
1765 }
1766
1767 static inline int
1768 xr17v35x_has_slave(struct serial_private *priv)
1769 {
1770         const int dev_id = priv->dev->device;
1771
1772         return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1773                 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1774 }
1775
1776 static int
1777 pci_xr17v35x_setup(struct serial_private *priv,
1778                   const struct pciserial_board *board,
1779                   struct uart_8250_port *port, int idx)
1780 {
1781         u8 __iomem *p;
1782
1783         p = pci_ioremap_bar(priv->dev, 0);
1784         if (p == NULL)
1785                 return -ENOMEM;
1786
1787         port->port.flags |= UPF_EXAR_EFR;
1788
1789         /*
1790          * Setup the uart clock for the devices on expansion slot to
1791          * half the clock speed of the main chip (which is 125MHz)
1792          */
1793         if (xr17v35x_has_slave(priv) && idx >= 8)
1794                 port->port.uartclk = (7812500 * 16 / 2);
1795
1796         /*
1797          * Setup Multipurpose Input/Output pins.
1798          */
1799         if (idx == 0) {
1800                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1801                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1802                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1803                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1804                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1805                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1806                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1807                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1808                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1809                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1810                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1811                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1812         }
1813         writeb(0x00, p + UART_EXAR_8XMODE);
1814         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1815         writeb(128, p + UART_EXAR_TXTRG);
1816         writeb(128, p + UART_EXAR_RXTRG);
1817         iounmap(p);
1818
1819         return pci_default_setup(priv, board, port, idx);
1820 }
1821
1822 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1823 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1824 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1825 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1826
1827 static int
1828 pci_fastcom335_setup(struct serial_private *priv,
1829                   const struct pciserial_board *board,
1830                   struct uart_8250_port *port, int idx)
1831 {
1832         u8 __iomem *p;
1833
1834         p = pci_ioremap_bar(priv->dev, 0);
1835         if (p == NULL)
1836                 return -ENOMEM;
1837
1838         port->port.flags |= UPF_EXAR_EFR;
1839
1840         /*
1841          * Setup Multipurpose Input/Output pins.
1842          */
1843         if (idx == 0) {
1844                 switch (priv->dev->device) {
1845                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1846                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1847                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1848                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1849                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1850                         break;
1851                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1852                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1853                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1854                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1855                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1856                         break;
1857                 }
1858                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1859                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1860                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1861         }
1862         writeb(0x00, p + UART_EXAR_8XMODE);
1863         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1864         writeb(32, p + UART_EXAR_TXTRG);
1865         writeb(32, p + UART_EXAR_RXTRG);
1866         iounmap(p);
1867
1868         return pci_default_setup(priv, board, port, idx);
1869 }
1870
1871 static int
1872 pci_wch_ch353_setup(struct serial_private *priv,
1873                     const struct pciserial_board *board,
1874                     struct uart_8250_port *port, int idx)
1875 {
1876         port->port.flags |= UPF_FIXED_TYPE;
1877         port->port.type = PORT_16550A;
1878         return pci_default_setup(priv, board, port, idx);
1879 }
1880
1881 static int
1882 pci_wch_ch38x_setup(struct serial_private *priv,
1883                     const struct pciserial_board *board,
1884                     struct uart_8250_port *port, int idx)
1885 {
1886         port->port.flags |= UPF_FIXED_TYPE;
1887         port->port.type = PORT_16850;
1888         return pci_default_setup(priv, board, port, idx);
1889 }
1890
1891 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1892 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1893 #define PCI_DEVICE_ID_OCTPRO            0x0001
1894 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1895 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1896 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1897 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1898 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1899 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1900 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1901 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1902 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1903 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1904 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1905 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1906 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1907 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1908 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1909 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1910 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1911 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1912 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1913 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1914 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1915 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1916 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1917 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1918 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1919 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1920 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1921 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1922 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1923 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1924 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1925 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1926 #define PCI_VENDOR_ID_WCH               0x4348
1927 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1928 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1929 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1930 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1931 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1932 #define PCI_VENDOR_ID_AGESTAR           0x5372
1933 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1934 #define PCI_VENDOR_ID_ASIX              0x9710
1935 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1936 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1937 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1938 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1939 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1940 #define PCI_DEVICE_ID_INTEL_QRK_UART    0x0936
1941
1942 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1943 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1944
1945 #define PCIE_VENDOR_ID_WCH              0x1c00
1946 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1947 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
1948 #define PCIE_DEVICE_ID_WCH_CH382_2S     0x3253
1949
1950 #define PCI_VENDOR_ID_PERICOM                   0x12D8
1951 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
1952 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
1953 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
1954 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
1955
1956 #define PCI_VENDOR_ID_ACCESIO                   0x494f
1957 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB     0x1051
1958 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S      0x1053
1959 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB     0x105C
1960 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S      0x105E
1961 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB   0x1091
1962 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2    0x1093
1963 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB   0x1099
1964 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4    0x109B
1965 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB    0x10D1
1966 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM     0x10D3
1967 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB    0x10DA
1968 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM     0x10DC
1969 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1    0x1108
1970 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2    0x1110
1971 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2    0x1111
1972 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4    0x1118
1973 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4    0x1119
1974 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S       0x1152
1975 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S       0x115A
1976 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2     0x1190
1977 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2    0x1191
1978 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4     0x1198
1979 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4    0x1199
1980 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM      0x11D0
1981 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4     0x105A
1982 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4     0x105B
1983 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8     0x106A
1984 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8     0x106B
1985 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4     0x1098
1986 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8     0x10A9
1987 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM      0x10D9
1988 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM      0x10E9
1989 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM      0x11D8
1990
1991
1992
1993 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1994 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1995 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1996
1997 /*
1998  * Master list of serial port init/setup/exit quirks.
1999  * This does not describe the general nature of the port.
2000  * (ie, baud base, number and location of ports, etc)
2001  *
2002  * This list is ordered alphabetically by vendor then device.
2003  * Specific entries must come before more generic entries.
2004  */
2005 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
2006         /*
2007         * ADDI-DATA GmbH communication cards <info@addi-data.com>
2008         */
2009         {
2010                 .vendor         = PCI_VENDOR_ID_AMCC,
2011                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2012                 .subvendor      = PCI_ANY_ID,
2013                 .subdevice      = PCI_ANY_ID,
2014                 .setup          = addidata_apci7800_setup,
2015         },
2016         /*
2017          * AFAVLAB cards - these may be called via parport_serial
2018          *  It is not clear whether this applies to all products.
2019          */
2020         {
2021                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
2022                 .device         = PCI_ANY_ID,
2023                 .subvendor      = PCI_ANY_ID,
2024                 .subdevice      = PCI_ANY_ID,
2025                 .setup          = afavlab_setup,
2026         },
2027         /*
2028          * HP Diva
2029          */
2030         {
2031                 .vendor         = PCI_VENDOR_ID_HP,
2032                 .device         = PCI_DEVICE_ID_HP_DIVA,
2033                 .subvendor      = PCI_ANY_ID,
2034                 .subdevice      = PCI_ANY_ID,
2035                 .init           = pci_hp_diva_init,
2036                 .setup          = pci_hp_diva_setup,
2037         },
2038         /*
2039          * Intel
2040          */
2041         {
2042                 .vendor         = PCI_VENDOR_ID_INTEL,
2043                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
2044                 .subvendor      = 0xe4bf,
2045                 .subdevice      = PCI_ANY_ID,
2046                 .init           = pci_inteli960ni_init,
2047                 .setup          = pci_default_setup,
2048         },
2049         {
2050                 .vendor         = PCI_VENDOR_ID_INTEL,
2051                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
2052                 .subvendor      = PCI_ANY_ID,
2053                 .subdevice      = PCI_ANY_ID,
2054                 .setup          = skip_tx_en_setup,
2055         },
2056         {
2057                 .vendor         = PCI_VENDOR_ID_INTEL,
2058                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
2059                 .subvendor      = PCI_ANY_ID,
2060                 .subdevice      = PCI_ANY_ID,
2061                 .setup          = skip_tx_en_setup,
2062         },
2063         {
2064                 .vendor         = PCI_VENDOR_ID_INTEL,
2065                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2066                 .subvendor      = PCI_ANY_ID,
2067                 .subdevice      = PCI_ANY_ID,
2068                 .setup          = skip_tx_en_setup,
2069         },
2070         {
2071                 .vendor         = PCI_VENDOR_ID_INTEL,
2072                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2073                 .subvendor      = PCI_ANY_ID,
2074                 .subdevice      = PCI_ANY_ID,
2075                 .setup          = ce4100_serial_setup,
2076         },
2077         {
2078                 .vendor         = PCI_VENDOR_ID_INTEL,
2079                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2080                 .subvendor      = PCI_ANY_ID,
2081                 .subdevice      = PCI_ANY_ID,
2082                 .setup          = kt_serial_setup,
2083         },
2084         {
2085                 .vendor         = PCI_VENDOR_ID_INTEL,
2086                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART1,
2087                 .subvendor      = PCI_ANY_ID,
2088                 .subdevice      = PCI_ANY_ID,
2089                 .setup          = byt_serial_setup,
2090         },
2091         {
2092                 .vendor         = PCI_VENDOR_ID_INTEL,
2093                 .device         = PCI_DEVICE_ID_INTEL_BYT_UART2,
2094                 .subvendor      = PCI_ANY_ID,
2095                 .subdevice      = PCI_ANY_ID,
2096                 .setup          = byt_serial_setup,
2097         },
2098         {
2099                 .vendor         = PCI_VENDOR_ID_INTEL,
2100                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART1,
2101                 .subvendor      = PCI_ANY_ID,
2102                 .subdevice      = PCI_ANY_ID,
2103                 .setup          = byt_serial_setup,
2104         },
2105         {
2106                 .vendor         = PCI_VENDOR_ID_INTEL,
2107                 .device         = PCI_DEVICE_ID_INTEL_BSW_UART2,
2108                 .subvendor      = PCI_ANY_ID,
2109                 .subdevice      = PCI_ANY_ID,
2110                 .setup          = byt_serial_setup,
2111         },
2112         {
2113                 .vendor         = PCI_VENDOR_ID_INTEL,
2114                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART1,
2115                 .subvendor      = PCI_ANY_ID,
2116                 .subdevice      = PCI_ANY_ID,
2117                 .setup          = byt_serial_setup,
2118         },
2119         {
2120                 .vendor         = PCI_VENDOR_ID_INTEL,
2121                 .device         = PCI_DEVICE_ID_INTEL_BDW_UART2,
2122                 .subvendor      = PCI_ANY_ID,
2123                 .subdevice      = PCI_ANY_ID,
2124                 .setup          = byt_serial_setup,
2125         },
2126         /*
2127          * ITE
2128          */
2129         {
2130                 .vendor         = PCI_VENDOR_ID_ITE,
2131                 .device         = PCI_DEVICE_ID_ITE_8872,
2132                 .subvendor      = PCI_ANY_ID,
2133                 .subdevice      = PCI_ANY_ID,
2134                 .init           = pci_ite887x_init,
2135                 .setup          = pci_default_setup,
2136                 .exit           = pci_ite887x_exit,
2137         },
2138         /*
2139          * National Instruments
2140          */
2141         {
2142                 .vendor         = PCI_VENDOR_ID_NI,
2143                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2144                 .subvendor      = PCI_ANY_ID,
2145                 .subdevice      = PCI_ANY_ID,
2146                 .init           = pci_ni8420_init,
2147                 .setup          = pci_default_setup,
2148                 .exit           = pci_ni8420_exit,
2149         },
2150         {
2151                 .vendor         = PCI_VENDOR_ID_NI,
2152                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2153                 .subvendor      = PCI_ANY_ID,
2154                 .subdevice      = PCI_ANY_ID,
2155                 .init           = pci_ni8420_init,
2156                 .setup          = pci_default_setup,
2157                 .exit           = pci_ni8420_exit,
2158         },
2159         {
2160                 .vendor         = PCI_VENDOR_ID_NI,
2161                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2162                 .subvendor      = PCI_ANY_ID,
2163                 .subdevice      = PCI_ANY_ID,
2164                 .init           = pci_ni8420_init,
2165                 .setup          = pci_default_setup,
2166                 .exit           = pci_ni8420_exit,
2167         },
2168         {
2169                 .vendor         = PCI_VENDOR_ID_NI,
2170                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2171                 .subvendor      = PCI_ANY_ID,
2172                 .subdevice      = PCI_ANY_ID,
2173                 .init           = pci_ni8420_init,
2174                 .setup          = pci_default_setup,
2175                 .exit           = pci_ni8420_exit,
2176         },
2177         {
2178                 .vendor         = PCI_VENDOR_ID_NI,
2179                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2180                 .subvendor      = PCI_ANY_ID,
2181                 .subdevice      = PCI_ANY_ID,
2182                 .init           = pci_ni8420_init,
2183                 .setup          = pci_default_setup,
2184                 .exit           = pci_ni8420_exit,
2185         },
2186         {
2187                 .vendor         = PCI_VENDOR_ID_NI,
2188                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2189                 .subvendor      = PCI_ANY_ID,
2190                 .subdevice      = PCI_ANY_ID,
2191                 .init           = pci_ni8420_init,
2192                 .setup          = pci_default_setup,
2193                 .exit           = pci_ni8420_exit,
2194         },
2195         {
2196                 .vendor         = PCI_VENDOR_ID_NI,
2197                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2198                 .subvendor      = PCI_ANY_ID,
2199                 .subdevice      = PCI_ANY_ID,
2200                 .init           = pci_ni8420_init,
2201                 .setup          = pci_default_setup,
2202                 .exit           = pci_ni8420_exit,
2203         },
2204         {
2205                 .vendor         = PCI_VENDOR_ID_NI,
2206                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2207                 .subvendor      = PCI_ANY_ID,
2208                 .subdevice      = PCI_ANY_ID,
2209                 .init           = pci_ni8420_init,
2210                 .setup          = pci_default_setup,
2211                 .exit           = pci_ni8420_exit,
2212         },
2213         {
2214                 .vendor         = PCI_VENDOR_ID_NI,
2215                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2216                 .subvendor      = PCI_ANY_ID,
2217                 .subdevice      = PCI_ANY_ID,
2218                 .init           = pci_ni8420_init,
2219                 .setup          = pci_default_setup,
2220                 .exit           = pci_ni8420_exit,
2221         },
2222         {
2223                 .vendor         = PCI_VENDOR_ID_NI,
2224                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2225                 .subvendor      = PCI_ANY_ID,
2226                 .subdevice      = PCI_ANY_ID,
2227                 .init           = pci_ni8420_init,
2228                 .setup          = pci_default_setup,
2229                 .exit           = pci_ni8420_exit,
2230         },
2231         {
2232                 .vendor         = PCI_VENDOR_ID_NI,
2233                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2234                 .subvendor      = PCI_ANY_ID,
2235                 .subdevice      = PCI_ANY_ID,
2236                 .init           = pci_ni8420_init,
2237                 .setup          = pci_default_setup,
2238                 .exit           = pci_ni8420_exit,
2239         },
2240         {
2241                 .vendor         = PCI_VENDOR_ID_NI,
2242                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2243                 .subvendor      = PCI_ANY_ID,
2244                 .subdevice      = PCI_ANY_ID,
2245                 .init           = pci_ni8420_init,
2246                 .setup          = pci_default_setup,
2247                 .exit           = pci_ni8420_exit,
2248         },
2249         {
2250                 .vendor         = PCI_VENDOR_ID_NI,
2251                 .device         = PCI_ANY_ID,
2252                 .subvendor      = PCI_ANY_ID,
2253                 .subdevice      = PCI_ANY_ID,
2254                 .init           = pci_ni8430_init,
2255                 .setup          = pci_ni8430_setup,
2256                 .exit           = pci_ni8430_exit,
2257         },
2258         /* Quatech */
2259         {
2260                 .vendor         = PCI_VENDOR_ID_QUATECH,
2261                 .device         = PCI_ANY_ID,
2262                 .subvendor      = PCI_ANY_ID,
2263                 .subdevice      = PCI_ANY_ID,
2264                 .init           = pci_quatech_init,
2265                 .setup          = pci_quatech_setup,
2266                 .exit           = pci_quatech_exit,
2267         },
2268         /*
2269          * Panacom
2270          */
2271         {
2272                 .vendor         = PCI_VENDOR_ID_PANACOM,
2273                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2274                 .subvendor      = PCI_ANY_ID,
2275                 .subdevice      = PCI_ANY_ID,
2276                 .init           = pci_plx9050_init,
2277                 .setup          = pci_default_setup,
2278                 .exit           = pci_plx9050_exit,
2279         },
2280         {
2281                 .vendor         = PCI_VENDOR_ID_PANACOM,
2282                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2283                 .subvendor      = PCI_ANY_ID,
2284                 .subdevice      = PCI_ANY_ID,
2285                 .init           = pci_plx9050_init,
2286                 .setup          = pci_default_setup,
2287                 .exit           = pci_plx9050_exit,
2288         },
2289         /*
2290          * Pericom
2291          */
2292         {
2293                 .vendor         = PCI_VENDOR_ID_PERICOM,
2294                 .device         = PCI_ANY_ID,
2295                 .subvendor      = PCI_ANY_ID,
2296                 .subdevice      = PCI_ANY_ID,
2297                 .setup          = pci_pericom_setup,
2298         },
2299         /*
2300          * PLX
2301          */
2302         {
2303                 .vendor         = PCI_VENDOR_ID_PLX,
2304                 .device         = PCI_DEVICE_ID_PLX_9050,
2305                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2306                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2307                 .init           = pci_plx9050_init,
2308                 .setup          = pci_default_setup,
2309                 .exit           = pci_plx9050_exit,
2310         },
2311         {
2312                 .vendor         = PCI_VENDOR_ID_PLX,
2313                 .device         = PCI_DEVICE_ID_PLX_9050,
2314                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2315                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2316                 .init           = pci_plx9050_init,
2317                 .setup          = pci_default_setup,
2318                 .exit           = pci_plx9050_exit,
2319         },
2320         {
2321                 .vendor         = PCI_VENDOR_ID_PLX,
2322                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2323                 .subvendor      = PCI_VENDOR_ID_PLX,
2324                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2325                 .init           = pci_plx9050_init,
2326                 .setup          = pci_default_setup,
2327                 .exit           = pci_plx9050_exit,
2328         },
2329         {
2330                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2331                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2332                 .subvendor  = PCI_ANY_ID,
2333                 .subdevice  = PCI_ANY_ID,
2334                 .setup      = pci_pericom_setup,
2335         },
2336         {
2337                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2338                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2339                 .subvendor  = PCI_ANY_ID,
2340                 .subdevice  = PCI_ANY_ID,
2341                 .setup      = pci_pericom_setup,
2342         },
2343         {
2344                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2345                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2346                 .subvendor  = PCI_ANY_ID,
2347                 .subdevice  = PCI_ANY_ID,
2348                 .setup      = pci_pericom_setup,
2349         },
2350         {
2351                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2352                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2353                 .subvendor  = PCI_ANY_ID,
2354                 .subdevice  = PCI_ANY_ID,
2355                 .setup      = pci_pericom_setup,
2356         },
2357         {
2358                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2359                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2360                 .subvendor  = PCI_ANY_ID,
2361                 .subdevice  = PCI_ANY_ID,
2362                 .setup      = pci_pericom_setup,
2363         },
2364         {
2365                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2366                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2367                 .subvendor  = PCI_ANY_ID,
2368                 .subdevice  = PCI_ANY_ID,
2369                 .setup      = pci_pericom_setup,
2370         },
2371         {
2372                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2373                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2374                 .subvendor  = PCI_ANY_ID,
2375                 .subdevice  = PCI_ANY_ID,
2376                 .setup      = pci_pericom_setup,
2377         },
2378         {
2379                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2380                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2381                 .subvendor  = PCI_ANY_ID,
2382                 .subdevice  = PCI_ANY_ID,
2383                 .setup      = pci_pericom_setup,
2384         },
2385         {
2386                 .vendor     = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2387                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2388                 .subvendor  = PCI_ANY_ID,
2389                 .subdevice  = PCI_ANY_ID,
2390                 .setup      = pci_pericom_setup,
2391         },
2392         {
2393                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2394                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2395                 .subvendor  = PCI_ANY_ID,
2396                 .subdevice  = PCI_ANY_ID,
2397                 .setup      = pci_pericom_setup,
2398         },
2399         {
2400                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2401                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2402                 .subvendor  = PCI_ANY_ID,
2403                 .subdevice  = PCI_ANY_ID,
2404                 .setup      = pci_pericom_setup,
2405         },
2406         {
2407                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2408                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2409                 .subvendor  = PCI_ANY_ID,
2410                 .subdevice  = PCI_ANY_ID,
2411                 .setup      = pci_pericom_setup,
2412         },
2413         {
2414                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2415                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2416                 .subvendor  = PCI_ANY_ID,
2417                 .subdevice  = PCI_ANY_ID,
2418                 .setup      = pci_pericom_setup,
2419         },
2420         {
2421                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2422                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2423                 .subvendor  = PCI_ANY_ID,
2424                 .subdevice  = PCI_ANY_ID,
2425                 .setup      = pci_pericom_setup,
2426         },
2427         {
2428                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2429                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2430                 .subvendor  = PCI_ANY_ID,
2431                 .subdevice  = PCI_ANY_ID,
2432                 .setup      = pci_pericom_setup,
2433         },
2434         /*
2435          * SBS Technologies, Inc., PMC-OCTALPRO 232
2436          */
2437         {
2438                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2439                 .device         = PCI_DEVICE_ID_OCTPRO,
2440                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2441                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2442                 .init           = sbs_init,
2443                 .setup          = sbs_setup,
2444                 .exit           = sbs_exit,
2445         },
2446         /*
2447          * SBS Technologies, Inc., PMC-OCTALPRO 422
2448          */
2449         {
2450                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2451                 .device         = PCI_DEVICE_ID_OCTPRO,
2452                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2453                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2454                 .init           = sbs_init,
2455                 .setup          = sbs_setup,
2456                 .exit           = sbs_exit,
2457         },
2458         /*
2459          * SBS Technologies, Inc., P-Octal 232
2460          */
2461         {
2462                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2463                 .device         = PCI_DEVICE_ID_OCTPRO,
2464                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2465                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2466                 .init           = sbs_init,
2467                 .setup          = sbs_setup,
2468                 .exit           = sbs_exit,
2469         },
2470         /*
2471          * SBS Technologies, Inc., P-Octal 422
2472          */
2473         {
2474                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2475                 .device         = PCI_DEVICE_ID_OCTPRO,
2476                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2477                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2478                 .init           = sbs_init,
2479                 .setup          = sbs_setup,
2480                 .exit           = sbs_exit,
2481         },
2482         /*
2483          * SIIG cards - these may be called via parport_serial
2484          */
2485         {
2486                 .vendor         = PCI_VENDOR_ID_SIIG,
2487                 .device         = PCI_ANY_ID,
2488                 .subvendor      = PCI_ANY_ID,
2489                 .subdevice      = PCI_ANY_ID,
2490                 .init           = pci_siig_init,
2491                 .setup          = pci_siig_setup,
2492         },
2493         /*
2494          * Titan cards
2495          */
2496         {
2497                 .vendor         = PCI_VENDOR_ID_TITAN,
2498                 .device         = PCI_DEVICE_ID_TITAN_400L,
2499                 .subvendor      = PCI_ANY_ID,
2500                 .subdevice      = PCI_ANY_ID,
2501                 .setup          = titan_400l_800l_setup,
2502         },
2503         {
2504                 .vendor         = PCI_VENDOR_ID_TITAN,
2505                 .device         = PCI_DEVICE_ID_TITAN_800L,
2506                 .subvendor      = PCI_ANY_ID,
2507                 .subdevice      = PCI_ANY_ID,
2508                 .setup          = titan_400l_800l_setup,
2509         },
2510         /*
2511          * Timedia cards
2512          */
2513         {
2514                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2515                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2516                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2517                 .subdevice      = PCI_ANY_ID,
2518                 .probe          = pci_timedia_probe,
2519                 .init           = pci_timedia_init,
2520                 .setup          = pci_timedia_setup,
2521         },
2522         {
2523                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2524                 .device         = PCI_ANY_ID,
2525                 .subvendor      = PCI_ANY_ID,
2526                 .subdevice      = PCI_ANY_ID,
2527                 .setup          = pci_timedia_setup,
2528         },
2529         /*
2530          * SUNIX (Timedia) cards
2531          * Do not "probe" for these cards as there is at least one combination
2532          * card that should be handled by parport_pc that doesn't match the
2533          * rule in pci_timedia_probe.
2534          * It is part number is MIO5079A but its subdevice ID is 0x0102.
2535          * There are some boards with part number SER5037AL that report
2536          * subdevice ID 0x0002.
2537          */
2538         {
2539                 .vendor         = PCI_VENDOR_ID_SUNIX,
2540                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2541                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2542                 .subdevice      = PCI_ANY_ID,
2543                 .init           = pci_timedia_init,
2544                 .setup          = pci_timedia_setup,
2545         },
2546         /*
2547          * Exar cards
2548          */
2549         {
2550                 .vendor = PCI_VENDOR_ID_EXAR,
2551                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2552                 .subvendor      = PCI_ANY_ID,
2553                 .subdevice      = PCI_ANY_ID,
2554                 .setup          = pci_xr17c154_setup,
2555         },
2556         {
2557                 .vendor = PCI_VENDOR_ID_EXAR,
2558                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2559                 .subvendor      = PCI_ANY_ID,
2560                 .subdevice      = PCI_ANY_ID,
2561                 .setup          = pci_xr17c154_setup,
2562         },
2563         {
2564                 .vendor = PCI_VENDOR_ID_EXAR,
2565                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2566                 .subvendor      = PCI_ANY_ID,
2567                 .subdevice      = PCI_ANY_ID,
2568                 .setup          = pci_xr17c154_setup,
2569         },
2570         {
2571                 .vendor = PCI_VENDOR_ID_EXAR,
2572                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2573                 .subvendor      = PCI_ANY_ID,
2574                 .subdevice      = PCI_ANY_ID,
2575                 .setup          = pci_xr17v35x_setup,
2576         },
2577         {
2578                 .vendor = PCI_VENDOR_ID_EXAR,
2579                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2580                 .subvendor      = PCI_ANY_ID,
2581                 .subdevice      = PCI_ANY_ID,
2582                 .setup          = pci_xr17v35x_setup,
2583         },
2584         {
2585                 .vendor = PCI_VENDOR_ID_EXAR,
2586                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2587                 .subvendor      = PCI_ANY_ID,
2588                 .subdevice      = PCI_ANY_ID,
2589                 .setup          = pci_xr17v35x_setup,
2590         },
2591         {
2592                 .vendor = PCI_VENDOR_ID_EXAR,
2593                 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2594                 .subvendor      = PCI_ANY_ID,
2595                 .subdevice      = PCI_ANY_ID,
2596                 .setup          = pci_xr17v35x_setup,
2597         },
2598         {
2599                 .vendor = PCI_VENDOR_ID_EXAR,
2600                 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2601                 .subvendor      = PCI_ANY_ID,
2602                 .subdevice      = PCI_ANY_ID,
2603                 .setup          = pci_xr17v35x_setup,
2604         },
2605         /*
2606          * Xircom cards
2607          */
2608         {
2609                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2610                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2611                 .subvendor      = PCI_ANY_ID,
2612                 .subdevice      = PCI_ANY_ID,
2613                 .init           = pci_xircom_init,
2614                 .setup          = pci_default_setup,
2615         },
2616         /*
2617          * Netmos cards - these may be called via parport_serial
2618          */
2619         {
2620                 .vendor         = PCI_VENDOR_ID_NETMOS,
2621                 .device         = PCI_ANY_ID,
2622                 .subvendor      = PCI_ANY_ID,
2623                 .subdevice      = PCI_ANY_ID,
2624                 .init           = pci_netmos_init,
2625                 .setup          = pci_netmos_9900_setup,
2626         },
2627         /*
2628          * EndRun Technologies
2629         */
2630         {
2631                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2632                 .device         = PCI_ANY_ID,
2633                 .subvendor      = PCI_ANY_ID,
2634                 .subdevice      = PCI_ANY_ID,
2635                 .init           = pci_endrun_init,
2636                 .setup          = pci_default_setup,
2637         },
2638         /*
2639          * For Oxford Semiconductor Tornado based devices
2640          */
2641         {
2642                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2643                 .device         = PCI_ANY_ID,
2644                 .subvendor      = PCI_ANY_ID,
2645                 .subdevice      = PCI_ANY_ID,
2646                 .init           = pci_oxsemi_tornado_init,
2647                 .setup          = pci_default_setup,
2648         },
2649         {
2650                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2651                 .device         = PCI_ANY_ID,
2652                 .subvendor      = PCI_ANY_ID,
2653                 .subdevice      = PCI_ANY_ID,
2654                 .init           = pci_oxsemi_tornado_init,
2655                 .setup          = pci_default_setup,
2656         },
2657         {
2658                 .vendor         = PCI_VENDOR_ID_DIGI,
2659                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2660                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2661                 .subdevice              = PCI_ANY_ID,
2662                 .init                   = pci_oxsemi_tornado_init,
2663                 .setup          = pci_default_setup,
2664         },
2665         {
2666                 .vendor         = PCI_VENDOR_ID_INTEL,
2667                 .device         = 0x8811,
2668                 .subvendor      = PCI_ANY_ID,
2669                 .subdevice      = PCI_ANY_ID,
2670                 .init           = pci_eg20t_init,
2671                 .setup          = pci_default_setup,
2672         },
2673         {
2674                 .vendor         = PCI_VENDOR_ID_INTEL,
2675                 .device         = 0x8812,
2676                 .subvendor      = PCI_ANY_ID,
2677                 .subdevice      = PCI_ANY_ID,
2678                 .init           = pci_eg20t_init,
2679                 .setup          = pci_default_setup,
2680         },
2681         {
2682                 .vendor         = PCI_VENDOR_ID_INTEL,
2683                 .device         = 0x8813,
2684                 .subvendor      = PCI_ANY_ID,
2685                 .subdevice      = PCI_ANY_ID,
2686                 .init           = pci_eg20t_init,
2687                 .setup          = pci_default_setup,
2688         },
2689         {
2690                 .vendor         = PCI_VENDOR_ID_INTEL,
2691                 .device         = 0x8814,
2692                 .subvendor      = PCI_ANY_ID,
2693                 .subdevice      = PCI_ANY_ID,
2694                 .init           = pci_eg20t_init,
2695                 .setup          = pci_default_setup,
2696         },
2697         {
2698                 .vendor         = 0x10DB,
2699                 .device         = 0x8027,
2700                 .subvendor      = PCI_ANY_ID,
2701                 .subdevice      = PCI_ANY_ID,
2702                 .init           = pci_eg20t_init,
2703                 .setup          = pci_default_setup,
2704         },
2705         {
2706                 .vendor         = 0x10DB,
2707                 .device         = 0x8028,
2708                 .subvendor      = PCI_ANY_ID,
2709                 .subdevice      = PCI_ANY_ID,
2710                 .init           = pci_eg20t_init,
2711                 .setup          = pci_default_setup,
2712         },
2713         {
2714                 .vendor         = 0x10DB,
2715                 .device         = 0x8029,
2716                 .subvendor      = PCI_ANY_ID,
2717                 .subdevice      = PCI_ANY_ID,
2718                 .init           = pci_eg20t_init,
2719                 .setup          = pci_default_setup,
2720         },
2721         {
2722                 .vendor         = 0x10DB,
2723                 .device         = 0x800C,
2724                 .subvendor      = PCI_ANY_ID,
2725                 .subdevice      = PCI_ANY_ID,
2726                 .init           = pci_eg20t_init,
2727                 .setup          = pci_default_setup,
2728         },
2729         {
2730                 .vendor         = 0x10DB,
2731                 .device         = 0x800D,
2732                 .subvendor      = PCI_ANY_ID,
2733                 .subdevice      = PCI_ANY_ID,
2734                 .init           = pci_eg20t_init,
2735                 .setup          = pci_default_setup,
2736         },
2737         /*
2738          * Cronyx Omega PCI (PLX-chip based)
2739          */
2740         {
2741                 .vendor         = PCI_VENDOR_ID_PLX,
2742                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2743                 .subvendor      = PCI_ANY_ID,
2744                 .subdevice      = PCI_ANY_ID,
2745                 .setup          = pci_omegapci_setup,
2746         },
2747         /* WCH CH353 1S1P card (16550 clone) */
2748         {
2749                 .vendor         = PCI_VENDOR_ID_WCH,
2750                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2751                 .subvendor      = PCI_ANY_ID,
2752                 .subdevice      = PCI_ANY_ID,
2753                 .setup          = pci_wch_ch353_setup,
2754         },
2755         /* WCH CH353 2S1P card (16550 clone) */
2756         {
2757                 .vendor         = PCI_VENDOR_ID_WCH,
2758                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2759                 .subvendor      = PCI_ANY_ID,
2760                 .subdevice      = PCI_ANY_ID,
2761                 .setup          = pci_wch_ch353_setup,
2762         },
2763         /* WCH CH353 4S card (16550 clone) */
2764         {
2765                 .vendor         = PCI_VENDOR_ID_WCH,
2766                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2767                 .subvendor      = PCI_ANY_ID,
2768                 .subdevice      = PCI_ANY_ID,
2769                 .setup          = pci_wch_ch353_setup,
2770         },
2771         /* WCH CH353 2S1PF card (16550 clone) */
2772         {
2773                 .vendor         = PCI_VENDOR_ID_WCH,
2774                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2775                 .subvendor      = PCI_ANY_ID,
2776                 .subdevice      = PCI_ANY_ID,
2777                 .setup          = pci_wch_ch353_setup,
2778         },
2779         /* WCH CH352 2S card (16550 clone) */
2780         {
2781                 .vendor         = PCI_VENDOR_ID_WCH,
2782                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2783                 .subvendor      = PCI_ANY_ID,
2784                 .subdevice      = PCI_ANY_ID,
2785                 .setup          = pci_wch_ch353_setup,
2786         },
2787         /* WCH CH382 2S card (16850 clone) */
2788         {
2789                 .vendor         = PCIE_VENDOR_ID_WCH,
2790                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2791                 .subvendor      = PCI_ANY_ID,
2792                 .subdevice      = PCI_ANY_ID,
2793                 .setup          = pci_wch_ch38x_setup,
2794         },
2795         /* WCH CH382 2S1P card (16850 clone) */
2796         {
2797                 .vendor         = PCIE_VENDOR_ID_WCH,
2798                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2799                 .subvendor      = PCI_ANY_ID,
2800                 .subdevice      = PCI_ANY_ID,
2801                 .setup          = pci_wch_ch38x_setup,
2802         },
2803         /* WCH CH384 4S card (16850 clone) */
2804         {
2805                 .vendor         = PCIE_VENDOR_ID_WCH,
2806                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2807                 .subvendor      = PCI_ANY_ID,
2808                 .subdevice      = PCI_ANY_ID,
2809                 .setup          = pci_wch_ch38x_setup,
2810         },
2811         /*
2812          * ASIX devices with FIFO bug
2813          */
2814         {
2815                 .vendor         = PCI_VENDOR_ID_ASIX,
2816                 .device         = PCI_ANY_ID,
2817                 .subvendor      = PCI_ANY_ID,
2818                 .subdevice      = PCI_ANY_ID,
2819                 .setup          = pci_asix_setup,
2820         },
2821         /*
2822          * Commtech, Inc. Fastcom adapters
2823          *
2824          */
2825         {
2826                 .vendor = PCI_VENDOR_ID_COMMTECH,
2827                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2828                 .subvendor      = PCI_ANY_ID,
2829                 .subdevice      = PCI_ANY_ID,
2830                 .setup          = pci_fastcom335_setup,
2831         },
2832         {
2833                 .vendor = PCI_VENDOR_ID_COMMTECH,
2834                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2835                 .subvendor      = PCI_ANY_ID,
2836                 .subdevice      = PCI_ANY_ID,
2837                 .setup          = pci_fastcom335_setup,
2838         },
2839         {
2840                 .vendor = PCI_VENDOR_ID_COMMTECH,
2841                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2842                 .subvendor      = PCI_ANY_ID,
2843                 .subdevice      = PCI_ANY_ID,
2844                 .setup          = pci_fastcom335_setup,
2845         },
2846         {
2847                 .vendor = PCI_VENDOR_ID_COMMTECH,
2848                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2849                 .subvendor      = PCI_ANY_ID,
2850                 .subdevice      = PCI_ANY_ID,
2851                 .setup          = pci_fastcom335_setup,
2852         },
2853         {
2854                 .vendor = PCI_VENDOR_ID_COMMTECH,
2855                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2856                 .subvendor      = PCI_ANY_ID,
2857                 .subdevice      = PCI_ANY_ID,
2858                 .setup          = pci_xr17v35x_setup,
2859         },
2860         {
2861                 .vendor = PCI_VENDOR_ID_COMMTECH,
2862                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2863                 .subvendor      = PCI_ANY_ID,
2864                 .subdevice      = PCI_ANY_ID,
2865                 .setup          = pci_xr17v35x_setup,
2866         },
2867         {
2868                 .vendor = PCI_VENDOR_ID_COMMTECH,
2869                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2870                 .subvendor      = PCI_ANY_ID,
2871                 .subdevice      = PCI_ANY_ID,
2872                 .setup          = pci_xr17v35x_setup,
2873         },
2874         /*
2875          * Broadcom TruManage (NetXtreme)
2876          */
2877         {
2878                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2879                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2880                 .subvendor      = PCI_ANY_ID,
2881                 .subdevice      = PCI_ANY_ID,
2882                 .setup          = pci_brcm_trumanage_setup,
2883         },
2884         {
2885                 .vendor         = 0x1c29,
2886                 .device         = 0x1104,
2887                 .subvendor      = PCI_ANY_ID,
2888                 .subdevice      = PCI_ANY_ID,
2889                 .setup          = pci_fintek_setup,
2890                 .init           = pci_fintek_init,
2891         },
2892         {
2893                 .vendor         = 0x1c29,
2894                 .device         = 0x1108,
2895                 .subvendor      = PCI_ANY_ID,
2896                 .subdevice      = PCI_ANY_ID,
2897                 .setup          = pci_fintek_setup,
2898                 .init           = pci_fintek_init,
2899         },
2900         {
2901                 .vendor         = 0x1c29,
2902                 .device         = 0x1112,
2903                 .subvendor      = PCI_ANY_ID,
2904                 .subdevice      = PCI_ANY_ID,
2905                 .setup          = pci_fintek_setup,
2906                 .init           = pci_fintek_init,
2907         },
2908
2909         /*
2910          * Default "match everything" terminator entry
2911          */
2912         {
2913                 .vendor         = PCI_ANY_ID,
2914                 .device         = PCI_ANY_ID,
2915                 .subvendor      = PCI_ANY_ID,
2916                 .subdevice      = PCI_ANY_ID,
2917                 .setup          = pci_default_setup,
2918         }
2919 };
2920
2921 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2922 {
2923         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2924 }
2925
2926 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2927 {
2928         struct pci_serial_quirk *quirk;
2929
2930         for (quirk = pci_serial_quirks; ; quirk++)
2931                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2932                     quirk_id_matches(quirk->device, dev->device) &&
2933                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2934                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2935                         break;
2936         return quirk;
2937 }
2938
2939 static inline int get_pci_irq(struct pci_dev *dev,
2940                                 const struct pciserial_board *board)
2941 {
2942         if (board->flags & FL_NOIRQ)
2943                 return 0;
2944         else
2945                 return dev->irq;
2946 }
2947
2948 /*
2949  * This is the configuration table for all of the PCI serial boards
2950  * which we support.  It is directly indexed by the pci_board_num_t enum
2951  * value, which is encoded in the pci_device_id PCI probe table's
2952  * driver_data member.
2953  *
2954  * The makeup of these names are:
2955  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2956  *
2957  *  bn          = PCI BAR number
2958  *  bt          = Index using PCI BARs
2959  *  n           = number of serial ports
2960  *  baud        = baud rate
2961  *  offsetinhex = offset for each sequential port (in hex)
2962  *
2963  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2964  *
2965  * Please note: in theory if n = 1, _bt infix should make no difference.
2966  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2967  */
2968 enum pci_board_num_t {
2969         pbn_default = 0,
2970
2971         pbn_b0_1_115200,
2972         pbn_b0_2_115200,
2973         pbn_b0_4_115200,
2974         pbn_b0_5_115200,
2975         pbn_b0_8_115200,
2976
2977         pbn_b0_1_921600,
2978         pbn_b0_2_921600,
2979         pbn_b0_4_921600,
2980
2981         pbn_b0_2_1130000,
2982
2983         pbn_b0_4_1152000,
2984
2985         pbn_b0_2_1152000_200,
2986         pbn_b0_4_1152000_200,
2987         pbn_b0_8_1152000_200,
2988
2989         pbn_b0_4_1250000,
2990
2991         pbn_b0_2_1843200,
2992         pbn_b0_4_1843200,
2993
2994         pbn_b0_2_1843200_200,
2995         pbn_b0_4_1843200_200,
2996         pbn_b0_8_1843200_200,
2997
2998         pbn_b0_1_4000000,
2999
3000         pbn_b0_bt_1_115200,
3001         pbn_b0_bt_2_115200,
3002         pbn_b0_bt_4_115200,
3003         pbn_b0_bt_8_115200,
3004
3005         pbn_b0_bt_1_460800,
3006         pbn_b0_bt_2_460800,
3007         pbn_b0_bt_4_460800,
3008
3009         pbn_b0_bt_1_921600,
3010         pbn_b0_bt_2_921600,
3011         pbn_b0_bt_4_921600,
3012         pbn_b0_bt_8_921600,
3013
3014         pbn_b1_1_115200,
3015         pbn_b1_2_115200,
3016         pbn_b1_4_115200,
3017         pbn_b1_8_115200,
3018         pbn_b1_16_115200,
3019
3020         pbn_b1_1_921600,
3021         pbn_b1_2_921600,
3022         pbn_b1_4_921600,
3023         pbn_b1_8_921600,
3024
3025         pbn_b1_2_1250000,
3026
3027         pbn_b1_bt_1_115200,
3028         pbn_b1_bt_2_115200,
3029         pbn_b1_bt_4_115200,
3030
3031         pbn_b1_bt_2_921600,
3032
3033         pbn_b1_1_1382400,
3034         pbn_b1_2_1382400,
3035         pbn_b1_4_1382400,
3036         pbn_b1_8_1382400,
3037
3038         pbn_b2_1_115200,
3039         pbn_b2_2_115200,
3040         pbn_b2_4_115200,
3041         pbn_b2_8_115200,
3042
3043         pbn_b2_1_460800,
3044         pbn_b2_4_460800,
3045         pbn_b2_8_460800,
3046         pbn_b2_16_460800,
3047
3048         pbn_b2_1_921600,
3049         pbn_b2_4_921600,
3050         pbn_b2_8_921600,
3051
3052         pbn_b2_8_1152000,
3053
3054         pbn_b2_bt_1_115200,
3055         pbn_b2_bt_2_115200,
3056         pbn_b2_bt_4_115200,
3057
3058         pbn_b2_bt_2_921600,
3059         pbn_b2_bt_4_921600,
3060
3061         pbn_b3_2_115200,
3062         pbn_b3_4_115200,
3063         pbn_b3_8_115200,
3064
3065         pbn_b4_bt_2_921600,
3066         pbn_b4_bt_4_921600,
3067         pbn_b4_bt_8_921600,
3068
3069         /*
3070          * Board-specific versions.
3071          */
3072         pbn_panacom,
3073         pbn_panacom2,
3074         pbn_panacom4,
3075         pbn_plx_romulus,
3076         pbn_endrun_2_4000000,
3077         pbn_oxsemi,
3078         pbn_oxsemi_1_4000000,
3079         pbn_oxsemi_2_4000000,
3080         pbn_oxsemi_4_4000000,
3081         pbn_oxsemi_8_4000000,
3082         pbn_intel_i960,
3083         pbn_sgi_ioc3,
3084         pbn_computone_4,
3085         pbn_computone_6,
3086         pbn_computone_8,
3087         pbn_sbsxrsio,
3088         pbn_exar_XR17C152,
3089         pbn_exar_XR17C154,
3090         pbn_exar_XR17C158,
3091         pbn_exar_XR17V352,
3092         pbn_exar_XR17V354,
3093         pbn_exar_XR17V358,
3094         pbn_exar_XR17V4358,
3095         pbn_exar_XR17V8358,
3096         pbn_exar_ibm_saturn,
3097         pbn_pasemi_1682M,
3098         pbn_ni8430_2,
3099         pbn_ni8430_4,
3100         pbn_ni8430_8,
3101         pbn_ni8430_16,
3102         pbn_ADDIDATA_PCIe_1_3906250,
3103         pbn_ADDIDATA_PCIe_2_3906250,
3104         pbn_ADDIDATA_PCIe_4_3906250,
3105         pbn_ADDIDATA_PCIe_8_3906250,
3106         pbn_ce4100_1_115200,
3107         pbn_byt,
3108         pbn_qrk,
3109         pbn_omegapci,
3110         pbn_NETMOS9900_2s_115200,
3111         pbn_brcm_trumanage,
3112         pbn_fintek_4,
3113         pbn_fintek_8,
3114         pbn_fintek_12,
3115         pbn_wch382_2,
3116         pbn_wch384_4,
3117         pbn_pericom_PI7C9X7951,
3118         pbn_pericom_PI7C9X7952,
3119         pbn_pericom_PI7C9X7954,
3120         pbn_pericom_PI7C9X7958,
3121 };
3122
3123 /*
3124  * uart_offset - the space between channels
3125  * reg_shift   - describes how the UART registers are mapped
3126  *               to PCI memory by the card.
3127  * For example IER register on SBS, Inc. PMC-OctPro is located at
3128  * offset 0x10 from the UART base, while UART_IER is defined as 1
3129  * in include/linux/serial_reg.h,
3130  * see first lines of serial_in() and serial_out() in 8250.c
3131 */
3132
3133 static struct pciserial_board pci_boards[] = {
3134         [pbn_default] = {
3135                 .flags          = FL_BASE0,
3136                 .num_ports      = 1,
3137                 .base_baud      = 115200,
3138                 .uart_offset    = 8,
3139         },
3140         [pbn_b0_1_115200] = {
3141                 .flags          = FL_BASE0,
3142                 .num_ports      = 1,
3143                 .base_baud      = 115200,
3144                 .uart_offset    = 8,
3145         },
3146         [pbn_b0_2_115200] = {
3147                 .flags          = FL_BASE0,
3148                 .num_ports      = 2,
3149                 .base_baud      = 115200,
3150                 .uart_offset    = 8,
3151         },
3152         [pbn_b0_4_115200] = {
3153                 .flags          = FL_BASE0,
3154                 .num_ports      = 4,
3155                 .base_baud      = 115200,
3156                 .uart_offset    = 8,
3157         },
3158         [pbn_b0_5_115200] = {
3159                 .flags          = FL_BASE0,
3160                 .num_ports      = 5,
3161                 .base_baud      = 115200,
3162                 .uart_offset    = 8,
3163         },
3164         [pbn_b0_8_115200] = {
3165                 .flags          = FL_BASE0,
3166                 .num_ports      = 8,
3167                 .base_baud      = 115200,
3168                 .uart_offset    = 8,
3169         },
3170         [pbn_b0_1_921600] = {
3171                 .flags          = FL_BASE0,
3172                 .num_ports      = 1,
3173                 .base_baud      = 921600,
3174                 .uart_offset    = 8,
3175         },
3176         [pbn_b0_2_921600] = {
3177                 .flags          = FL_BASE0,
3178                 .num_ports      = 2,
3179                 .base_baud      = 921600,
3180                 .uart_offset    = 8,
3181         },
3182         [pbn_b0_4_921600] = {
3183                 .flags          = FL_BASE0,
3184                 .num_ports      = 4,
3185                 .base_baud      = 921600,
3186                 .uart_offset    = 8,
3187         },
3188
3189         [pbn_b0_2_1130000] = {
3190                 .flags          = FL_BASE0,
3191                 .num_ports      = 2,
3192                 .base_baud      = 1130000,
3193                 .uart_offset    = 8,
3194         },
3195
3196         [pbn_b0_4_1152000] = {
3197                 .flags          = FL_BASE0,
3198                 .num_ports      = 4,
3199                 .base_baud      = 1152000,
3200                 .uart_offset    = 8,
3201         },
3202
3203         [pbn_b0_2_1152000_200] = {
3204                 .flags          = FL_BASE0,
3205                 .num_ports      = 2,
3206                 .base_baud      = 1152000,
3207                 .uart_offset    = 0x200,
3208         },
3209
3210         [pbn_b0_4_1152000_200] = {
3211                 .flags          = FL_BASE0,
3212                 .num_ports      = 4,
3213                 .base_baud      = 1152000,
3214                 .uart_offset    = 0x200,
3215         },
3216
3217         [pbn_b0_8_1152000_200] = {
3218                 .flags          = FL_BASE0,
3219                 .num_ports      = 8,
3220                 .base_baud      = 1152000,
3221                 .uart_offset    = 0x200,
3222         },
3223
3224         [pbn_b0_4_1250000] = {
3225                 .flags          = FL_BASE0,
3226                 .num_ports      = 4,
3227                 .base_baud      = 1250000,
3228                 .uart_offset    = 8,
3229         },
3230
3231         [pbn_b0_2_1843200] = {
3232                 .flags          = FL_BASE0,
3233                 .num_ports      = 2,
3234                 .base_baud      = 1843200,
3235                 .uart_offset    = 8,
3236         },
3237         [pbn_b0_4_1843200] = {
3238                 .flags          = FL_BASE0,
3239                 .num_ports      = 4,
3240                 .base_baud      = 1843200,
3241                 .uart_offset    = 8,
3242         },
3243
3244         [pbn_b0_2_1843200_200] = {
3245                 .flags          = FL_BASE0,
3246                 .num_ports      = 2,
3247                 .base_baud      = 1843200,
3248                 .uart_offset    = 0x200,
3249         },
3250         [pbn_b0_4_1843200_200] = {
3251                 .flags          = FL_BASE0,
3252                 .num_ports      = 4,
3253                 .base_baud      = 1843200,
3254                 .uart_offset    = 0x200,
3255         },
3256         [pbn_b0_8_1843200_200] = {
3257                 .flags          = FL_BASE0,
3258                 .num_ports      = 8,
3259                 .base_baud      = 1843200,
3260                 .uart_offset    = 0x200,
3261         },
3262         [pbn_b0_1_4000000] = {
3263                 .flags          = FL_BASE0,
3264                 .num_ports      = 1,
3265                 .base_baud      = 4000000,
3266                 .uart_offset    = 8,
3267         },
3268
3269         [pbn_b0_bt_1_115200] = {
3270                 .flags          = FL_BASE0|FL_BASE_BARS,
3271                 .num_ports      = 1,
3272                 .base_baud      = 115200,
3273                 .uart_offset    = 8,
3274         },
3275         [pbn_b0_bt_2_115200] = {
3276                 .flags          = FL_BASE0|FL_BASE_BARS,
3277                 .num_ports      = 2,
3278                 .base_baud      = 115200,
3279                 .uart_offset    = 8,
3280         },
3281         [pbn_b0_bt_4_115200] = {
3282                 .flags          = FL_BASE0|FL_BASE_BARS,
3283                 .num_ports      = 4,
3284                 .base_baud      = 115200,
3285                 .uart_offset    = 8,
3286         },
3287         [pbn_b0_bt_8_115200] = {
3288                 .flags          = FL_BASE0|FL_BASE_BARS,
3289                 .num_ports      = 8,
3290                 .base_baud      = 115200,
3291                 .uart_offset    = 8,
3292         },
3293
3294         [pbn_b0_bt_1_460800] = {
3295                 .flags          = FL_BASE0|FL_BASE_BARS,
3296                 .num_ports      = 1,
3297                 .base_baud      = 460800,
3298                 .uart_offset    = 8,
3299         },
3300         [pbn_b0_bt_2_460800] = {
3301                 .flags          = FL_BASE0|FL_BASE_BARS,
3302                 .num_ports      = 2,
3303                 .base_baud      = 460800,
3304                 .uart_offset    = 8,
3305         },
3306         [pbn_b0_bt_4_460800] = {
3307                 .flags          = FL_BASE0|FL_BASE_BARS,
3308                 .num_ports      = 4,
3309                 .base_baud      = 460800,
3310                 .uart_offset    = 8,
3311         },
3312
3313         [pbn_b0_bt_1_921600] = {
3314                 .flags          = FL_BASE0|FL_BASE_BARS,
3315                 .num_ports      = 1,
3316                 .base_baud      = 921600,
3317                 .uart_offset    = 8,
3318         },
3319         [pbn_b0_bt_2_921600] = {
3320                 .flags          = FL_BASE0|FL_BASE_BARS,
3321                 .num_ports      = 2,
3322                 .base_baud      = 921600,
3323                 .uart_offset    = 8,
3324         },
3325         [pbn_b0_bt_4_921600] = {
3326                 .flags          = FL_BASE0|FL_BASE_BARS,
3327                 .num_ports      = 4,
3328                 .base_baud      = 921600,
3329                 .uart_offset    = 8,
3330         },
3331         [pbn_b0_bt_8_921600] = {
3332                 .flags          = FL_BASE0|FL_BASE_BARS,
3333                 .num_ports      = 8,
3334                 .base_baud      = 921600,
3335                 .uart_offset    = 8,
3336         },
3337
3338         [pbn_b1_1_115200] = {
3339                 .flags          = FL_BASE1,
3340                 .num_ports      = 1,
3341                 .base_baud      = 115200,
3342                 .uart_offset    = 8,
3343         },
3344         [pbn_b1_2_115200] = {
3345                 .flags          = FL_BASE1,
3346                 .num_ports      = 2,
3347                 .base_baud      = 115200,
3348                 .uart_offset    = 8,
3349         },
3350         [pbn_b1_4_115200] = {
3351                 .flags          = FL_BASE1,
3352                 .num_ports      = 4,
3353                 .base_baud      = 115200,
3354                 .uart_offset    = 8,
3355         },
3356         [pbn_b1_8_115200] = {
3357                 .flags          = FL_BASE1,
3358                 .num_ports      = 8,
3359                 .base_baud      = 115200,
3360                 .uart_offset    = 8,
3361         },
3362         [pbn_b1_16_115200] = {
3363                 .flags          = FL_BASE1,
3364                 .num_ports      = 16,
3365                 .base_baud      = 115200,
3366                 .uart_offset    = 8,
3367         },
3368
3369         [pbn_b1_1_921600] = {
3370                 .flags          = FL_BASE1,
3371                 .num_ports      = 1,
3372                 .base_baud      = 921600,
3373                 .uart_offset    = 8,
3374         },
3375         [pbn_b1_2_921600] = {
3376                 .flags          = FL_BASE1,
3377                 .num_ports      = 2,
3378                 .base_baud      = 921600,
3379                 .uart_offset    = 8,
3380         },
3381         [pbn_b1_4_921600] = {
3382                 .flags          = FL_BASE1,
3383                 .num_ports      = 4,
3384                 .base_baud      = 921600,
3385                 .uart_offset    = 8,
3386         },
3387         [pbn_b1_8_921600] = {
3388                 .flags          = FL_BASE1,
3389                 .num_ports      = 8,
3390                 .base_baud      = 921600,
3391                 .uart_offset    = 8,
3392         },
3393         [pbn_b1_2_1250000] = {
3394                 .flags          = FL_BASE1,
3395                 .num_ports      = 2,
3396                 .base_baud      = 1250000,
3397                 .uart_offset    = 8,
3398         },
3399
3400         [pbn_b1_bt_1_115200] = {
3401                 .flags          = FL_BASE1|FL_BASE_BARS,
3402                 .num_ports      = 1,
3403                 .base_baud      = 115200,
3404                 .uart_offset    = 8,
3405         },
3406         [pbn_b1_bt_2_115200] = {
3407                 .flags          = FL_BASE1|FL_BASE_BARS,
3408                 .num_ports      = 2,
3409                 .base_baud      = 115200,
3410                 .uart_offset    = 8,
3411         },
3412         [pbn_b1_bt_4_115200] = {
3413                 .flags          = FL_BASE1|FL_BASE_BARS,
3414                 .num_ports      = 4,
3415                 .base_baud      = 115200,
3416                 .uart_offset    = 8,
3417         },
3418
3419         [pbn_b1_bt_2_921600] = {
3420                 .flags          = FL_BASE1|FL_BASE_BARS,
3421                 .num_ports      = 2,
3422                 .base_baud      = 921600,
3423                 .uart_offset    = 8,
3424         },
3425
3426         [pbn_b1_1_1382400] = {
3427                 .flags          = FL_BASE1,
3428                 .num_ports      = 1,
3429                 .base_baud      = 1382400,
3430                 .uart_offset    = 8,
3431         },
3432         [pbn_b1_2_1382400] = {
3433                 .flags          = FL_BASE1,
3434                 .num_ports      = 2,
3435                 .base_baud      = 1382400,
3436                 .uart_offset    = 8,
3437         },
3438         [pbn_b1_4_1382400] = {
3439                 .flags          = FL_BASE1,
3440                 .num_ports      = 4,
3441                 .base_baud      = 1382400,
3442                 .uart_offset    = 8,
3443         },
3444         [pbn_b1_8_1382400] = {
3445                 .flags          = FL_BASE1,
3446                 .num_ports      = 8,
3447                 .base_baud      = 1382400,
3448                 .uart_offset    = 8,
3449         },
3450
3451         [pbn_b2_1_115200] = {
3452                 .flags          = FL_BASE2,
3453                 .num_ports      = 1,
3454                 .base_baud      = 115200,
3455                 .uart_offset    = 8,
3456         },
3457         [pbn_b2_2_115200] = {
3458                 .flags          = FL_BASE2,
3459                 .num_ports      = 2,
3460                 .base_baud      = 115200,
3461                 .uart_offset    = 8,
3462         },
3463         [pbn_b2_4_115200] = {
3464                 .flags          = FL_BASE2,
3465                 .num_ports      = 4,
3466                 .base_baud      = 115200,
3467                 .uart_offset    = 8,
3468         },
3469         [pbn_b2_8_115200] = {
3470                 .flags          = FL_BASE2,
3471                 .num_ports      = 8,
3472                 .base_baud      = 115200,
3473                 .uart_offset    = 8,
3474         },
3475
3476         [pbn_b2_1_460800] = {
3477                 .flags          = FL_BASE2,
3478                 .num_ports      = 1,
3479                 .base_baud      = 460800,
3480                 .uart_offset    = 8,
3481         },
3482         [pbn_b2_4_460800] = {
3483                 .flags          = FL_BASE2,
3484                 .num_ports      = 4,
3485                 .base_baud      = 460800,
3486                 .uart_offset    = 8,
3487         },
3488         [pbn_b2_8_460800] = {
3489                 .flags          = FL_BASE2,
3490                 .num_ports      = 8,
3491                 .base_baud      = 460800,
3492                 .uart_offset    = 8,
3493         },
3494         [pbn_b2_16_460800] = {
3495                 .flags          = FL_BASE2,
3496                 .num_ports      = 16,
3497                 .base_baud      = 460800,
3498                 .uart_offset    = 8,
3499          },
3500
3501         [pbn_b2_1_921600] = {
3502                 .flags          = FL_BASE2,
3503                 .num_ports      = 1,
3504                 .base_baud      = 921600,
3505                 .uart_offset    = 8,
3506         },
3507         [pbn_b2_4_921600] = {
3508                 .flags          = FL_BASE2,
3509                 .num_ports      = 4,
3510                 .base_baud      = 921600,
3511                 .uart_offset    = 8,
3512         },
3513         [pbn_b2_8_921600] = {
3514                 .flags          = FL_BASE2,
3515                 .num_ports      = 8,
3516                 .base_baud      = 921600,
3517                 .uart_offset    = 8,
3518         },
3519
3520         [pbn_b2_8_1152000] = {
3521                 .flags          = FL_BASE2,
3522                 .num_ports      = 8,
3523                 .base_baud      = 1152000,
3524                 .uart_offset    = 8,
3525         },
3526
3527         [pbn_b2_bt_1_115200] = {
3528                 .flags          = FL_BASE2|FL_BASE_BARS,
3529                 .num_ports      = 1,
3530                 .base_baud      = 115200,
3531                 .uart_offset    = 8,
3532         },
3533         [pbn_b2_bt_2_115200] = {
3534                 .flags          = FL_BASE2|FL_BASE_BARS,
3535                 .num_ports      = 2,
3536                 .base_baud      = 115200,
3537                 .uart_offset    = 8,
3538         },
3539         [pbn_b2_bt_4_115200] = {
3540                 .flags          = FL_BASE2|FL_BASE_BARS,
3541                 .num_ports      = 4,
3542                 .base_baud      = 115200,
3543                 .uart_offset    = 8,
3544         },
3545
3546         [pbn_b2_bt_2_921600] = {
3547                 .flags          = FL_BASE2|FL_BASE_BARS,
3548                 .num_ports      = 2,
3549                 .base_baud      = 921600,
3550                 .uart_offset    = 8,
3551         },
3552         [pbn_b2_bt_4_921600] = {
3553                 .flags          = FL_BASE2|FL_BASE_BARS,
3554                 .num_ports      = 4,
3555                 .base_baud      = 921600,
3556                 .uart_offset    = 8,
3557         },
3558
3559         [pbn_b3_2_115200] = {
3560                 .flags          = FL_BASE3,
3561                 .num_ports      = 2,
3562                 .base_baud      = 115200,
3563                 .uart_offset    = 8,
3564         },
3565         [pbn_b3_4_115200] = {
3566                 .flags          = FL_BASE3,
3567                 .num_ports      = 4,
3568                 .base_baud      = 115200,
3569                 .uart_offset    = 8,
3570         },
3571         [pbn_b3_8_115200] = {
3572                 .flags          = FL_BASE3,
3573                 .num_ports      = 8,
3574                 .base_baud      = 115200,
3575                 .uart_offset    = 8,
3576         },
3577
3578         [pbn_b4_bt_2_921600] = {
3579                 .flags          = FL_BASE4,
3580                 .num_ports      = 2,
3581                 .base_baud      = 921600,
3582                 .uart_offset    = 8,
3583         },
3584         [pbn_b4_bt_4_921600] = {
3585                 .flags          = FL_BASE4,
3586                 .num_ports      = 4,
3587                 .base_baud      = 921600,
3588                 .uart_offset    = 8,
3589         },
3590         [pbn_b4_bt_8_921600] = {
3591                 .flags          = FL_BASE4,
3592                 .num_ports      = 8,
3593                 .base_baud      = 921600,
3594                 .uart_offset    = 8,
3595         },
3596
3597         /*
3598          * Entries following this are board-specific.
3599          */
3600
3601         /*
3602          * Panacom - IOMEM
3603          */
3604         [pbn_panacom] = {
3605                 .flags          = FL_BASE2,
3606                 .num_ports      = 2,
3607                 .base_baud      = 921600,
3608                 .uart_offset    = 0x400,
3609                 .reg_shift      = 7,
3610         },
3611         [pbn_panacom2] = {
3612                 .flags          = FL_BASE2|FL_BASE_BARS,
3613                 .num_ports      = 2,
3614                 .base_baud      = 921600,
3615                 .uart_offset    = 0x400,
3616                 .reg_shift      = 7,
3617         },
3618         [pbn_panacom4] = {
3619                 .flags          = FL_BASE2|FL_BASE_BARS,
3620                 .num_ports      = 4,
3621                 .base_baud      = 921600,
3622                 .uart_offset    = 0x400,
3623                 .reg_shift      = 7,
3624         },
3625
3626         /* I think this entry is broken - the first_offset looks wrong --rmk */
3627         [pbn_plx_romulus] = {
3628                 .flags          = FL_BASE2,
3629                 .num_ports      = 4,
3630                 .base_baud      = 921600,
3631                 .uart_offset    = 8 << 2,
3632                 .reg_shift      = 2,
3633                 .first_offset   = 0x03,
3634         },
3635
3636         /*
3637          * EndRun Technologies
3638         * Uses the size of PCI Base region 0 to
3639         * signal now many ports are available
3640         * 2 port 952 Uart support
3641         */
3642         [pbn_endrun_2_4000000] = {
3643                 .flags          = FL_BASE0,
3644                 .num_ports      = 2,
3645                 .base_baud      = 4000000,
3646                 .uart_offset    = 0x200,
3647                 .first_offset   = 0x1000,
3648         },
3649
3650         /*
3651          * This board uses the size of PCI Base region 0 to
3652          * signal now many ports are available
3653          */
3654         [pbn_oxsemi] = {
3655                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3656                 .num_ports      = 32,
3657                 .base_baud      = 115200,
3658                 .uart_offset    = 8,
3659         },
3660         [pbn_oxsemi_1_4000000] = {
3661                 .flags          = FL_BASE0,
3662                 .num_ports      = 1,
3663                 .base_baud      = 4000000,
3664                 .uart_offset    = 0x200,
3665                 .first_offset   = 0x1000,
3666         },
3667         [pbn_oxsemi_2_4000000] = {
3668                 .flags          = FL_BASE0,
3669                 .num_ports      = 2,
3670                 .base_baud      = 4000000,
3671                 .uart_offset    = 0x200,
3672                 .first_offset   = 0x1000,
3673         },
3674         [pbn_oxsemi_4_4000000] = {
3675                 .flags          = FL_BASE0,
3676                 .num_ports      = 4,
3677                 .base_baud      = 4000000,
3678                 .uart_offset    = 0x200,
3679                 .first_offset   = 0x1000,
3680         },
3681         [pbn_oxsemi_8_4000000] = {
3682                 .flags          = FL_BASE0,
3683                 .num_ports      = 8,
3684                 .base_baud      = 4000000,
3685                 .uart_offset    = 0x200,
3686                 .first_offset   = 0x1000,
3687         },
3688
3689
3690         /*
3691          * EKF addition for i960 Boards form EKF with serial port.
3692          * Max 256 ports.
3693          */
3694         [pbn_intel_i960] = {
3695                 .flags          = FL_BASE0,
3696                 .num_ports      = 32,
3697                 .base_baud      = 921600,
3698                 .uart_offset    = 8 << 2,
3699                 .reg_shift      = 2,
3700                 .first_offset   = 0x10000,
3701         },
3702         [pbn_sgi_ioc3] = {
3703                 .flags          = FL_BASE0|FL_NOIRQ,
3704                 .num_ports      = 1,
3705                 .base_baud      = 458333,
3706                 .uart_offset    = 8,
3707                 .reg_shift      = 0,
3708                 .first_offset   = 0x20178,
3709         },
3710
3711         /*
3712          * Computone - uses IOMEM.
3713          */
3714         [pbn_computone_4] = {
3715                 .flags          = FL_BASE0,
3716                 .num_ports      = 4,
3717                 .base_baud      = 921600,
3718                 .uart_offset    = 0x40,
3719                 .reg_shift      = 2,
3720                 .first_offset   = 0x200,
3721         },
3722         [pbn_computone_6] = {
3723                 .flags          = FL_BASE0,
3724                 .num_ports      = 6,
3725                 .base_baud      = 921600,
3726                 .uart_offset    = 0x40,
3727                 .reg_shift      = 2,
3728                 .first_offset   = 0x200,
3729         },
3730         [pbn_computone_8] = {
3731                 .flags          = FL_BASE0,
3732                 .num_ports      = 8,
3733                 .base_baud      = 921600,
3734                 .uart_offset    = 0x40,
3735                 .reg_shift      = 2,
3736                 .first_offset   = 0x200,
3737         },
3738         [pbn_sbsxrsio] = {
3739                 .flags          = FL_BASE0,
3740                 .num_ports      = 8,
3741                 .base_baud      = 460800,
3742                 .uart_offset    = 256,
3743                 .reg_shift      = 4,
3744         },
3745         /*
3746          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3747          *  Only basic 16550A support.
3748          *  XR17C15[24] are not tested, but they should work.
3749          */
3750         [pbn_exar_XR17C152] = {
3751                 .flags          = FL_BASE0,
3752                 .num_ports      = 2,
3753                 .base_baud      = 921600,
3754                 .uart_offset    = 0x200,
3755         },
3756         [pbn_exar_XR17C154] = {
3757                 .flags          = FL_BASE0,
3758                 .num_ports      = 4,
3759                 .base_baud      = 921600,
3760                 .uart_offset    = 0x200,
3761         },
3762         [pbn_exar_XR17C158] = {
3763                 .flags          = FL_BASE0,
3764                 .num_ports      = 8,
3765                 .base_baud      = 921600,
3766                 .uart_offset    = 0x200,
3767         },
3768         [pbn_exar_XR17V352] = {
3769                 .flags          = FL_BASE0,
3770                 .num_ports      = 2,
3771                 .base_baud      = 7812500,
3772                 .uart_offset    = 0x400,
3773                 .reg_shift      = 0,
3774                 .first_offset   = 0,
3775         },
3776         [pbn_exar_XR17V354] = {
3777                 .flags          = FL_BASE0,
3778                 .num_ports      = 4,
3779                 .base_baud      = 7812500,
3780                 .uart_offset    = 0x400,
3781                 .reg_shift      = 0,
3782                 .first_offset   = 0,
3783         },
3784         [pbn_exar_XR17V358] = {
3785                 .flags          = FL_BASE0,
3786                 .num_ports      = 8,
3787                 .base_baud      = 7812500,
3788                 .uart_offset    = 0x400,
3789                 .reg_shift      = 0,
3790                 .first_offset   = 0,
3791         },
3792         [pbn_exar_XR17V4358] = {
3793                 .flags          = FL_BASE0,
3794                 .num_ports      = 12,
3795                 .base_baud      = 7812500,
3796                 .uart_offset    = 0x400,
3797                 .reg_shift      = 0,
3798                 .first_offset   = 0,
3799         },
3800         [pbn_exar_XR17V8358] = {
3801                 .flags          = FL_BASE0,
3802                 .num_ports      = 16,
3803                 .base_baud      = 7812500,
3804                 .uart_offset    = 0x400,
3805                 .reg_shift      = 0,
3806                 .first_offset   = 0,
3807         },
3808         [pbn_exar_ibm_saturn] = {
3809                 .flags          = FL_BASE0,
3810                 .num_ports      = 1,
3811                 .base_baud      = 921600,
3812                 .uart_offset    = 0x200,
3813         },
3814
3815         /*
3816          * PA Semi PWRficient PA6T-1682M on-chip UART
3817          */
3818         [pbn_pasemi_1682M] = {
3819                 .flags          = FL_BASE0,
3820                 .num_ports      = 1,
3821                 .base_baud      = 8333333,
3822         },
3823         /*
3824          * National Instruments 843x
3825          */
3826         [pbn_ni8430_16] = {
3827                 .flags          = FL_BASE0,
3828                 .num_ports      = 16,
3829                 .base_baud      = 3686400,
3830                 .uart_offset    = 0x10,
3831                 .first_offset   = 0x800,
3832         },
3833         [pbn_ni8430_8] = {
3834                 .flags          = FL_BASE0,
3835                 .num_ports      = 8,
3836                 .base_baud      = 3686400,
3837                 .uart_offset    = 0x10,
3838                 .first_offset   = 0x800,
3839         },
3840         [pbn_ni8430_4] = {
3841                 .flags          = FL_BASE0,
3842                 .num_ports      = 4,
3843                 .base_baud      = 3686400,
3844                 .uart_offset    = 0x10,
3845                 .first_offset   = 0x800,
3846         },
3847         [pbn_ni8430_2] = {
3848                 .flags          = FL_BASE0,
3849                 .num_ports      = 2,
3850                 .base_baud      = 3686400,
3851                 .uart_offset    = 0x10,
3852                 .first_offset   = 0x800,
3853         },
3854         /*
3855          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3856          */
3857         [pbn_ADDIDATA_PCIe_1_3906250] = {
3858                 .flags          = FL_BASE0,
3859                 .num_ports      = 1,
3860                 .base_baud      = 3906250,
3861                 .uart_offset    = 0x200,
3862                 .first_offset   = 0x1000,
3863         },
3864         [pbn_ADDIDATA_PCIe_2_3906250] = {
3865                 .flags          = FL_BASE0,
3866                 .num_ports      = 2,
3867                 .base_baud      = 3906250,
3868                 .uart_offset    = 0x200,
3869                 .first_offset   = 0x1000,
3870         },
3871         [pbn_ADDIDATA_PCIe_4_3906250] = {
3872                 .flags          = FL_BASE0,
3873                 .num_ports      = 4,
3874                 .base_baud      = 3906250,
3875                 .uart_offset    = 0x200,
3876                 .first_offset   = 0x1000,
3877         },
3878         [pbn_ADDIDATA_PCIe_8_3906250] = {
3879                 .flags          = FL_BASE0,
3880                 .num_ports      = 8,
3881                 .base_baud      = 3906250,
3882                 .uart_offset    = 0x200,
3883                 .first_offset   = 0x1000,
3884         },
3885         [pbn_ce4100_1_115200] = {
3886                 .flags          = FL_BASE_BARS,
3887                 .num_ports      = 2,
3888                 .base_baud      = 921600,
3889                 .reg_shift      = 2,
3890         },
3891         /*
3892          * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3893          * but is overridden by byt_set_termios.
3894          */
3895         [pbn_byt] = {
3896                 .flags          = FL_BASE0,
3897                 .num_ports      = 1,
3898                 .base_baud      = 2764800,
3899                 .uart_offset    = 0x80,
3900                 .reg_shift      = 2,
3901         },
3902         [pbn_qrk] = {
3903                 .flags          = FL_BASE0,
3904                 .num_ports      = 1,
3905                 .base_baud      = 2764800,
3906                 .reg_shift      = 2,
3907         },
3908         [pbn_omegapci] = {
3909                 .flags          = FL_BASE0,
3910                 .num_ports      = 8,
3911                 .base_baud      = 115200,
3912                 .uart_offset    = 0x200,
3913         },
3914         [pbn_NETMOS9900_2s_115200] = {
3915                 .flags          = FL_BASE0,
3916                 .num_ports      = 2,
3917                 .base_baud      = 115200,
3918         },
3919         [pbn_brcm_trumanage] = {
3920                 .flags          = FL_BASE0,
3921                 .num_ports      = 1,
3922                 .reg_shift      = 2,
3923                 .base_baud      = 115200,
3924         },
3925         [pbn_fintek_4] = {
3926                 .num_ports      = 4,
3927                 .uart_offset    = 8,
3928                 .base_baud      = 115200,
3929                 .first_offset   = 0x40,
3930         },
3931         [pbn_fintek_8] = {
3932                 .num_ports      = 8,
3933                 .uart_offset    = 8,
3934                 .base_baud      = 115200,
3935                 .first_offset   = 0x40,
3936         },
3937         [pbn_fintek_12] = {
3938                 .num_ports      = 12,
3939                 .uart_offset    = 8,
3940                 .base_baud      = 115200,
3941                 .first_offset   = 0x40,
3942         },
3943         [pbn_wch382_2] = {
3944                 .flags          = FL_BASE0,
3945                 .num_ports      = 2,
3946                 .base_baud      = 115200,
3947                 .uart_offset    = 8,
3948                 .first_offset   = 0xC0,
3949         },
3950         [pbn_wch384_4] = {
3951                 .flags          = FL_BASE0,
3952                 .num_ports      = 4,
3953                 .base_baud      = 115200,
3954                 .uart_offset    = 8,
3955                 .first_offset   = 0xC0,
3956         },
3957         /*
3958          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3959          */
3960         [pbn_pericom_PI7C9X7951] = {
3961                 .flags          = FL_BASE0,
3962                 .num_ports      = 1,
3963                 .base_baud      = 921600,
3964                 .uart_offset    = 0x8,
3965         },
3966         [pbn_pericom_PI7C9X7952] = {
3967                 .flags          = FL_BASE0,
3968                 .num_ports      = 2,
3969                 .base_baud      = 921600,
3970                 .uart_offset    = 0x8,
3971         },
3972         [pbn_pericom_PI7C9X7954] = {
3973                 .flags          = FL_BASE0,
3974                 .num_ports      = 4,
3975                 .base_baud      = 921600,
3976                 .uart_offset    = 0x8,
3977         },
3978         [pbn_pericom_PI7C9X7958] = {
3979                 .flags          = FL_BASE0,
3980                 .num_ports      = 8,
3981                 .base_baud      = 921600,
3982                 .uart_offset    = 0x8,
3983         },
3984 };
3985
3986 static const struct pci_device_id blacklist[] = {
3987         /* softmodems */
3988         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3989         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3990         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3991
3992         /* multi-io cards handled by parport_serial */
3993         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3994         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3995         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3996         { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3997
3998         /* Intel platforms with MID UART */
3999         { PCI_VDEVICE(INTEL, 0x081b), },
4000         { PCI_VDEVICE(INTEL, 0x081c), },
4001         { PCI_VDEVICE(INTEL, 0x081d), },
4002         { PCI_VDEVICE(INTEL, 0x1191), },
4003         { PCI_VDEVICE(INTEL, 0x19d8), },
4004 };
4005
4006 /*
4007  * Given a complete unknown PCI device, try to use some heuristics to
4008  * guess what the configuration might be, based on the pitiful PCI
4009  * serial specs.  Returns 0 on success, 1 on failure.
4010  */
4011 static int
4012 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
4013 {
4014         const struct pci_device_id *bldev;
4015         int num_iomem, num_port, first_port = -1, i;
4016
4017         /*
4018          * If it is not a communications device or the programming
4019          * interface is greater than 6, give up.
4020          *
4021          * (Should we try to make guesses for multiport serial devices
4022          * later?)
4023          */
4024         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
4025              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
4026             (dev->class & 0xff) > 6)
4027                 return -ENODEV;
4028
4029         /*
4030          * Do not access blacklisted devices that are known not to
4031          * feature serial ports or are handled by other modules.
4032          */
4033         for (bldev = blacklist;
4034              bldev < blacklist + ARRAY_SIZE(blacklist);
4035              bldev++) {
4036                 if (dev->vendor == bldev->vendor &&
4037                     dev->device == bldev->device)
4038                         return -ENODEV;
4039         }
4040
4041         num_iomem = num_port = 0;
4042         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4043                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4044                         num_port++;
4045                         if (first_port == -1)
4046                                 first_port = i;
4047                 }
4048                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4049                         num_iomem++;
4050         }
4051
4052         /*
4053          * If there is 1 or 0 iomem regions, and exactly one port,
4054          * use it.  We guess the number of ports based on the IO
4055          * region size.
4056          */
4057         if (num_iomem <= 1 && num_port == 1) {
4058                 board->flags = first_port;
4059                 board->num_ports = pci_resource_len(dev, first_port) / 8;
4060                 return 0;
4061         }
4062
4063         /*
4064          * Now guess if we've got a board which indexes by BARs.
4065          * Each IO BAR should be 8 bytes, and they should follow
4066          * consecutively.
4067          */
4068         first_port = -1;
4069         num_port = 0;
4070         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4071                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4072                     pci_resource_len(dev, i) == 8 &&
4073                     (first_port == -1 || (first_port + num_port) == i)) {
4074                         num_port++;
4075                         if (first_port == -1)
4076                                 first_port = i;
4077                 }
4078         }
4079
4080         if (num_port > 1) {
4081                 board->flags = first_port | FL_BASE_BARS;
4082                 board->num_ports = num_port;
4083                 return 0;
4084         }
4085
4086         return -ENODEV;
4087 }
4088
4089 static inline int
4090 serial_pci_matches(const struct pciserial_board *board,
4091                    const struct pciserial_board *guessed)
4092 {
4093         return
4094             board->num_ports == guessed->num_ports &&
4095             board->base_baud == guessed->base_baud &&
4096             board->uart_offset == guessed->uart_offset &&
4097             board->reg_shift == guessed->reg_shift &&
4098             board->first_offset == guessed->first_offset;
4099 }
4100
4101 struct serial_private *
4102 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4103 {
4104         struct uart_8250_port uart;
4105         struct serial_private *priv;
4106         struct pci_serial_quirk *quirk;
4107         int rc, nr_ports, i;
4108
4109         nr_ports = board->num_ports;
4110
4111         /*
4112          * Find an init and setup quirks.
4113          */
4114         quirk = find_quirk(dev);
4115
4116         /*
4117          * Run the new-style initialization function.
4118          * The initialization function returns:
4119          *  <0  - error
4120          *   0  - use board->num_ports
4121          *  >0  - number of ports
4122          */
4123         if (quirk->init) {
4124                 rc = quirk->init(dev);
4125                 if (rc < 0) {
4126                         priv = ERR_PTR(rc);
4127                         goto err_out;
4128                 }
4129                 if (rc)
4130                         nr_ports = rc;
4131         }
4132
4133         priv = kzalloc(sizeof(struct serial_private) +
4134                        sizeof(unsigned int) * nr_ports,
4135                        GFP_KERNEL);
4136         if (!priv) {
4137                 priv = ERR_PTR(-ENOMEM);
4138                 goto err_deinit;
4139         }
4140
4141         priv->dev = dev;
4142         priv->quirk = quirk;
4143
4144         memset(&uart, 0, sizeof(uart));
4145         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4146         uart.port.uartclk = board->base_baud * 16;
4147         uart.port.irq = get_pci_irq(dev, board);
4148         uart.port.dev = &dev->dev;
4149
4150         for (i = 0; i < nr_ports; i++) {
4151                 if (quirk->setup(priv, board, &uart, i))
4152                         break;
4153
4154                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4155                         uart.port.iobase, uart.port.irq, uart.port.iotype);
4156
4157                 priv->line[i] = serial8250_register_8250_port(&uart);
4158                 if (priv->line[i] < 0) {
4159                         dev_err(&dev->dev,
4160                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4161                                 uart.port.iobase, uart.port.irq,
4162                                 uart.port.iotype, priv->line[i]);
4163                         break;
4164                 }
4165         }
4166         priv->nr = i;
4167         priv->board = board;
4168         return priv;
4169
4170 err_deinit:
4171         if (quirk->exit)
4172                 quirk->exit(dev);
4173 err_out:
4174         return priv;
4175 }
4176 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4177
4178 void pciserial_detach_ports(struct serial_private *priv)
4179 {
4180         struct pci_serial_quirk *quirk;
4181         int i;
4182
4183         for (i = 0; i < priv->nr; i++)
4184                 serial8250_unregister_port(priv->line[i]);
4185
4186         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4187                 if (priv->remapped_bar[i])
4188                         iounmap(priv->remapped_bar[i]);
4189                 priv->remapped_bar[i] = NULL;
4190         }
4191
4192         /*
4193          * Find the exit quirks.
4194          */
4195         quirk = find_quirk(priv->dev);
4196         if (quirk->exit)
4197                 quirk->exit(priv->dev);
4198 }
4199
4200 void pciserial_remove_ports(struct serial_private *priv)
4201 {
4202         pciserial_detach_ports(priv);
4203         kfree(priv);
4204 }
4205 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4206
4207 void pciserial_suspend_ports(struct serial_private *priv)
4208 {
4209         int i;
4210
4211         for (i = 0; i < priv->nr; i++)
4212                 if (priv->line[i] >= 0)
4213                         serial8250_suspend_port(priv->line[i]);
4214
4215         /*
4216          * Ensure that every init quirk is properly torn down
4217          */
4218         if (priv->quirk->exit)
4219                 priv->quirk->exit(priv->dev);
4220 }
4221 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4222
4223 void pciserial_resume_ports(struct serial_private *priv)
4224 {
4225         int i;
4226
4227         /*
4228          * Ensure that the board is correctly configured.
4229          */
4230         if (priv->quirk->init)
4231                 priv->quirk->init(priv->dev);
4232
4233         for (i = 0; i < priv->nr; i++)
4234                 if (priv->line[i] >= 0)
4235                         serial8250_resume_port(priv->line[i]);
4236 }
4237 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4238
4239 /*
4240  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4241  * to the arrangement of serial ports on a PCI card.
4242  */
4243 static int
4244 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4245 {
4246         struct pci_serial_quirk *quirk;
4247         struct serial_private *priv;
4248         const struct pciserial_board *board;
4249         struct pciserial_board tmp;
4250         int rc;
4251
4252         quirk = find_quirk(dev);
4253         if (quirk->probe) {
4254                 rc = quirk->probe(dev);
4255                 if (rc)
4256                         return rc;
4257         }
4258
4259         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4260                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4261                         ent->driver_data);
4262                 return -EINVAL;
4263         }
4264
4265         board = &pci_boards[ent->driver_data];
4266
4267         rc = pci_enable_device(dev);
4268         pci_save_state(dev);
4269         if (rc)
4270                 return rc;
4271
4272         if (ent->driver_data == pbn_default) {
4273                 /*
4274                  * Use a copy of the pci_board entry for this;
4275                  * avoid changing entries in the table.
4276                  */
4277                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4278                 board = &tmp;
4279
4280                 /*
4281                  * We matched one of our class entries.  Try to
4282                  * determine the parameters of this board.
4283                  */
4284                 rc = serial_pci_guess_board(dev, &tmp);
4285                 if (rc)
4286                         goto disable;
4287         } else {
4288                 /*
4289                  * We matched an explicit entry.  If we are able to
4290                  * detect this boards settings with our heuristic,
4291                  * then we no longer need this entry.
4292                  */
4293                 memcpy(&tmp, &pci_boards[pbn_default],
4294                        sizeof(struct pciserial_board));
4295                 rc = serial_pci_guess_board(dev, &tmp);
4296                 if (rc == 0 && serial_pci_matches(board, &tmp))
4297                         moan_device("Redundant entry in serial pci_table.",
4298                                     dev);
4299         }
4300
4301         priv = pciserial_init_ports(dev, board);
4302         if (!IS_ERR(priv)) {
4303                 pci_set_drvdata(dev, priv);
4304                 return 0;
4305         }
4306
4307         rc = PTR_ERR(priv);
4308
4309  disable:
4310         pci_disable_device(dev);
4311         return rc;
4312 }
4313
4314 static void pciserial_remove_one(struct pci_dev *dev)
4315 {
4316         struct serial_private *priv = pci_get_drvdata(dev);
4317
4318         pciserial_remove_ports(priv);
4319
4320         pci_disable_device(dev);
4321 }
4322
4323 #ifdef CONFIG_PM_SLEEP
4324 static int pciserial_suspend_one(struct device *dev)
4325 {
4326         struct pci_dev *pdev = to_pci_dev(dev);
4327         struct serial_private *priv = pci_get_drvdata(pdev);
4328
4329         if (priv)
4330                 pciserial_suspend_ports(priv);
4331
4332         return 0;
4333 }
4334
4335 static int pciserial_resume_one(struct device *dev)
4336 {
4337         struct pci_dev *pdev = to_pci_dev(dev);
4338         struct serial_private *priv = pci_get_drvdata(pdev);
4339         int err;
4340
4341         if (priv) {
4342                 /*
4343                  * The device may have been disabled.  Re-enable it.
4344                  */
4345                 err = pci_enable_device(pdev);
4346                 /* FIXME: We cannot simply error out here */
4347                 if (err)
4348                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4349                 pciserial_resume_ports(priv);
4350         }
4351         return 0;
4352 }
4353 #endif
4354
4355 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4356                          pciserial_resume_one);
4357
4358 static struct pci_device_id serial_pci_tbl[] = {
4359         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4360         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4361                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4362                 pbn_b2_8_921600 },
4363         /* Advantech also use 0x3618 and 0xf618 */
4364         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4365                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4366                 pbn_b0_4_921600 },
4367         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4368                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4369                 pbn_b0_4_921600 },
4370         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4371                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4372                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4373                 pbn_b1_8_1382400 },
4374         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4375                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4376                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4377                 pbn_b1_4_1382400 },
4378         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4379                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4380                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4381                 pbn_b1_2_1382400 },
4382         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4383                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4384                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4385                 pbn_b1_8_1382400 },
4386         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4387                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4388                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4389                 pbn_b1_4_1382400 },
4390         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4391                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4392                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4393                 pbn_b1_2_1382400 },
4394         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4395                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4396                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4397                 pbn_b1_8_921600 },
4398         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4399                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4400                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4401                 pbn_b1_8_921600 },
4402         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4403                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4404                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4405                 pbn_b1_4_921600 },
4406         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4407                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4408                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4409                 pbn_b1_4_921600 },
4410         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4411                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4412                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4413                 pbn_b1_2_921600 },
4414         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4415                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4416                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4417                 pbn_b1_8_921600 },
4418         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4419                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4420                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4421                 pbn_b1_8_921600 },
4422         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4423                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4424                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4425                 pbn_b1_4_921600 },
4426         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4427                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4428                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4429                 pbn_b1_2_1250000 },
4430         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4431                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4432                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4433                 pbn_b0_2_1843200 },
4434         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4435                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4436                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4437                 pbn_b0_4_1843200 },
4438         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4439                 PCI_VENDOR_ID_AFAVLAB,
4440                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4441                 pbn_b0_4_1152000 },
4442         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4443                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4444                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4445                 pbn_b0_2_1843200_200 },
4446         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4447                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4448                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4449                 pbn_b0_4_1843200_200 },
4450         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4451                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4452                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4453                 pbn_b0_8_1843200_200 },
4454         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4455                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4456                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4457                 pbn_b0_2_1843200_200 },
4458         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4459                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4460                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4461                 pbn_b0_4_1843200_200 },
4462         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4463                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4464                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4465                 pbn_b0_8_1843200_200 },
4466         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4467                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4468                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4469                 pbn_b0_2_1843200_200 },
4470         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4471                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4472                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4473                 pbn_b0_4_1843200_200 },
4474         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4475                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4476                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4477                 pbn_b0_8_1843200_200 },
4478         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4479                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4480                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4481                 pbn_b0_2_1843200_200 },
4482         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4483                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4484                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4485                 pbn_b0_4_1843200_200 },
4486         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4487                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4488                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4489                 pbn_b0_8_1843200_200 },
4490         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4491                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4492                 0, 0, pbn_exar_ibm_saturn },
4493
4494         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4495                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496                 pbn_b2_bt_1_115200 },
4497         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4498                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499                 pbn_b2_bt_2_115200 },
4500         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4501                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502                 pbn_b2_bt_4_115200 },
4503         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4504                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505                 pbn_b2_bt_2_115200 },
4506         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4507                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508                 pbn_b2_bt_4_115200 },
4509         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4510                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511                 pbn_b2_8_115200 },
4512         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4513                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514                 pbn_b2_8_460800 },
4515         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4516                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517                 pbn_b2_8_115200 },
4518
4519         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4520                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521                 pbn_b2_bt_2_115200 },
4522         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4523                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524                 pbn_b2_bt_2_921600 },
4525         /*
4526          * VScom SPCOM800, from sl@s.pl
4527          */
4528         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4529                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530                 pbn_b2_8_921600 },
4531         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4532                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533                 pbn_b2_4_921600 },
4534         /* Unknown card - subdevice 0x1584 */
4535         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4536                 PCI_VENDOR_ID_PLX,
4537                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4538                 pbn_b2_4_115200 },
4539         /* Unknown card - subdevice 0x1588 */
4540         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4541                 PCI_VENDOR_ID_PLX,
4542                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4543                 pbn_b2_8_115200 },
4544         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4545                 PCI_SUBVENDOR_ID_KEYSPAN,
4546                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4547                 pbn_panacom },
4548         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4549                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550                 pbn_panacom4 },
4551         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4552                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553                 pbn_panacom2 },
4554         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4555                 PCI_VENDOR_ID_ESDGMBH,
4556                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4557                 pbn_b2_4_115200 },
4558         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4559                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4560                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4561                 pbn_b2_4_460800 },
4562         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4563                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4564                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4565                 pbn_b2_8_460800 },
4566         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4567                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4568                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4569                 pbn_b2_16_460800 },
4570         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4571                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4572                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4573                 pbn_b2_16_460800 },
4574         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4575                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4576                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4577                 pbn_b2_4_460800 },
4578         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4579                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4580                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4581                 pbn_b2_8_460800 },
4582         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4583                 PCI_SUBVENDOR_ID_EXSYS,
4584                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4585                 pbn_b2_4_115200 },
4586         /*
4587          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4588          * (Exoray@isys.ca)
4589          */
4590         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4591                 0x10b5, 0x106a, 0, 0,
4592                 pbn_plx_romulus },
4593         /*
4594         * EndRun Technologies. PCI express device range.
4595         *    EndRun PTP/1588 has 2 Native UARTs.
4596         */
4597         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4598                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599                 pbn_endrun_2_4000000 },
4600         /*
4601          * Quatech cards. These actually have configurable clocks but for
4602          * now we just use the default.
4603          *
4604          * 100 series are RS232, 200 series RS422,
4605          */
4606         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4607                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608                 pbn_b1_4_115200 },
4609         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4610                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611                 pbn_b1_2_115200 },
4612         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4613                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614                 pbn_b2_2_115200 },
4615         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4616                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617                 pbn_b1_2_115200 },
4618         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4619                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620                 pbn_b2_2_115200 },
4621         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4622                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623                 pbn_b1_4_115200 },
4624         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4625                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626                 pbn_b1_8_115200 },
4627         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4628                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629                 pbn_b1_8_115200 },
4630         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4631                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632                 pbn_b1_4_115200 },
4633         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4634                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635                 pbn_b1_2_115200 },
4636         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4637                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638                 pbn_b1_4_115200 },
4639         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4640                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641                 pbn_b1_2_115200 },
4642         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4643                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644                 pbn_b2_4_115200 },
4645         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4646                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647                 pbn_b2_2_115200 },
4648         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4649                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650                 pbn_b2_1_115200 },
4651         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4652                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653                 pbn_b2_4_115200 },
4654         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4655                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656                 pbn_b2_2_115200 },
4657         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4658                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659                 pbn_b2_1_115200 },
4660         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4661                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662                 pbn_b0_8_115200 },
4663
4664         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4665                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4666                 0, 0,
4667                 pbn_b0_4_921600 },
4668         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4669                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4670                 0, 0,
4671                 pbn_b0_4_1152000 },
4672         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4673                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674                 pbn_b0_bt_2_921600 },
4675
4676                 /*
4677                  * The below card is a little controversial since it is the
4678                  * subject of a PCI vendor/device ID clash.  (See
4679                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4680                  * For now just used the hex ID 0x950a.
4681                  */
4682         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4683                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4684                 0, 0, pbn_b0_2_115200 },
4685         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4686                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4687                 0, 0, pbn_b0_2_115200 },
4688         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4689                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690                 pbn_b0_2_1130000 },
4691         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4692                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4693                 pbn_b0_1_921600 },
4694         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4695                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696                 pbn_b0_4_115200 },
4697         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4698                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699                 pbn_b0_bt_2_921600 },
4700         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4701                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4702                 pbn_b2_8_1152000 },
4703
4704         /*
4705          * Oxford Semiconductor Inc. Tornado PCI express device range.
4706          */
4707         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4708                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709                 pbn_b0_1_4000000 },
4710         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4711                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712                 pbn_b0_1_4000000 },
4713         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4714                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715                 pbn_oxsemi_1_4000000 },
4716         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4717                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718                 pbn_oxsemi_1_4000000 },
4719         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4720                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721                 pbn_b0_1_4000000 },
4722         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4723                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724                 pbn_b0_1_4000000 },
4725         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4726                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727                 pbn_oxsemi_1_4000000 },
4728         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4729                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730                 pbn_oxsemi_1_4000000 },
4731         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4732                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733                 pbn_b0_1_4000000 },
4734         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4735                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736                 pbn_b0_1_4000000 },
4737         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4738                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739                 pbn_b0_1_4000000 },
4740         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4741                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742                 pbn_b0_1_4000000 },
4743         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4744                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745                 pbn_oxsemi_2_4000000 },
4746         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4747                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748                 pbn_oxsemi_2_4000000 },
4749         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4750                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751                 pbn_oxsemi_4_4000000 },
4752         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4753                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754                 pbn_oxsemi_4_4000000 },
4755         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4756                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757                 pbn_oxsemi_8_4000000 },
4758         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4759                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760                 pbn_oxsemi_8_4000000 },
4761         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4762                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763                 pbn_oxsemi_1_4000000 },
4764         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4765                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766                 pbn_oxsemi_1_4000000 },
4767         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4768                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769                 pbn_oxsemi_1_4000000 },
4770         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4771                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772                 pbn_oxsemi_1_4000000 },
4773         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4774                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775                 pbn_oxsemi_1_4000000 },
4776         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4777                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778                 pbn_oxsemi_1_4000000 },
4779         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4780                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781                 pbn_oxsemi_1_4000000 },
4782         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4783                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784                 pbn_oxsemi_1_4000000 },
4785         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4786                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787                 pbn_oxsemi_1_4000000 },
4788         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4789                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790                 pbn_oxsemi_1_4000000 },
4791         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4792                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793                 pbn_oxsemi_1_4000000 },
4794         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4795                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796                 pbn_oxsemi_1_4000000 },
4797         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4798                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799                 pbn_oxsemi_1_4000000 },
4800         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4801                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802                 pbn_oxsemi_1_4000000 },
4803         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4804                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805                 pbn_oxsemi_1_4000000 },
4806         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4807                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808                 pbn_oxsemi_1_4000000 },
4809         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4810                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811                 pbn_oxsemi_1_4000000 },
4812         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4813                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814                 pbn_oxsemi_1_4000000 },
4815         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4816                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817                 pbn_oxsemi_1_4000000 },
4818         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4819                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820                 pbn_oxsemi_1_4000000 },
4821         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4822                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823                 pbn_oxsemi_1_4000000 },
4824         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4825                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826                 pbn_oxsemi_1_4000000 },
4827         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4828                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829                 pbn_oxsemi_1_4000000 },
4830         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4831                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832                 pbn_oxsemi_1_4000000 },
4833         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4834                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835                 pbn_oxsemi_1_4000000 },
4836         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4837                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838                 pbn_oxsemi_1_4000000 },
4839         /*
4840          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4841          */
4842         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4843                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4844                 pbn_oxsemi_1_4000000 },
4845         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4846                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4847                 pbn_oxsemi_2_4000000 },
4848         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4849                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4850                 pbn_oxsemi_4_4000000 },
4851         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4852                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4853                 pbn_oxsemi_8_4000000 },
4854
4855         /*
4856          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4857          */
4858         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4859                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4860                 pbn_oxsemi_2_4000000 },
4861
4862         /*
4863          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4864          * from skokodyn@yahoo.com
4865          */
4866         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4867                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4868                 pbn_sbsxrsio },
4869         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4870                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4871                 pbn_sbsxrsio },
4872         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4873                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4874                 pbn_sbsxrsio },
4875         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4876                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4877                 pbn_sbsxrsio },
4878
4879         /*
4880          * Digitan DS560-558, from jimd@esoft.com
4881          */
4882         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4883                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884                 pbn_b1_1_115200 },
4885
4886         /*
4887          * Titan Electronic cards
4888          *  The 400L and 800L have a custom setup quirk.
4889          */
4890         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4891                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892                 pbn_b0_1_921600 },
4893         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4894                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895                 pbn_b0_2_921600 },
4896         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4897                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898                 pbn_b0_4_921600 },
4899         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4900                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901                 pbn_b0_4_921600 },
4902         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4903                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904                 pbn_b1_1_921600 },
4905         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4906                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907                 pbn_b1_bt_2_921600 },
4908         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4909                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910                 pbn_b0_bt_4_921600 },
4911         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4912                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913                 pbn_b0_bt_8_921600 },
4914         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4915                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916                 pbn_b4_bt_2_921600 },
4917         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4918                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4919                 pbn_b4_bt_4_921600 },
4920         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4921                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4922                 pbn_b4_bt_8_921600 },
4923         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4924                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4925                 pbn_b0_4_921600 },
4926         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4927                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4928                 pbn_b0_4_921600 },
4929         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4930                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931                 pbn_b0_4_921600 },
4932         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4933                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934                 pbn_oxsemi_1_4000000 },
4935         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4936                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4937                 pbn_oxsemi_2_4000000 },
4938         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4939                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940                 pbn_oxsemi_4_4000000 },
4941         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4942                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4943                 pbn_oxsemi_8_4000000 },
4944         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4945                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4946                 pbn_oxsemi_2_4000000 },
4947         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4948                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4949                 pbn_oxsemi_2_4000000 },
4950         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4951                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4952                 pbn_b0_bt_2_921600 },
4953         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4954                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4955                 pbn_b0_4_921600 },
4956         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4957                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4958                 pbn_b0_4_921600 },
4959         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4960                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4961                 pbn_b0_4_921600 },
4962         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4963                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4964                 pbn_b0_4_921600 },
4965
4966         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4967                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968                 pbn_b2_1_460800 },
4969         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4970                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971                 pbn_b2_1_460800 },
4972         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4973                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974                 pbn_b2_1_460800 },
4975         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4976                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977                 pbn_b2_bt_2_921600 },
4978         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4979                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980                 pbn_b2_bt_2_921600 },
4981         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4982                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983                 pbn_b2_bt_2_921600 },
4984         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4985                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986                 pbn_b2_bt_4_921600 },
4987         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4988                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989                 pbn_b2_bt_4_921600 },
4990         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4991                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992                 pbn_b2_bt_4_921600 },
4993         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4994                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995                 pbn_b0_1_921600 },
4996         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998                 pbn_b0_1_921600 },
4999         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
5000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001                 pbn_b0_1_921600 },
5002         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
5003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004                 pbn_b0_bt_2_921600 },
5005         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
5006                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007                 pbn_b0_bt_2_921600 },
5008         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
5009                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5010                 pbn_b0_bt_2_921600 },
5011         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
5012                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5013                 pbn_b0_bt_4_921600 },
5014         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
5015                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5016                 pbn_b0_bt_4_921600 },
5017         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
5018                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5019                 pbn_b0_bt_4_921600 },
5020         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
5021                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5022                 pbn_b0_bt_8_921600 },
5023         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
5024                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5025                 pbn_b0_bt_8_921600 },
5026         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
5027                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5028                 pbn_b0_bt_8_921600 },
5029
5030         /*
5031          * Computone devices submitted by Doug McNash dmcnash@computone.com
5032          */
5033         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5034                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
5035                 0, 0, pbn_computone_4 },
5036         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5037                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
5038                 0, 0, pbn_computone_8 },
5039         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5040                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
5041                 0, 0, pbn_computone_6 },
5042
5043         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5044                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5045                 pbn_oxsemi },
5046         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5047                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5048                 pbn_b0_bt_1_921600 },
5049
5050         /*
5051          * SUNIX (TIMEDIA)
5052          */
5053         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5054                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
5055                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
5056                 pbn_b0_bt_1_921600 },
5057
5058         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5059                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
5060                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5061                 pbn_b0_bt_1_921600 },
5062
5063         /*
5064          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5065          */
5066         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5067                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5068                 pbn_b0_bt_8_115200 },
5069         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5070                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5071                 pbn_b0_bt_8_115200 },
5072
5073         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5074                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075                 pbn_b0_bt_2_115200 },
5076         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5077                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5078                 pbn_b0_bt_2_115200 },
5079         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5080                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5081                 pbn_b0_bt_2_115200 },
5082         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
5083                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5084                 pbn_b0_bt_2_115200 },
5085         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
5086                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5087                 pbn_b0_bt_2_115200 },
5088         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5089                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5090                 pbn_b0_bt_4_460800 },
5091         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5092                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5093                 pbn_b0_bt_4_460800 },
5094         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5095                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5096                 pbn_b0_bt_2_460800 },
5097         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5098                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5099                 pbn_b0_bt_2_460800 },
5100         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5101                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5102                 pbn_b0_bt_2_460800 },
5103         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5104                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5105                 pbn_b0_bt_1_115200 },
5106         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5107                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5108                 pbn_b0_bt_1_460800 },
5109
5110         /*
5111          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5112          * Cards are identified by their subsystem vendor IDs, which
5113          * (in hex) match the model number.
5114          *
5115          * Note that JC140x are RS422/485 cards which require ox950
5116          * ACR = 0x10, and as such are not currently fully supported.
5117          */
5118         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5119                 0x1204, 0x0004, 0, 0,
5120                 pbn_b0_4_921600 },
5121         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5122                 0x1208, 0x0004, 0, 0,
5123                 pbn_b0_4_921600 },
5124 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5125                 0x1402, 0x0002, 0, 0,
5126                 pbn_b0_2_921600 }, */
5127 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5128                 0x1404, 0x0004, 0, 0,
5129                 pbn_b0_4_921600 }, */
5130         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5131                 0x1208, 0x0004, 0, 0,
5132                 pbn_b0_4_921600 },
5133
5134         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5135                 0x1204, 0x0004, 0, 0,
5136                 pbn_b0_4_921600 },
5137         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5138                 0x1208, 0x0004, 0, 0,
5139                 pbn_b0_4_921600 },
5140         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5141                 0x1208, 0x0004, 0, 0,
5142                 pbn_b0_4_921600 },
5143         /*
5144          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5145          */
5146         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5147                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5148                 pbn_b1_1_1382400 },
5149
5150         /*
5151          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5152          */
5153         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5154                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5155                 pbn_b1_1_1382400 },
5156
5157         /*
5158          * RAStel 2 port modem, gerg@moreton.com.au
5159          */
5160         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5161                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5162                 pbn_b2_bt_2_115200 },
5163
5164         /*
5165          * EKF addition for i960 Boards form EKF with serial port
5166          */
5167         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5168                 0xE4BF, PCI_ANY_ID, 0, 0,
5169                 pbn_intel_i960 },
5170
5171         /*
5172          * Xircom Cardbus/Ethernet combos
5173          */
5174         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5175                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5176                 pbn_b0_1_115200 },
5177         /*
5178          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5179          */
5180         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5182                 pbn_b0_1_115200 },
5183
5184         /*
5185          * Untested PCI modems, sent in from various folks...
5186          */
5187
5188         /*
5189          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5190          */
5191         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
5192                 0x1048, 0x1500, 0, 0,
5193                 pbn_b1_1_115200 },
5194
5195         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5196                 0xFF00, 0, 0, 0,
5197                 pbn_sgi_ioc3 },
5198
5199         /*
5200          * HP Diva card
5201          */
5202         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5203                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5204                 pbn_b1_1_115200 },
5205         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5206                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5207                 pbn_b0_5_115200 },
5208         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5209                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5210                 pbn_b2_1_115200 },
5211
5212         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5213                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5214                 pbn_b3_2_115200 },
5215         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5216                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5217                 pbn_b3_4_115200 },
5218         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5220                 pbn_b3_8_115200 },
5221
5222         /*
5223          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5224          */
5225         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5226                 PCI_ANY_ID, PCI_ANY_ID,
5227                 0,
5228                 0, pbn_exar_XR17C152 },
5229         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5230                 PCI_ANY_ID, PCI_ANY_ID,
5231                 0,
5232                 0, pbn_exar_XR17C154 },
5233         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5234                 PCI_ANY_ID, PCI_ANY_ID,
5235                 0,
5236                 0, pbn_exar_XR17C158 },
5237         /*
5238          * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5239          */
5240         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5241                 PCI_ANY_ID, PCI_ANY_ID,
5242                 0,
5243                 0, pbn_exar_XR17V352 },
5244         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5245                 PCI_ANY_ID, PCI_ANY_ID,
5246                 0,
5247                 0, pbn_exar_XR17V354 },
5248         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5249                 PCI_ANY_ID, PCI_ANY_ID,
5250                 0,
5251                 0, pbn_exar_XR17V358 },
5252         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5253                 PCI_ANY_ID, PCI_ANY_ID,
5254                 0,
5255                 0, pbn_exar_XR17V4358 },
5256         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5257                 PCI_ANY_ID, PCI_ANY_ID,
5258                 0,
5259                 0, pbn_exar_XR17V8358 },
5260         /*
5261          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5262          */
5263         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5264                 PCI_ANY_ID, PCI_ANY_ID,
5265                 0,
5266                 0, pbn_pericom_PI7C9X7951 },
5267         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5268                 PCI_ANY_ID, PCI_ANY_ID,
5269                 0,
5270                 0, pbn_pericom_PI7C9X7952 },
5271         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5272                 PCI_ANY_ID, PCI_ANY_ID,
5273                 0,
5274                 0, pbn_pericom_PI7C9X7954 },
5275         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5276                 PCI_ANY_ID, PCI_ANY_ID,
5277                 0,
5278                 0, pbn_pericom_PI7C9X7958 },
5279         /*
5280          * ACCES I/O Products quad
5281          */
5282         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5284                 pbn_pericom_PI7C9X7952 },
5285         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5287                 pbn_pericom_PI7C9X7952 },
5288         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5289                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5290                 pbn_pericom_PI7C9X7954 },
5291         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5292                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5293                 pbn_pericom_PI7C9X7954 },
5294         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5295                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5296                 pbn_pericom_PI7C9X7952 },
5297         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5298                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5299                 pbn_pericom_PI7C9X7952 },
5300         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5301                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5302                 pbn_pericom_PI7C9X7954 },
5303         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5304                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5305                 pbn_pericom_PI7C9X7954 },
5306         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5307                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5308                 pbn_pericom_PI7C9X7952 },
5309         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5310                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5311                 pbn_pericom_PI7C9X7952 },
5312         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5313                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5314                 pbn_pericom_PI7C9X7954 },
5315         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5316                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5317                 pbn_pericom_PI7C9X7954 },
5318         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5319                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5320                 pbn_pericom_PI7C9X7951 },
5321         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5322                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5323                 pbn_pericom_PI7C9X7952 },
5324         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5325                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5326                 pbn_pericom_PI7C9X7952 },
5327         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5328                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5329                 pbn_pericom_PI7C9X7954 },
5330         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5331                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5332                 pbn_pericom_PI7C9X7954 },
5333         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5334                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5335                 pbn_pericom_PI7C9X7952 },
5336         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5337                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5338                 pbn_pericom_PI7C9X7954 },
5339         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5340                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5341                 pbn_pericom_PI7C9X7952 },
5342         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5343                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5344                 pbn_pericom_PI7C9X7952 },
5345         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5346                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5347                 pbn_pericom_PI7C9X7954 },
5348         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5349                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5350                 pbn_pericom_PI7C9X7954 },
5351         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5352                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5353                 pbn_pericom_PI7C9X7952 },
5354         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5355                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5356                 pbn_pericom_PI7C9X7954 },
5357         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5358                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5359                 pbn_pericom_PI7C9X7954 },
5360         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5361                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5362                 pbn_pericom_PI7C9X7958 },
5363         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5364                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5365                 pbn_pericom_PI7C9X7958 },
5366         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5367                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5368                 pbn_pericom_PI7C9X7954 },
5369         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5370                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5371                 pbn_pericom_PI7C9X7958 },
5372         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5373                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5374                 pbn_pericom_PI7C9X7954 },
5375         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5376                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5377                 pbn_pericom_PI7C9X7958 },
5378         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5379                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5380                 pbn_pericom_PI7C9X7954 },
5381         /*
5382          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5383          */
5384         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5385                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5386                 pbn_b0_1_115200 },
5387         /*
5388          * ITE
5389          */
5390         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5391                 PCI_ANY_ID, PCI_ANY_ID,
5392                 0, 0,
5393                 pbn_b1_bt_1_115200 },
5394
5395         /*
5396          * IntaShield IS-200
5397          */
5398         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5400                 pbn_b2_2_115200 },
5401         /*
5402          * IntaShield IS-400
5403          */
5404         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5406                 pbn_b2_4_115200 },
5407         /*
5408          * BrainBoxes UC-260
5409          */
5410         {       PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5411                 PCI_ANY_ID, PCI_ANY_ID,
5412                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5413                 pbn_b2_4_115200 },
5414         {       PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5415                 PCI_ANY_ID, PCI_ANY_ID,
5416                  PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5417                 pbn_b2_4_115200 },
5418         /*
5419          * Perle PCI-RAS cards
5420          */
5421         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5422                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5423                 0, 0, pbn_b2_4_921600 },
5424         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5425                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5426                 0, 0, pbn_b2_8_921600 },
5427
5428         /*
5429          * Mainpine series cards: Fairly standard layout but fools
5430          * parts of the autodetect in some cases and uses otherwise
5431          * unmatched communications subclasses in the PCI Express case
5432          */
5433
5434         {       /* RockForceDUO */
5435                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5436                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5437                 0, 0, pbn_b0_2_115200 },
5438         {       /* RockForceQUATRO */
5439                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5440                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5441                 0, 0, pbn_b0_4_115200 },
5442         {       /* RockForceDUO+ */
5443                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5444                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5445                 0, 0, pbn_b0_2_115200 },
5446         {       /* RockForceQUATRO+ */
5447                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5448                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5449                 0, 0, pbn_b0_4_115200 },
5450         {       /* RockForce+ */
5451                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5452                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5453                 0, 0, pbn_b0_2_115200 },
5454         {       /* RockForce+ */
5455                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5456                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5457                 0, 0, pbn_b0_4_115200 },
5458         {       /* RockForceOCTO+ */
5459                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5460                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5461                 0, 0, pbn_b0_8_115200 },
5462         {       /* RockForceDUO+ */
5463                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5464                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5465                 0, 0, pbn_b0_2_115200 },
5466         {       /* RockForceQUARTRO+ */
5467                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5468                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5469                 0, 0, pbn_b0_4_115200 },
5470         {       /* RockForceOCTO+ */
5471                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5472                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5473                 0, 0, pbn_b0_8_115200 },
5474         {       /* RockForceD1 */
5475                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5476                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5477                 0, 0, pbn_b0_1_115200 },
5478         {       /* RockForceF1 */
5479                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5480                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5481                 0, 0, pbn_b0_1_115200 },
5482         {       /* RockForceD2 */
5483                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5484                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5485                 0, 0, pbn_b0_2_115200 },
5486         {       /* RockForceF2 */
5487                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5488                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5489                 0, 0, pbn_b0_2_115200 },
5490         {       /* RockForceD4 */
5491                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5492                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5493                 0, 0, pbn_b0_4_115200 },
5494         {       /* RockForceF4 */
5495                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5496                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5497                 0, 0, pbn_b0_4_115200 },
5498         {       /* RockForceD8 */
5499                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5500                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5501                 0, 0, pbn_b0_8_115200 },
5502         {       /* RockForceF8 */
5503                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5504                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5505                 0, 0, pbn_b0_8_115200 },
5506         {       /* IQ Express D1 */
5507                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5508                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5509                 0, 0, pbn_b0_1_115200 },
5510         {       /* IQ Express F1 */
5511                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5512                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5513                 0, 0, pbn_b0_1_115200 },
5514         {       /* IQ Express D2 */
5515                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5516                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5517                 0, 0, pbn_b0_2_115200 },
5518         {       /* IQ Express F2 */
5519                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5520                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5521                 0, 0, pbn_b0_2_115200 },
5522         {       /* IQ Express D4 */
5523                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5524                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5525                 0, 0, pbn_b0_4_115200 },
5526         {       /* IQ Express F4 */
5527                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5528                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5529                 0, 0, pbn_b0_4_115200 },
5530         {       /* IQ Express D8 */
5531                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5532                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5533                 0, 0, pbn_b0_8_115200 },
5534         {       /* IQ Express F8 */
5535                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5536                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5537                 0, 0, pbn_b0_8_115200 },
5538
5539
5540         /*
5541          * PA Semi PA6T-1682M on-chip UART
5542          */
5543         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5544                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5545                 pbn_pasemi_1682M },
5546
5547         /*
5548          * National Instruments
5549          */
5550         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5551                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5552                 pbn_b1_16_115200 },
5553         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5554                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5555                 pbn_b1_8_115200 },
5556         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5557                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5558                 pbn_b1_bt_4_115200 },
5559         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5560                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5561                 pbn_b1_bt_2_115200 },
5562         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5563                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5564                 pbn_b1_bt_4_115200 },
5565         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5566                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5567                 pbn_b1_bt_2_115200 },
5568         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5569                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5570                 pbn_b1_16_115200 },
5571         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5572                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5573                 pbn_b1_8_115200 },
5574         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5575                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5576                 pbn_b1_bt_4_115200 },
5577         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5578                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5579                 pbn_b1_bt_2_115200 },
5580         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5581                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5582                 pbn_b1_bt_4_115200 },
5583         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5584                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5585                 pbn_b1_bt_2_115200 },
5586         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5587                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5588                 pbn_ni8430_2 },
5589         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5590                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5591                 pbn_ni8430_2 },
5592         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5593                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5594                 pbn_ni8430_4 },
5595         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5596                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5597                 pbn_ni8430_4 },
5598         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5599                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5600                 pbn_ni8430_8 },
5601         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5602                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5603                 pbn_ni8430_8 },
5604         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5605                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5606                 pbn_ni8430_16 },
5607         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5608                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5609                 pbn_ni8430_16 },
5610         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5611                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5612                 pbn_ni8430_2 },
5613         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5614                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5615                 pbn_ni8430_2 },
5616         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5617                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5618                 pbn_ni8430_4 },
5619         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5620                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5621                 pbn_ni8430_4 },
5622
5623         /*
5624         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5625         */
5626         {       PCI_VENDOR_ID_ADDIDATA,
5627                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5628                 PCI_ANY_ID,
5629                 PCI_ANY_ID,
5630                 0,
5631                 0,
5632                 pbn_b0_4_115200 },
5633
5634         {       PCI_VENDOR_ID_ADDIDATA,
5635                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5636                 PCI_ANY_ID,
5637                 PCI_ANY_ID,
5638                 0,
5639                 0,
5640                 pbn_b0_2_115200 },
5641
5642         {       PCI_VENDOR_ID_ADDIDATA,
5643                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5644                 PCI_ANY_ID,
5645                 PCI_ANY_ID,
5646                 0,
5647                 0,
5648                 pbn_b0_1_115200 },
5649
5650         {       PCI_VENDOR_ID_AMCC,
5651                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5652                 PCI_ANY_ID,
5653                 PCI_ANY_ID,
5654                 0,
5655                 0,
5656                 pbn_b1_8_115200 },
5657
5658         {       PCI_VENDOR_ID_ADDIDATA,
5659                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5660                 PCI_ANY_ID,
5661                 PCI_ANY_ID,
5662                 0,
5663                 0,
5664                 pbn_b0_4_115200 },
5665
5666         {       PCI_VENDOR_ID_ADDIDATA,
5667                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5668                 PCI_ANY_ID,
5669                 PCI_ANY_ID,
5670                 0,
5671                 0,
5672                 pbn_b0_2_115200 },
5673
5674         {       PCI_VENDOR_ID_ADDIDATA,
5675                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5676                 PCI_ANY_ID,
5677                 PCI_ANY_ID,
5678                 0,
5679                 0,
5680                 pbn_b0_1_115200 },
5681
5682         {       PCI_VENDOR_ID_ADDIDATA,
5683                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5684                 PCI_ANY_ID,
5685                 PCI_ANY_ID,
5686                 0,
5687                 0,
5688                 pbn_b0_4_115200 },
5689
5690         {       PCI_VENDOR_ID_ADDIDATA,
5691                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5692                 PCI_ANY_ID,
5693                 PCI_ANY_ID,
5694                 0,
5695                 0,
5696                 pbn_b0_2_115200 },
5697
5698         {       PCI_VENDOR_ID_ADDIDATA,
5699                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5700                 PCI_ANY_ID,
5701                 PCI_ANY_ID,
5702                 0,
5703                 0,
5704                 pbn_b0_1_115200 },
5705
5706         {       PCI_VENDOR_ID_ADDIDATA,
5707                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5708                 PCI_ANY_ID,
5709                 PCI_ANY_ID,
5710                 0,
5711                 0,
5712                 pbn_b0_8_115200 },
5713
5714         {       PCI_VENDOR_ID_ADDIDATA,
5715                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5716                 PCI_ANY_ID,
5717                 PCI_ANY_ID,
5718                 0,
5719                 0,
5720                 pbn_ADDIDATA_PCIe_4_3906250 },
5721
5722         {       PCI_VENDOR_ID_ADDIDATA,
5723                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5724                 PCI_ANY_ID,
5725                 PCI_ANY_ID,
5726                 0,
5727                 0,
5728                 pbn_ADDIDATA_PCIe_2_3906250 },
5729
5730         {       PCI_VENDOR_ID_ADDIDATA,
5731                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5732                 PCI_ANY_ID,
5733                 PCI_ANY_ID,
5734                 0,
5735                 0,
5736                 pbn_ADDIDATA_PCIe_1_3906250 },
5737
5738         {       PCI_VENDOR_ID_ADDIDATA,
5739                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5740                 PCI_ANY_ID,
5741                 PCI_ANY_ID,
5742                 0,
5743                 0,
5744                 pbn_ADDIDATA_PCIe_8_3906250 },
5745
5746         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5747                 PCI_VENDOR_ID_IBM, 0x0299,
5748                 0, 0, pbn_b0_bt_2_115200 },
5749
5750         /*
5751          * other NetMos 9835 devices are most likely handled by the
5752          * parport_serial driver, check drivers/parport/parport_serial.c
5753          * before adding them here.
5754          */
5755
5756         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5757                 0xA000, 0x1000,
5758                 0, 0, pbn_b0_1_115200 },
5759
5760         /* the 9901 is a rebranded 9912 */
5761         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5762                 0xA000, 0x1000,
5763                 0, 0, pbn_b0_1_115200 },
5764
5765         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5766                 0xA000, 0x1000,
5767                 0, 0, pbn_b0_1_115200 },
5768
5769         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5770                 0xA000, 0x1000,
5771                 0, 0, pbn_b0_1_115200 },
5772
5773         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5774                 0xA000, 0x1000,
5775                 0, 0, pbn_b0_1_115200 },
5776
5777         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5778                 0xA000, 0x3002,
5779                 0, 0, pbn_NETMOS9900_2s_115200 },
5780
5781         /*
5782          * Best Connectivity and Rosewill PCI Multi I/O cards
5783          */
5784
5785         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5786                 0xA000, 0x1000,
5787                 0, 0, pbn_b0_1_115200 },
5788
5789         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5790                 0xA000, 0x3002,
5791                 0, 0, pbn_b0_bt_2_115200 },
5792
5793         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5794                 0xA000, 0x3004,
5795                 0, 0, pbn_b0_bt_4_115200 },
5796         /* Intel CE4100 */
5797         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5798                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5799                 pbn_ce4100_1_115200 },
5800         /* Intel BayTrail */
5801         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5802                 PCI_ANY_ID,  PCI_ANY_ID,
5803                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5804                 pbn_byt },
5805         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5806                 PCI_ANY_ID,  PCI_ANY_ID,
5807                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5808                 pbn_byt },
5809         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5810                 PCI_ANY_ID,  PCI_ANY_ID,
5811                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5812                 pbn_byt },
5813         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5814                 PCI_ANY_ID,  PCI_ANY_ID,
5815                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5816                 pbn_byt },
5817
5818         /* Intel Broadwell */
5819         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5820                 PCI_ANY_ID,  PCI_ANY_ID,
5821                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5822                 pbn_byt },
5823         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5824                 PCI_ANY_ID,  PCI_ANY_ID,
5825                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5826                 pbn_byt },
5827
5828         /*
5829          * Intel Quark x1000
5830          */
5831         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5832                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5833                 pbn_qrk },
5834         /*
5835          * Cronyx Omega PCI
5836          */
5837         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5838                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5839                 pbn_omegapci },
5840
5841         /*
5842          * Broadcom TruManage
5843          */
5844         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5845                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5846                 pbn_brcm_trumanage },
5847
5848         /*
5849          * AgeStar as-prs2-009
5850          */
5851         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5852                 PCI_ANY_ID, PCI_ANY_ID,
5853                 0, 0, pbn_b0_bt_2_115200 },
5854
5855         /*
5856          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5857          * so not listed here.
5858          */
5859         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5860                 PCI_ANY_ID, PCI_ANY_ID,
5861                 0, 0, pbn_b0_bt_4_115200 },
5862
5863         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5864                 PCI_ANY_ID, PCI_ANY_ID,
5865                 0, 0, pbn_b0_bt_2_115200 },
5866
5867         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5868                 PCI_ANY_ID, PCI_ANY_ID,
5869                 0, 0, pbn_wch382_2 },
5870
5871         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5872                 PCI_ANY_ID, PCI_ANY_ID,
5873                 0, 0, pbn_wch384_4 },
5874
5875         /*
5876          * Commtech, Inc. Fastcom adapters
5877          */
5878         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5879                 PCI_ANY_ID, PCI_ANY_ID,
5880                 0,
5881                 0, pbn_b0_2_1152000_200 },
5882         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5883                 PCI_ANY_ID, PCI_ANY_ID,
5884                 0,
5885                 0, pbn_b0_4_1152000_200 },
5886         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5887                 PCI_ANY_ID, PCI_ANY_ID,
5888                 0,
5889                 0, pbn_b0_4_1152000_200 },
5890         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5891                 PCI_ANY_ID, PCI_ANY_ID,
5892                 0,
5893                 0, pbn_b0_8_1152000_200 },
5894         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5895                 PCI_ANY_ID, PCI_ANY_ID,
5896                 0,
5897                 0, pbn_exar_XR17V352 },
5898         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5899                 PCI_ANY_ID, PCI_ANY_ID,
5900                 0,
5901                 0, pbn_exar_XR17V354 },
5902         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5903                 PCI_ANY_ID, PCI_ANY_ID,
5904                 0,
5905                 0, pbn_exar_XR17V358 },
5906
5907         /*
5908          * Realtek RealManage
5909          */
5910         {       PCI_VENDOR_ID_REALTEK, 0x816a,
5911                 PCI_ANY_ID, PCI_ANY_ID,
5912                 0, 0, pbn_b0_1_115200 },
5913
5914         {       PCI_VENDOR_ID_REALTEK, 0x816b,
5915                 PCI_ANY_ID, PCI_ANY_ID,
5916                 0, 0, pbn_b0_1_115200 },
5917
5918         /* Fintek PCI serial cards */
5919         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5920         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5921         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5922
5923         /* MKS Tenta SCOM-080x serial cards */
5924         { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5925         { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5926
5927         /* Amazon PCI serial device */
5928         { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5929
5930         /*
5931          * These entries match devices with class COMMUNICATION_SERIAL,
5932          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5933          */
5934         {       PCI_ANY_ID, PCI_ANY_ID,
5935                 PCI_ANY_ID, PCI_ANY_ID,
5936                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5937                 0xffff00, pbn_default },
5938         {       PCI_ANY_ID, PCI_ANY_ID,
5939                 PCI_ANY_ID, PCI_ANY_ID,
5940                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5941                 0xffff00, pbn_default },
5942         {       PCI_ANY_ID, PCI_ANY_ID,
5943                 PCI_ANY_ID, PCI_ANY_ID,
5944                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5945                 0xffff00, pbn_default },
5946         { 0, }
5947 };
5948
5949 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5950                                                 pci_channel_state_t state)
5951 {
5952         struct serial_private *priv = pci_get_drvdata(dev);
5953
5954         if (state == pci_channel_io_perm_failure)
5955                 return PCI_ERS_RESULT_DISCONNECT;
5956
5957         if (priv)
5958                 pciserial_detach_ports(priv);
5959
5960         pci_disable_device(dev);
5961
5962         return PCI_ERS_RESULT_NEED_RESET;
5963 }
5964
5965 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5966 {
5967         int rc;
5968
5969         rc = pci_enable_device(dev);
5970
5971         if (rc)
5972                 return PCI_ERS_RESULT_DISCONNECT;
5973
5974         pci_restore_state(dev);
5975         pci_save_state(dev);
5976
5977         return PCI_ERS_RESULT_RECOVERED;
5978 }
5979
5980 static void serial8250_io_resume(struct pci_dev *dev)
5981 {
5982         struct serial_private *priv = pci_get_drvdata(dev);
5983         struct serial_private *new;
5984
5985         if (!priv)
5986                 return;
5987
5988         new = pciserial_init_ports(dev, priv->board);
5989         if (!IS_ERR(new)) {
5990                 pci_set_drvdata(dev, new);
5991                 kfree(priv);
5992         }
5993 }
5994
5995 static const struct pci_error_handlers serial8250_err_handler = {
5996         .error_detected = serial8250_io_error_detected,
5997         .slot_reset = serial8250_io_slot_reset,
5998         .resume = serial8250_io_resume,
5999 };
6000
6001 static struct pci_driver serial_pci_driver = {
6002         .name           = "serial",
6003         .probe          = pciserial_init_one,
6004         .remove         = pciserial_remove_one,
6005         .driver         = {
6006                 .pm     = &pciserial_pm_ops,
6007         },
6008         .id_table       = serial_pci_tbl,
6009         .err_handler    = &serial8250_err_handler,
6010 };
6011
6012 module_pci_driver(serial_pci_driver);
6013
6014 MODULE_LICENSE("GPL");
6015 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6016 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);