1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type PCI serial ports.
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
22 #include <asm/byteorder.h>
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
33 struct pci_serial_quirk {
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
51 struct serial_private {
54 struct pci_serial_quirk *quirk;
55 const struct pciserial_board *board;
59 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
61 static const struct pci_device_id pci_use_msi[] = {
62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
69 PCI_ANY_ID, PCI_ANY_ID) },
73 static int pci_default_setup(struct serial_private*,
74 const struct pciserial_board*, struct uart_8250_port *, int);
76 static void moan_device(const char *str, struct pci_dev *dev)
79 "Please send the output of lspci -vv, this\n"
80 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
81 "manufacturer and name of serial board or\n"
82 "modem board to <linux-serial@vger.kernel.org>.\n",
83 str, dev->vendor, dev->device,
84 dev->subsystem_vendor, dev->subsystem_device);
88 setup_port(struct serial_private *priv, struct uart_8250_port *port,
89 u8 bar, unsigned int offset, int regshift)
91 struct pci_dev *dev = priv->dev;
93 if (bar >= PCI_STD_NUM_BARS)
96 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
97 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
100 port->port.iotype = UPIO_MEM;
101 port->port.iobase = 0;
102 port->port.mapbase = pci_resource_start(dev, bar) + offset;
103 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
104 port->port.regshift = regshift;
106 port->port.iotype = UPIO_PORT;
107 port->port.iobase = pci_resource_start(dev, bar) + offset;
108 port->port.mapbase = 0;
109 port->port.membase = NULL;
110 port->port.regshift = 0;
116 * ADDI-DATA GmbH communication cards <info@addi-data.com>
118 static int addidata_apci7800_setup(struct serial_private *priv,
119 const struct pciserial_board *board,
120 struct uart_8250_port *port, int idx)
122 unsigned int bar = 0, offset = board->first_offset;
123 bar = FL_GET_BASE(board->flags);
126 offset += idx * board->uart_offset;
127 } else if ((idx >= 2) && (idx < 4)) {
129 offset += ((idx - 2) * board->uart_offset);
130 } else if ((idx >= 4) && (idx < 6)) {
132 offset += ((idx - 4) * board->uart_offset);
133 } else if (idx >= 6) {
135 offset += ((idx - 6) * board->uart_offset);
138 return setup_port(priv, port, bar, offset, board->reg_shift);
142 * AFAVLAB uses a different mixture of BARs and offsets
143 * Not that ugly ;) -- HW
146 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
147 struct uart_8250_port *port, int idx)
149 unsigned int bar, offset = board->first_offset;
151 bar = FL_GET_BASE(board->flags);
156 offset += (idx - 4) * board->uart_offset;
159 return setup_port(priv, port, bar, offset, board->reg_shift);
163 * HP's Remote Management Console. The Diva chip came in several
164 * different versions. N-class, L2000 and A500 have two Diva chips, each
165 * with 3 UARTs (the third UART on the second chip is unused). Superdome
166 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
167 * one Diva chip, but it has been expanded to 5 UARTs.
169 static int pci_hp_diva_init(struct pci_dev *dev)
173 switch (dev->subsystem_device) {
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
175 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
176 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
177 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
180 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
183 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
186 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
187 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
196 * HP's Diva chip puts the 4th/5th serial port further out, and
197 * some serial ports are supposed to be hidden on certain models.
200 pci_hp_diva_setup(struct serial_private *priv,
201 const struct pciserial_board *board,
202 struct uart_8250_port *port, int idx)
204 unsigned int offset = board->first_offset;
205 unsigned int bar = FL_GET_BASE(board->flags);
207 switch (priv->dev->subsystem_device) {
208 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
212 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
222 offset += idx * board->uart_offset;
224 return setup_port(priv, port, bar, offset, board->reg_shift);
228 * Added for EKF Intel i960 serial boards
230 static int pci_inteli960ni_init(struct pci_dev *dev)
234 if (!(dev->subsystem_device & 0x1000))
237 /* is firmware started? */
238 pci_read_config_dword(dev, 0x44, &oldval);
239 if (oldval == 0x00001000L) { /* RESET value */
240 pci_dbg(dev, "Local i960 firmware missing\n");
247 * Some PCI serial cards using the PLX 9050 PCI interface chip require
248 * that the card interrupt be explicitly enabled or disabled. This
249 * seems to be mainly needed on card using the PLX which also use I/O
252 static int pci_plx9050_init(struct pci_dev *dev)
257 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
258 moan_device("no memory in bar 0", dev);
263 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
264 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
267 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
268 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
270 * As the megawolf cards have the int pins active
271 * high, and have 2 UART chips, both ints must be
272 * enabled on the 9050. Also, the UARTS are set in
273 * 16450 mode by default, so we have to enable the
274 * 16C950 'enhanced' mode so that we can use the
279 * enable/disable interrupts
281 p = ioremap(pci_resource_start(dev, 0), 0x80);
284 writel(irq_config, p + 0x4c);
287 * Read the register back to ensure that it took effect.
295 static void pci_plx9050_exit(struct pci_dev *dev)
299 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
305 p = ioremap(pci_resource_start(dev, 0), 0x80);
310 * Read the register back to ensure that it took effect.
317 #define NI8420_INT_ENABLE_REG 0x38
318 #define NI8420_INT_ENABLE_BIT 0x2000
320 static void pci_ni8420_exit(struct pci_dev *dev)
323 unsigned int bar = 0;
325 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
326 moan_device("no memory in bar", dev);
330 p = pci_ioremap_bar(dev, bar);
334 /* Disable the CPU Interrupt */
335 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
336 p + NI8420_INT_ENABLE_REG);
342 #define MITE_IOWBSR1 0xc4
343 #define MITE_IOWCR1 0xf4
344 #define MITE_LCIMR1 0x08
345 #define MITE_LCIMR2 0x10
347 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
349 static void pci_ni8430_exit(struct pci_dev *dev)
352 unsigned int bar = 0;
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
359 p = pci_ioremap_bar(dev, bar);
363 /* Disable the CPU Interrupt */
364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
371 struct uart_8250_port *port, int idx)
373 unsigned int bar, offset = board->first_offset;
378 /* first four channels map to 0, 0x100, 0x200, 0x300 */
379 offset += idx * board->uart_offset;
380 } else if (idx < 8) {
381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
382 offset += idx * board->uart_offset + 0xC00;
383 } else /* we have only 8 ports on PMC-OCTALPRO */
386 return setup_port(priv, port, bar, offset, board->reg_shift);
390 * This does initialization for PMC OCTALPRO cards:
391 * maps the device memory, resets the UARTs (needed, bc
392 * if the module is removed and inserted again, the card
393 * is in the sleep mode) and enables global interrupt.
396 /* global control register offset for SBS PMC-OctalPro */
397 #define OCT_REG_CR_OFF 0x500
399 static int sbs_init(struct pci_dev *dev)
403 p = pci_ioremap_bar(dev, 0);
407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
408 writeb(0x10, p + OCT_REG_CR_OFF);
410 writeb(0x0, p + OCT_REG_CR_OFF);
412 /* Set bit-2 (INTENABLE) of Control Register */
413 writeb(0x4, p + OCT_REG_CR_OFF);
420 * Disables the global interrupt of PMC-OctalPro
423 static void sbs_exit(struct pci_dev *dev)
427 p = pci_ioremap_bar(dev, 0);
428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 writeb(0, p + OCT_REG_CR_OFF);
435 * SIIG serial cards have an PCI interface chip which also controls
436 * the UART clocking frequency. Each UART can be clocked independently
437 * (except cards equipped with 4 UARTs) and initial clocking settings
438 * are stored in the EEPROM chip. It can cause problems because this
439 * version of serial driver doesn't support differently clocked UART's
440 * on single PCI card. To prevent this, initialization functions set
441 * high frequency clocking for all UART's on given card. It is safe (I
442 * hope) because it doesn't touch EEPROM settings to prevent conflicts
443 * with other OSes (like M$ DOS).
445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
447 * There is two family of SIIG serial cards with different PCI
448 * interface chip and different configuration methods:
449 * - 10x cards have control registers in IO and/or memory space;
450 * - 20x cards have control registers in standard PCI configuration space.
452 * Note: all 10x cards have PCI device ids 0x10..
453 * all 20x cards have PCI device ids 0x20..
455 * There are also Quartet Serial cards which use Oxford Semiconductor
456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 * Note: some SIIG cards are probed by the parport_serial object.
461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464 static int pci_siig10x_init(struct pci_dev *dev)
469 switch (dev->device & 0xfff8) {
470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476 default: /* 1S1P, 4S */
481 p = ioremap(pci_resource_start(dev, 0), 0x80);
485 writew(readw(p + 0x28) & data, p + 0x28);
491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494 static int pci_siig20x_init(struct pci_dev *dev)
498 /* Change clock frequency for the first UART. */
499 pci_read_config_byte(dev, 0x6f, &data);
500 pci_write_config_byte(dev, 0x6f, data & 0xef);
502 /* If this card has 2 UART, we have to do the same with second UART. */
503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
505 pci_read_config_byte(dev, 0x73, &data);
506 pci_write_config_byte(dev, 0x73, data & 0xef);
511 static int pci_siig_init(struct pci_dev *dev)
513 unsigned int type = dev->device & 0xff00;
516 return pci_siig10x_init(dev);
517 else if (type == 0x2000)
518 return pci_siig20x_init(dev);
520 moan_device("Unknown SIIG card", dev);
524 static int pci_siig_setup(struct serial_private *priv,
525 const struct pciserial_board *board,
526 struct uart_8250_port *port, int idx)
528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
532 offset = (idx - 4) * 8;
535 return setup_port(priv, port, bar, offset, 0);
539 * Timedia has an explosion of boards, and to avoid the PCI table from
540 * growing *huge*, we use this function to collapse some 70 entries
541 * in the PCI table into one, for sanity's and compactness's sake.
543 static const unsigned short timedia_single_port[] = {
544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547 static const unsigned short timedia_dual_port[] = {
548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
555 static const unsigned short timedia_quad_port[] = {
556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
562 static const unsigned short timedia_eight_port[] = {
563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567 static const struct timedia_struct {
569 const unsigned short *ids;
571 { 1, timedia_single_port },
572 { 2, timedia_dual_port },
573 { 4, timedia_quad_port },
574 { 8, timedia_eight_port }
578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
579 * listing them individually, this driver merely grabs them all with
580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
581 * and should be left free to be claimed by parport_serial instead.
583 static int pci_timedia_probe(struct pci_dev *dev)
586 * Check the third digit of the subdevice ID
587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
590 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
591 dev->subsystem_device);
598 static int pci_timedia_init(struct pci_dev *dev)
600 const unsigned short *ids;
603 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
604 ids = timedia_data[i].ids;
605 for (j = 0; ids[j]; j++)
606 if (dev->subsystem_device == ids[j])
607 return timedia_data[i].num;
613 * Timedia/SUNIX uses a mixture of BARs and offsets
614 * Ugh, this is ugly as all hell --- TYT
617 pci_timedia_setup(struct serial_private *priv,
618 const struct pciserial_board *board,
619 struct uart_8250_port *port, int idx)
621 unsigned int bar = 0, offset = board->first_offset;
628 offset = board->uart_offset;
635 offset = board->uart_offset;
644 return setup_port(priv, port, bar, offset, board->reg_shift);
648 * Some Titan cards are also a little weird
651 titan_400l_800l_setup(struct serial_private *priv,
652 const struct pciserial_board *board,
653 struct uart_8250_port *port, int idx)
655 unsigned int bar, offset = board->first_offset;
666 offset = (idx - 2) * board->uart_offset;
669 return setup_port(priv, port, bar, offset, board->reg_shift);
672 static int pci_xircom_init(struct pci_dev *dev)
678 static int pci_ni8420_init(struct pci_dev *dev)
681 unsigned int bar = 0;
683 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
684 moan_device("no memory in bar", dev);
688 p = pci_ioremap_bar(dev, bar);
692 /* Enable CPU Interrupt */
693 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
694 p + NI8420_INT_ENABLE_REG);
700 #define MITE_IOWBSR1_WSIZE 0xa
701 #define MITE_IOWBSR1_WIN_OFFSET 0x800
702 #define MITE_IOWBSR1_WENAB (1 << 7)
703 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
704 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
705 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
707 static int pci_ni8430_init(struct pci_dev *dev)
710 struct pci_bus_region region;
712 unsigned int bar = 0;
714 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
715 moan_device("no memory in bar", dev);
719 p = pci_ioremap_bar(dev, bar);
724 * Set device window address and size in BAR0, while acknowledging that
725 * the resource structure may contain a translated address that differs
726 * from the address the device responds to.
728 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
729 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
730 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
731 writel(device_window, p + MITE_IOWBSR1);
733 /* Set window access to go to RAMSEL IO address space */
734 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 /* Enable IO Bus Interrupt 0 */
738 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
740 /* Enable CPU Interrupt */
741 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
747 /* UART Port Control Register */
748 #define NI8430_PORTCON 0x0f
749 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752 pci_ni8430_setup(struct serial_private *priv,
753 const struct pciserial_board *board,
754 struct uart_8250_port *port, int idx)
756 struct pci_dev *dev = priv->dev;
758 unsigned int bar, offset = board->first_offset;
760 if (idx >= board->num_ports)
763 bar = FL_GET_BASE(board->flags);
764 offset += idx * board->uart_offset;
766 p = pci_ioremap_bar(dev, bar);
770 /* enable the transceiver */
771 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
772 p + offset + NI8430_PORTCON);
776 return setup_port(priv, port, bar, offset, board->reg_shift);
779 static int pci_netmos_9900_setup(struct serial_private *priv,
780 const struct pciserial_board *board,
781 struct uart_8250_port *port, int idx)
785 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
786 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
787 /* netmos apparently orders BARs by datasheet layout, so serial
788 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
792 return setup_port(priv, port, bar, 0, board->reg_shift);
794 return pci_default_setup(priv, board, port, idx);
798 /* the 99xx series comes with a range of device IDs and a variety
801 * 9900 has varying capabilities and can cascade to sub-controllers
802 * (cascading should be purely internal)
803 * 9904 is hardwired with 4 serial ports
804 * 9912 and 9922 are hardwired with 2 serial ports
806 static int pci_netmos_9900_numports(struct pci_dev *dev)
808 unsigned int c = dev->class;
810 unsigned short sub_serports;
817 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
818 /* two possibilities: 0x30ps encodes number of parallel and
819 * serial ports, or 0x1000 indicates *something*. This is not
820 * immediately obvious, since the 2s1p+4s configuration seems
821 * to offer all functionality on functions 0..2, while still
822 * advertising the same function 3 as the 4s+2s1p config.
824 sub_serports = dev->subsystem_device & 0xf;
825 if (sub_serports > 0)
828 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
832 moan_device("unknown NetMos/Mostech program interface", dev);
836 static int pci_netmos_init(struct pci_dev *dev)
838 /* subdevice 0x00PS means <P> parallel, <S> serial */
839 unsigned int num_serial = dev->subsystem_device & 0xf;
841 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
842 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
845 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
846 dev->subsystem_device == 0x0299)
849 switch (dev->device) { /* FALLTHROUGH on all */
850 case PCI_DEVICE_ID_NETMOS_9904:
851 case PCI_DEVICE_ID_NETMOS_9912:
852 case PCI_DEVICE_ID_NETMOS_9922:
853 case PCI_DEVICE_ID_NETMOS_9900:
854 num_serial = pci_netmos_9900_numports(dev);
861 if (num_serial == 0) {
862 moan_device("unknown NetMos/Mostech device", dev);
870 * These chips are available with optionally one parallel port and up to
871 * two serial ports. Unfortunately they all have the same product id.
873 * Basic configuration is done over a region of 32 I/O ports. The base
874 * ioport is called INTA or INTC, depending on docs/other drivers.
876 * The region of the 32 I/O ports is configured in POSIO0R...
880 #define ITE_887x_MISCR 0x9c
881 #define ITE_887x_INTCBAR 0x78
882 #define ITE_887x_UARTBAR 0x7c
883 #define ITE_887x_PS0BAR 0x10
884 #define ITE_887x_POSIO0 0x60
887 #define ITE_887x_IOSIZE 32
888 /* I/O space size (bits 26-24; 8 bytes = 011b) */
889 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
890 /* I/O space size (bits 26-24; 32 bytes = 101b) */
891 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
892 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
893 #define ITE_887x_POSIO_SPEED (3 << 29)
894 /* enable IO_Space bit */
895 #define ITE_887x_POSIO_ENABLE (1 << 31)
897 /* inta_addr are the configuration addresses of the ITE */
898 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
899 static int pci_ite887x_init(struct pci_dev *dev)
902 struct resource *iobase = NULL;
903 u32 miscr, uartbar, ioport;
905 /* search for the base-ioport */
906 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
907 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
909 if (iobase != NULL) {
910 /* write POSIO0R - speed | size | ioport */
911 pci_write_config_dword(dev, ITE_887x_POSIO0,
912 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
913 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
914 /* write INTCBAR - ioport */
915 pci_write_config_dword(dev, ITE_887x_INTCBAR,
917 ret = inb(inta_addr[i]);
919 /* ioport connected */
922 release_region(iobase->start, ITE_887x_IOSIZE);
926 if (i == ARRAY_SIZE(inta_addr)) {
927 pci_err(dev, "could not find iobase\n");
931 /* start of undocumented type checking (see parport_pc.c) */
932 type = inb(iobase->start + 0x18) & 0x0f;
935 case 0x2: /* ITE8871 (1P) */
936 case 0xa: /* ITE8875 (1P) */
939 case 0xe: /* ITE8872 (2S1P) */
942 case 0x6: /* ITE8873 (1S) */
945 case 0x8: /* ITE8874 (2S) */
949 moan_device("Unknown ITE887x", dev);
953 /* configure all serial ports */
954 for (i = 0; i < ret; i++) {
955 /* read the I/O port from the device */
956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
958 ioport &= 0x0000FF00; /* the actual base address */
959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
961 ITE_887x_POSIO_IOSIZE_8 | ioport);
963 /* write the ioport to the UARTBAR */
964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
966 uartbar |= (ioport << (16 * i)); /* set the ioport */
967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
969 /* get current config */
970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
971 /* disable interrupts (UARTx_Routing[3:0]) */
972 miscr &= ~(0xf << (12 - 4 * i));
973 /* activate the UART (UARTx_En) */
974 miscr |= 1 << (23 - i);
975 /* write new config with activated UART */
976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
980 /* the device has no UARTs if we get here */
981 release_region(iobase->start, ITE_887x_IOSIZE);
987 static void pci_ite887x_exit(struct pci_dev *dev)
990 /* the ioport is bit 0-15 in POSIO0R */
991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
993 release_region(ioport, ITE_887x_IOSIZE);
997 * Oxford Semiconductor Inc.
998 * Check if an OxSemi device is part of the Tornado range of devices.
1000 #define PCI_VENDOR_ID_ENDRUN 0x7401
1001 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1003 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1005 /* OxSemi Tornado devices are all 0xCxxx */
1006 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1007 (dev->device & 0xf000) != 0xc000)
1010 /* EndRun devices are all 0xExxx */
1011 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1012 (dev->device & 0xf000) != 0xe000)
1019 * Determine the number of ports available on a Tornado device.
1021 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1024 unsigned long deviceID;
1025 unsigned int number_uarts = 0;
1027 if (!pci_oxsemi_tornado_p(dev))
1030 p = pci_iomap(dev, 0, 5);
1034 deviceID = ioread32(p);
1035 /* Tornado device */
1036 if (deviceID == 0x07000200) {
1037 number_uarts = ioread8(p + 4);
1038 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1040 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1041 "EndRun" : "Oxford");
1043 pci_iounmap(dev, p);
1044 return number_uarts;
1047 static int pci_asix_setup(struct serial_private *priv,
1048 const struct pciserial_board *board,
1049 struct uart_8250_port *port, int idx)
1051 port->bugs |= UART_BUG_PARITY;
1052 return pci_default_setup(priv, board, port, idx);
1055 /* Quatech devices have their own extra interface features */
1057 struct quatech_feature {
1062 #define QPCR_TEST_FOR1 0x3F
1063 #define QPCR_TEST_GET1 0x00
1064 #define QPCR_TEST_FOR2 0x40
1065 #define QPCR_TEST_GET2 0x40
1066 #define QPCR_TEST_FOR3 0x80
1067 #define QPCR_TEST_GET3 0x40
1068 #define QPCR_TEST_FOR4 0xC0
1069 #define QPCR_TEST_GET4 0x80
1071 #define QOPR_CLOCK_X1 0x0000
1072 #define QOPR_CLOCK_X2 0x0001
1073 #define QOPR_CLOCK_X4 0x0002
1074 #define QOPR_CLOCK_X8 0x0003
1075 #define QOPR_CLOCK_RATE_MASK 0x0003
1078 static struct quatech_feature quatech_cards[] = {
1079 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1080 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1081 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1083 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1084 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1085 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1086 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1087 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1088 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1089 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1090 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1091 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1092 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1093 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1094 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1095 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1096 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1097 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1101 static int pci_quatech_amcc(struct pci_dev *dev)
1103 struct quatech_feature *qf = &quatech_cards[0];
1105 if (qf->devid == dev->device)
1109 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1113 static int pci_quatech_rqopr(struct uart_8250_port *port)
1115 unsigned long base = port->port.iobase;
1118 LCR = inb(base + UART_LCR);
1119 outb(0xBF, base + UART_LCR);
1120 val = inb(base + UART_SCR);
1121 outb(LCR, base + UART_LCR);
1125 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1127 unsigned long base = port->port.iobase;
1130 LCR = inb(base + UART_LCR);
1131 outb(0xBF, base + UART_LCR);
1132 inb(base + UART_SCR);
1133 outb(qopr, base + UART_SCR);
1134 outb(LCR, base + UART_LCR);
1137 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1139 unsigned long base = port->port.iobase;
1142 LCR = inb(base + UART_LCR);
1143 outb(0xBF, base + UART_LCR);
1144 val = inb(base + UART_SCR);
1145 outb(val | 0x10, base + UART_SCR);
1146 qmcr = inb(base + UART_MCR);
1147 outb(val, base + UART_SCR);
1148 outb(LCR, base + UART_LCR);
1153 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1155 unsigned long base = port->port.iobase;
1158 LCR = inb(base + UART_LCR);
1159 outb(0xBF, base + UART_LCR);
1160 val = inb(base + UART_SCR);
1161 outb(val | 0x10, base + UART_SCR);
1162 outb(qmcr, base + UART_MCR);
1163 outb(val, base + UART_SCR);
1164 outb(LCR, base + UART_LCR);
1167 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1169 unsigned long base = port->port.iobase;
1172 LCR = inb(base + UART_LCR);
1173 outb(0xBF, base + UART_LCR);
1174 val = inb(base + UART_SCR);
1176 outb(0x80, UART_LCR);
1177 if (!(inb(UART_SCR) & 0x20)) {
1178 outb(LCR, base + UART_LCR);
1185 static int pci_quatech_test(struct uart_8250_port *port)
1189 qopr = pci_quatech_rqopr(port);
1190 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1191 reg = pci_quatech_rqopr(port) & 0xC0;
1192 if (reg != QPCR_TEST_GET1)
1194 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1195 reg = pci_quatech_rqopr(port) & 0xC0;
1196 if (reg != QPCR_TEST_GET2)
1198 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1199 reg = pci_quatech_rqopr(port) & 0xC0;
1200 if (reg != QPCR_TEST_GET3)
1202 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1203 reg = pci_quatech_rqopr(port) & 0xC0;
1204 if (reg != QPCR_TEST_GET4)
1207 pci_quatech_wqopr(port, qopr);
1211 static int pci_quatech_clock(struct uart_8250_port *port)
1214 unsigned long clock;
1216 if (pci_quatech_test(port) < 0)
1219 qopr = pci_quatech_rqopr(port);
1221 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1222 reg = pci_quatech_rqopr(port);
1223 if (reg & QOPR_CLOCK_X8) {
1227 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1228 reg = pci_quatech_rqopr(port);
1229 if (!(reg & QOPR_CLOCK_X8)) {
1233 reg &= QOPR_CLOCK_X8;
1234 if (reg == QOPR_CLOCK_X2) {
1236 set = QOPR_CLOCK_X2;
1237 } else if (reg == QOPR_CLOCK_X4) {
1239 set = QOPR_CLOCK_X4;
1240 } else if (reg == QOPR_CLOCK_X8) {
1242 set = QOPR_CLOCK_X8;
1245 set = QOPR_CLOCK_X1;
1247 qopr &= ~QOPR_CLOCK_RATE_MASK;
1251 pci_quatech_wqopr(port, qopr);
1255 static int pci_quatech_rs422(struct uart_8250_port *port)
1260 if (!pci_quatech_has_qmcr(port))
1262 qmcr = pci_quatech_rqmcr(port);
1263 pci_quatech_wqmcr(port, 0xFF);
1264 if (pci_quatech_rqmcr(port))
1266 pci_quatech_wqmcr(port, qmcr);
1270 static int pci_quatech_init(struct pci_dev *dev)
1272 if (pci_quatech_amcc(dev)) {
1273 unsigned long base = pci_resource_start(dev, 0);
1277 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1278 tmp = inl(base + 0x3c);
1279 outl(tmp | 0x01000000, base + 0x3c);
1280 outl(tmp &= ~0x01000000, base + 0x3c);
1286 static int pci_quatech_setup(struct serial_private *priv,
1287 const struct pciserial_board *board,
1288 struct uart_8250_port *port, int idx)
1290 /* Needed by pci_quatech calls below */
1291 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1292 /* Set up the clocking */
1293 port->port.uartclk = pci_quatech_clock(port);
1294 /* For now just warn about RS422 */
1295 if (pci_quatech_rs422(port))
1296 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1297 return pci_default_setup(priv, board, port, idx);
1300 static void pci_quatech_exit(struct pci_dev *dev)
1304 static int pci_default_setup(struct serial_private *priv,
1305 const struct pciserial_board *board,
1306 struct uart_8250_port *port, int idx)
1308 unsigned int bar, offset = board->first_offset, maxnr;
1310 bar = FL_GET_BASE(board->flags);
1311 if (board->flags & FL_BASE_BARS)
1314 offset += idx * board->uart_offset;
1316 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1317 (board->reg_shift + 3);
1319 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1322 return setup_port(priv, port, bar, offset, board->reg_shift);
1325 pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
1326 unsigned int quot, unsigned int quot_frac)
1331 for (scr = 16; scr > 4; scr--) {
1332 unsigned int maxrate = port->uartclk / scr;
1333 unsigned int divisor = max(maxrate / baud, 1U);
1334 int delta = maxrate / divisor - baud;
1336 if (baud > maxrate + baud / 50)
1339 if (delta > baud / 50)
1342 if (divisor > 0xffff)
1345 /* Update delta due to possible divisor change */
1346 delta = maxrate / divisor - baud;
1347 if (abs(delta) < baud / 50) {
1348 lcr = serial_port_in(port, UART_LCR);
1349 serial_port_out(port, UART_LCR, lcr | 0x80);
1350 serial_port_out(port, UART_DLL, divisor & 0xff);
1351 serial_port_out(port, UART_DLM, divisor >> 8 & 0xff);
1352 serial_port_out(port, 2, 16 - scr);
1353 serial_port_out(port, UART_LCR, lcr);
1358 static int pci_pericom_setup(struct serial_private *priv,
1359 const struct pciserial_board *board,
1360 struct uart_8250_port *port, int idx)
1362 unsigned int bar, offset = board->first_offset, maxnr;
1364 bar = FL_GET_BASE(board->flags);
1365 if (board->flags & FL_BASE_BARS)
1368 offset += idx * board->uart_offset;
1371 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1372 (board->reg_shift + 3);
1374 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1377 port->port.set_divisor = pericom_do_set_divisor;
1379 return setup_port(priv, port, bar, offset, board->reg_shift);
1382 static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
1383 const struct pciserial_board *board,
1384 struct uart_8250_port *port, int idx)
1386 unsigned int bar, offset = board->first_offset, maxnr;
1388 bar = FL_GET_BASE(board->flags);
1389 if (board->flags & FL_BASE_BARS)
1392 offset += idx * board->uart_offset;
1397 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1398 (board->reg_shift + 3);
1400 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1403 port->port.set_divisor = pericom_do_set_divisor;
1405 return setup_port(priv, port, bar, offset, board->reg_shift);
1409 ce4100_serial_setup(struct serial_private *priv,
1410 const struct pciserial_board *board,
1411 struct uart_8250_port *port, int idx)
1415 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1416 port->port.iotype = UPIO_MEM32;
1417 port->port.type = PORT_XSCALE;
1418 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1419 port->port.regshift = 2;
1425 pci_omegapci_setup(struct serial_private *priv,
1426 const struct pciserial_board *board,
1427 struct uart_8250_port *port, int idx)
1429 return setup_port(priv, port, 2, idx * 8, 0);
1433 pci_brcm_trumanage_setup(struct serial_private *priv,
1434 const struct pciserial_board *board,
1435 struct uart_8250_port *port, int idx)
1437 int ret = pci_default_setup(priv, board, port, idx);
1439 port->port.type = PORT_BRCM_TRUMANAGE;
1440 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1444 /* RTS will control by MCR if this bit is 0 */
1445 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1446 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1447 #define FINTEK_RTS_INVERT BIT(5)
1449 /* We should do proper H/W transceiver setting before change to RS485 mode */
1450 static int pci_fintek_rs485_config(struct uart_port *port,
1451 struct serial_rs485 *rs485)
1453 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1455 u8 *index = (u8 *) port->private_data;
1457 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1460 rs485 = &port->rs485;
1461 else if (rs485->flags & SER_RS485_ENABLED)
1462 memset(rs485->padding, 0, sizeof(rs485->padding));
1464 memset(rs485, 0, sizeof(*rs485));
1466 /* F81504/508/512 not support RTS delay before or after send */
1467 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1469 if (rs485->flags & SER_RS485_ENABLED) {
1470 /* Enable RTS H/W control mode */
1471 setting |= FINTEK_RTS_CONTROL_BY_HW;
1473 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1474 /* RTS driving high on TX */
1475 setting &= ~FINTEK_RTS_INVERT;
1477 /* RTS driving low on TX */
1478 setting |= FINTEK_RTS_INVERT;
1481 rs485->delay_rts_after_send = 0;
1482 rs485->delay_rts_before_send = 0;
1484 /* Disable RTS H/W control mode */
1485 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1488 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1490 if (rs485 != &port->rs485)
1491 port->rs485 = *rs485;
1496 static int pci_fintek_setup(struct serial_private *priv,
1497 const struct pciserial_board *board,
1498 struct uart_8250_port *port, int idx)
1500 struct pci_dev *pdev = priv->dev;
1505 config_base = 0x40 + 0x08 * idx;
1507 /* Get the io address from configuration space */
1508 pci_read_config_word(pdev, config_base + 4, &iobase);
1510 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1512 port->port.iotype = UPIO_PORT;
1513 port->port.iobase = iobase;
1514 port->port.rs485_config = pci_fintek_rs485_config;
1516 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1520 /* preserve index in PCI configuration space */
1522 port->port.private_data = data;
1527 static int pci_fintek_init(struct pci_dev *dev)
1529 unsigned long iobase;
1531 resource_size_t bar_data[3];
1533 struct serial_private *priv = pci_get_drvdata(dev);
1535 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1536 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1537 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1540 switch (dev->device) {
1541 case 0x1104: /* 4 ports */
1542 case 0x1108: /* 8 ports */
1543 max_port = dev->device & 0xff;
1545 case 0x1112: /* 12 ports */
1552 /* Get the io address dispatch from the BIOS */
1553 bar_data[0] = pci_resource_start(dev, 5);
1554 bar_data[1] = pci_resource_start(dev, 4);
1555 bar_data[2] = pci_resource_start(dev, 3);
1557 for (i = 0; i < max_port; ++i) {
1558 /* UART0 configuration offset start from 0x40 */
1559 config_base = 0x40 + 0x08 * i;
1561 /* Calculate Real IO Port */
1562 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1564 /* Enable UART I/O port */
1565 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1567 /* Select 128-byte FIFO and 8x FIFO threshold */
1568 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1571 pci_write_config_byte(dev, config_base + 0x04,
1572 (u8)(iobase & 0xff));
1575 pci_write_config_byte(dev, config_base + 0x05,
1576 (u8)((iobase & 0xff00) >> 8));
1578 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1581 /* First init without port data
1582 * force init to RS232 Mode
1584 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1591 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1593 struct f815xxa_data *data = p->private_data;
1594 unsigned long flags;
1596 spin_lock_irqsave(&data->lock, flags);
1597 writeb(value, p->membase + offset);
1598 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1599 spin_unlock_irqrestore(&data->lock, flags);
1602 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1603 const struct pciserial_board *board,
1604 struct uart_8250_port *port, int idx)
1606 struct pci_dev *pdev = priv->dev;
1607 struct f815xxa_data *data;
1609 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1614 spin_lock_init(&data->lock);
1616 port->port.private_data = data;
1617 port->port.iotype = UPIO_MEM;
1618 port->port.flags |= UPF_IOREMAP;
1619 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1620 port->port.serial_out = f815xxa_mem_serial_out;
1625 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1630 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1633 switch (dev->device) {
1634 case 0x1204: /* 4 ports */
1635 case 0x1208: /* 8 ports */
1636 max_port = dev->device & 0xff;
1638 case 0x1212: /* 12 ports */
1645 /* Set to mmio decode */
1646 pci_write_config_byte(dev, 0x209, 0x40);
1648 for (i = 0; i < max_port; ++i) {
1649 /* UART0 configuration offset start from 0x2A0 */
1650 config_base = 0x2A0 + 0x08 * i;
1652 /* Select 128-byte FIFO and 8x FIFO threshold */
1653 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1655 /* Enable UART I/O port */
1656 pci_write_config_byte(dev, config_base + 0, 0x01);
1662 static int skip_tx_en_setup(struct serial_private *priv,
1663 const struct pciserial_board *board,
1664 struct uart_8250_port *port, int idx)
1666 port->port.quirks |= UPQ_NO_TXEN_TEST;
1668 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1669 priv->dev->vendor, priv->dev->device,
1670 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1672 return pci_default_setup(priv, board, port, idx);
1675 static void kt_handle_break(struct uart_port *p)
1677 struct uart_8250_port *up = up_to_u8250p(p);
1679 * On receipt of a BI, serial device in Intel ME (Intel
1680 * management engine) needs to have its fifos cleared for sane
1681 * SOL (Serial Over Lan) output.
1683 serial8250_clear_and_reinit_fifos(up);
1686 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1688 struct uart_8250_port *up = up_to_u8250p(p);
1692 * When the Intel ME (management engine) gets reset its serial
1693 * port registers could return 0 momentarily. Functions like
1694 * serial8250_console_write, read and save the IER, perform
1695 * some operation and then restore it. In order to avoid
1696 * setting IER register inadvertently to 0, if the value read
1697 * is 0, double check with ier value in uart_8250_port and use
1698 * that instead. up->ier should be the same value as what is
1699 * currently configured.
1701 val = inb(p->iobase + offset);
1702 if (offset == UART_IER) {
1709 static int kt_serial_setup(struct serial_private *priv,
1710 const struct pciserial_board *board,
1711 struct uart_8250_port *port, int idx)
1713 port->port.flags |= UPF_BUG_THRE;
1714 port->port.serial_in = kt_serial_in;
1715 port->port.handle_break = kt_handle_break;
1716 return skip_tx_en_setup(priv, board, port, idx);
1719 static int pci_eg20t_init(struct pci_dev *dev)
1721 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1729 pci_wch_ch353_setup(struct serial_private *priv,
1730 const struct pciserial_board *board,
1731 struct uart_8250_port *port, int idx)
1733 port->port.flags |= UPF_FIXED_TYPE;
1734 port->port.type = PORT_16550A;
1735 return pci_default_setup(priv, board, port, idx);
1739 pci_wch_ch355_setup(struct serial_private *priv,
1740 const struct pciserial_board *board,
1741 struct uart_8250_port *port, int idx)
1743 port->port.flags |= UPF_FIXED_TYPE;
1744 port->port.type = PORT_16550A;
1745 return pci_default_setup(priv, board, port, idx);
1749 pci_wch_ch38x_setup(struct serial_private *priv,
1750 const struct pciserial_board *board,
1751 struct uart_8250_port *port, int idx)
1753 port->port.flags |= UPF_FIXED_TYPE;
1754 port->port.type = PORT_16850;
1755 return pci_default_setup(priv, board, port, idx);
1759 #define CH384_XINT_ENABLE_REG 0xEB
1760 #define CH384_XINT_ENABLE_BIT 0x02
1762 static int pci_wch_ch38x_init(struct pci_dev *dev)
1765 unsigned long iobase;
1768 switch (dev->device) {
1769 case 0x3853: /* 8 ports */
1776 iobase = pci_resource_start(dev, 0);
1777 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1782 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1784 unsigned long iobase;
1786 iobase = pci_resource_start(dev, 0);
1787 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1792 pci_sunix_setup(struct serial_private *priv,
1793 const struct pciserial_board *board,
1794 struct uart_8250_port *port, int idx)
1799 port->port.flags |= UPF_FIXED_TYPE;
1800 port->port.type = PORT_SUNIX;
1804 offset = idx * board->uart_offset;
1808 idx = div_s64_rem(idx, 4, &offset);
1809 offset = idx * 64 + offset * board->uart_offset;
1812 return setup_port(priv, port, bar, offset, 0);
1816 pci_moxa_setup(struct serial_private *priv,
1817 const struct pciserial_board *board,
1818 struct uart_8250_port *port, int idx)
1820 unsigned int bar = FL_GET_BASE(board->flags);
1823 if (board->num_ports == 4 && idx == 3)
1824 offset = 7 * board->uart_offset;
1826 offset = idx * board->uart_offset;
1828 return setup_port(priv, port, bar, offset, 0);
1831 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1832 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1833 #define PCI_DEVICE_ID_OCTPRO 0x0001
1834 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1835 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1836 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1837 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1838 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1839 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1840 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1841 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1842 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1843 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1844 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1845 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1846 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1847 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1848 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1849 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1850 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1851 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1852 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1853 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1854 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1855 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1856 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1857 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1858 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1859 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1860 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1861 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1862 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1863 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1864 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1865 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1866 #define PCI_VENDOR_ID_WCH 0x4348
1867 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1868 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1869 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1870 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1871 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1872 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1873 #define PCI_VENDOR_ID_AGESTAR 0x5372
1874 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1875 #define PCI_VENDOR_ID_ASIX 0x9710
1876 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1877 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1879 #define PCIE_VENDOR_ID_WCH 0x1c00
1880 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1881 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1882 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
1883 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1885 #define PCI_VENDOR_ID_ACCESIO 0x494f
1886 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1887 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1888 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1889 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1890 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1891 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1892 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1893 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1894 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1895 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1896 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1897 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1898 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1899 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1900 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1901 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1902 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1903 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1904 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1905 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1906 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1907 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1908 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1909 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1910 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1912 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1913 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1914 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1915 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1916 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1917 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1918 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1921 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
1922 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
1923 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
1924 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
1925 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
1926 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
1927 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
1928 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
1929 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
1930 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
1931 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
1932 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
1934 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1935 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1936 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1939 * Master list of serial port init/setup/exit quirks.
1940 * This does not describe the general nature of the port.
1941 * (ie, baud base, number and location of ports, etc)
1943 * This list is ordered alphabetically by vendor then device.
1944 * Specific entries must come before more generic entries.
1946 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1948 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1951 .vendor = PCI_VENDOR_ID_AMCC,
1952 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1953 .subvendor = PCI_ANY_ID,
1954 .subdevice = PCI_ANY_ID,
1955 .setup = addidata_apci7800_setup,
1958 * AFAVLAB cards - these may be called via parport_serial
1959 * It is not clear whether this applies to all products.
1962 .vendor = PCI_VENDOR_ID_AFAVLAB,
1963 .device = PCI_ANY_ID,
1964 .subvendor = PCI_ANY_ID,
1965 .subdevice = PCI_ANY_ID,
1966 .setup = afavlab_setup,
1972 .vendor = PCI_VENDOR_ID_HP,
1973 .device = PCI_DEVICE_ID_HP_DIVA,
1974 .subvendor = PCI_ANY_ID,
1975 .subdevice = PCI_ANY_ID,
1976 .init = pci_hp_diva_init,
1977 .setup = pci_hp_diva_setup,
1980 * HPE PCI serial device
1983 .vendor = PCI_VENDOR_ID_HP_3PAR,
1984 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
1985 .subvendor = PCI_ANY_ID,
1986 .subdevice = PCI_ANY_ID,
1987 .setup = pci_hp_diva_setup,
1993 .vendor = PCI_VENDOR_ID_INTEL,
1994 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1995 .subvendor = 0xe4bf,
1996 .subdevice = PCI_ANY_ID,
1997 .init = pci_inteli960ni_init,
1998 .setup = pci_default_setup,
2001 .vendor = PCI_VENDOR_ID_INTEL,
2002 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .setup = skip_tx_en_setup,
2008 .vendor = PCI_VENDOR_ID_INTEL,
2009 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2010 .subvendor = PCI_ANY_ID,
2011 .subdevice = PCI_ANY_ID,
2012 .setup = skip_tx_en_setup,
2015 .vendor = PCI_VENDOR_ID_INTEL,
2016 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2017 .subvendor = PCI_ANY_ID,
2018 .subdevice = PCI_ANY_ID,
2019 .setup = skip_tx_en_setup,
2022 .vendor = PCI_VENDOR_ID_INTEL,
2023 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2024 .subvendor = PCI_ANY_ID,
2025 .subdevice = PCI_ANY_ID,
2026 .setup = ce4100_serial_setup,
2029 .vendor = PCI_VENDOR_ID_INTEL,
2030 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2031 .subvendor = PCI_ANY_ID,
2032 .subdevice = PCI_ANY_ID,
2033 .setup = kt_serial_setup,
2039 .vendor = PCI_VENDOR_ID_ITE,
2040 .device = PCI_DEVICE_ID_ITE_8872,
2041 .subvendor = PCI_ANY_ID,
2042 .subdevice = PCI_ANY_ID,
2043 .init = pci_ite887x_init,
2044 .setup = pci_default_setup,
2045 .exit = pci_ite887x_exit,
2048 * National Instruments
2051 .vendor = PCI_VENDOR_ID_NI,
2052 .device = PCI_DEVICE_ID_NI_PCI23216,
2053 .subvendor = PCI_ANY_ID,
2054 .subdevice = PCI_ANY_ID,
2055 .init = pci_ni8420_init,
2056 .setup = pci_default_setup,
2057 .exit = pci_ni8420_exit,
2060 .vendor = PCI_VENDOR_ID_NI,
2061 .device = PCI_DEVICE_ID_NI_PCI2328,
2062 .subvendor = PCI_ANY_ID,
2063 .subdevice = PCI_ANY_ID,
2064 .init = pci_ni8420_init,
2065 .setup = pci_default_setup,
2066 .exit = pci_ni8420_exit,
2069 .vendor = PCI_VENDOR_ID_NI,
2070 .device = PCI_DEVICE_ID_NI_PCI2324,
2071 .subvendor = PCI_ANY_ID,
2072 .subdevice = PCI_ANY_ID,
2073 .init = pci_ni8420_init,
2074 .setup = pci_default_setup,
2075 .exit = pci_ni8420_exit,
2078 .vendor = PCI_VENDOR_ID_NI,
2079 .device = PCI_DEVICE_ID_NI_PCI2322,
2080 .subvendor = PCI_ANY_ID,
2081 .subdevice = PCI_ANY_ID,
2082 .init = pci_ni8420_init,
2083 .setup = pci_default_setup,
2084 .exit = pci_ni8420_exit,
2087 .vendor = PCI_VENDOR_ID_NI,
2088 .device = PCI_DEVICE_ID_NI_PCI2324I,
2089 .subvendor = PCI_ANY_ID,
2090 .subdevice = PCI_ANY_ID,
2091 .init = pci_ni8420_init,
2092 .setup = pci_default_setup,
2093 .exit = pci_ni8420_exit,
2096 .vendor = PCI_VENDOR_ID_NI,
2097 .device = PCI_DEVICE_ID_NI_PCI2322I,
2098 .subvendor = PCI_ANY_ID,
2099 .subdevice = PCI_ANY_ID,
2100 .init = pci_ni8420_init,
2101 .setup = pci_default_setup,
2102 .exit = pci_ni8420_exit,
2105 .vendor = PCI_VENDOR_ID_NI,
2106 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2107 .subvendor = PCI_ANY_ID,
2108 .subdevice = PCI_ANY_ID,
2109 .init = pci_ni8420_init,
2110 .setup = pci_default_setup,
2111 .exit = pci_ni8420_exit,
2114 .vendor = PCI_VENDOR_ID_NI,
2115 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2116 .subvendor = PCI_ANY_ID,
2117 .subdevice = PCI_ANY_ID,
2118 .init = pci_ni8420_init,
2119 .setup = pci_default_setup,
2120 .exit = pci_ni8420_exit,
2123 .vendor = PCI_VENDOR_ID_NI,
2124 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2125 .subvendor = PCI_ANY_ID,
2126 .subdevice = PCI_ANY_ID,
2127 .init = pci_ni8420_init,
2128 .setup = pci_default_setup,
2129 .exit = pci_ni8420_exit,
2132 .vendor = PCI_VENDOR_ID_NI,
2133 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2134 .subvendor = PCI_ANY_ID,
2135 .subdevice = PCI_ANY_ID,
2136 .init = pci_ni8420_init,
2137 .setup = pci_default_setup,
2138 .exit = pci_ni8420_exit,
2141 .vendor = PCI_VENDOR_ID_NI,
2142 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2143 .subvendor = PCI_ANY_ID,
2144 .subdevice = PCI_ANY_ID,
2145 .init = pci_ni8420_init,
2146 .setup = pci_default_setup,
2147 .exit = pci_ni8420_exit,
2150 .vendor = PCI_VENDOR_ID_NI,
2151 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2152 .subvendor = PCI_ANY_ID,
2153 .subdevice = PCI_ANY_ID,
2154 .init = pci_ni8420_init,
2155 .setup = pci_default_setup,
2156 .exit = pci_ni8420_exit,
2159 .vendor = PCI_VENDOR_ID_NI,
2160 .device = PCI_ANY_ID,
2161 .subvendor = PCI_ANY_ID,
2162 .subdevice = PCI_ANY_ID,
2163 .init = pci_ni8430_init,
2164 .setup = pci_ni8430_setup,
2165 .exit = pci_ni8430_exit,
2169 .vendor = PCI_VENDOR_ID_QUATECH,
2170 .device = PCI_ANY_ID,
2171 .subvendor = PCI_ANY_ID,
2172 .subdevice = PCI_ANY_ID,
2173 .init = pci_quatech_init,
2174 .setup = pci_quatech_setup,
2175 .exit = pci_quatech_exit,
2181 .vendor = PCI_VENDOR_ID_PANACOM,
2182 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2183 .subvendor = PCI_ANY_ID,
2184 .subdevice = PCI_ANY_ID,
2185 .init = pci_plx9050_init,
2186 .setup = pci_default_setup,
2187 .exit = pci_plx9050_exit,
2190 .vendor = PCI_VENDOR_ID_PANACOM,
2191 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2192 .subvendor = PCI_ANY_ID,
2193 .subdevice = PCI_ANY_ID,
2194 .init = pci_plx9050_init,
2195 .setup = pci_default_setup,
2196 .exit = pci_plx9050_exit,
2199 * Pericom (Only 7954 - It have a offset jump for port 4)
2202 .vendor = PCI_VENDOR_ID_PERICOM,
2203 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2204 .subvendor = PCI_ANY_ID,
2205 .subdevice = PCI_ANY_ID,
2206 .setup = pci_pericom_setup_four_at_eight,
2212 .vendor = PCI_VENDOR_ID_PLX,
2213 .device = PCI_DEVICE_ID_PLX_9050,
2214 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2215 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2216 .init = pci_plx9050_init,
2217 .setup = pci_default_setup,
2218 .exit = pci_plx9050_exit,
2221 .vendor = PCI_VENDOR_ID_PLX,
2222 .device = PCI_DEVICE_ID_PLX_9050,
2223 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2224 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2225 .init = pci_plx9050_init,
2226 .setup = pci_default_setup,
2227 .exit = pci_plx9050_exit,
2230 .vendor = PCI_VENDOR_ID_PLX,
2231 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2232 .subvendor = PCI_VENDOR_ID_PLX,
2233 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2234 .init = pci_plx9050_init,
2235 .setup = pci_default_setup,
2236 .exit = pci_plx9050_exit,
2239 .vendor = PCI_VENDOR_ID_ACCESIO,
2240 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2241 .subvendor = PCI_ANY_ID,
2242 .subdevice = PCI_ANY_ID,
2243 .setup = pci_pericom_setup_four_at_eight,
2246 .vendor = PCI_VENDOR_ID_ACCESIO,
2247 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2248 .subvendor = PCI_ANY_ID,
2249 .subdevice = PCI_ANY_ID,
2250 .setup = pci_pericom_setup_four_at_eight,
2253 .vendor = PCI_VENDOR_ID_ACCESIO,
2254 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2255 .subvendor = PCI_ANY_ID,
2256 .subdevice = PCI_ANY_ID,
2257 .setup = pci_pericom_setup_four_at_eight,
2260 .vendor = PCI_VENDOR_ID_ACCESIO,
2261 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2262 .subvendor = PCI_ANY_ID,
2263 .subdevice = PCI_ANY_ID,
2264 .setup = pci_pericom_setup_four_at_eight,
2267 .vendor = PCI_VENDOR_ID_ACCESIO,
2268 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2269 .subvendor = PCI_ANY_ID,
2270 .subdevice = PCI_ANY_ID,
2271 .setup = pci_pericom_setup_four_at_eight,
2274 .vendor = PCI_VENDOR_ID_ACCESIO,
2275 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2276 .subvendor = PCI_ANY_ID,
2277 .subdevice = PCI_ANY_ID,
2278 .setup = pci_pericom_setup_four_at_eight,
2281 .vendor = PCI_VENDOR_ID_ACCESIO,
2282 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2283 .subvendor = PCI_ANY_ID,
2284 .subdevice = PCI_ANY_ID,
2285 .setup = pci_pericom_setup_four_at_eight,
2288 .vendor = PCI_VENDOR_ID_ACCESIO,
2289 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2290 .subvendor = PCI_ANY_ID,
2291 .subdevice = PCI_ANY_ID,
2292 .setup = pci_pericom_setup_four_at_eight,
2295 .vendor = PCI_VENDOR_ID_ACCESIO,
2296 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2297 .subvendor = PCI_ANY_ID,
2298 .subdevice = PCI_ANY_ID,
2299 .setup = pci_pericom_setup_four_at_eight,
2302 .vendor = PCI_VENDOR_ID_ACCESIO,
2303 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2304 .subvendor = PCI_ANY_ID,
2305 .subdevice = PCI_ANY_ID,
2306 .setup = pci_pericom_setup_four_at_eight,
2309 .vendor = PCI_VENDOR_ID_ACCESIO,
2310 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2311 .subvendor = PCI_ANY_ID,
2312 .subdevice = PCI_ANY_ID,
2313 .setup = pci_pericom_setup_four_at_eight,
2316 .vendor = PCI_VENDOR_ID_ACCESIO,
2317 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2318 .subvendor = PCI_ANY_ID,
2319 .subdevice = PCI_ANY_ID,
2320 .setup = pci_pericom_setup_four_at_eight,
2323 .vendor = PCI_VENDOR_ID_ACCESIO,
2324 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2325 .subvendor = PCI_ANY_ID,
2326 .subdevice = PCI_ANY_ID,
2327 .setup = pci_pericom_setup_four_at_eight,
2330 .vendor = PCI_VENDOR_ID_ACCESIO,
2331 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2332 .subvendor = PCI_ANY_ID,
2333 .subdevice = PCI_ANY_ID,
2334 .setup = pci_pericom_setup_four_at_eight,
2337 .vendor = PCI_VENDOR_ID_ACCESIO,
2338 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2339 .subvendor = PCI_ANY_ID,
2340 .subdevice = PCI_ANY_ID,
2341 .setup = pci_pericom_setup_four_at_eight,
2344 .vendor = PCI_VENDOR_ID_ACCESIO,
2345 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2346 .subvendor = PCI_ANY_ID,
2347 .subdevice = PCI_ANY_ID,
2348 .setup = pci_pericom_setup_four_at_eight,
2351 .vendor = PCI_VENDOR_ID_ACCESIO,
2352 .device = PCI_ANY_ID,
2353 .subvendor = PCI_ANY_ID,
2354 .subdevice = PCI_ANY_ID,
2355 .setup = pci_pericom_setup,
2357 * SBS Technologies, Inc., PMC-OCTALPRO 232
2360 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2361 .device = PCI_DEVICE_ID_OCTPRO,
2362 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2363 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2369 * SBS Technologies, Inc., PMC-OCTALPRO 422
2372 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2373 .device = PCI_DEVICE_ID_OCTPRO,
2374 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2375 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2381 * SBS Technologies, Inc., P-Octal 232
2384 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2385 .device = PCI_DEVICE_ID_OCTPRO,
2386 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2387 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2393 * SBS Technologies, Inc., P-Octal 422
2396 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2397 .device = PCI_DEVICE_ID_OCTPRO,
2398 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2399 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2405 * SIIG cards - these may be called via parport_serial
2408 .vendor = PCI_VENDOR_ID_SIIG,
2409 .device = PCI_ANY_ID,
2410 .subvendor = PCI_ANY_ID,
2411 .subdevice = PCI_ANY_ID,
2412 .init = pci_siig_init,
2413 .setup = pci_siig_setup,
2419 .vendor = PCI_VENDOR_ID_TITAN,
2420 .device = PCI_DEVICE_ID_TITAN_400L,
2421 .subvendor = PCI_ANY_ID,
2422 .subdevice = PCI_ANY_ID,
2423 .setup = titan_400l_800l_setup,
2426 .vendor = PCI_VENDOR_ID_TITAN,
2427 .device = PCI_DEVICE_ID_TITAN_800L,
2428 .subvendor = PCI_ANY_ID,
2429 .subdevice = PCI_ANY_ID,
2430 .setup = titan_400l_800l_setup,
2436 .vendor = PCI_VENDOR_ID_TIMEDIA,
2437 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2438 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2439 .subdevice = PCI_ANY_ID,
2440 .probe = pci_timedia_probe,
2441 .init = pci_timedia_init,
2442 .setup = pci_timedia_setup,
2445 .vendor = PCI_VENDOR_ID_TIMEDIA,
2446 .device = PCI_ANY_ID,
2447 .subvendor = PCI_ANY_ID,
2448 .subdevice = PCI_ANY_ID,
2449 .setup = pci_timedia_setup,
2452 * Sunix PCI serial boards
2455 .vendor = PCI_VENDOR_ID_SUNIX,
2456 .device = PCI_DEVICE_ID_SUNIX_1999,
2457 .subvendor = PCI_VENDOR_ID_SUNIX,
2458 .subdevice = PCI_ANY_ID,
2459 .setup = pci_sunix_setup,
2465 .vendor = PCI_VENDOR_ID_XIRCOM,
2466 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2467 .subvendor = PCI_ANY_ID,
2468 .subdevice = PCI_ANY_ID,
2469 .init = pci_xircom_init,
2470 .setup = pci_default_setup,
2473 * Netmos cards - these may be called via parport_serial
2476 .vendor = PCI_VENDOR_ID_NETMOS,
2477 .device = PCI_ANY_ID,
2478 .subvendor = PCI_ANY_ID,
2479 .subdevice = PCI_ANY_ID,
2480 .init = pci_netmos_init,
2481 .setup = pci_netmos_9900_setup,
2484 * EndRun Technologies
2487 .vendor = PCI_VENDOR_ID_ENDRUN,
2488 .device = PCI_ANY_ID,
2489 .subvendor = PCI_ANY_ID,
2490 .subdevice = PCI_ANY_ID,
2491 .init = pci_oxsemi_tornado_init,
2492 .setup = pci_default_setup,
2495 * For Oxford Semiconductor Tornado based devices
2498 .vendor = PCI_VENDOR_ID_OXSEMI,
2499 .device = PCI_ANY_ID,
2500 .subvendor = PCI_ANY_ID,
2501 .subdevice = PCI_ANY_ID,
2502 .init = pci_oxsemi_tornado_init,
2503 .setup = pci_default_setup,
2506 .vendor = PCI_VENDOR_ID_MAINPINE,
2507 .device = PCI_ANY_ID,
2508 .subvendor = PCI_ANY_ID,
2509 .subdevice = PCI_ANY_ID,
2510 .init = pci_oxsemi_tornado_init,
2511 .setup = pci_default_setup,
2514 .vendor = PCI_VENDOR_ID_DIGI,
2515 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2516 .subvendor = PCI_SUBVENDOR_ID_IBM,
2517 .subdevice = PCI_ANY_ID,
2518 .init = pci_oxsemi_tornado_init,
2519 .setup = pci_default_setup,
2522 .vendor = PCI_VENDOR_ID_INTEL,
2524 .subvendor = PCI_ANY_ID,
2525 .subdevice = PCI_ANY_ID,
2526 .init = pci_eg20t_init,
2527 .setup = pci_default_setup,
2530 .vendor = PCI_VENDOR_ID_INTEL,
2532 .subvendor = PCI_ANY_ID,
2533 .subdevice = PCI_ANY_ID,
2534 .init = pci_eg20t_init,
2535 .setup = pci_default_setup,
2538 .vendor = PCI_VENDOR_ID_INTEL,
2540 .subvendor = PCI_ANY_ID,
2541 .subdevice = PCI_ANY_ID,
2542 .init = pci_eg20t_init,
2543 .setup = pci_default_setup,
2546 .vendor = PCI_VENDOR_ID_INTEL,
2548 .subvendor = PCI_ANY_ID,
2549 .subdevice = PCI_ANY_ID,
2550 .init = pci_eg20t_init,
2551 .setup = pci_default_setup,
2556 .subvendor = PCI_ANY_ID,
2557 .subdevice = PCI_ANY_ID,
2558 .init = pci_eg20t_init,
2559 .setup = pci_default_setup,
2564 .subvendor = PCI_ANY_ID,
2565 .subdevice = PCI_ANY_ID,
2566 .init = pci_eg20t_init,
2567 .setup = pci_default_setup,
2572 .subvendor = PCI_ANY_ID,
2573 .subdevice = PCI_ANY_ID,
2574 .init = pci_eg20t_init,
2575 .setup = pci_default_setup,
2580 .subvendor = PCI_ANY_ID,
2581 .subdevice = PCI_ANY_ID,
2582 .init = pci_eg20t_init,
2583 .setup = pci_default_setup,
2588 .subvendor = PCI_ANY_ID,
2589 .subdevice = PCI_ANY_ID,
2590 .init = pci_eg20t_init,
2591 .setup = pci_default_setup,
2594 * Cronyx Omega PCI (PLX-chip based)
2597 .vendor = PCI_VENDOR_ID_PLX,
2598 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2599 .subvendor = PCI_ANY_ID,
2600 .subdevice = PCI_ANY_ID,
2601 .setup = pci_omegapci_setup,
2603 /* WCH CH353 1S1P card (16550 clone) */
2605 .vendor = PCI_VENDOR_ID_WCH,
2606 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2607 .subvendor = PCI_ANY_ID,
2608 .subdevice = PCI_ANY_ID,
2609 .setup = pci_wch_ch353_setup,
2611 /* WCH CH353 2S1P card (16550 clone) */
2613 .vendor = PCI_VENDOR_ID_WCH,
2614 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2615 .subvendor = PCI_ANY_ID,
2616 .subdevice = PCI_ANY_ID,
2617 .setup = pci_wch_ch353_setup,
2619 /* WCH CH353 4S card (16550 clone) */
2621 .vendor = PCI_VENDOR_ID_WCH,
2622 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2623 .subvendor = PCI_ANY_ID,
2624 .subdevice = PCI_ANY_ID,
2625 .setup = pci_wch_ch353_setup,
2627 /* WCH CH353 2S1PF card (16550 clone) */
2629 .vendor = PCI_VENDOR_ID_WCH,
2630 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2631 .subvendor = PCI_ANY_ID,
2632 .subdevice = PCI_ANY_ID,
2633 .setup = pci_wch_ch353_setup,
2635 /* WCH CH352 2S card (16550 clone) */
2637 .vendor = PCI_VENDOR_ID_WCH,
2638 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2639 .subvendor = PCI_ANY_ID,
2640 .subdevice = PCI_ANY_ID,
2641 .setup = pci_wch_ch353_setup,
2643 /* WCH CH355 4S card (16550 clone) */
2645 .vendor = PCI_VENDOR_ID_WCH,
2646 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2647 .subvendor = PCI_ANY_ID,
2648 .subdevice = PCI_ANY_ID,
2649 .setup = pci_wch_ch355_setup,
2651 /* WCH CH382 2S card (16850 clone) */
2653 .vendor = PCIE_VENDOR_ID_WCH,
2654 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2655 .subvendor = PCI_ANY_ID,
2656 .subdevice = PCI_ANY_ID,
2657 .setup = pci_wch_ch38x_setup,
2659 /* WCH CH382 2S1P card (16850 clone) */
2661 .vendor = PCIE_VENDOR_ID_WCH,
2662 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2663 .subvendor = PCI_ANY_ID,
2664 .subdevice = PCI_ANY_ID,
2665 .setup = pci_wch_ch38x_setup,
2667 /* WCH CH384 4S card (16850 clone) */
2669 .vendor = PCIE_VENDOR_ID_WCH,
2670 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2671 .subvendor = PCI_ANY_ID,
2672 .subdevice = PCI_ANY_ID,
2673 .setup = pci_wch_ch38x_setup,
2675 /* WCH CH384 8S card (16850 clone) */
2677 .vendor = PCIE_VENDOR_ID_WCH,
2678 .device = PCIE_DEVICE_ID_WCH_CH384_8S,
2679 .subvendor = PCI_ANY_ID,
2680 .subdevice = PCI_ANY_ID,
2681 .init = pci_wch_ch38x_init,
2682 .exit = pci_wch_ch38x_exit,
2683 .setup = pci_wch_ch38x_setup,
2686 * ASIX devices with FIFO bug
2689 .vendor = PCI_VENDOR_ID_ASIX,
2690 .device = PCI_ANY_ID,
2691 .subvendor = PCI_ANY_ID,
2692 .subdevice = PCI_ANY_ID,
2693 .setup = pci_asix_setup,
2696 * Broadcom TruManage (NetXtreme)
2699 .vendor = PCI_VENDOR_ID_BROADCOM,
2700 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2701 .subvendor = PCI_ANY_ID,
2702 .subdevice = PCI_ANY_ID,
2703 .setup = pci_brcm_trumanage_setup,
2708 .subvendor = PCI_ANY_ID,
2709 .subdevice = PCI_ANY_ID,
2710 .setup = pci_fintek_setup,
2711 .init = pci_fintek_init,
2716 .subvendor = PCI_ANY_ID,
2717 .subdevice = PCI_ANY_ID,
2718 .setup = pci_fintek_setup,
2719 .init = pci_fintek_init,
2724 .subvendor = PCI_ANY_ID,
2725 .subdevice = PCI_ANY_ID,
2726 .setup = pci_fintek_setup,
2727 .init = pci_fintek_init,
2733 .vendor = PCI_VENDOR_ID_MOXA,
2734 .device = PCI_ANY_ID,
2735 .subvendor = PCI_ANY_ID,
2736 .subdevice = PCI_ANY_ID,
2737 .setup = pci_moxa_setup,
2742 .subvendor = PCI_ANY_ID,
2743 .subdevice = PCI_ANY_ID,
2744 .setup = pci_fintek_f815xxa_setup,
2745 .init = pci_fintek_f815xxa_init,
2750 .subvendor = PCI_ANY_ID,
2751 .subdevice = PCI_ANY_ID,
2752 .setup = pci_fintek_f815xxa_setup,
2753 .init = pci_fintek_f815xxa_init,
2758 .subvendor = PCI_ANY_ID,
2759 .subdevice = PCI_ANY_ID,
2760 .setup = pci_fintek_f815xxa_setup,
2761 .init = pci_fintek_f815xxa_init,
2765 * Default "match everything" terminator entry
2768 .vendor = PCI_ANY_ID,
2769 .device = PCI_ANY_ID,
2770 .subvendor = PCI_ANY_ID,
2771 .subdevice = PCI_ANY_ID,
2772 .setup = pci_default_setup,
2776 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2778 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2781 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2783 struct pci_serial_quirk *quirk;
2785 for (quirk = pci_serial_quirks; ; quirk++)
2786 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2787 quirk_id_matches(quirk->device, dev->device) &&
2788 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2789 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2795 * This is the configuration table for all of the PCI serial boards
2796 * which we support. It is directly indexed by the pci_board_num_t enum
2797 * value, which is encoded in the pci_device_id PCI probe table's
2798 * driver_data member.
2800 * The makeup of these names are:
2801 * pbn_bn{_bt}_n_baud{_offsetinhex}
2803 * bn = PCI BAR number
2804 * bt = Index using PCI BARs
2805 * n = number of serial ports
2807 * offsetinhex = offset for each sequential port (in hex)
2809 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2811 * Please note: in theory if n = 1, _bt infix should make no difference.
2812 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2814 enum pci_board_num_t {
2908 * Board-specific versions.
2915 pbn_oxsemi_1_3906250,
2916 pbn_oxsemi_2_3906250,
2917 pbn_oxsemi_4_3906250,
2918 pbn_oxsemi_8_3906250,
2930 pbn_ADDIDATA_PCIe_1_3906250,
2931 pbn_ADDIDATA_PCIe_2_3906250,
2932 pbn_ADDIDATA_PCIe_4_3906250,
2933 pbn_ADDIDATA_PCIe_8_3906250,
2934 pbn_ce4100_1_115200,
2936 pbn_NETMOS9900_2s_115200,
2947 pbn_pericom_PI7C9X7951,
2948 pbn_pericom_PI7C9X7952,
2949 pbn_pericom_PI7C9X7954,
2950 pbn_pericom_PI7C9X7958,
2956 pbn_titan_1_4000000,
2957 pbn_titan_2_4000000,
2958 pbn_titan_4_4000000,
2959 pbn_titan_8_4000000,
2966 * uart_offset - the space between channels
2967 * reg_shift - describes how the UART registers are mapped
2968 * to PCI memory by the card.
2969 * For example IER register on SBS, Inc. PMC-OctPro is located at
2970 * offset 0x10 from the UART base, while UART_IER is defined as 1
2971 * in include/linux/serial_reg.h,
2972 * see first lines of serial_in() and serial_out() in 8250.c
2975 static struct pciserial_board pci_boards[] = {
2979 .base_baud = 115200,
2982 [pbn_b0_1_115200] = {
2985 .base_baud = 115200,
2988 [pbn_b0_2_115200] = {
2991 .base_baud = 115200,
2994 [pbn_b0_4_115200] = {
2997 .base_baud = 115200,
3000 [pbn_b0_5_115200] = {
3003 .base_baud = 115200,
3006 [pbn_b0_8_115200] = {
3009 .base_baud = 115200,
3012 [pbn_b0_1_921600] = {
3015 .base_baud = 921600,
3018 [pbn_b0_2_921600] = {
3021 .base_baud = 921600,
3024 [pbn_b0_4_921600] = {
3027 .base_baud = 921600,
3031 [pbn_b0_2_1130000] = {
3034 .base_baud = 1130000,
3038 [pbn_b0_4_1152000] = {
3041 .base_baud = 1152000,
3045 [pbn_b0_4_1250000] = {
3048 .base_baud = 1250000,
3052 [pbn_b0_2_1843200] = {
3055 .base_baud = 1843200,
3058 [pbn_b0_4_1843200] = {
3061 .base_baud = 1843200,
3065 [pbn_b0_1_3906250] = {
3068 .base_baud = 3906250,
3072 [pbn_b0_bt_1_115200] = {
3073 .flags = FL_BASE0|FL_BASE_BARS,
3075 .base_baud = 115200,
3078 [pbn_b0_bt_2_115200] = {
3079 .flags = FL_BASE0|FL_BASE_BARS,
3081 .base_baud = 115200,
3084 [pbn_b0_bt_4_115200] = {
3085 .flags = FL_BASE0|FL_BASE_BARS,
3087 .base_baud = 115200,
3090 [pbn_b0_bt_8_115200] = {
3091 .flags = FL_BASE0|FL_BASE_BARS,
3093 .base_baud = 115200,
3097 [pbn_b0_bt_1_460800] = {
3098 .flags = FL_BASE0|FL_BASE_BARS,
3100 .base_baud = 460800,
3103 [pbn_b0_bt_2_460800] = {
3104 .flags = FL_BASE0|FL_BASE_BARS,
3106 .base_baud = 460800,
3109 [pbn_b0_bt_4_460800] = {
3110 .flags = FL_BASE0|FL_BASE_BARS,
3112 .base_baud = 460800,
3116 [pbn_b0_bt_1_921600] = {
3117 .flags = FL_BASE0|FL_BASE_BARS,
3119 .base_baud = 921600,
3122 [pbn_b0_bt_2_921600] = {
3123 .flags = FL_BASE0|FL_BASE_BARS,
3125 .base_baud = 921600,
3128 [pbn_b0_bt_4_921600] = {
3129 .flags = FL_BASE0|FL_BASE_BARS,
3131 .base_baud = 921600,
3134 [pbn_b0_bt_8_921600] = {
3135 .flags = FL_BASE0|FL_BASE_BARS,
3137 .base_baud = 921600,
3141 [pbn_b1_1_115200] = {
3144 .base_baud = 115200,
3147 [pbn_b1_2_115200] = {
3150 .base_baud = 115200,
3153 [pbn_b1_4_115200] = {
3156 .base_baud = 115200,
3159 [pbn_b1_8_115200] = {
3162 .base_baud = 115200,
3165 [pbn_b1_16_115200] = {
3168 .base_baud = 115200,
3172 [pbn_b1_1_921600] = {
3175 .base_baud = 921600,
3178 [pbn_b1_2_921600] = {
3181 .base_baud = 921600,
3184 [pbn_b1_4_921600] = {
3187 .base_baud = 921600,
3190 [pbn_b1_8_921600] = {
3193 .base_baud = 921600,
3196 [pbn_b1_2_1250000] = {
3199 .base_baud = 1250000,
3203 [pbn_b1_bt_1_115200] = {
3204 .flags = FL_BASE1|FL_BASE_BARS,
3206 .base_baud = 115200,
3209 [pbn_b1_bt_2_115200] = {
3210 .flags = FL_BASE1|FL_BASE_BARS,
3212 .base_baud = 115200,
3215 [pbn_b1_bt_4_115200] = {
3216 .flags = FL_BASE1|FL_BASE_BARS,
3218 .base_baud = 115200,
3222 [pbn_b1_bt_2_921600] = {
3223 .flags = FL_BASE1|FL_BASE_BARS,
3225 .base_baud = 921600,
3229 [pbn_b1_1_1382400] = {
3232 .base_baud = 1382400,
3235 [pbn_b1_2_1382400] = {
3238 .base_baud = 1382400,
3241 [pbn_b1_4_1382400] = {
3244 .base_baud = 1382400,
3247 [pbn_b1_8_1382400] = {
3250 .base_baud = 1382400,
3254 [pbn_b2_1_115200] = {
3257 .base_baud = 115200,
3260 [pbn_b2_2_115200] = {
3263 .base_baud = 115200,
3266 [pbn_b2_4_115200] = {
3269 .base_baud = 115200,
3272 [pbn_b2_8_115200] = {
3275 .base_baud = 115200,
3279 [pbn_b2_1_460800] = {
3282 .base_baud = 460800,
3285 [pbn_b2_4_460800] = {
3288 .base_baud = 460800,
3291 [pbn_b2_8_460800] = {
3294 .base_baud = 460800,
3297 [pbn_b2_16_460800] = {
3300 .base_baud = 460800,
3304 [pbn_b2_1_921600] = {
3307 .base_baud = 921600,
3310 [pbn_b2_4_921600] = {
3313 .base_baud = 921600,
3316 [pbn_b2_8_921600] = {
3319 .base_baud = 921600,
3323 [pbn_b2_8_1152000] = {
3326 .base_baud = 1152000,
3330 [pbn_b2_bt_1_115200] = {
3331 .flags = FL_BASE2|FL_BASE_BARS,
3333 .base_baud = 115200,
3336 [pbn_b2_bt_2_115200] = {
3337 .flags = FL_BASE2|FL_BASE_BARS,
3339 .base_baud = 115200,
3342 [pbn_b2_bt_4_115200] = {
3343 .flags = FL_BASE2|FL_BASE_BARS,
3345 .base_baud = 115200,
3349 [pbn_b2_bt_2_921600] = {
3350 .flags = FL_BASE2|FL_BASE_BARS,
3352 .base_baud = 921600,
3355 [pbn_b2_bt_4_921600] = {
3356 .flags = FL_BASE2|FL_BASE_BARS,
3358 .base_baud = 921600,
3362 [pbn_b3_2_115200] = {
3365 .base_baud = 115200,
3368 [pbn_b3_4_115200] = {
3371 .base_baud = 115200,
3374 [pbn_b3_8_115200] = {
3377 .base_baud = 115200,
3381 [pbn_b4_bt_2_921600] = {
3384 .base_baud = 921600,
3387 [pbn_b4_bt_4_921600] = {
3390 .base_baud = 921600,
3393 [pbn_b4_bt_8_921600] = {
3396 .base_baud = 921600,
3401 * Entries following this are board-specific.
3410 .base_baud = 921600,
3411 .uart_offset = 0x400,
3415 .flags = FL_BASE2|FL_BASE_BARS,
3417 .base_baud = 921600,
3418 .uart_offset = 0x400,
3422 .flags = FL_BASE2|FL_BASE_BARS,
3424 .base_baud = 921600,
3425 .uart_offset = 0x400,
3429 /* I think this entry is broken - the first_offset looks wrong --rmk */
3430 [pbn_plx_romulus] = {
3433 .base_baud = 921600,
3434 .uart_offset = 8 << 2,
3436 .first_offset = 0x03,
3440 * This board uses the size of PCI Base region 0 to
3441 * signal now many ports are available
3444 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3446 .base_baud = 115200,
3449 [pbn_oxsemi_1_3906250] = {
3452 .base_baud = 3906250,
3453 .uart_offset = 0x200,
3454 .first_offset = 0x1000,
3456 [pbn_oxsemi_2_3906250] = {
3459 .base_baud = 3906250,
3460 .uart_offset = 0x200,
3461 .first_offset = 0x1000,
3463 [pbn_oxsemi_4_3906250] = {
3466 .base_baud = 3906250,
3467 .uart_offset = 0x200,
3468 .first_offset = 0x1000,
3470 [pbn_oxsemi_8_3906250] = {
3473 .base_baud = 3906250,
3474 .uart_offset = 0x200,
3475 .first_offset = 0x1000,
3480 * EKF addition for i960 Boards form EKF with serial port.
3483 [pbn_intel_i960] = {
3486 .base_baud = 921600,
3487 .uart_offset = 8 << 2,
3489 .first_offset = 0x10000,
3492 .flags = FL_BASE0|FL_NOIRQ,
3494 .base_baud = 458333,
3497 .first_offset = 0x20178,
3501 * Computone - uses IOMEM.
3503 [pbn_computone_4] = {
3506 .base_baud = 921600,
3507 .uart_offset = 0x40,
3509 .first_offset = 0x200,
3511 [pbn_computone_6] = {
3514 .base_baud = 921600,
3515 .uart_offset = 0x40,
3517 .first_offset = 0x200,
3519 [pbn_computone_8] = {
3522 .base_baud = 921600,
3523 .uart_offset = 0x40,
3525 .first_offset = 0x200,
3530 .base_baud = 460800,
3535 * PA Semi PWRficient PA6T-1682M on-chip UART
3537 [pbn_pasemi_1682M] = {
3540 .base_baud = 8333333,
3543 * National Instruments 843x
3548 .base_baud = 3686400,
3549 .uart_offset = 0x10,
3550 .first_offset = 0x800,
3555 .base_baud = 3686400,
3556 .uart_offset = 0x10,
3557 .first_offset = 0x800,
3562 .base_baud = 3686400,
3563 .uart_offset = 0x10,
3564 .first_offset = 0x800,
3569 .base_baud = 3686400,
3570 .uart_offset = 0x10,
3571 .first_offset = 0x800,
3574 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3576 [pbn_ADDIDATA_PCIe_1_3906250] = {
3579 .base_baud = 3906250,
3580 .uart_offset = 0x200,
3581 .first_offset = 0x1000,
3583 [pbn_ADDIDATA_PCIe_2_3906250] = {
3586 .base_baud = 3906250,
3587 .uart_offset = 0x200,
3588 .first_offset = 0x1000,
3590 [pbn_ADDIDATA_PCIe_4_3906250] = {
3593 .base_baud = 3906250,
3594 .uart_offset = 0x200,
3595 .first_offset = 0x1000,
3597 [pbn_ADDIDATA_PCIe_8_3906250] = {
3600 .base_baud = 3906250,
3601 .uart_offset = 0x200,
3602 .first_offset = 0x1000,
3604 [pbn_ce4100_1_115200] = {
3605 .flags = FL_BASE_BARS,
3607 .base_baud = 921600,
3613 .base_baud = 115200,
3614 .uart_offset = 0x200,
3616 [pbn_NETMOS9900_2s_115200] = {
3619 .base_baud = 115200,
3621 [pbn_brcm_trumanage] = {
3625 .base_baud = 115200,
3630 .base_baud = 115200,
3631 .first_offset = 0x40,
3636 .base_baud = 115200,
3637 .first_offset = 0x40,
3642 .base_baud = 115200,
3643 .first_offset = 0x40,
3645 [pbn_fintek_F81504A] = {
3648 .base_baud = 115200,
3650 [pbn_fintek_F81508A] = {
3653 .base_baud = 115200,
3655 [pbn_fintek_F81512A] = {
3658 .base_baud = 115200,
3663 .base_baud = 115200,
3665 .first_offset = 0xC0,
3670 .base_baud = 115200,
3672 .first_offset = 0xC0,
3677 .base_baud = 115200,
3679 .first_offset = 0x00,
3682 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3684 [pbn_pericom_PI7C9X7951] = {
3687 .base_baud = 921600,
3690 [pbn_pericom_PI7C9X7952] = {
3693 .base_baud = 921600,
3696 [pbn_pericom_PI7C9X7954] = {
3699 .base_baud = 921600,
3702 [pbn_pericom_PI7C9X7958] = {
3705 .base_baud = 921600,
3708 [pbn_sunix_pci_1s] = {
3710 .base_baud = 921600,
3713 [pbn_sunix_pci_2s] = {
3715 .base_baud = 921600,
3718 [pbn_sunix_pci_4s] = {
3720 .base_baud = 921600,
3723 [pbn_sunix_pci_8s] = {
3725 .base_baud = 921600,
3728 [pbn_sunix_pci_16s] = {
3730 .base_baud = 921600,
3733 [pbn_titan_1_4000000] = {
3736 .base_baud = 4000000,
3737 .uart_offset = 0x200,
3738 .first_offset = 0x1000,
3740 [pbn_titan_2_4000000] = {
3743 .base_baud = 4000000,
3744 .uart_offset = 0x200,
3745 .first_offset = 0x1000,
3747 [pbn_titan_4_4000000] = {
3750 .base_baud = 4000000,
3751 .uart_offset = 0x200,
3752 .first_offset = 0x1000,
3754 [pbn_titan_8_4000000] = {
3757 .base_baud = 4000000,
3758 .uart_offset = 0x200,
3759 .first_offset = 0x1000,
3761 [pbn_moxa8250_2p] = {
3764 .base_baud = 921600,
3765 .uart_offset = 0x200,
3767 [pbn_moxa8250_4p] = {
3770 .base_baud = 921600,
3771 .uart_offset = 0x200,
3773 [pbn_moxa8250_8p] = {
3776 .base_baud = 921600,
3777 .uart_offset = 0x200,
3781 static const struct pci_device_id blacklist[] = {
3783 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3784 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3785 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3787 /* multi-io cards handled by parport_serial */
3788 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3789 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3790 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3792 /* Intel platforms with MID UART */
3793 { PCI_VDEVICE(INTEL, 0x081b), },
3794 { PCI_VDEVICE(INTEL, 0x081c), },
3795 { PCI_VDEVICE(INTEL, 0x081d), },
3796 { PCI_VDEVICE(INTEL, 0x1191), },
3797 { PCI_VDEVICE(INTEL, 0x18d8), },
3798 { PCI_VDEVICE(INTEL, 0x19d8), },
3800 /* Intel platforms with DesignWare UART */
3801 { PCI_VDEVICE(INTEL, 0x0936), },
3802 { PCI_VDEVICE(INTEL, 0x0f0a), },
3803 { PCI_VDEVICE(INTEL, 0x0f0c), },
3804 { PCI_VDEVICE(INTEL, 0x228a), },
3805 { PCI_VDEVICE(INTEL, 0x228c), },
3806 { PCI_VDEVICE(INTEL, 0x4b96), },
3807 { PCI_VDEVICE(INTEL, 0x4b97), },
3808 { PCI_VDEVICE(INTEL, 0x4b98), },
3809 { PCI_VDEVICE(INTEL, 0x4b99), },
3810 { PCI_VDEVICE(INTEL, 0x4b9a), },
3811 { PCI_VDEVICE(INTEL, 0x4b9b), },
3812 { PCI_VDEVICE(INTEL, 0x9ce3), },
3813 { PCI_VDEVICE(INTEL, 0x9ce4), },
3816 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3817 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3819 /* End of the black list */
3823 static int serial_pci_is_class_communication(struct pci_dev *dev)
3826 * If it is not a communications device or the programming
3827 * interface is greater than 6, give up.
3829 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3830 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3831 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3832 (dev->class & 0xff) > 6)
3839 * Given a complete unknown PCI device, try to use some heuristics to
3840 * guess what the configuration might be, based on the pitiful PCI
3841 * serial specs. Returns 0 on success, -ENODEV on failure.
3844 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3846 int num_iomem, num_port, first_port = -1, i;
3849 rc = serial_pci_is_class_communication(dev);
3854 * Should we try to make guesses for multiport serial devices later?
3856 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3859 num_iomem = num_port = 0;
3860 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3861 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3863 if (first_port == -1)
3866 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3871 * If there is 1 or 0 iomem regions, and exactly one port,
3872 * use it. We guess the number of ports based on the IO
3875 if (num_iomem <= 1 && num_port == 1) {
3876 board->flags = first_port;
3877 board->num_ports = pci_resource_len(dev, first_port) / 8;
3882 * Now guess if we've got a board which indexes by BARs.
3883 * Each IO BAR should be 8 bytes, and they should follow
3888 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3889 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3890 pci_resource_len(dev, i) == 8 &&
3891 (first_port == -1 || (first_port + num_port) == i)) {
3893 if (first_port == -1)
3899 board->flags = first_port | FL_BASE_BARS;
3900 board->num_ports = num_port;
3908 serial_pci_matches(const struct pciserial_board *board,
3909 const struct pciserial_board *guessed)
3912 board->num_ports == guessed->num_ports &&
3913 board->base_baud == guessed->base_baud &&
3914 board->uart_offset == guessed->uart_offset &&
3915 board->reg_shift == guessed->reg_shift &&
3916 board->first_offset == guessed->first_offset;
3919 struct serial_private *
3920 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3922 struct uart_8250_port uart;
3923 struct serial_private *priv;
3924 struct pci_serial_quirk *quirk;
3925 int rc, nr_ports, i;
3927 nr_ports = board->num_ports;
3930 * Find an init and setup quirks.
3932 quirk = find_quirk(dev);
3935 * Run the new-style initialization function.
3936 * The initialization function returns:
3938 * 0 - use board->num_ports
3939 * >0 - number of ports
3942 rc = quirk->init(dev);
3951 priv = kzalloc(sizeof(struct serial_private) +
3952 sizeof(unsigned int) * nr_ports,
3955 priv = ERR_PTR(-ENOMEM);
3960 priv->quirk = quirk;
3962 memset(&uart, 0, sizeof(uart));
3963 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3964 uart.port.uartclk = board->base_baud * 16;
3966 if (board->flags & FL_NOIRQ) {
3969 if (pci_match_id(pci_use_msi, dev)) {
3970 pci_dbg(dev, "Using MSI(-X) interrupts\n");
3971 pci_set_master(dev);
3972 uart.port.flags &= ~UPF_SHARE_IRQ;
3973 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
3975 pci_dbg(dev, "Using legacy interrupts\n");
3976 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
3984 uart.port.irq = pci_irq_vector(dev, 0);
3987 uart.port.dev = &dev->dev;
3989 for (i = 0; i < nr_ports; i++) {
3990 if (quirk->setup(priv, board, &uart, i))
3993 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3994 uart.port.iobase, uart.port.irq, uart.port.iotype);
3996 priv->line[i] = serial8250_register_8250_port(&uart);
3997 if (priv->line[i] < 0) {
3999 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4000 uart.port.iobase, uart.port.irq,
4001 uart.port.iotype, priv->line[i]);
4006 priv->board = board;
4015 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4017 static void pciserial_detach_ports(struct serial_private *priv)
4019 struct pci_serial_quirk *quirk;
4022 for (i = 0; i < priv->nr; i++)
4023 serial8250_unregister_port(priv->line[i]);
4026 * Find the exit quirks.
4028 quirk = find_quirk(priv->dev);
4030 quirk->exit(priv->dev);
4033 void pciserial_remove_ports(struct serial_private *priv)
4035 pciserial_detach_ports(priv);
4038 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4040 void pciserial_suspend_ports(struct serial_private *priv)
4044 for (i = 0; i < priv->nr; i++)
4045 if (priv->line[i] >= 0)
4046 serial8250_suspend_port(priv->line[i]);
4049 * Ensure that every init quirk is properly torn down
4051 if (priv->quirk->exit)
4052 priv->quirk->exit(priv->dev);
4054 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4056 void pciserial_resume_ports(struct serial_private *priv)
4061 * Ensure that the board is correctly configured.
4063 if (priv->quirk->init)
4064 priv->quirk->init(priv->dev);
4066 for (i = 0; i < priv->nr; i++)
4067 if (priv->line[i] >= 0)
4068 serial8250_resume_port(priv->line[i]);
4070 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4073 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4074 * to the arrangement of serial ports on a PCI card.
4077 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4079 struct pci_serial_quirk *quirk;
4080 struct serial_private *priv;
4081 const struct pciserial_board *board;
4082 const struct pci_device_id *exclude;
4083 struct pciserial_board tmp;
4086 quirk = find_quirk(dev);
4088 rc = quirk->probe(dev);
4093 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4094 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4098 board = &pci_boards[ent->driver_data];
4100 exclude = pci_match_id(blacklist, dev);
4104 rc = pcim_enable_device(dev);
4105 pci_save_state(dev);
4109 if (ent->driver_data == pbn_default) {
4111 * Use a copy of the pci_board entry for this;
4112 * avoid changing entries in the table.
4114 memcpy(&tmp, board, sizeof(struct pciserial_board));
4118 * We matched one of our class entries. Try to
4119 * determine the parameters of this board.
4121 rc = serial_pci_guess_board(dev, &tmp);
4126 * We matched an explicit entry. If we are able to
4127 * detect this boards settings with our heuristic,
4128 * then we no longer need this entry.
4130 memcpy(&tmp, &pci_boards[pbn_default],
4131 sizeof(struct pciserial_board));
4132 rc = serial_pci_guess_board(dev, &tmp);
4133 if (rc == 0 && serial_pci_matches(board, &tmp))
4134 moan_device("Redundant entry in serial pci_table.",
4138 priv = pciserial_init_ports(dev, board);
4140 return PTR_ERR(priv);
4142 pci_set_drvdata(dev, priv);
4146 static void pciserial_remove_one(struct pci_dev *dev)
4148 struct serial_private *priv = pci_get_drvdata(dev);
4150 pciserial_remove_ports(priv);
4153 #ifdef CONFIG_PM_SLEEP
4154 static int pciserial_suspend_one(struct device *dev)
4156 struct serial_private *priv = dev_get_drvdata(dev);
4159 pciserial_suspend_ports(priv);
4164 static int pciserial_resume_one(struct device *dev)
4166 struct pci_dev *pdev = to_pci_dev(dev);
4167 struct serial_private *priv = pci_get_drvdata(pdev);
4172 * The device may have been disabled. Re-enable it.
4174 err = pci_enable_device(pdev);
4175 /* FIXME: We cannot simply error out here */
4177 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4178 pciserial_resume_ports(priv);
4184 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4185 pciserial_resume_one);
4187 static const struct pci_device_id serial_pci_tbl[] = {
4188 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4189 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4190 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4192 /* Advantech also use 0x3618 and 0xf618 */
4193 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4194 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4196 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4197 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4199 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4200 PCI_SUBVENDOR_ID_CONNECT_TECH,
4201 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4203 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4204 PCI_SUBVENDOR_ID_CONNECT_TECH,
4205 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4207 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4208 PCI_SUBVENDOR_ID_CONNECT_TECH,
4209 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4211 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4212 PCI_SUBVENDOR_ID_CONNECT_TECH,
4213 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4215 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4216 PCI_SUBVENDOR_ID_CONNECT_TECH,
4217 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4219 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4220 PCI_SUBVENDOR_ID_CONNECT_TECH,
4221 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4223 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4224 PCI_SUBVENDOR_ID_CONNECT_TECH,
4225 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4227 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4228 PCI_SUBVENDOR_ID_CONNECT_TECH,
4229 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4231 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4232 PCI_SUBVENDOR_ID_CONNECT_TECH,
4233 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4235 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4236 PCI_SUBVENDOR_ID_CONNECT_TECH,
4237 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4239 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4240 PCI_SUBVENDOR_ID_CONNECT_TECH,
4241 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4243 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4244 PCI_SUBVENDOR_ID_CONNECT_TECH,
4245 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4247 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4248 PCI_SUBVENDOR_ID_CONNECT_TECH,
4249 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4251 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4252 PCI_SUBVENDOR_ID_CONNECT_TECH,
4253 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4255 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4256 PCI_SUBVENDOR_ID_CONNECT_TECH,
4257 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4259 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4260 PCI_SUBVENDOR_ID_CONNECT_TECH,
4261 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4263 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4264 PCI_SUBVENDOR_ID_CONNECT_TECH,
4265 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4267 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4268 PCI_VENDOR_ID_AFAVLAB,
4269 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4271 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 pbn_b2_bt_1_115200 },
4274 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276 pbn_b2_bt_2_115200 },
4277 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279 pbn_b2_bt_4_115200 },
4280 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282 pbn_b2_bt_2_115200 },
4283 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285 pbn_b2_bt_4_115200 },
4286 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4292 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 pbn_b2_bt_2_115200 },
4299 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301 pbn_b2_bt_2_921600 },
4303 * VScom SPCOM800, from sl@s.pl
4305 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4308 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4311 /* Unknown card - subdevice 0x1584 */
4312 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4314 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4316 /* Unknown card - subdevice 0x1588 */
4317 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4319 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4321 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4322 PCI_SUBVENDOR_ID_KEYSPAN,
4323 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4325 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4332 PCI_VENDOR_ID_ESDGMBH,
4333 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4335 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4336 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4337 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4339 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4340 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4341 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4343 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4344 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4345 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4347 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4348 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4349 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4351 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4352 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4353 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4355 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4356 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4357 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4359 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4360 PCI_SUBVENDOR_ID_EXSYS,
4361 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4364 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4367 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4368 0x10b5, 0x106a, 0, 0,
4371 * Quatech cards. These actually have configurable clocks but for
4372 * now we just use the default.
4374 * 100 series are RS232, 200 series RS422,
4376 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4379 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4382 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4385 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4388 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4391 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4435 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4438 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4439 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4442 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 pbn_b0_bt_2_921600 },
4447 * The below card is a little controversial since it is the
4448 * subject of a PCI vendor/device ID clash. (See
4449 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4450 * For now just used the hex ID 0x950a.
4452 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4453 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4454 0, 0, pbn_b0_2_115200 },
4455 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4456 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4457 0, 0, pbn_b0_2_115200 },
4458 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4461 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4462 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4464 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4467 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 pbn_b0_bt_2_921600 },
4470 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475 * Oxford Semiconductor Inc. Tornado PCI express device range.
4477 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485 pbn_oxsemi_1_3906250 },
4486 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4488 pbn_oxsemi_1_3906250 },
4489 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_oxsemi_1_3906250 },
4498 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_oxsemi_1_3906250 },
4501 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515 pbn_oxsemi_2_3906250 },
4516 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518 pbn_oxsemi_2_3906250 },
4519 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 pbn_oxsemi_4_3906250 },
4522 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524 pbn_oxsemi_4_3906250 },
4525 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 pbn_oxsemi_8_3906250 },
4528 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 pbn_oxsemi_8_3906250 },
4531 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_oxsemi_1_3906250 },
4534 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 pbn_oxsemi_1_3906250 },
4537 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 pbn_oxsemi_1_3906250 },
4540 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 pbn_oxsemi_1_3906250 },
4543 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 pbn_oxsemi_1_3906250 },
4546 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_oxsemi_1_3906250 },
4549 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_oxsemi_1_3906250 },
4552 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 pbn_oxsemi_1_3906250 },
4555 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 pbn_oxsemi_1_3906250 },
4558 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 pbn_oxsemi_1_3906250 },
4561 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 pbn_oxsemi_1_3906250 },
4564 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 pbn_oxsemi_1_3906250 },
4567 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569 pbn_oxsemi_1_3906250 },
4570 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572 pbn_oxsemi_1_3906250 },
4573 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 pbn_oxsemi_1_3906250 },
4576 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_oxsemi_1_3906250 },
4579 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_oxsemi_1_3906250 },
4582 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_oxsemi_1_3906250 },
4585 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_oxsemi_1_3906250 },
4588 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_oxsemi_1_3906250 },
4591 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_oxsemi_1_3906250 },
4594 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_oxsemi_1_3906250 },
4597 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_oxsemi_1_3906250 },
4600 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_oxsemi_1_3906250 },
4603 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_oxsemi_1_3906250 },
4606 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_oxsemi_1_3906250 },
4610 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4612 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4613 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4614 pbn_oxsemi_1_3906250 },
4615 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4616 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4617 pbn_oxsemi_2_3906250 },
4618 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4619 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4620 pbn_oxsemi_4_3906250 },
4621 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4622 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4623 pbn_oxsemi_8_3906250 },
4626 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4628 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4629 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4630 pbn_oxsemi_2_3906250 },
4632 * EndRun Technologies. PCI express device range.
4633 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4635 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_oxsemi_2_3906250 },
4640 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4641 * from skokodyn@yahoo.com
4643 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4644 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4646 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4647 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4649 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4650 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4652 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4653 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4657 * Digitan DS560-558, from jimd@esoft.com
4659 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 * Titan Electronic cards
4665 * The 400L and 800L have a custom setup quirk.
4667 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4679 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_b1_bt_2_921600 },
4685 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b0_bt_4_921600 },
4688 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_b0_bt_8_921600 },
4691 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_b4_bt_2_921600 },
4694 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_b4_bt_4_921600 },
4697 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 pbn_b4_bt_8_921600 },
4700 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_titan_1_4000000 },
4712 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_titan_2_4000000 },
4715 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_titan_4_4000000 },
4718 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_titan_8_4000000 },
4721 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 pbn_titan_2_4000000 },
4724 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_titan_2_4000000 },
4727 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 pbn_b0_bt_2_921600 },
4730 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_b2_bt_2_921600 },
4755 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_b2_bt_2_921600 },
4758 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_b2_bt_2_921600 },
4761 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 pbn_b2_bt_4_921600 },
4764 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_b2_bt_4_921600 },
4767 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_b2_bt_4_921600 },
4770 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_b0_bt_2_921600 },
4782 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_b0_bt_2_921600 },
4785 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_b0_bt_2_921600 },
4788 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_b0_bt_4_921600 },
4791 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_b0_bt_4_921600 },
4794 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_b0_bt_4_921600 },
4797 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_b0_bt_8_921600 },
4800 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_b0_bt_8_921600 },
4803 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_b0_bt_8_921600 },
4808 * Computone devices submitted by Doug McNash dmcnash@computone.com
4810 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4811 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4812 0, 0, pbn_computone_4 },
4813 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4814 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4815 0, 0, pbn_computone_8 },
4816 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4817 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4818 0, 0, pbn_computone_6 },
4820 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4824 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4825 pbn_b0_bt_1_921600 },
4828 * Sunix PCI serial boards
4830 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4831 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4833 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4834 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4836 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4837 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4839 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4840 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4842 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4843 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4845 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4846 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4848 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4849 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4850 pbn_sunix_pci_16s },
4853 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4855 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4857 pbn_b0_bt_8_115200 },
4858 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 pbn_b0_bt_8_115200 },
4862 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864 pbn_b0_bt_2_115200 },
4865 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867 pbn_b0_bt_2_115200 },
4868 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4870 pbn_b0_bt_2_115200 },
4871 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4873 pbn_b0_bt_2_115200 },
4874 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876 pbn_b0_bt_2_115200 },
4877 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 pbn_b0_bt_4_460800 },
4880 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 pbn_b0_bt_4_460800 },
4883 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 pbn_b0_bt_2_460800 },
4886 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 pbn_b0_bt_2_460800 },
4889 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 pbn_b0_bt_2_460800 },
4892 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 pbn_b0_bt_1_115200 },
4895 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897 pbn_b0_bt_1_460800 },
4900 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4901 * Cards are identified by their subsystem vendor IDs, which
4902 * (in hex) match the model number.
4904 * Note that JC140x are RS422/485 cards which require ox950
4905 * ACR = 0x10, and as such are not currently fully supported.
4907 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4908 0x1204, 0x0004, 0, 0,
4910 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4911 0x1208, 0x0004, 0, 0,
4913 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4914 0x1402, 0x0002, 0, 0,
4915 pbn_b0_2_921600 }, */
4916 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4917 0x1404, 0x0004, 0, 0,
4918 pbn_b0_4_921600 }, */
4919 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4920 0x1208, 0x0004, 0, 0,
4923 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4924 0x1204, 0x0004, 0, 0,
4926 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4927 0x1208, 0x0004, 0, 0,
4929 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4930 0x1208, 0x0004, 0, 0,
4933 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4935 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4942 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 * RAStel 2 port modem, gerg@moreton.com.au
4949 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951 pbn_b2_bt_2_115200 },
4954 * EKF addition for i960 Boards form EKF with serial port
4956 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4957 0xE4BF, PCI_ANY_ID, 0, 0,
4961 * Xircom Cardbus/Ethernet combos
4963 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4967 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4969 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974 * Untested PCI modems, sent in from various folks...
4978 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4980 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4981 0x1048, 0x1500, 0, 0,
4984 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4991 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4992 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4994 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4997 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5000 /* HPE PCI serial device */
5001 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5015 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5017 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5018 PCI_ANY_ID, PCI_ANY_ID,
5020 0, pbn_pericom_PI7C9X7951 },
5021 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5022 PCI_ANY_ID, PCI_ANY_ID,
5024 0, pbn_pericom_PI7C9X7952 },
5025 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5026 PCI_ANY_ID, PCI_ANY_ID,
5028 0, pbn_pericom_PI7C9X7954 },
5029 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5030 PCI_ANY_ID, PCI_ANY_ID,
5032 0, pbn_pericom_PI7C9X7958 },
5034 * ACCES I/O Products quad
5036 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038 pbn_pericom_PI7C9X7952 },
5039 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041 pbn_pericom_PI7C9X7952 },
5042 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044 pbn_pericom_PI7C9X7954 },
5045 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5047 pbn_pericom_PI7C9X7954 },
5048 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050 pbn_pericom_PI7C9X7952 },
5051 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053 pbn_pericom_PI7C9X7952 },
5054 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5056 pbn_pericom_PI7C9X7954 },
5057 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5059 pbn_pericom_PI7C9X7954 },
5060 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5062 pbn_pericom_PI7C9X7952 },
5063 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5065 pbn_pericom_PI7C9X7952 },
5066 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5068 pbn_pericom_PI7C9X7954 },
5069 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5071 pbn_pericom_PI7C9X7954 },
5072 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5074 pbn_pericom_PI7C9X7951 },
5075 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5077 pbn_pericom_PI7C9X7952 },
5078 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5080 pbn_pericom_PI7C9X7952 },
5081 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5083 pbn_pericom_PI7C9X7954 },
5084 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5086 pbn_pericom_PI7C9X7954 },
5087 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5089 pbn_pericom_PI7C9X7952 },
5090 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092 pbn_pericom_PI7C9X7954 },
5093 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5095 pbn_pericom_PI7C9X7952 },
5096 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5098 pbn_pericom_PI7C9X7952 },
5099 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5101 pbn_pericom_PI7C9X7954 },
5102 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5104 pbn_pericom_PI7C9X7954 },
5105 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5107 pbn_pericom_PI7C9X7952 },
5108 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5110 pbn_pericom_PI7C9X7954 },
5111 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5113 pbn_pericom_PI7C9X7954 },
5114 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5116 pbn_pericom_PI7C9X7958 },
5117 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5119 pbn_pericom_PI7C9X7958 },
5120 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5122 pbn_pericom_PI7C9X7954 },
5123 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5125 pbn_pericom_PI7C9X7958 },
5126 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5128 pbn_pericom_PI7C9X7954 },
5129 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5131 pbn_pericom_PI7C9X7958 },
5132 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5134 pbn_pericom_PI7C9X7954 },
5136 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5138 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5144 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5145 PCI_ANY_ID, PCI_ANY_ID,
5147 pbn_b1_bt_1_115200 },
5152 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5158 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5161 /* Brainboxes Devices */
5165 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5166 PCI_ANY_ID, PCI_ANY_ID,
5170 * Brainboxes UC-235/246
5172 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5173 PCI_ANY_ID, PCI_ANY_ID,
5179 { PCI_VENDOR_ID_INTASHIELD, 0x0861,
5180 PCI_ANY_ID, PCI_ANY_ID,
5184 * Brainboxes UC-260/271/701/756
5186 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5187 PCI_ANY_ID, PCI_ANY_ID,
5188 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5190 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5191 PCI_ANY_ID, PCI_ANY_ID,
5192 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5197 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5198 PCI_ANY_ID, PCI_ANY_ID,
5202 * Brainboxes UC-275/279
5204 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5205 PCI_ANY_ID, PCI_ANY_ID,
5211 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5212 PCI_ANY_ID, PCI_ANY_ID,
5218 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5219 PCI_ANY_ID, PCI_ANY_ID,
5225 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5226 PCI_ANY_ID, PCI_ANY_ID,
5230 * Brainboxes UC-320/324
5232 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5233 PCI_ANY_ID, PCI_ANY_ID,
5239 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5240 PCI_ANY_ID, PCI_ANY_ID,
5246 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5247 PCI_ANY_ID, PCI_ANY_ID,
5250 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5251 PCI_ANY_ID, PCI_ANY_ID,
5257 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5258 PCI_ANY_ID, PCI_ANY_ID,
5262 * Brainboxes UC-420/431
5264 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5265 PCI_ANY_ID, PCI_ANY_ID,
5269 * Perle PCI-RAS cards
5271 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5272 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5273 0, 0, pbn_b2_4_921600 },
5274 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5275 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5276 0, 0, pbn_b2_8_921600 },
5279 * Mainpine series cards: Fairly standard layout but fools
5280 * parts of the autodetect in some cases and uses otherwise
5281 * unmatched communications subclasses in the PCI Express case
5284 { /* RockForceDUO */
5285 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5286 PCI_VENDOR_ID_MAINPINE, 0x0200,
5287 0, 0, pbn_b0_2_115200 },
5288 { /* RockForceQUATRO */
5289 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5290 PCI_VENDOR_ID_MAINPINE, 0x0300,
5291 0, 0, pbn_b0_4_115200 },
5292 { /* RockForceDUO+ */
5293 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5294 PCI_VENDOR_ID_MAINPINE, 0x0400,
5295 0, 0, pbn_b0_2_115200 },
5296 { /* RockForceQUATRO+ */
5297 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5298 PCI_VENDOR_ID_MAINPINE, 0x0500,
5299 0, 0, pbn_b0_4_115200 },
5301 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5302 PCI_VENDOR_ID_MAINPINE, 0x0600,
5303 0, 0, pbn_b0_2_115200 },
5305 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5306 PCI_VENDOR_ID_MAINPINE, 0x0700,
5307 0, 0, pbn_b0_4_115200 },
5308 { /* RockForceOCTO+ */
5309 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5310 PCI_VENDOR_ID_MAINPINE, 0x0800,
5311 0, 0, pbn_b0_8_115200 },
5312 { /* RockForceDUO+ */
5313 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5314 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5315 0, 0, pbn_b0_2_115200 },
5316 { /* RockForceQUARTRO+ */
5317 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5318 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5319 0, 0, pbn_b0_4_115200 },
5320 { /* RockForceOCTO+ */
5321 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5322 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5323 0, 0, pbn_b0_8_115200 },
5325 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5326 PCI_VENDOR_ID_MAINPINE, 0x2000,
5327 0, 0, pbn_b0_1_115200 },
5329 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5330 PCI_VENDOR_ID_MAINPINE, 0x2100,
5331 0, 0, pbn_b0_1_115200 },
5333 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5334 PCI_VENDOR_ID_MAINPINE, 0x2200,
5335 0, 0, pbn_b0_2_115200 },
5337 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5338 PCI_VENDOR_ID_MAINPINE, 0x2300,
5339 0, 0, pbn_b0_2_115200 },
5341 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5342 PCI_VENDOR_ID_MAINPINE, 0x2400,
5343 0, 0, pbn_b0_4_115200 },
5345 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5346 PCI_VENDOR_ID_MAINPINE, 0x2500,
5347 0, 0, pbn_b0_4_115200 },
5349 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5350 PCI_VENDOR_ID_MAINPINE, 0x2600,
5351 0, 0, pbn_b0_8_115200 },
5353 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5354 PCI_VENDOR_ID_MAINPINE, 0x2700,
5355 0, 0, pbn_b0_8_115200 },
5356 { /* IQ Express D1 */
5357 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5358 PCI_VENDOR_ID_MAINPINE, 0x3000,
5359 0, 0, pbn_b0_1_115200 },
5360 { /* IQ Express F1 */
5361 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5362 PCI_VENDOR_ID_MAINPINE, 0x3100,
5363 0, 0, pbn_b0_1_115200 },
5364 { /* IQ Express D2 */
5365 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5366 PCI_VENDOR_ID_MAINPINE, 0x3200,
5367 0, 0, pbn_b0_2_115200 },
5368 { /* IQ Express F2 */
5369 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5370 PCI_VENDOR_ID_MAINPINE, 0x3300,
5371 0, 0, pbn_b0_2_115200 },
5372 { /* IQ Express D4 */
5373 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5374 PCI_VENDOR_ID_MAINPINE, 0x3400,
5375 0, 0, pbn_b0_4_115200 },
5376 { /* IQ Express F4 */
5377 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5378 PCI_VENDOR_ID_MAINPINE, 0x3500,
5379 0, 0, pbn_b0_4_115200 },
5380 { /* IQ Express D8 */
5381 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5382 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5383 0, 0, pbn_b0_8_115200 },
5384 { /* IQ Express F8 */
5385 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5386 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5387 0, 0, pbn_b0_8_115200 },
5391 * PA Semi PA6T-1682M on-chip UART
5393 { PCI_VENDOR_ID_PASEMI, 0xa004,
5394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5398 * National Instruments
5400 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5403 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5406 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5408 pbn_b1_bt_4_115200 },
5409 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5411 pbn_b1_bt_2_115200 },
5412 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5414 pbn_b1_bt_4_115200 },
5415 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5417 pbn_b1_bt_2_115200 },
5418 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5421 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5424 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5426 pbn_b1_bt_4_115200 },
5427 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5429 pbn_b1_bt_2_115200 },
5430 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5432 pbn_b1_bt_4_115200 },
5433 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5435 pbn_b1_bt_2_115200 },
5436 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5439 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5442 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5445 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5448 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5451 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5454 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5457 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5460 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5463 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5466 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5469 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5476 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
5477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5479 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
5480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5482 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
5483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5485 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
5486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5488 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
5489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5491 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
5492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5494 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
5495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5497 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
5498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5500 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
5501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5503 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
5504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5506 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
5507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5509 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
5510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5514 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5516 { PCI_VENDOR_ID_ADDIDATA,
5517 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5524 { PCI_VENDOR_ID_ADDIDATA,
5525 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5532 { PCI_VENDOR_ID_ADDIDATA,
5533 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5540 { PCI_VENDOR_ID_AMCC,
5541 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5548 { PCI_VENDOR_ID_ADDIDATA,
5549 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5556 { PCI_VENDOR_ID_ADDIDATA,
5557 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5564 { PCI_VENDOR_ID_ADDIDATA,
5565 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5572 { PCI_VENDOR_ID_ADDIDATA,
5573 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5580 { PCI_VENDOR_ID_ADDIDATA,
5581 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5588 { PCI_VENDOR_ID_ADDIDATA,
5589 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5596 { PCI_VENDOR_ID_ADDIDATA,
5597 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5604 { PCI_VENDOR_ID_ADDIDATA,
5605 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5610 pbn_ADDIDATA_PCIe_4_3906250 },
5612 { PCI_VENDOR_ID_ADDIDATA,
5613 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5618 pbn_ADDIDATA_PCIe_2_3906250 },
5620 { PCI_VENDOR_ID_ADDIDATA,
5621 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5626 pbn_ADDIDATA_PCIe_1_3906250 },
5628 { PCI_VENDOR_ID_ADDIDATA,
5629 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5634 pbn_ADDIDATA_PCIe_8_3906250 },
5636 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5637 PCI_VENDOR_ID_IBM, 0x0299,
5638 0, 0, pbn_b0_bt_2_115200 },
5641 * other NetMos 9835 devices are most likely handled by the
5642 * parport_serial driver, check drivers/parport/parport_serial.c
5643 * before adding them here.
5646 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5648 0, 0, pbn_b0_1_115200 },
5650 /* the 9901 is a rebranded 9912 */
5651 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5653 0, 0, pbn_b0_1_115200 },
5655 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5657 0, 0, pbn_b0_1_115200 },
5659 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5661 0, 0, pbn_b0_1_115200 },
5663 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5665 0, 0, pbn_b0_1_115200 },
5667 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5669 0, 0, pbn_NETMOS9900_2s_115200 },
5672 * Best Connectivity and Rosewill PCI Multi I/O cards
5675 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5677 0, 0, pbn_b0_1_115200 },
5679 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5681 0, 0, pbn_b0_bt_2_115200 },
5683 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5685 0, 0, pbn_b0_bt_4_115200 },
5687 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5689 pbn_ce4100_1_115200 },
5694 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5699 * Broadcom TruManage
5701 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5703 pbn_brcm_trumanage },
5706 * AgeStar as-prs2-009
5708 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5709 PCI_ANY_ID, PCI_ANY_ID,
5710 0, 0, pbn_b0_bt_2_115200 },
5713 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5714 * so not listed here.
5716 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5717 PCI_ANY_ID, PCI_ANY_ID,
5718 0, 0, pbn_b0_bt_4_115200 },
5720 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5721 PCI_ANY_ID, PCI_ANY_ID,
5722 0, 0, pbn_b0_bt_2_115200 },
5724 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5725 PCI_ANY_ID, PCI_ANY_ID,
5726 0, 0, pbn_b0_bt_4_115200 },
5728 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5729 PCI_ANY_ID, PCI_ANY_ID,
5730 0, 0, pbn_wch382_2 },
5732 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5733 PCI_ANY_ID, PCI_ANY_ID,
5734 0, 0, pbn_wch384_4 },
5736 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
5737 PCI_ANY_ID, PCI_ANY_ID,
5738 0, 0, pbn_wch384_8 },
5740 * Realtek RealManage
5742 { PCI_VENDOR_ID_REALTEK, 0x816a,
5743 PCI_ANY_ID, PCI_ANY_ID,
5744 0, 0, pbn_b0_1_115200 },
5746 { PCI_VENDOR_ID_REALTEK, 0x816b,
5747 PCI_ANY_ID, PCI_ANY_ID,
5748 0, 0, pbn_b0_1_115200 },
5750 /* Fintek PCI serial cards */
5751 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5752 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5753 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5754 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5755 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5756 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5758 /* MKS Tenta SCOM-080x serial cards */
5759 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5760 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5762 /* Amazon PCI serial device */
5763 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5766 * These entries match devices with class COMMUNICATION_SERIAL,
5767 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5769 { PCI_ANY_ID, PCI_ANY_ID,
5770 PCI_ANY_ID, PCI_ANY_ID,
5771 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5772 0xffff00, pbn_default },
5773 { PCI_ANY_ID, PCI_ANY_ID,
5774 PCI_ANY_ID, PCI_ANY_ID,
5775 PCI_CLASS_COMMUNICATION_MODEM << 8,
5776 0xffff00, pbn_default },
5777 { PCI_ANY_ID, PCI_ANY_ID,
5778 PCI_ANY_ID, PCI_ANY_ID,
5779 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5780 0xffff00, pbn_default },
5784 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5785 pci_channel_state_t state)
5787 struct serial_private *priv = pci_get_drvdata(dev);
5789 if (state == pci_channel_io_perm_failure)
5790 return PCI_ERS_RESULT_DISCONNECT;
5793 pciserial_detach_ports(priv);
5795 pci_disable_device(dev);
5797 return PCI_ERS_RESULT_NEED_RESET;
5800 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5804 rc = pci_enable_device(dev);
5807 return PCI_ERS_RESULT_DISCONNECT;
5809 pci_restore_state(dev);
5810 pci_save_state(dev);
5812 return PCI_ERS_RESULT_RECOVERED;
5815 static void serial8250_io_resume(struct pci_dev *dev)
5817 struct serial_private *priv = pci_get_drvdata(dev);
5818 struct serial_private *new;
5823 new = pciserial_init_ports(dev, priv->board);
5825 pci_set_drvdata(dev, new);
5830 static const struct pci_error_handlers serial8250_err_handler = {
5831 .error_detected = serial8250_io_error_detected,
5832 .slot_reset = serial8250_io_slot_reset,
5833 .resume = serial8250_io_resume,
5836 static struct pci_driver serial_pci_driver = {
5838 .probe = pciserial_init_one,
5839 .remove = pciserial_remove_one,
5841 .pm = &pciserial_pm_ops,
5843 .id_table = serial_pci_tbl,
5844 .err_handler = &serial8250_err_handler,
5847 module_pci_driver(serial_pci_driver);
5849 MODULE_LICENSE("GPL");
5850 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5851 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);