2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
25 #include <asm/byteorder.h>
31 * init function returns:
32 * > 0 - number of ports
33 * = 0 - use board->num_ports
36 struct pci_serial_quirk {
41 int (*probe)(struct pci_dev *dev);
42 int (*init)(struct pci_dev *dev);
43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
45 struct uart_8250_port *, int);
46 void (*exit)(struct pci_dev *dev);
49 #define PCI_NUM_BAR_RESOURCES 6
51 struct serial_private {
54 struct pci_serial_quirk *quirk;
55 const struct pciserial_board *board;
59 static int pci_default_setup(struct serial_private*,
60 const struct pciserial_board*, struct uart_8250_port *, int);
62 static void moan_device(const char *str, struct pci_dev *dev)
66 "Please send the output of lspci -vv, this\n"
67 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 "manufacturer and name of serial board or\n"
69 "modem board to <linux-serial@vger.kernel.org>.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
75 setup_port(struct serial_private *priv, struct uart_8250_port *port,
76 u8 bar, unsigned int offset, int regshift)
78 struct pci_dev *dev = priv->dev;
80 if (bar >= PCI_NUM_BAR_RESOURCES)
83 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
84 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
87 port->port.iotype = UPIO_MEM;
88 port->port.iobase = 0;
89 port->port.mapbase = pci_resource_start(dev, bar) + offset;
90 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
91 port->port.regshift = regshift;
93 port->port.iotype = UPIO_PORT;
94 port->port.iobase = pci_resource_start(dev, bar) + offset;
95 port->port.mapbase = 0;
96 port->port.membase = NULL;
97 port->port.regshift = 0;
103 * ADDI-DATA GmbH communication cards <info@addi-data.com>
105 static int addidata_apci7800_setup(struct serial_private *priv,
106 const struct pciserial_board *board,
107 struct uart_8250_port *port, int idx)
109 unsigned int bar = 0, offset = board->first_offset;
110 bar = FL_GET_BASE(board->flags);
113 offset += idx * board->uart_offset;
114 } else if ((idx >= 2) && (idx < 4)) {
116 offset += ((idx - 2) * board->uart_offset);
117 } else if ((idx >= 4) && (idx < 6)) {
119 offset += ((idx - 4) * board->uart_offset);
120 } else if (idx >= 6) {
122 offset += ((idx - 6) * board->uart_offset);
125 return setup_port(priv, port, bar, offset, board->reg_shift);
129 * AFAVLAB uses a different mixture of BARs and offsets
130 * Not that ugly ;) -- HW
133 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
134 struct uart_8250_port *port, int idx)
136 unsigned int bar, offset = board->first_offset;
138 bar = FL_GET_BASE(board->flags);
143 offset += (idx - 4) * board->uart_offset;
146 return setup_port(priv, port, bar, offset, board->reg_shift);
150 * HP's Remote Management Console. The Diva chip came in several
151 * different versions. N-class, L2000 and A500 have two Diva chips, each
152 * with 3 UARTs (the third UART on the second chip is unused). Superdome
153 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
154 * one Diva chip, but it has been expanded to 5 UARTs.
156 static int pci_hp_diva_init(struct pci_dev *dev)
160 switch (dev->subsystem_device) {
161 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
162 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
163 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
164 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
170 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
173 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
174 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
183 * HP's Diva chip puts the 4th/5th serial port further out, and
184 * some serial ports are supposed to be hidden on certain models.
187 pci_hp_diva_setup(struct serial_private *priv,
188 const struct pciserial_board *board,
189 struct uart_8250_port *port, int idx)
191 unsigned int offset = board->first_offset;
192 unsigned int bar = FL_GET_BASE(board->flags);
194 switch (priv->dev->subsystem_device) {
195 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
199 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 offset += idx * board->uart_offset;
211 return setup_port(priv, port, bar, offset, board->reg_shift);
215 * Added for EKF Intel i960 serial boards
217 static int pci_inteli960ni_init(struct pci_dev *dev)
221 if (!(dev->subsystem_device & 0x1000))
224 /* is firmware started? */
225 pci_read_config_dword(dev, 0x44, &oldval);
226 if (oldval == 0x00001000L) { /* RESET value */
227 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
234 * Some PCI serial cards using the PLX 9050 PCI interface chip require
235 * that the card interrupt be explicitly enabled or disabled. This
236 * seems to be mainly needed on card using the PLX which also use I/O
239 static int pci_plx9050_init(struct pci_dev *dev)
244 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
245 moan_device("no memory in bar 0", dev);
250 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
251 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
254 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
255 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
257 * As the megawolf cards have the int pins active
258 * high, and have 2 UART chips, both ints must be
259 * enabled on the 9050. Also, the UARTS are set in
260 * 16450 mode by default, so we have to enable the
261 * 16C950 'enhanced' mode so that we can use the
266 * enable/disable interrupts
268 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
271 writel(irq_config, p + 0x4c);
274 * Read the register back to ensure that it took effect.
282 static void pci_plx9050_exit(struct pci_dev *dev)
286 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
297 * Read the register back to ensure that it took effect.
304 #define NI8420_INT_ENABLE_REG 0x38
305 #define NI8420_INT_ENABLE_BIT 0x2000
307 static void pci_ni8420_exit(struct pci_dev *dev)
310 unsigned int bar = 0;
312 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
313 moan_device("no memory in bar", dev);
317 p = pci_ioremap_bar(dev, bar);
321 /* Disable the CPU Interrupt */
322 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
323 p + NI8420_INT_ENABLE_REG);
329 #define MITE_IOWBSR1 0xc4
330 #define MITE_IOWCR1 0xf4
331 #define MITE_LCIMR1 0x08
332 #define MITE_LCIMR2 0x10
334 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
336 static void pci_ni8430_exit(struct pci_dev *dev)
339 unsigned int bar = 0;
341 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
342 moan_device("no memory in bar", dev);
346 p = pci_ioremap_bar(dev, bar);
350 /* Disable the CPU Interrupt */
351 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
355 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
357 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
358 struct uart_8250_port *port, int idx)
360 unsigned int bar, offset = board->first_offset;
365 /* first four channels map to 0, 0x100, 0x200, 0x300 */
366 offset += idx * board->uart_offset;
367 } else if (idx < 8) {
368 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
369 offset += idx * board->uart_offset + 0xC00;
370 } else /* we have only 8 ports on PMC-OCTALPRO */
373 return setup_port(priv, port, bar, offset, board->reg_shift);
377 * This does initialization for PMC OCTALPRO cards:
378 * maps the device memory, resets the UARTs (needed, bc
379 * if the module is removed and inserted again, the card
380 * is in the sleep mode) and enables global interrupt.
383 /* global control register offset for SBS PMC-OctalPro */
384 #define OCT_REG_CR_OFF 0x500
386 static int sbs_init(struct pci_dev *dev)
390 p = pci_ioremap_bar(dev, 0);
394 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
395 writeb(0x10, p + OCT_REG_CR_OFF);
397 writeb(0x0, p + OCT_REG_CR_OFF);
399 /* Set bit-2 (INTENABLE) of Control Register */
400 writeb(0x4, p + OCT_REG_CR_OFF);
407 * Disables the global interrupt of PMC-OctalPro
410 static void sbs_exit(struct pci_dev *dev)
414 p = pci_ioremap_bar(dev, 0);
415 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
417 writeb(0, p + OCT_REG_CR_OFF);
422 * SIIG serial cards have an PCI interface chip which also controls
423 * the UART clocking frequency. Each UART can be clocked independently
424 * (except cards equipped with 4 UARTs) and initial clocking settings
425 * are stored in the EEPROM chip. It can cause problems because this
426 * version of serial driver doesn't support differently clocked UART's
427 * on single PCI card. To prevent this, initialization functions set
428 * high frequency clocking for all UART's on given card. It is safe (I
429 * hope) because it doesn't touch EEPROM settings to prevent conflicts
430 * with other OSes (like M$ DOS).
432 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
434 * There is two family of SIIG serial cards with different PCI
435 * interface chip and different configuration methods:
436 * - 10x cards have control registers in IO and/or memory space;
437 * - 20x cards have control registers in standard PCI configuration space.
439 * Note: all 10x cards have PCI device ids 0x10..
440 * all 20x cards have PCI device ids 0x20..
442 * There are also Quartet Serial cards which use Oxford Semiconductor
443 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
445 * Note: some SIIG cards are probed by the parport_serial object.
448 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
449 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
451 static int pci_siig10x_init(struct pci_dev *dev)
456 switch (dev->device & 0xfff8) {
457 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
460 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
463 default: /* 1S1P, 4S */
468 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
472 writew(readw(p + 0x28) & data, p + 0x28);
478 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
479 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
481 static int pci_siig20x_init(struct pci_dev *dev)
485 /* Change clock frequency for the first UART. */
486 pci_read_config_byte(dev, 0x6f, &data);
487 pci_write_config_byte(dev, 0x6f, data & 0xef);
489 /* If this card has 2 UART, we have to do the same with second UART. */
490 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
491 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
492 pci_read_config_byte(dev, 0x73, &data);
493 pci_write_config_byte(dev, 0x73, data & 0xef);
498 static int pci_siig_init(struct pci_dev *dev)
500 unsigned int type = dev->device & 0xff00;
503 return pci_siig10x_init(dev);
504 else if (type == 0x2000)
505 return pci_siig20x_init(dev);
507 moan_device("Unknown SIIG card", dev);
511 static int pci_siig_setup(struct serial_private *priv,
512 const struct pciserial_board *board,
513 struct uart_8250_port *port, int idx)
515 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
519 offset = (idx - 4) * 8;
522 return setup_port(priv, port, bar, offset, 0);
526 * Timedia has an explosion of boards, and to avoid the PCI table from
527 * growing *huge*, we use this function to collapse some 70 entries
528 * in the PCI table into one, for sanity's and compactness's sake.
530 static const unsigned short timedia_single_port[] = {
531 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
534 static const unsigned short timedia_dual_port[] = {
535 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
536 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
537 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
538 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
542 static const unsigned short timedia_quad_port[] = {
543 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
544 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
545 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
549 static const unsigned short timedia_eight_port[] = {
550 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
551 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
554 static const struct timedia_struct {
556 const unsigned short *ids;
558 { 1, timedia_single_port },
559 { 2, timedia_dual_port },
560 { 4, timedia_quad_port },
561 { 8, timedia_eight_port }
565 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
566 * listing them individually, this driver merely grabs them all with
567 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
568 * and should be left free to be claimed by parport_serial instead.
570 static int pci_timedia_probe(struct pci_dev *dev)
573 * Check the third digit of the subdevice ID
574 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
576 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
578 "ignoring Timedia subdevice %04x for parport_serial\n",
579 dev->subsystem_device);
586 static int pci_timedia_init(struct pci_dev *dev)
588 const unsigned short *ids;
591 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
592 ids = timedia_data[i].ids;
593 for (j = 0; ids[j]; j++)
594 if (dev->subsystem_device == ids[j])
595 return timedia_data[i].num;
601 * Timedia/SUNIX uses a mixture of BARs and offsets
602 * Ugh, this is ugly as all hell --- TYT
605 pci_timedia_setup(struct serial_private *priv,
606 const struct pciserial_board *board,
607 struct uart_8250_port *port, int idx)
609 unsigned int bar = 0, offset = board->first_offset;
616 offset = board->uart_offset;
623 offset = board->uart_offset;
632 return setup_port(priv, port, bar, offset, board->reg_shift);
636 * Some Titan cards are also a little weird
639 titan_400l_800l_setup(struct serial_private *priv,
640 const struct pciserial_board *board,
641 struct uart_8250_port *port, int idx)
643 unsigned int bar, offset = board->first_offset;
654 offset = (idx - 2) * board->uart_offset;
657 return setup_port(priv, port, bar, offset, board->reg_shift);
660 static int pci_xircom_init(struct pci_dev *dev)
666 static int pci_ni8420_init(struct pci_dev *dev)
669 unsigned int bar = 0;
671 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
672 moan_device("no memory in bar", dev);
676 p = pci_ioremap_bar(dev, bar);
680 /* Enable CPU Interrupt */
681 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
682 p + NI8420_INT_ENABLE_REG);
688 #define MITE_IOWBSR1_WSIZE 0xa
689 #define MITE_IOWBSR1_WIN_OFFSET 0x800
690 #define MITE_IOWBSR1_WENAB (1 << 7)
691 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
692 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
693 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
695 static int pci_ni8430_init(struct pci_dev *dev)
698 struct pci_bus_region region;
700 unsigned int bar = 0;
702 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
703 moan_device("no memory in bar", dev);
707 p = pci_ioremap_bar(dev, bar);
712 * Set device window address and size in BAR0, while acknowledging that
713 * the resource structure may contain a translated address that differs
714 * from the address the device responds to.
716 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
717 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
718 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
719 writel(device_window, p + MITE_IOWBSR1);
721 /* Set window access to go to RAMSEL IO address space */
722 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
725 /* Enable IO Bus Interrupt 0 */
726 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
728 /* Enable CPU Interrupt */
729 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
735 /* UART Port Control Register */
736 #define NI8430_PORTCON 0x0f
737 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
740 pci_ni8430_setup(struct serial_private *priv,
741 const struct pciserial_board *board,
742 struct uart_8250_port *port, int idx)
744 struct pci_dev *dev = priv->dev;
746 unsigned int bar, offset = board->first_offset;
748 if (idx >= board->num_ports)
751 bar = FL_GET_BASE(board->flags);
752 offset += idx * board->uart_offset;
754 p = pci_ioremap_bar(dev, bar);
758 /* enable the transceiver */
759 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
760 p + offset + NI8430_PORTCON);
764 return setup_port(priv, port, bar, offset, board->reg_shift);
767 static int pci_netmos_9900_setup(struct serial_private *priv,
768 const struct pciserial_board *board,
769 struct uart_8250_port *port, int idx)
773 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
774 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
775 /* netmos apparently orders BARs by datasheet layout, so serial
776 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
780 return setup_port(priv, port, bar, 0, board->reg_shift);
782 return pci_default_setup(priv, board, port, idx);
786 /* the 99xx series comes with a range of device IDs and a variety
789 * 9900 has varying capabilities and can cascade to sub-controllers
790 * (cascading should be purely internal)
791 * 9904 is hardwired with 4 serial ports
792 * 9912 and 9922 are hardwired with 2 serial ports
794 static int pci_netmos_9900_numports(struct pci_dev *dev)
796 unsigned int c = dev->class;
798 unsigned short sub_serports;
805 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
806 /* two possibilities: 0x30ps encodes number of parallel and
807 * serial ports, or 0x1000 indicates *something*. This is not
808 * immediately obvious, since the 2s1p+4s configuration seems
809 * to offer all functionality on functions 0..2, while still
810 * advertising the same function 3 as the 4s+2s1p config.
812 sub_serports = dev->subsystem_device & 0xf;
813 if (sub_serports > 0)
817 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
821 moan_device("unknown NetMos/Mostech program interface", dev);
825 static int pci_netmos_init(struct pci_dev *dev)
827 /* subdevice 0x00PS means <P> parallel, <S> serial */
828 unsigned int num_serial = dev->subsystem_device & 0xf;
830 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
831 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
834 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
835 dev->subsystem_device == 0x0299)
838 switch (dev->device) { /* FALLTHROUGH on all */
839 case PCI_DEVICE_ID_NETMOS_9904:
840 case PCI_DEVICE_ID_NETMOS_9912:
841 case PCI_DEVICE_ID_NETMOS_9922:
842 case PCI_DEVICE_ID_NETMOS_9900:
843 num_serial = pci_netmos_9900_numports(dev);
850 if (num_serial == 0) {
851 moan_device("unknown NetMos/Mostech device", dev);
859 * These chips are available with optionally one parallel port and up to
860 * two serial ports. Unfortunately they all have the same product id.
862 * Basic configuration is done over a region of 32 I/O ports. The base
863 * ioport is called INTA or INTC, depending on docs/other drivers.
865 * The region of the 32 I/O ports is configured in POSIO0R...
869 #define ITE_887x_MISCR 0x9c
870 #define ITE_887x_INTCBAR 0x78
871 #define ITE_887x_UARTBAR 0x7c
872 #define ITE_887x_PS0BAR 0x10
873 #define ITE_887x_POSIO0 0x60
876 #define ITE_887x_IOSIZE 32
877 /* I/O space size (bits 26-24; 8 bytes = 011b) */
878 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
879 /* I/O space size (bits 26-24; 32 bytes = 101b) */
880 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
881 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
882 #define ITE_887x_POSIO_SPEED (3 << 29)
883 /* enable IO_Space bit */
884 #define ITE_887x_POSIO_ENABLE (1 << 31)
886 static int pci_ite887x_init(struct pci_dev *dev)
888 /* inta_addr are the configuration addresses of the ITE */
889 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
892 struct resource *iobase = NULL;
893 u32 miscr, uartbar, ioport;
895 /* search for the base-ioport */
897 while (inta_addr[i] && iobase == NULL) {
898 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
900 if (iobase != NULL) {
901 /* write POSIO0R - speed | size | ioport */
902 pci_write_config_dword(dev, ITE_887x_POSIO0,
903 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
904 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
905 /* write INTCBAR - ioport */
906 pci_write_config_dword(dev, ITE_887x_INTCBAR,
908 ret = inb(inta_addr[i]);
910 /* ioport connected */
913 release_region(iobase->start, ITE_887x_IOSIZE);
920 dev_err(&dev->dev, "ite887x: could not find iobase\n");
924 /* start of undocumented type checking (see parport_pc.c) */
925 type = inb(iobase->start + 0x18) & 0x0f;
928 case 0x2: /* ITE8871 (1P) */
929 case 0xa: /* ITE8875 (1P) */
932 case 0xe: /* ITE8872 (2S1P) */
935 case 0x6: /* ITE8873 (1S) */
938 case 0x8: /* ITE8874 (2S) */
942 moan_device("Unknown ITE887x", dev);
946 /* configure all serial ports */
947 for (i = 0; i < ret; i++) {
948 /* read the I/O port from the device */
949 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
951 ioport &= 0x0000FF00; /* the actual base address */
952 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
953 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
954 ITE_887x_POSIO_IOSIZE_8 | ioport);
956 /* write the ioport to the UARTBAR */
957 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
958 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
959 uartbar |= (ioport << (16 * i)); /* set the ioport */
960 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
962 /* get current config */
963 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
964 /* disable interrupts (UARTx_Routing[3:0]) */
965 miscr &= ~(0xf << (12 - 4 * i));
966 /* activate the UART (UARTx_En) */
967 miscr |= 1 << (23 - i);
968 /* write new config with activated UART */
969 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
973 /* the device has no UARTs if we get here */
974 release_region(iobase->start, ITE_887x_IOSIZE);
980 static void pci_ite887x_exit(struct pci_dev *dev)
983 /* the ioport is bit 0-15 in POSIO0R */
984 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
986 release_region(ioport, ITE_887x_IOSIZE);
990 * EndRun Technologies.
991 * Determine the number of ports available on the device.
993 #define PCI_VENDOR_ID_ENDRUN 0x7401
994 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
996 static int pci_endrun_init(struct pci_dev *dev)
999 unsigned long deviceID;
1000 unsigned int number_uarts = 0;
1002 /* EndRun device is all 0xexxx */
1003 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1004 (dev->device & 0xf000) != 0xe000)
1007 p = pci_iomap(dev, 0, 5);
1011 deviceID = ioread32(p);
1013 if (deviceID == 0x07000200) {
1014 number_uarts = ioread8(p + 4);
1016 "%d ports detected on EndRun PCI Express device\n",
1019 pci_iounmap(dev, p);
1020 return number_uarts;
1024 * Oxford Semiconductor Inc.
1025 * Check that device is part of the Tornado range of devices, then determine
1026 * the number of ports available on the device.
1028 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1031 unsigned long deviceID;
1032 unsigned int number_uarts = 0;
1034 /* OxSemi Tornado devices are all 0xCxxx */
1035 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1036 (dev->device & 0xF000) != 0xC000)
1039 p = pci_iomap(dev, 0, 5);
1043 deviceID = ioread32(p);
1044 /* Tornado device */
1045 if (deviceID == 0x07000200) {
1046 number_uarts = ioread8(p + 4);
1048 "%d ports detected on Oxford PCI Express device\n",
1051 pci_iounmap(dev, p);
1052 return number_uarts;
1055 static int pci_asix_setup(struct serial_private *priv,
1056 const struct pciserial_board *board,
1057 struct uart_8250_port *port, int idx)
1059 port->bugs |= UART_BUG_PARITY;
1060 return pci_default_setup(priv, board, port, idx);
1063 /* Quatech devices have their own extra interface features */
1065 struct quatech_feature {
1070 #define QPCR_TEST_FOR1 0x3F
1071 #define QPCR_TEST_GET1 0x00
1072 #define QPCR_TEST_FOR2 0x40
1073 #define QPCR_TEST_GET2 0x40
1074 #define QPCR_TEST_FOR3 0x80
1075 #define QPCR_TEST_GET3 0x40
1076 #define QPCR_TEST_FOR4 0xC0
1077 #define QPCR_TEST_GET4 0x80
1079 #define QOPR_CLOCK_X1 0x0000
1080 #define QOPR_CLOCK_X2 0x0001
1081 #define QOPR_CLOCK_X4 0x0002
1082 #define QOPR_CLOCK_X8 0x0003
1083 #define QOPR_CLOCK_RATE_MASK 0x0003
1086 static struct quatech_feature quatech_cards[] = {
1087 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1088 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1089 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1090 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1091 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1092 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1093 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1094 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1096 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1097 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1098 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1099 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1100 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1101 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1102 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1103 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1104 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1105 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1109 static int pci_quatech_amcc(u16 devid)
1111 struct quatech_feature *qf = &quatech_cards[0];
1113 if (qf->devid == devid)
1117 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1121 static int pci_quatech_rqopr(struct uart_8250_port *port)
1123 unsigned long base = port->port.iobase;
1126 LCR = inb(base + UART_LCR);
1127 outb(0xBF, base + UART_LCR);
1128 val = inb(base + UART_SCR);
1129 outb(LCR, base + UART_LCR);
1133 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1135 unsigned long base = port->port.iobase;
1138 LCR = inb(base + UART_LCR);
1139 outb(0xBF, base + UART_LCR);
1140 inb(base + UART_SCR);
1141 outb(qopr, base + UART_SCR);
1142 outb(LCR, base + UART_LCR);
1145 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1147 unsigned long base = port->port.iobase;
1150 LCR = inb(base + UART_LCR);
1151 outb(0xBF, base + UART_LCR);
1152 val = inb(base + UART_SCR);
1153 outb(val | 0x10, base + UART_SCR);
1154 qmcr = inb(base + UART_MCR);
1155 outb(val, base + UART_SCR);
1156 outb(LCR, base + UART_LCR);
1161 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1163 unsigned long base = port->port.iobase;
1166 LCR = inb(base + UART_LCR);
1167 outb(0xBF, base + UART_LCR);
1168 val = inb(base + UART_SCR);
1169 outb(val | 0x10, base + UART_SCR);
1170 outb(qmcr, base + UART_MCR);
1171 outb(val, base + UART_SCR);
1172 outb(LCR, base + UART_LCR);
1175 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1177 unsigned long base = port->port.iobase;
1180 LCR = inb(base + UART_LCR);
1181 outb(0xBF, base + UART_LCR);
1182 val = inb(base + UART_SCR);
1184 outb(0x80, UART_LCR);
1185 if (!(inb(UART_SCR) & 0x20)) {
1186 outb(LCR, base + UART_LCR);
1193 static int pci_quatech_test(struct uart_8250_port *port)
1197 qopr = pci_quatech_rqopr(port);
1198 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1199 reg = pci_quatech_rqopr(port) & 0xC0;
1200 if (reg != QPCR_TEST_GET1)
1202 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1203 reg = pci_quatech_rqopr(port) & 0xC0;
1204 if (reg != QPCR_TEST_GET2)
1206 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1207 reg = pci_quatech_rqopr(port) & 0xC0;
1208 if (reg != QPCR_TEST_GET3)
1210 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1211 reg = pci_quatech_rqopr(port) & 0xC0;
1212 if (reg != QPCR_TEST_GET4)
1215 pci_quatech_wqopr(port, qopr);
1219 static int pci_quatech_clock(struct uart_8250_port *port)
1222 unsigned long clock;
1224 if (pci_quatech_test(port) < 0)
1227 qopr = pci_quatech_rqopr(port);
1229 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1230 reg = pci_quatech_rqopr(port);
1231 if (reg & QOPR_CLOCK_X8) {
1235 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1236 reg = pci_quatech_rqopr(port);
1237 if (!(reg & QOPR_CLOCK_X8)) {
1241 reg &= QOPR_CLOCK_X8;
1242 if (reg == QOPR_CLOCK_X2) {
1244 set = QOPR_CLOCK_X2;
1245 } else if (reg == QOPR_CLOCK_X4) {
1247 set = QOPR_CLOCK_X4;
1248 } else if (reg == QOPR_CLOCK_X8) {
1250 set = QOPR_CLOCK_X8;
1253 set = QOPR_CLOCK_X1;
1255 qopr &= ~QOPR_CLOCK_RATE_MASK;
1259 pci_quatech_wqopr(port, qopr);
1263 static int pci_quatech_rs422(struct uart_8250_port *port)
1268 if (!pci_quatech_has_qmcr(port))
1270 qmcr = pci_quatech_rqmcr(port);
1271 pci_quatech_wqmcr(port, 0xFF);
1272 if (pci_quatech_rqmcr(port))
1274 pci_quatech_wqmcr(port, qmcr);
1278 static int pci_quatech_init(struct pci_dev *dev)
1280 if (pci_quatech_amcc(dev->device)) {
1281 unsigned long base = pci_resource_start(dev, 0);
1285 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1286 tmp = inl(base + 0x3c);
1287 outl(tmp | 0x01000000, base + 0x3c);
1288 outl(tmp &= ~0x01000000, base + 0x3c);
1294 static int pci_quatech_setup(struct serial_private *priv,
1295 const struct pciserial_board *board,
1296 struct uart_8250_port *port, int idx)
1298 /* Needed by pci_quatech calls below */
1299 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1300 /* Set up the clocking */
1301 port->port.uartclk = pci_quatech_clock(port);
1302 /* For now just warn about RS422 */
1303 if (pci_quatech_rs422(port))
1304 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1305 return pci_default_setup(priv, board, port, idx);
1308 static void pci_quatech_exit(struct pci_dev *dev)
1312 static int pci_default_setup(struct serial_private *priv,
1313 const struct pciserial_board *board,
1314 struct uart_8250_port *port, int idx)
1316 unsigned int bar, offset = board->first_offset, maxnr;
1318 bar = FL_GET_BASE(board->flags);
1319 if (board->flags & FL_BASE_BARS)
1322 offset += idx * board->uart_offset;
1324 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1325 (board->reg_shift + 3);
1327 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1330 return setup_port(priv, port, bar, offset, board->reg_shift);
1333 static int pci_pericom_setup(struct serial_private *priv,
1334 const struct pciserial_board *board,
1335 struct uart_8250_port *port, int idx)
1337 unsigned int bar, offset = board->first_offset, maxnr;
1339 bar = FL_GET_BASE(board->flags);
1340 if (board->flags & FL_BASE_BARS)
1343 offset += idx * board->uart_offset;
1348 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1349 (board->reg_shift + 3);
1351 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354 return setup_port(priv, port, bar, offset, board->reg_shift);
1358 ce4100_serial_setup(struct serial_private *priv,
1359 const struct pciserial_board *board,
1360 struct uart_8250_port *port, int idx)
1364 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1365 port->port.iotype = UPIO_MEM32;
1366 port->port.type = PORT_XSCALE;
1367 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1368 port->port.regshift = 2;
1374 pci_omegapci_setup(struct serial_private *priv,
1375 const struct pciserial_board *board,
1376 struct uart_8250_port *port, int idx)
1378 return setup_port(priv, port, 2, idx * 8, 0);
1382 pci_brcm_trumanage_setup(struct serial_private *priv,
1383 const struct pciserial_board *board,
1384 struct uart_8250_port *port, int idx)
1386 int ret = pci_default_setup(priv, board, port, idx);
1388 port->port.type = PORT_BRCM_TRUMANAGE;
1389 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1393 /* RTS will control by MCR if this bit is 0 */
1394 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1395 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1396 #define FINTEK_RTS_INVERT BIT(5)
1398 /* We should do proper H/W transceiver setting before change to RS485 mode */
1399 static int pci_fintek_rs485_config(struct uart_port *port,
1400 struct serial_rs485 *rs485)
1402 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1404 u8 *index = (u8 *) port->private_data;
1406 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1409 rs485 = &port->rs485;
1410 else if (rs485->flags & SER_RS485_ENABLED)
1411 memset(rs485->padding, 0, sizeof(rs485->padding));
1413 memset(rs485, 0, sizeof(*rs485));
1415 /* F81504/508/512 not support RTS delay before or after send */
1416 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1418 if (rs485->flags & SER_RS485_ENABLED) {
1419 /* Enable RTS H/W control mode */
1420 setting |= FINTEK_RTS_CONTROL_BY_HW;
1422 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1423 /* RTS driving high on TX */
1424 setting &= ~FINTEK_RTS_INVERT;
1426 /* RTS driving low on TX */
1427 setting |= FINTEK_RTS_INVERT;
1430 rs485->delay_rts_after_send = 0;
1431 rs485->delay_rts_before_send = 0;
1433 /* Disable RTS H/W control mode */
1434 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1437 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1439 if (rs485 != &port->rs485)
1440 port->rs485 = *rs485;
1445 static int pci_fintek_setup(struct serial_private *priv,
1446 const struct pciserial_board *board,
1447 struct uart_8250_port *port, int idx)
1449 struct pci_dev *pdev = priv->dev;
1454 config_base = 0x40 + 0x08 * idx;
1456 /* Get the io address from configuration space */
1457 pci_read_config_word(pdev, config_base + 4, &iobase);
1459 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1461 port->port.iotype = UPIO_PORT;
1462 port->port.iobase = iobase;
1463 port->port.rs485_config = pci_fintek_rs485_config;
1465 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1469 /* preserve index in PCI configuration space */
1471 port->port.private_data = data;
1476 static int pci_fintek_init(struct pci_dev *dev)
1478 unsigned long iobase;
1480 resource_size_t bar_data[3];
1482 struct serial_private *priv = pci_get_drvdata(dev);
1483 struct uart_8250_port *port;
1485 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1486 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1487 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1490 switch (dev->device) {
1491 case 0x1104: /* 4 ports */
1492 case 0x1108: /* 8 ports */
1493 max_port = dev->device & 0xff;
1495 case 0x1112: /* 12 ports */
1502 /* Get the io address dispatch from the BIOS */
1503 bar_data[0] = pci_resource_start(dev, 5);
1504 bar_data[1] = pci_resource_start(dev, 4);
1505 bar_data[2] = pci_resource_start(dev, 3);
1507 for (i = 0; i < max_port; ++i) {
1508 /* UART0 configuration offset start from 0x40 */
1509 config_base = 0x40 + 0x08 * i;
1511 /* Calculate Real IO Port */
1512 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1514 /* Enable UART I/O port */
1515 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1517 /* Select 128-byte FIFO and 8x FIFO threshold */
1518 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1521 pci_write_config_byte(dev, config_base + 0x04,
1522 (u8)(iobase & 0xff));
1525 pci_write_config_byte(dev, config_base + 0x05,
1526 (u8)((iobase & 0xff00) >> 8));
1528 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1531 /* re-apply RS232/485 mode when
1532 * pciserial_resume_ports()
1534 port = serial8250_get_port(priv->line[i]);
1535 pci_fintek_rs485_config(&port->port, NULL);
1537 /* First init without port data
1538 * force init to RS232 Mode
1540 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1547 static int skip_tx_en_setup(struct serial_private *priv,
1548 const struct pciserial_board *board,
1549 struct uart_8250_port *port, int idx)
1551 port->port.quirks |= UPQ_NO_TXEN_TEST;
1552 dev_dbg(&priv->dev->dev,
1553 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1554 priv->dev->vendor, priv->dev->device,
1555 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1557 return pci_default_setup(priv, board, port, idx);
1560 static void kt_handle_break(struct uart_port *p)
1562 struct uart_8250_port *up = up_to_u8250p(p);
1564 * On receipt of a BI, serial device in Intel ME (Intel
1565 * management engine) needs to have its fifos cleared for sane
1566 * SOL (Serial Over Lan) output.
1568 serial8250_clear_and_reinit_fifos(up);
1571 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1573 struct uart_8250_port *up = up_to_u8250p(p);
1577 * When the Intel ME (management engine) gets reset its serial
1578 * port registers could return 0 momentarily. Functions like
1579 * serial8250_console_write, read and save the IER, perform
1580 * some operation and then restore it. In order to avoid
1581 * setting IER register inadvertently to 0, if the value read
1582 * is 0, double check with ier value in uart_8250_port and use
1583 * that instead. up->ier should be the same value as what is
1584 * currently configured.
1586 val = inb(p->iobase + offset);
1587 if (offset == UART_IER) {
1594 static int kt_serial_setup(struct serial_private *priv,
1595 const struct pciserial_board *board,
1596 struct uart_8250_port *port, int idx)
1598 port->port.flags |= UPF_BUG_THRE;
1599 port->port.serial_in = kt_serial_in;
1600 port->port.handle_break = kt_handle_break;
1601 return skip_tx_en_setup(priv, board, port, idx);
1604 static int pci_eg20t_init(struct pci_dev *dev)
1606 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1614 pci_wch_ch353_setup(struct serial_private *priv,
1615 const struct pciserial_board *board,
1616 struct uart_8250_port *port, int idx)
1618 port->port.flags |= UPF_FIXED_TYPE;
1619 port->port.type = PORT_16550A;
1620 return pci_default_setup(priv, board, port, idx);
1624 pci_wch_ch355_setup(struct serial_private *priv,
1625 const struct pciserial_board *board,
1626 struct uart_8250_port *port, int idx)
1628 port->port.flags |= UPF_FIXED_TYPE;
1629 port->port.type = PORT_16550A;
1630 return pci_default_setup(priv, board, port, idx);
1634 pci_wch_ch38x_setup(struct serial_private *priv,
1635 const struct pciserial_board *board,
1636 struct uart_8250_port *port, int idx)
1638 port->port.flags |= UPF_FIXED_TYPE;
1639 port->port.type = PORT_16850;
1640 return pci_default_setup(priv, board, port, idx);
1643 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1644 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1645 #define PCI_DEVICE_ID_OCTPRO 0x0001
1646 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1647 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1648 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1649 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1650 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1651 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1652 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1653 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1654 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1655 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1656 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1657 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1658 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1659 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1660 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1661 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1662 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1663 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1664 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1665 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1666 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1667 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1668 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1669 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1670 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1671 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1672 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1673 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1674 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1675 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1676 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1677 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1678 #define PCI_VENDOR_ID_WCH 0x4348
1679 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1680 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1681 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1682 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1683 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1684 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1685 #define PCI_VENDOR_ID_AGESTAR 0x5372
1686 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1687 #define PCI_VENDOR_ID_ASIX 0x9710
1688 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1689 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1691 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1692 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1694 #define PCIE_VENDOR_ID_WCH 0x1c00
1695 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1696 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1697 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1699 #define PCI_VENDOR_ID_PERICOM 0x12D8
1700 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1701 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1702 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1703 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1705 #define PCI_VENDOR_ID_ACCESIO 0x494f
1706 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1707 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1708 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1709 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1710 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1711 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1712 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1713 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1714 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1715 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1716 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1717 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1718 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1719 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1720 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1721 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1722 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1723 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1724 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1725 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1726 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1727 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1728 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1729 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1730 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1731 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1732 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1733 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1734 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1735 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1736 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1737 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1738 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1742 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1743 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1744 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1747 * Master list of serial port init/setup/exit quirks.
1748 * This does not describe the general nature of the port.
1749 * (ie, baud base, number and location of ports, etc)
1751 * This list is ordered alphabetically by vendor then device.
1752 * Specific entries must come before more generic entries.
1754 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1756 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1759 .vendor = PCI_VENDOR_ID_AMCC,
1760 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1761 .subvendor = PCI_ANY_ID,
1762 .subdevice = PCI_ANY_ID,
1763 .setup = addidata_apci7800_setup,
1766 * AFAVLAB cards - these may be called via parport_serial
1767 * It is not clear whether this applies to all products.
1770 .vendor = PCI_VENDOR_ID_AFAVLAB,
1771 .device = PCI_ANY_ID,
1772 .subvendor = PCI_ANY_ID,
1773 .subdevice = PCI_ANY_ID,
1774 .setup = afavlab_setup,
1780 .vendor = PCI_VENDOR_ID_HP,
1781 .device = PCI_DEVICE_ID_HP_DIVA,
1782 .subvendor = PCI_ANY_ID,
1783 .subdevice = PCI_ANY_ID,
1784 .init = pci_hp_diva_init,
1785 .setup = pci_hp_diva_setup,
1791 .vendor = PCI_VENDOR_ID_INTEL,
1792 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1793 .subvendor = 0xe4bf,
1794 .subdevice = PCI_ANY_ID,
1795 .init = pci_inteli960ni_init,
1796 .setup = pci_default_setup,
1799 .vendor = PCI_VENDOR_ID_INTEL,
1800 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1801 .subvendor = PCI_ANY_ID,
1802 .subdevice = PCI_ANY_ID,
1803 .setup = skip_tx_en_setup,
1806 .vendor = PCI_VENDOR_ID_INTEL,
1807 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1808 .subvendor = PCI_ANY_ID,
1809 .subdevice = PCI_ANY_ID,
1810 .setup = skip_tx_en_setup,
1813 .vendor = PCI_VENDOR_ID_INTEL,
1814 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1815 .subvendor = PCI_ANY_ID,
1816 .subdevice = PCI_ANY_ID,
1817 .setup = skip_tx_en_setup,
1820 .vendor = PCI_VENDOR_ID_INTEL,
1821 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1822 .subvendor = PCI_ANY_ID,
1823 .subdevice = PCI_ANY_ID,
1824 .setup = ce4100_serial_setup,
1827 .vendor = PCI_VENDOR_ID_INTEL,
1828 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1829 .subvendor = PCI_ANY_ID,
1830 .subdevice = PCI_ANY_ID,
1831 .setup = kt_serial_setup,
1837 .vendor = PCI_VENDOR_ID_ITE,
1838 .device = PCI_DEVICE_ID_ITE_8872,
1839 .subvendor = PCI_ANY_ID,
1840 .subdevice = PCI_ANY_ID,
1841 .init = pci_ite887x_init,
1842 .setup = pci_default_setup,
1843 .exit = pci_ite887x_exit,
1846 * National Instruments
1849 .vendor = PCI_VENDOR_ID_NI,
1850 .device = PCI_DEVICE_ID_NI_PCI23216,
1851 .subvendor = PCI_ANY_ID,
1852 .subdevice = PCI_ANY_ID,
1853 .init = pci_ni8420_init,
1854 .setup = pci_default_setup,
1855 .exit = pci_ni8420_exit,
1858 .vendor = PCI_VENDOR_ID_NI,
1859 .device = PCI_DEVICE_ID_NI_PCI2328,
1860 .subvendor = PCI_ANY_ID,
1861 .subdevice = PCI_ANY_ID,
1862 .init = pci_ni8420_init,
1863 .setup = pci_default_setup,
1864 .exit = pci_ni8420_exit,
1867 .vendor = PCI_VENDOR_ID_NI,
1868 .device = PCI_DEVICE_ID_NI_PCI2324,
1869 .subvendor = PCI_ANY_ID,
1870 .subdevice = PCI_ANY_ID,
1871 .init = pci_ni8420_init,
1872 .setup = pci_default_setup,
1873 .exit = pci_ni8420_exit,
1876 .vendor = PCI_VENDOR_ID_NI,
1877 .device = PCI_DEVICE_ID_NI_PCI2322,
1878 .subvendor = PCI_ANY_ID,
1879 .subdevice = PCI_ANY_ID,
1880 .init = pci_ni8420_init,
1881 .setup = pci_default_setup,
1882 .exit = pci_ni8420_exit,
1885 .vendor = PCI_VENDOR_ID_NI,
1886 .device = PCI_DEVICE_ID_NI_PCI2324I,
1887 .subvendor = PCI_ANY_ID,
1888 .subdevice = PCI_ANY_ID,
1889 .init = pci_ni8420_init,
1890 .setup = pci_default_setup,
1891 .exit = pci_ni8420_exit,
1894 .vendor = PCI_VENDOR_ID_NI,
1895 .device = PCI_DEVICE_ID_NI_PCI2322I,
1896 .subvendor = PCI_ANY_ID,
1897 .subdevice = PCI_ANY_ID,
1898 .init = pci_ni8420_init,
1899 .setup = pci_default_setup,
1900 .exit = pci_ni8420_exit,
1903 .vendor = PCI_VENDOR_ID_NI,
1904 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1905 .subvendor = PCI_ANY_ID,
1906 .subdevice = PCI_ANY_ID,
1907 .init = pci_ni8420_init,
1908 .setup = pci_default_setup,
1909 .exit = pci_ni8420_exit,
1912 .vendor = PCI_VENDOR_ID_NI,
1913 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1914 .subvendor = PCI_ANY_ID,
1915 .subdevice = PCI_ANY_ID,
1916 .init = pci_ni8420_init,
1917 .setup = pci_default_setup,
1918 .exit = pci_ni8420_exit,
1921 .vendor = PCI_VENDOR_ID_NI,
1922 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1923 .subvendor = PCI_ANY_ID,
1924 .subdevice = PCI_ANY_ID,
1925 .init = pci_ni8420_init,
1926 .setup = pci_default_setup,
1927 .exit = pci_ni8420_exit,
1930 .vendor = PCI_VENDOR_ID_NI,
1931 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1932 .subvendor = PCI_ANY_ID,
1933 .subdevice = PCI_ANY_ID,
1934 .init = pci_ni8420_init,
1935 .setup = pci_default_setup,
1936 .exit = pci_ni8420_exit,
1939 .vendor = PCI_VENDOR_ID_NI,
1940 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1941 .subvendor = PCI_ANY_ID,
1942 .subdevice = PCI_ANY_ID,
1943 .init = pci_ni8420_init,
1944 .setup = pci_default_setup,
1945 .exit = pci_ni8420_exit,
1948 .vendor = PCI_VENDOR_ID_NI,
1949 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1950 .subvendor = PCI_ANY_ID,
1951 .subdevice = PCI_ANY_ID,
1952 .init = pci_ni8420_init,
1953 .setup = pci_default_setup,
1954 .exit = pci_ni8420_exit,
1957 .vendor = PCI_VENDOR_ID_NI,
1958 .device = PCI_ANY_ID,
1959 .subvendor = PCI_ANY_ID,
1960 .subdevice = PCI_ANY_ID,
1961 .init = pci_ni8430_init,
1962 .setup = pci_ni8430_setup,
1963 .exit = pci_ni8430_exit,
1967 .vendor = PCI_VENDOR_ID_QUATECH,
1968 .device = PCI_ANY_ID,
1969 .subvendor = PCI_ANY_ID,
1970 .subdevice = PCI_ANY_ID,
1971 .init = pci_quatech_init,
1972 .setup = pci_quatech_setup,
1973 .exit = pci_quatech_exit,
1979 .vendor = PCI_VENDOR_ID_PANACOM,
1980 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1981 .subvendor = PCI_ANY_ID,
1982 .subdevice = PCI_ANY_ID,
1983 .init = pci_plx9050_init,
1984 .setup = pci_default_setup,
1985 .exit = pci_plx9050_exit,
1988 .vendor = PCI_VENDOR_ID_PANACOM,
1989 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1990 .subvendor = PCI_ANY_ID,
1991 .subdevice = PCI_ANY_ID,
1992 .init = pci_plx9050_init,
1993 .setup = pci_default_setup,
1994 .exit = pci_plx9050_exit,
1997 * Pericom (Only 7954 - It have a offset jump for port 4)
2000 .vendor = PCI_VENDOR_ID_PERICOM,
2001 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2002 .subvendor = PCI_ANY_ID,
2003 .subdevice = PCI_ANY_ID,
2004 .setup = pci_pericom_setup,
2010 .vendor = PCI_VENDOR_ID_PLX,
2011 .device = PCI_DEVICE_ID_PLX_9050,
2012 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2013 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2014 .init = pci_plx9050_init,
2015 .setup = pci_default_setup,
2016 .exit = pci_plx9050_exit,
2019 .vendor = PCI_VENDOR_ID_PLX,
2020 .device = PCI_DEVICE_ID_PLX_9050,
2021 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2022 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2023 .init = pci_plx9050_init,
2024 .setup = pci_default_setup,
2025 .exit = pci_plx9050_exit,
2028 .vendor = PCI_VENDOR_ID_PLX,
2029 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2030 .subvendor = PCI_VENDOR_ID_PLX,
2031 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2032 .init = pci_plx9050_init,
2033 .setup = pci_default_setup,
2034 .exit = pci_plx9050_exit,
2037 .vendor = PCI_VENDOR_ID_ACCESIO,
2038 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2039 .subvendor = PCI_ANY_ID,
2040 .subdevice = PCI_ANY_ID,
2041 .setup = pci_pericom_setup,
2044 .vendor = PCI_VENDOR_ID_ACCESIO,
2045 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2046 .subvendor = PCI_ANY_ID,
2047 .subdevice = PCI_ANY_ID,
2048 .setup = pci_pericom_setup,
2051 .vendor = PCI_VENDOR_ID_ACCESIO,
2052 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2053 .subvendor = PCI_ANY_ID,
2054 .subdevice = PCI_ANY_ID,
2055 .setup = pci_pericom_setup,
2058 .vendor = PCI_VENDOR_ID_ACCESIO,
2059 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2060 .subvendor = PCI_ANY_ID,
2061 .subdevice = PCI_ANY_ID,
2062 .setup = pci_pericom_setup,
2065 .vendor = PCI_VENDOR_ID_ACCESIO,
2066 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2067 .subvendor = PCI_ANY_ID,
2068 .subdevice = PCI_ANY_ID,
2069 .setup = pci_pericom_setup,
2072 .vendor = PCI_VENDOR_ID_ACCESIO,
2073 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2074 .subvendor = PCI_ANY_ID,
2075 .subdevice = PCI_ANY_ID,
2076 .setup = pci_pericom_setup,
2079 .vendor = PCI_VENDOR_ID_ACCESIO,
2080 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2081 .subvendor = PCI_ANY_ID,
2082 .subdevice = PCI_ANY_ID,
2083 .setup = pci_pericom_setup,
2086 .vendor = PCI_VENDOR_ID_ACCESIO,
2087 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2088 .subvendor = PCI_ANY_ID,
2089 .subdevice = PCI_ANY_ID,
2090 .setup = pci_pericom_setup,
2093 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2094 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2095 .subvendor = PCI_ANY_ID,
2096 .subdevice = PCI_ANY_ID,
2097 .setup = pci_pericom_setup,
2100 .vendor = PCI_VENDOR_ID_ACCESIO,
2101 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2102 .subvendor = PCI_ANY_ID,
2103 .subdevice = PCI_ANY_ID,
2104 .setup = pci_pericom_setup,
2107 .vendor = PCI_VENDOR_ID_ACCESIO,
2108 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2109 .subvendor = PCI_ANY_ID,
2110 .subdevice = PCI_ANY_ID,
2111 .setup = pci_pericom_setup,
2114 .vendor = PCI_VENDOR_ID_ACCESIO,
2115 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2116 .subvendor = PCI_ANY_ID,
2117 .subdevice = PCI_ANY_ID,
2118 .setup = pci_pericom_setup,
2121 .vendor = PCI_VENDOR_ID_ACCESIO,
2122 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2123 .subvendor = PCI_ANY_ID,
2124 .subdevice = PCI_ANY_ID,
2125 .setup = pci_pericom_setup,
2128 .vendor = PCI_VENDOR_ID_ACCESIO,
2129 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2130 .subvendor = PCI_ANY_ID,
2131 .subdevice = PCI_ANY_ID,
2132 .setup = pci_pericom_setup,
2135 .vendor = PCI_VENDOR_ID_ACCESIO,
2136 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2137 .subvendor = PCI_ANY_ID,
2138 .subdevice = PCI_ANY_ID,
2139 .setup = pci_pericom_setup,
2142 * SBS Technologies, Inc., PMC-OCTALPRO 232
2145 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2146 .device = PCI_DEVICE_ID_OCTPRO,
2147 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2148 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2154 * SBS Technologies, Inc., PMC-OCTALPRO 422
2157 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2158 .device = PCI_DEVICE_ID_OCTPRO,
2159 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2160 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2166 * SBS Technologies, Inc., P-Octal 232
2169 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2170 .device = PCI_DEVICE_ID_OCTPRO,
2171 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2172 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2178 * SBS Technologies, Inc., P-Octal 422
2181 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2182 .device = PCI_DEVICE_ID_OCTPRO,
2183 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2184 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2190 * SIIG cards - these may be called via parport_serial
2193 .vendor = PCI_VENDOR_ID_SIIG,
2194 .device = PCI_ANY_ID,
2195 .subvendor = PCI_ANY_ID,
2196 .subdevice = PCI_ANY_ID,
2197 .init = pci_siig_init,
2198 .setup = pci_siig_setup,
2204 .vendor = PCI_VENDOR_ID_TITAN,
2205 .device = PCI_DEVICE_ID_TITAN_400L,
2206 .subvendor = PCI_ANY_ID,
2207 .subdevice = PCI_ANY_ID,
2208 .setup = titan_400l_800l_setup,
2211 .vendor = PCI_VENDOR_ID_TITAN,
2212 .device = PCI_DEVICE_ID_TITAN_800L,
2213 .subvendor = PCI_ANY_ID,
2214 .subdevice = PCI_ANY_ID,
2215 .setup = titan_400l_800l_setup,
2221 .vendor = PCI_VENDOR_ID_TIMEDIA,
2222 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2223 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2224 .subdevice = PCI_ANY_ID,
2225 .probe = pci_timedia_probe,
2226 .init = pci_timedia_init,
2227 .setup = pci_timedia_setup,
2230 .vendor = PCI_VENDOR_ID_TIMEDIA,
2231 .device = PCI_ANY_ID,
2232 .subvendor = PCI_ANY_ID,
2233 .subdevice = PCI_ANY_ID,
2234 .setup = pci_timedia_setup,
2237 * SUNIX (Timedia) cards
2238 * Do not "probe" for these cards as there is at least one combination
2239 * card that should be handled by parport_pc that doesn't match the
2240 * rule in pci_timedia_probe.
2241 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2242 * There are some boards with part number SER5037AL that report
2243 * subdevice ID 0x0002.
2246 .vendor = PCI_VENDOR_ID_SUNIX,
2247 .device = PCI_DEVICE_ID_SUNIX_1999,
2248 .subvendor = PCI_VENDOR_ID_SUNIX,
2249 .subdevice = PCI_ANY_ID,
2250 .init = pci_timedia_init,
2251 .setup = pci_timedia_setup,
2257 .vendor = PCI_VENDOR_ID_XIRCOM,
2258 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2259 .subvendor = PCI_ANY_ID,
2260 .subdevice = PCI_ANY_ID,
2261 .init = pci_xircom_init,
2262 .setup = pci_default_setup,
2265 * Netmos cards - these may be called via parport_serial
2268 .vendor = PCI_VENDOR_ID_NETMOS,
2269 .device = PCI_ANY_ID,
2270 .subvendor = PCI_ANY_ID,
2271 .subdevice = PCI_ANY_ID,
2272 .init = pci_netmos_init,
2273 .setup = pci_netmos_9900_setup,
2276 * EndRun Technologies
2279 .vendor = PCI_VENDOR_ID_ENDRUN,
2280 .device = PCI_ANY_ID,
2281 .subvendor = PCI_ANY_ID,
2282 .subdevice = PCI_ANY_ID,
2283 .init = pci_endrun_init,
2284 .setup = pci_default_setup,
2287 * For Oxford Semiconductor Tornado based devices
2290 .vendor = PCI_VENDOR_ID_OXSEMI,
2291 .device = PCI_ANY_ID,
2292 .subvendor = PCI_ANY_ID,
2293 .subdevice = PCI_ANY_ID,
2294 .init = pci_oxsemi_tornado_init,
2295 .setup = pci_default_setup,
2298 .vendor = PCI_VENDOR_ID_MAINPINE,
2299 .device = PCI_ANY_ID,
2300 .subvendor = PCI_ANY_ID,
2301 .subdevice = PCI_ANY_ID,
2302 .init = pci_oxsemi_tornado_init,
2303 .setup = pci_default_setup,
2306 .vendor = PCI_VENDOR_ID_DIGI,
2307 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2308 .subvendor = PCI_SUBVENDOR_ID_IBM,
2309 .subdevice = PCI_ANY_ID,
2310 .init = pci_oxsemi_tornado_init,
2311 .setup = pci_default_setup,
2314 .vendor = PCI_VENDOR_ID_INTEL,
2316 .subvendor = PCI_ANY_ID,
2317 .subdevice = PCI_ANY_ID,
2318 .init = pci_eg20t_init,
2319 .setup = pci_default_setup,
2322 .vendor = PCI_VENDOR_ID_INTEL,
2324 .subvendor = PCI_ANY_ID,
2325 .subdevice = PCI_ANY_ID,
2326 .init = pci_eg20t_init,
2327 .setup = pci_default_setup,
2330 .vendor = PCI_VENDOR_ID_INTEL,
2332 .subvendor = PCI_ANY_ID,
2333 .subdevice = PCI_ANY_ID,
2334 .init = pci_eg20t_init,
2335 .setup = pci_default_setup,
2338 .vendor = PCI_VENDOR_ID_INTEL,
2340 .subvendor = PCI_ANY_ID,
2341 .subdevice = PCI_ANY_ID,
2342 .init = pci_eg20t_init,
2343 .setup = pci_default_setup,
2348 .subvendor = PCI_ANY_ID,
2349 .subdevice = PCI_ANY_ID,
2350 .init = pci_eg20t_init,
2351 .setup = pci_default_setup,
2356 .subvendor = PCI_ANY_ID,
2357 .subdevice = PCI_ANY_ID,
2358 .init = pci_eg20t_init,
2359 .setup = pci_default_setup,
2364 .subvendor = PCI_ANY_ID,
2365 .subdevice = PCI_ANY_ID,
2366 .init = pci_eg20t_init,
2367 .setup = pci_default_setup,
2372 .subvendor = PCI_ANY_ID,
2373 .subdevice = PCI_ANY_ID,
2374 .init = pci_eg20t_init,
2375 .setup = pci_default_setup,
2380 .subvendor = PCI_ANY_ID,
2381 .subdevice = PCI_ANY_ID,
2382 .init = pci_eg20t_init,
2383 .setup = pci_default_setup,
2386 * Cronyx Omega PCI (PLX-chip based)
2389 .vendor = PCI_VENDOR_ID_PLX,
2390 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2391 .subvendor = PCI_ANY_ID,
2392 .subdevice = PCI_ANY_ID,
2393 .setup = pci_omegapci_setup,
2395 /* WCH CH353 1S1P card (16550 clone) */
2397 .vendor = PCI_VENDOR_ID_WCH,
2398 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2399 .subvendor = PCI_ANY_ID,
2400 .subdevice = PCI_ANY_ID,
2401 .setup = pci_wch_ch353_setup,
2403 /* WCH CH353 2S1P card (16550 clone) */
2405 .vendor = PCI_VENDOR_ID_WCH,
2406 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2407 .subvendor = PCI_ANY_ID,
2408 .subdevice = PCI_ANY_ID,
2409 .setup = pci_wch_ch353_setup,
2411 /* WCH CH353 4S card (16550 clone) */
2413 .vendor = PCI_VENDOR_ID_WCH,
2414 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2415 .subvendor = PCI_ANY_ID,
2416 .subdevice = PCI_ANY_ID,
2417 .setup = pci_wch_ch353_setup,
2419 /* WCH CH353 2S1PF card (16550 clone) */
2421 .vendor = PCI_VENDOR_ID_WCH,
2422 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2423 .subvendor = PCI_ANY_ID,
2424 .subdevice = PCI_ANY_ID,
2425 .setup = pci_wch_ch353_setup,
2427 /* WCH CH352 2S card (16550 clone) */
2429 .vendor = PCI_VENDOR_ID_WCH,
2430 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2431 .subvendor = PCI_ANY_ID,
2432 .subdevice = PCI_ANY_ID,
2433 .setup = pci_wch_ch353_setup,
2435 /* WCH CH355 4S card (16550 clone) */
2437 .vendor = PCI_VENDOR_ID_WCH,
2438 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2439 .subvendor = PCI_ANY_ID,
2440 .subdevice = PCI_ANY_ID,
2441 .setup = pci_wch_ch355_setup,
2443 /* WCH CH382 2S card (16850 clone) */
2445 .vendor = PCIE_VENDOR_ID_WCH,
2446 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2447 .subvendor = PCI_ANY_ID,
2448 .subdevice = PCI_ANY_ID,
2449 .setup = pci_wch_ch38x_setup,
2451 /* WCH CH382 2S1P card (16850 clone) */
2453 .vendor = PCIE_VENDOR_ID_WCH,
2454 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2455 .subvendor = PCI_ANY_ID,
2456 .subdevice = PCI_ANY_ID,
2457 .setup = pci_wch_ch38x_setup,
2459 /* WCH CH384 4S card (16850 clone) */
2461 .vendor = PCIE_VENDOR_ID_WCH,
2462 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2463 .subvendor = PCI_ANY_ID,
2464 .subdevice = PCI_ANY_ID,
2465 .setup = pci_wch_ch38x_setup,
2468 * ASIX devices with FIFO bug
2471 .vendor = PCI_VENDOR_ID_ASIX,
2472 .device = PCI_ANY_ID,
2473 .subvendor = PCI_ANY_ID,
2474 .subdevice = PCI_ANY_ID,
2475 .setup = pci_asix_setup,
2478 * Broadcom TruManage (NetXtreme)
2481 .vendor = PCI_VENDOR_ID_BROADCOM,
2482 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2483 .subvendor = PCI_ANY_ID,
2484 .subdevice = PCI_ANY_ID,
2485 .setup = pci_brcm_trumanage_setup,
2490 .subvendor = PCI_ANY_ID,
2491 .subdevice = PCI_ANY_ID,
2492 .setup = pci_fintek_setup,
2493 .init = pci_fintek_init,
2498 .subvendor = PCI_ANY_ID,
2499 .subdevice = PCI_ANY_ID,
2500 .setup = pci_fintek_setup,
2501 .init = pci_fintek_init,
2506 .subvendor = PCI_ANY_ID,
2507 .subdevice = PCI_ANY_ID,
2508 .setup = pci_fintek_setup,
2509 .init = pci_fintek_init,
2513 * Default "match everything" terminator entry
2516 .vendor = PCI_ANY_ID,
2517 .device = PCI_ANY_ID,
2518 .subvendor = PCI_ANY_ID,
2519 .subdevice = PCI_ANY_ID,
2520 .setup = pci_default_setup,
2524 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2526 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2529 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2531 struct pci_serial_quirk *quirk;
2533 for (quirk = pci_serial_quirks; ; quirk++)
2534 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2535 quirk_id_matches(quirk->device, dev->device) &&
2536 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2537 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2542 static inline int get_pci_irq(struct pci_dev *dev,
2543 const struct pciserial_board *board)
2545 if (board->flags & FL_NOIRQ)
2552 * This is the configuration table for all of the PCI serial boards
2553 * which we support. It is directly indexed by the pci_board_num_t enum
2554 * value, which is encoded in the pci_device_id PCI probe table's
2555 * driver_data member.
2557 * The makeup of these names are:
2558 * pbn_bn{_bt}_n_baud{_offsetinhex}
2560 * bn = PCI BAR number
2561 * bt = Index using PCI BARs
2562 * n = number of serial ports
2564 * offsetinhex = offset for each sequential port (in hex)
2566 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2568 * Please note: in theory if n = 1, _bt infix should make no difference.
2569 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2571 enum pci_board_num_t {
2665 * Board-specific versions.
2671 pbn_endrun_2_4000000,
2673 pbn_oxsemi_1_4000000,
2674 pbn_oxsemi_2_4000000,
2675 pbn_oxsemi_4_4000000,
2676 pbn_oxsemi_8_4000000,
2688 pbn_ADDIDATA_PCIe_1_3906250,
2689 pbn_ADDIDATA_PCIe_2_3906250,
2690 pbn_ADDIDATA_PCIe_4_3906250,
2691 pbn_ADDIDATA_PCIe_8_3906250,
2692 pbn_ce4100_1_115200,
2694 pbn_NETMOS9900_2s_115200,
2701 pbn_pericom_PI7C9X7951,
2702 pbn_pericom_PI7C9X7952,
2703 pbn_pericom_PI7C9X7954,
2704 pbn_pericom_PI7C9X7958,
2708 * uart_offset - the space between channels
2709 * reg_shift - describes how the UART registers are mapped
2710 * to PCI memory by the card.
2711 * For example IER register on SBS, Inc. PMC-OctPro is located at
2712 * offset 0x10 from the UART base, while UART_IER is defined as 1
2713 * in include/linux/serial_reg.h,
2714 * see first lines of serial_in() and serial_out() in 8250.c
2717 static struct pciserial_board pci_boards[] = {
2721 .base_baud = 115200,
2724 [pbn_b0_1_115200] = {
2727 .base_baud = 115200,
2730 [pbn_b0_2_115200] = {
2733 .base_baud = 115200,
2736 [pbn_b0_4_115200] = {
2739 .base_baud = 115200,
2742 [pbn_b0_5_115200] = {
2745 .base_baud = 115200,
2748 [pbn_b0_8_115200] = {
2751 .base_baud = 115200,
2754 [pbn_b0_1_921600] = {
2757 .base_baud = 921600,
2760 [pbn_b0_2_921600] = {
2763 .base_baud = 921600,
2766 [pbn_b0_4_921600] = {
2769 .base_baud = 921600,
2773 [pbn_b0_2_1130000] = {
2776 .base_baud = 1130000,
2780 [pbn_b0_4_1152000] = {
2783 .base_baud = 1152000,
2787 [pbn_b0_4_1250000] = {
2790 .base_baud = 1250000,
2794 [pbn_b0_2_1843200] = {
2797 .base_baud = 1843200,
2800 [pbn_b0_4_1843200] = {
2803 .base_baud = 1843200,
2807 [pbn_b0_1_4000000] = {
2810 .base_baud = 4000000,
2814 [pbn_b0_bt_1_115200] = {
2815 .flags = FL_BASE0|FL_BASE_BARS,
2817 .base_baud = 115200,
2820 [pbn_b0_bt_2_115200] = {
2821 .flags = FL_BASE0|FL_BASE_BARS,
2823 .base_baud = 115200,
2826 [pbn_b0_bt_4_115200] = {
2827 .flags = FL_BASE0|FL_BASE_BARS,
2829 .base_baud = 115200,
2832 [pbn_b0_bt_8_115200] = {
2833 .flags = FL_BASE0|FL_BASE_BARS,
2835 .base_baud = 115200,
2839 [pbn_b0_bt_1_460800] = {
2840 .flags = FL_BASE0|FL_BASE_BARS,
2842 .base_baud = 460800,
2845 [pbn_b0_bt_2_460800] = {
2846 .flags = FL_BASE0|FL_BASE_BARS,
2848 .base_baud = 460800,
2851 [pbn_b0_bt_4_460800] = {
2852 .flags = FL_BASE0|FL_BASE_BARS,
2854 .base_baud = 460800,
2858 [pbn_b0_bt_1_921600] = {
2859 .flags = FL_BASE0|FL_BASE_BARS,
2861 .base_baud = 921600,
2864 [pbn_b0_bt_2_921600] = {
2865 .flags = FL_BASE0|FL_BASE_BARS,
2867 .base_baud = 921600,
2870 [pbn_b0_bt_4_921600] = {
2871 .flags = FL_BASE0|FL_BASE_BARS,
2873 .base_baud = 921600,
2876 [pbn_b0_bt_8_921600] = {
2877 .flags = FL_BASE0|FL_BASE_BARS,
2879 .base_baud = 921600,
2883 [pbn_b1_1_115200] = {
2886 .base_baud = 115200,
2889 [pbn_b1_2_115200] = {
2892 .base_baud = 115200,
2895 [pbn_b1_4_115200] = {
2898 .base_baud = 115200,
2901 [pbn_b1_8_115200] = {
2904 .base_baud = 115200,
2907 [pbn_b1_16_115200] = {
2910 .base_baud = 115200,
2914 [pbn_b1_1_921600] = {
2917 .base_baud = 921600,
2920 [pbn_b1_2_921600] = {
2923 .base_baud = 921600,
2926 [pbn_b1_4_921600] = {
2929 .base_baud = 921600,
2932 [pbn_b1_8_921600] = {
2935 .base_baud = 921600,
2938 [pbn_b1_2_1250000] = {
2941 .base_baud = 1250000,
2945 [pbn_b1_bt_1_115200] = {
2946 .flags = FL_BASE1|FL_BASE_BARS,
2948 .base_baud = 115200,
2951 [pbn_b1_bt_2_115200] = {
2952 .flags = FL_BASE1|FL_BASE_BARS,
2954 .base_baud = 115200,
2957 [pbn_b1_bt_4_115200] = {
2958 .flags = FL_BASE1|FL_BASE_BARS,
2960 .base_baud = 115200,
2964 [pbn_b1_bt_2_921600] = {
2965 .flags = FL_BASE1|FL_BASE_BARS,
2967 .base_baud = 921600,
2971 [pbn_b1_1_1382400] = {
2974 .base_baud = 1382400,
2977 [pbn_b1_2_1382400] = {
2980 .base_baud = 1382400,
2983 [pbn_b1_4_1382400] = {
2986 .base_baud = 1382400,
2989 [pbn_b1_8_1382400] = {
2992 .base_baud = 1382400,
2996 [pbn_b2_1_115200] = {
2999 .base_baud = 115200,
3002 [pbn_b2_2_115200] = {
3005 .base_baud = 115200,
3008 [pbn_b2_4_115200] = {
3011 .base_baud = 115200,
3014 [pbn_b2_8_115200] = {
3017 .base_baud = 115200,
3021 [pbn_b2_1_460800] = {
3024 .base_baud = 460800,
3027 [pbn_b2_4_460800] = {
3030 .base_baud = 460800,
3033 [pbn_b2_8_460800] = {
3036 .base_baud = 460800,
3039 [pbn_b2_16_460800] = {
3042 .base_baud = 460800,
3046 [pbn_b2_1_921600] = {
3049 .base_baud = 921600,
3052 [pbn_b2_4_921600] = {
3055 .base_baud = 921600,
3058 [pbn_b2_8_921600] = {
3061 .base_baud = 921600,
3065 [pbn_b2_8_1152000] = {
3068 .base_baud = 1152000,
3072 [pbn_b2_bt_1_115200] = {
3073 .flags = FL_BASE2|FL_BASE_BARS,
3075 .base_baud = 115200,
3078 [pbn_b2_bt_2_115200] = {
3079 .flags = FL_BASE2|FL_BASE_BARS,
3081 .base_baud = 115200,
3084 [pbn_b2_bt_4_115200] = {
3085 .flags = FL_BASE2|FL_BASE_BARS,
3087 .base_baud = 115200,
3091 [pbn_b2_bt_2_921600] = {
3092 .flags = FL_BASE2|FL_BASE_BARS,
3094 .base_baud = 921600,
3097 [pbn_b2_bt_4_921600] = {
3098 .flags = FL_BASE2|FL_BASE_BARS,
3100 .base_baud = 921600,
3104 [pbn_b3_2_115200] = {
3107 .base_baud = 115200,
3110 [pbn_b3_4_115200] = {
3113 .base_baud = 115200,
3116 [pbn_b3_8_115200] = {
3119 .base_baud = 115200,
3123 [pbn_b4_bt_2_921600] = {
3126 .base_baud = 921600,
3129 [pbn_b4_bt_4_921600] = {
3132 .base_baud = 921600,
3135 [pbn_b4_bt_8_921600] = {
3138 .base_baud = 921600,
3143 * Entries following this are board-specific.
3152 .base_baud = 921600,
3153 .uart_offset = 0x400,
3157 .flags = FL_BASE2|FL_BASE_BARS,
3159 .base_baud = 921600,
3160 .uart_offset = 0x400,
3164 .flags = FL_BASE2|FL_BASE_BARS,
3166 .base_baud = 921600,
3167 .uart_offset = 0x400,
3171 /* I think this entry is broken - the first_offset looks wrong --rmk */
3172 [pbn_plx_romulus] = {
3175 .base_baud = 921600,
3176 .uart_offset = 8 << 2,
3178 .first_offset = 0x03,
3182 * EndRun Technologies
3183 * Uses the size of PCI Base region 0 to
3184 * signal now many ports are available
3185 * 2 port 952 Uart support
3187 [pbn_endrun_2_4000000] = {
3190 .base_baud = 4000000,
3191 .uart_offset = 0x200,
3192 .first_offset = 0x1000,
3196 * This board uses the size of PCI Base region 0 to
3197 * signal now many ports are available
3200 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3202 .base_baud = 115200,
3205 [pbn_oxsemi_1_4000000] = {
3208 .base_baud = 4000000,
3209 .uart_offset = 0x200,
3210 .first_offset = 0x1000,
3212 [pbn_oxsemi_2_4000000] = {
3215 .base_baud = 4000000,
3216 .uart_offset = 0x200,
3217 .first_offset = 0x1000,
3219 [pbn_oxsemi_4_4000000] = {
3222 .base_baud = 4000000,
3223 .uart_offset = 0x200,
3224 .first_offset = 0x1000,
3226 [pbn_oxsemi_8_4000000] = {
3229 .base_baud = 4000000,
3230 .uart_offset = 0x200,
3231 .first_offset = 0x1000,
3236 * EKF addition for i960 Boards form EKF with serial port.
3239 [pbn_intel_i960] = {
3242 .base_baud = 921600,
3243 .uart_offset = 8 << 2,
3245 .first_offset = 0x10000,
3248 .flags = FL_BASE0|FL_NOIRQ,
3250 .base_baud = 458333,
3253 .first_offset = 0x20178,
3257 * Computone - uses IOMEM.
3259 [pbn_computone_4] = {
3262 .base_baud = 921600,
3263 .uart_offset = 0x40,
3265 .first_offset = 0x200,
3267 [pbn_computone_6] = {
3270 .base_baud = 921600,
3271 .uart_offset = 0x40,
3273 .first_offset = 0x200,
3275 [pbn_computone_8] = {
3278 .base_baud = 921600,
3279 .uart_offset = 0x40,
3281 .first_offset = 0x200,
3286 .base_baud = 460800,
3291 * PA Semi PWRficient PA6T-1682M on-chip UART
3293 [pbn_pasemi_1682M] = {
3296 .base_baud = 8333333,
3299 * National Instruments 843x
3304 .base_baud = 3686400,
3305 .uart_offset = 0x10,
3306 .first_offset = 0x800,
3311 .base_baud = 3686400,
3312 .uart_offset = 0x10,
3313 .first_offset = 0x800,
3318 .base_baud = 3686400,
3319 .uart_offset = 0x10,
3320 .first_offset = 0x800,
3325 .base_baud = 3686400,
3326 .uart_offset = 0x10,
3327 .first_offset = 0x800,
3330 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3332 [pbn_ADDIDATA_PCIe_1_3906250] = {
3335 .base_baud = 3906250,
3336 .uart_offset = 0x200,
3337 .first_offset = 0x1000,
3339 [pbn_ADDIDATA_PCIe_2_3906250] = {
3342 .base_baud = 3906250,
3343 .uart_offset = 0x200,
3344 .first_offset = 0x1000,
3346 [pbn_ADDIDATA_PCIe_4_3906250] = {
3349 .base_baud = 3906250,
3350 .uart_offset = 0x200,
3351 .first_offset = 0x1000,
3353 [pbn_ADDIDATA_PCIe_8_3906250] = {
3356 .base_baud = 3906250,
3357 .uart_offset = 0x200,
3358 .first_offset = 0x1000,
3360 [pbn_ce4100_1_115200] = {
3361 .flags = FL_BASE_BARS,
3363 .base_baud = 921600,
3369 .base_baud = 115200,
3370 .uart_offset = 0x200,
3372 [pbn_NETMOS9900_2s_115200] = {
3375 .base_baud = 115200,
3377 [pbn_brcm_trumanage] = {
3381 .base_baud = 115200,
3386 .base_baud = 115200,
3387 .first_offset = 0x40,
3392 .base_baud = 115200,
3393 .first_offset = 0x40,
3398 .base_baud = 115200,
3399 .first_offset = 0x40,
3404 .base_baud = 115200,
3406 .first_offset = 0xC0,
3411 .base_baud = 115200,
3413 .first_offset = 0xC0,
3416 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3418 [pbn_pericom_PI7C9X7951] = {
3421 .base_baud = 921600,
3424 [pbn_pericom_PI7C9X7952] = {
3427 .base_baud = 921600,
3430 [pbn_pericom_PI7C9X7954] = {
3433 .base_baud = 921600,
3436 [pbn_pericom_PI7C9X7958] = {
3439 .base_baud = 921600,
3444 static const struct pci_device_id blacklist[] = {
3446 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3447 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3448 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3450 /* multi-io cards handled by parport_serial */
3451 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3452 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3453 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3455 /* Moxa Smartio MUE boards handled by 8250_moxa */
3456 { PCI_VDEVICE(MOXA, 0x1024), },
3457 { PCI_VDEVICE(MOXA, 0x1025), },
3458 { PCI_VDEVICE(MOXA, 0x1045), },
3459 { PCI_VDEVICE(MOXA, 0x1144), },
3460 { PCI_VDEVICE(MOXA, 0x1160), },
3461 { PCI_VDEVICE(MOXA, 0x1161), },
3462 { PCI_VDEVICE(MOXA, 0x1182), },
3463 { PCI_VDEVICE(MOXA, 0x1183), },
3464 { PCI_VDEVICE(MOXA, 0x1322), },
3465 { PCI_VDEVICE(MOXA, 0x1342), },
3466 { PCI_VDEVICE(MOXA, 0x1381), },
3467 { PCI_VDEVICE(MOXA, 0x1683), },
3469 /* Intel platforms with MID UART */
3470 { PCI_VDEVICE(INTEL, 0x081b), },
3471 { PCI_VDEVICE(INTEL, 0x081c), },
3472 { PCI_VDEVICE(INTEL, 0x081d), },
3473 { PCI_VDEVICE(INTEL, 0x1191), },
3474 { PCI_VDEVICE(INTEL, 0x19d8), },
3476 /* Intel platforms with DesignWare UART */
3477 { PCI_VDEVICE(INTEL, 0x0936), },
3478 { PCI_VDEVICE(INTEL, 0x0f0a), },
3479 { PCI_VDEVICE(INTEL, 0x0f0c), },
3480 { PCI_VDEVICE(INTEL, 0x228a), },
3481 { PCI_VDEVICE(INTEL, 0x228c), },
3482 { PCI_VDEVICE(INTEL, 0x9ce3), },
3483 { PCI_VDEVICE(INTEL, 0x9ce4), },
3486 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3487 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3490 static int serial_pci_is_class_communication(struct pci_dev *dev)
3493 * If it is not a communications device or the programming
3494 * interface is greater than 6, give up.
3496 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3497 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3498 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3499 (dev->class & 0xff) > 6)
3505 static int serial_pci_is_blacklisted(struct pci_dev *dev)
3507 const struct pci_device_id *bldev;
3510 * Do not access blacklisted devices that are known not to
3511 * feature serial ports or are handled by other modules.
3513 for (bldev = blacklist;
3514 bldev < blacklist + ARRAY_SIZE(blacklist);
3516 if (dev->vendor == bldev->vendor &&
3517 dev->device == bldev->device)
3525 * Given a complete unknown PCI device, try to use some heuristics to
3526 * guess what the configuration might be, based on the pitiful PCI
3527 * serial specs. Returns 0 on success, -ENODEV on failure.
3530 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3532 int num_iomem, num_port, first_port = -1, i;
3535 rc = serial_pci_is_class_communication(dev);
3540 * Should we try to make guesses for multiport serial devices later?
3542 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3545 num_iomem = num_port = 0;
3546 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3547 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3549 if (first_port == -1)
3552 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3557 * If there is 1 or 0 iomem regions, and exactly one port,
3558 * use it. We guess the number of ports based on the IO
3561 if (num_iomem <= 1 && num_port == 1) {
3562 board->flags = first_port;
3563 board->num_ports = pci_resource_len(dev, first_port) / 8;
3568 * Now guess if we've got a board which indexes by BARs.
3569 * Each IO BAR should be 8 bytes, and they should follow
3574 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3575 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3576 pci_resource_len(dev, i) == 8 &&
3577 (first_port == -1 || (first_port + num_port) == i)) {
3579 if (first_port == -1)
3585 board->flags = first_port | FL_BASE_BARS;
3586 board->num_ports = num_port;
3594 serial_pci_matches(const struct pciserial_board *board,
3595 const struct pciserial_board *guessed)
3598 board->num_ports == guessed->num_ports &&
3599 board->base_baud == guessed->base_baud &&
3600 board->uart_offset == guessed->uart_offset &&
3601 board->reg_shift == guessed->reg_shift &&
3602 board->first_offset == guessed->first_offset;
3605 struct serial_private *
3606 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3608 struct uart_8250_port uart;
3609 struct serial_private *priv;
3610 struct pci_serial_quirk *quirk;
3611 int rc, nr_ports, i;
3613 nr_ports = board->num_ports;
3616 * Find an init and setup quirks.
3618 quirk = find_quirk(dev);
3621 * Run the new-style initialization function.
3622 * The initialization function returns:
3624 * 0 - use board->num_ports
3625 * >0 - number of ports
3628 rc = quirk->init(dev);
3637 priv = kzalloc(sizeof(struct serial_private) +
3638 sizeof(unsigned int) * nr_ports,
3641 priv = ERR_PTR(-ENOMEM);
3646 priv->quirk = quirk;
3648 memset(&uart, 0, sizeof(uart));
3649 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3650 uart.port.uartclk = board->base_baud * 16;
3651 uart.port.irq = get_pci_irq(dev, board);
3652 uart.port.dev = &dev->dev;
3654 for (i = 0; i < nr_ports; i++) {
3655 if (quirk->setup(priv, board, &uart, i))
3658 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3659 uart.port.iobase, uart.port.irq, uart.port.iotype);
3661 priv->line[i] = serial8250_register_8250_port(&uart);
3662 if (priv->line[i] < 0) {
3664 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3665 uart.port.iobase, uart.port.irq,
3666 uart.port.iotype, priv->line[i]);
3671 priv->board = board;
3680 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3682 static void pciserial_detach_ports(struct serial_private *priv)
3684 struct pci_serial_quirk *quirk;
3687 for (i = 0; i < priv->nr; i++)
3688 serial8250_unregister_port(priv->line[i]);
3691 * Find the exit quirks.
3693 quirk = find_quirk(priv->dev);
3695 quirk->exit(priv->dev);
3698 void pciserial_remove_ports(struct serial_private *priv)
3700 pciserial_detach_ports(priv);
3703 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3705 void pciserial_suspend_ports(struct serial_private *priv)
3709 for (i = 0; i < priv->nr; i++)
3710 if (priv->line[i] >= 0)
3711 serial8250_suspend_port(priv->line[i]);
3714 * Ensure that every init quirk is properly torn down
3716 if (priv->quirk->exit)
3717 priv->quirk->exit(priv->dev);
3719 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3721 void pciserial_resume_ports(struct serial_private *priv)
3726 * Ensure that the board is correctly configured.
3728 if (priv->quirk->init)
3729 priv->quirk->init(priv->dev);
3731 for (i = 0; i < priv->nr; i++)
3732 if (priv->line[i] >= 0)
3733 serial8250_resume_port(priv->line[i]);
3735 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3738 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3739 * to the arrangement of serial ports on a PCI card.
3742 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3744 struct pci_serial_quirk *quirk;
3745 struct serial_private *priv;
3746 const struct pciserial_board *board;
3747 struct pciserial_board tmp;
3750 quirk = find_quirk(dev);
3752 rc = quirk->probe(dev);
3757 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3758 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3763 board = &pci_boards[ent->driver_data];
3765 rc = serial_pci_is_blacklisted(dev);
3769 rc = pcim_enable_device(dev);
3770 pci_save_state(dev);
3774 if (ent->driver_data == pbn_default) {
3776 * Use a copy of the pci_board entry for this;
3777 * avoid changing entries in the table.
3779 memcpy(&tmp, board, sizeof(struct pciserial_board));
3783 * We matched one of our class entries. Try to
3784 * determine the parameters of this board.
3786 rc = serial_pci_guess_board(dev, &tmp);
3791 * We matched an explicit entry. If we are able to
3792 * detect this boards settings with our heuristic,
3793 * then we no longer need this entry.
3795 memcpy(&tmp, &pci_boards[pbn_default],
3796 sizeof(struct pciserial_board));
3797 rc = serial_pci_guess_board(dev, &tmp);
3798 if (rc == 0 && serial_pci_matches(board, &tmp))
3799 moan_device("Redundant entry in serial pci_table.",
3803 priv = pciserial_init_ports(dev, board);
3805 return PTR_ERR(priv);
3807 pci_set_drvdata(dev, priv);
3811 static void pciserial_remove_one(struct pci_dev *dev)
3813 struct serial_private *priv = pci_get_drvdata(dev);
3815 pciserial_remove_ports(priv);
3818 #ifdef CONFIG_PM_SLEEP
3819 static int pciserial_suspend_one(struct device *dev)
3821 struct pci_dev *pdev = to_pci_dev(dev);
3822 struct serial_private *priv = pci_get_drvdata(pdev);
3825 pciserial_suspend_ports(priv);
3830 static int pciserial_resume_one(struct device *dev)
3832 struct pci_dev *pdev = to_pci_dev(dev);
3833 struct serial_private *priv = pci_get_drvdata(pdev);
3838 * The device may have been disabled. Re-enable it.
3840 err = pci_enable_device(pdev);
3841 /* FIXME: We cannot simply error out here */
3843 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
3844 pciserial_resume_ports(priv);
3850 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
3851 pciserial_resume_one);
3853 static const struct pci_device_id serial_pci_tbl[] = {
3854 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3855 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3856 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3858 /* Advantech also use 0x3618 and 0xf618 */
3859 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3860 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3862 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3863 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3865 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3866 PCI_SUBVENDOR_ID_CONNECT_TECH,
3867 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3869 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3870 PCI_SUBVENDOR_ID_CONNECT_TECH,
3871 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3873 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3874 PCI_SUBVENDOR_ID_CONNECT_TECH,
3875 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3877 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3878 PCI_SUBVENDOR_ID_CONNECT_TECH,
3879 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3881 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3882 PCI_SUBVENDOR_ID_CONNECT_TECH,
3883 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3885 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3886 PCI_SUBVENDOR_ID_CONNECT_TECH,
3887 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3889 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3890 PCI_SUBVENDOR_ID_CONNECT_TECH,
3891 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3893 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3894 PCI_SUBVENDOR_ID_CONNECT_TECH,
3895 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3897 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3898 PCI_SUBVENDOR_ID_CONNECT_TECH,
3899 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3901 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3902 PCI_SUBVENDOR_ID_CONNECT_TECH,
3903 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3905 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3906 PCI_SUBVENDOR_ID_CONNECT_TECH,
3907 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3909 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3910 PCI_SUBVENDOR_ID_CONNECT_TECH,
3911 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3913 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3914 PCI_SUBVENDOR_ID_CONNECT_TECH,
3915 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3917 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3918 PCI_SUBVENDOR_ID_CONNECT_TECH,
3919 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3921 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3922 PCI_SUBVENDOR_ID_CONNECT_TECH,
3923 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3925 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3926 PCI_SUBVENDOR_ID_CONNECT_TECH,
3927 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3929 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3930 PCI_SUBVENDOR_ID_CONNECT_TECH,
3931 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3933 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3934 PCI_VENDOR_ID_AFAVLAB,
3935 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3937 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3939 pbn_b2_bt_1_115200 },
3940 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3942 pbn_b2_bt_2_115200 },
3943 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3945 pbn_b2_bt_4_115200 },
3946 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3948 pbn_b2_bt_2_115200 },
3949 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3951 pbn_b2_bt_4_115200 },
3952 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3955 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3964 pbn_b2_bt_2_115200 },
3965 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3967 pbn_b2_bt_2_921600 },
3969 * VScom SPCOM800, from sl@s.pl
3971 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3977 /* Unknown card - subdevice 0x1584 */
3978 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3980 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3982 /* Unknown card - subdevice 0x1588 */
3983 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3985 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3987 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3988 PCI_SUBVENDOR_ID_KEYSPAN,
3989 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3991 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3994 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3997 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3998 PCI_VENDOR_ID_ESDGMBH,
3999 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4001 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4002 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4003 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4005 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4006 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4007 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4009 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4010 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4011 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4013 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4014 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4015 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4017 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4018 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4019 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4021 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4022 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4023 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4025 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4026 PCI_SUBVENDOR_ID_EXSYS,
4027 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4030 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4033 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4034 0x10b5, 0x106a, 0, 0,
4037 * EndRun Technologies. PCI express device range.
4038 * EndRun PTP/1588 has 2 Native UARTs.
4040 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4042 pbn_endrun_2_4000000 },
4044 * Quatech cards. These actually have configurable clocks but for
4045 * now we just use the default.
4047 * 100 series are RS232, 200 series RS422,
4049 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4052 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4055 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4058 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4061 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4064 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4067 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4070 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4073 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4076 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4079 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4082 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4085 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4088 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4091 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4097 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4100 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4103 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4107 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4108 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4111 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4112 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4115 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4117 pbn_b0_bt_2_921600 },
4120 * The below card is a little controversial since it is the
4121 * subject of a PCI vendor/device ID clash. (See
4122 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4123 * For now just used the hex ID 0x950a.
4125 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4126 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4127 0, 0, pbn_b0_2_115200 },
4128 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4129 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4130 0, 0, pbn_b0_2_115200 },
4131 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4135 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4137 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4142 pbn_b0_bt_2_921600 },
4143 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4148 * Oxford Semiconductor Inc. Tornado PCI express device range.
4150 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4153 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4156 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4158 pbn_oxsemi_1_4000000 },
4159 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 pbn_oxsemi_1_4000000 },
4162 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4165 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4168 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 pbn_oxsemi_1_4000000 },
4171 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4173 pbn_oxsemi_1_4000000 },
4174 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4177 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4180 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4183 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4186 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4188 pbn_oxsemi_2_4000000 },
4189 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4191 pbn_oxsemi_2_4000000 },
4192 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4194 pbn_oxsemi_4_4000000 },
4195 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4197 pbn_oxsemi_4_4000000 },
4198 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4200 pbn_oxsemi_8_4000000 },
4201 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4203 pbn_oxsemi_8_4000000 },
4204 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4206 pbn_oxsemi_1_4000000 },
4207 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4209 pbn_oxsemi_1_4000000 },
4210 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4212 pbn_oxsemi_1_4000000 },
4213 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4215 pbn_oxsemi_1_4000000 },
4216 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4218 pbn_oxsemi_1_4000000 },
4219 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4221 pbn_oxsemi_1_4000000 },
4222 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4224 pbn_oxsemi_1_4000000 },
4225 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4227 pbn_oxsemi_1_4000000 },
4228 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4230 pbn_oxsemi_1_4000000 },
4231 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4233 pbn_oxsemi_1_4000000 },
4234 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4236 pbn_oxsemi_1_4000000 },
4237 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4239 pbn_oxsemi_1_4000000 },
4240 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4242 pbn_oxsemi_1_4000000 },
4243 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4245 pbn_oxsemi_1_4000000 },
4246 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4248 pbn_oxsemi_1_4000000 },
4249 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251 pbn_oxsemi_1_4000000 },
4252 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4254 pbn_oxsemi_1_4000000 },
4255 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4257 pbn_oxsemi_1_4000000 },
4258 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4260 pbn_oxsemi_1_4000000 },
4261 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4263 pbn_oxsemi_1_4000000 },
4264 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4266 pbn_oxsemi_1_4000000 },
4267 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4269 pbn_oxsemi_1_4000000 },
4270 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4272 pbn_oxsemi_1_4000000 },
4273 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4275 pbn_oxsemi_1_4000000 },
4276 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4278 pbn_oxsemi_1_4000000 },
4279 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4281 pbn_oxsemi_1_4000000 },
4283 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4285 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4286 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4287 pbn_oxsemi_1_4000000 },
4288 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4289 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4290 pbn_oxsemi_2_4000000 },
4291 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4292 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4293 pbn_oxsemi_4_4000000 },
4294 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4295 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4296 pbn_oxsemi_8_4000000 },
4299 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4301 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4302 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4303 pbn_oxsemi_2_4000000 },
4306 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4307 * from skokodyn@yahoo.com
4309 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4310 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4312 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4313 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4315 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4316 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4318 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4319 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4323 * Digitan DS560-558, from jimd@esoft.com
4325 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 * Titan Electronic cards
4331 * The 400L and 800L have a custom setup quirk.
4333 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4350 pbn_b1_bt_2_921600 },
4351 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4353 pbn_b0_bt_4_921600 },
4354 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4356 pbn_b0_bt_8_921600 },
4357 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4359 pbn_b4_bt_2_921600 },
4360 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4362 pbn_b4_bt_4_921600 },
4363 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4365 pbn_b4_bt_8_921600 },
4366 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4367 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4373 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4377 pbn_oxsemi_1_4000000 },
4378 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4380 pbn_oxsemi_2_4000000 },
4381 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4383 pbn_oxsemi_4_4000000 },
4384 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4386 pbn_oxsemi_8_4000000 },
4387 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4389 pbn_oxsemi_2_4000000 },
4390 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4392 pbn_oxsemi_2_4000000 },
4393 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4395 pbn_b0_bt_2_921600 },
4396 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4402 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4405 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4420 pbn_b2_bt_2_921600 },
4421 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4423 pbn_b2_bt_2_921600 },
4424 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426 pbn_b2_bt_2_921600 },
4427 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429 pbn_b2_bt_4_921600 },
4430 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 pbn_b2_bt_4_921600 },
4433 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 pbn_b2_bt_4_921600 },
4436 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 pbn_b0_bt_2_921600 },
4448 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450 pbn_b0_bt_2_921600 },
4451 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453 pbn_b0_bt_2_921600 },
4454 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 pbn_b0_bt_4_921600 },
4457 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 pbn_b0_bt_4_921600 },
4460 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 pbn_b0_bt_4_921600 },
4463 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 pbn_b0_bt_8_921600 },
4466 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 pbn_b0_bt_8_921600 },
4469 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_b0_bt_8_921600 },
4474 * Computone devices submitted by Doug McNash dmcnash@computone.com
4476 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4477 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4478 0, 0, pbn_computone_4 },
4479 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4480 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4481 0, 0, pbn_computone_8 },
4482 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4483 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4484 0, 0, pbn_computone_6 },
4486 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4490 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4491 pbn_b0_bt_1_921600 },
4496 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4497 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4498 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4499 pbn_b0_bt_1_921600 },
4501 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4502 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4503 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4504 pbn_b0_bt_1_921600 },
4507 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4509 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511 pbn_b0_bt_8_115200 },
4512 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_b0_bt_8_115200 },
4516 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518 pbn_b0_bt_2_115200 },
4519 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 pbn_b0_bt_2_115200 },
4522 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524 pbn_b0_bt_2_115200 },
4525 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 pbn_b0_bt_2_115200 },
4528 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 pbn_b0_bt_2_115200 },
4531 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_b0_bt_4_460800 },
4534 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 pbn_b0_bt_4_460800 },
4537 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 pbn_b0_bt_2_460800 },
4540 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 pbn_b0_bt_2_460800 },
4543 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 pbn_b0_bt_2_460800 },
4546 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_b0_bt_1_115200 },
4549 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_b0_bt_1_460800 },
4554 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4555 * Cards are identified by their subsystem vendor IDs, which
4556 * (in hex) match the model number.
4558 * Note that JC140x are RS422/485 cards which require ox950
4559 * ACR = 0x10, and as such are not currently fully supported.
4561 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4562 0x1204, 0x0004, 0, 0,
4564 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4565 0x1208, 0x0004, 0, 0,
4567 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4568 0x1402, 0x0002, 0, 0,
4569 pbn_b0_2_921600 }, */
4570 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4571 0x1404, 0x0004, 0, 0,
4572 pbn_b0_4_921600 }, */
4573 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4574 0x1208, 0x0004, 0, 0,
4577 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4578 0x1204, 0x0004, 0, 0,
4580 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4581 0x1208, 0x0004, 0, 0,
4583 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4584 0x1208, 0x0004, 0, 0,
4587 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4589 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4596 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 * RAStel 2 port modem, gerg@moreton.com.au
4603 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b2_bt_2_115200 },
4608 * EKF addition for i960 Boards form EKF with serial port
4610 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4611 0xE4BF, PCI_ANY_ID, 0, 0,
4615 * Xircom Cardbus/Ethernet combos
4617 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4623 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 * Untested PCI modems, sent in from various folks...
4632 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4634 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4635 0x1048, 0x1500, 0, 0,
4638 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4645 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4646 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4648 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4667 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4668 PCI_ANY_ID, PCI_ANY_ID,
4670 0, pbn_pericom_PI7C9X7951 },
4671 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4672 PCI_ANY_ID, PCI_ANY_ID,
4674 0, pbn_pericom_PI7C9X7952 },
4675 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4676 PCI_ANY_ID, PCI_ANY_ID,
4678 0, pbn_pericom_PI7C9X7954 },
4679 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4680 PCI_ANY_ID, PCI_ANY_ID,
4682 0, pbn_pericom_PI7C9X7958 },
4684 * ACCES I/O Products quad
4686 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4688 pbn_pericom_PI7C9X7952 },
4689 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691 pbn_pericom_PI7C9X7952 },
4692 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694 pbn_pericom_PI7C9X7954 },
4695 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 pbn_pericom_PI7C9X7954 },
4698 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 pbn_pericom_PI7C9X7952 },
4701 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 pbn_pericom_PI7C9X7952 },
4704 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706 pbn_pericom_PI7C9X7954 },
4707 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 pbn_pericom_PI7C9X7954 },
4710 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712 pbn_pericom_PI7C9X7952 },
4713 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715 pbn_pericom_PI7C9X7952 },
4716 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718 pbn_pericom_PI7C9X7954 },
4719 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721 pbn_pericom_PI7C9X7954 },
4722 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724 pbn_pericom_PI7C9X7951 },
4725 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727 pbn_pericom_PI7C9X7952 },
4728 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 pbn_pericom_PI7C9X7952 },
4731 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 pbn_pericom_PI7C9X7954 },
4734 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 pbn_pericom_PI7C9X7954 },
4737 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 pbn_pericom_PI7C9X7952 },
4740 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742 pbn_pericom_PI7C9X7954 },
4743 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_pericom_PI7C9X7952 },
4746 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 pbn_pericom_PI7C9X7952 },
4749 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751 pbn_pericom_PI7C9X7954 },
4752 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_pericom_PI7C9X7954 },
4755 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_pericom_PI7C9X7952 },
4758 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_pericom_PI7C9X7954 },
4761 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 pbn_pericom_PI7C9X7954 },
4764 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_pericom_PI7C9X7958 },
4767 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_pericom_PI7C9X7958 },
4770 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772 pbn_pericom_PI7C9X7954 },
4773 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_pericom_PI7C9X7958 },
4776 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778 pbn_pericom_PI7C9X7954 },
4779 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_pericom_PI7C9X7958 },
4782 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_pericom_PI7C9X7954 },
4786 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4788 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4795 PCI_ANY_ID, PCI_ANY_ID,
4797 pbn_b1_bt_1_115200 },
4802 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4808 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4814 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
4815 PCI_ANY_ID, PCI_ANY_ID,
4816 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4818 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
4819 PCI_ANY_ID, PCI_ANY_ID,
4820 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4823 * Perle PCI-RAS cards
4825 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4826 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4827 0, 0, pbn_b2_4_921600 },
4828 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4829 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4830 0, 0, pbn_b2_8_921600 },
4833 * Mainpine series cards: Fairly standard layout but fools
4834 * parts of the autodetect in some cases and uses otherwise
4835 * unmatched communications subclasses in the PCI Express case
4838 { /* RockForceDUO */
4839 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4840 PCI_VENDOR_ID_MAINPINE, 0x0200,
4841 0, 0, pbn_b0_2_115200 },
4842 { /* RockForceQUATRO */
4843 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4844 PCI_VENDOR_ID_MAINPINE, 0x0300,
4845 0, 0, pbn_b0_4_115200 },
4846 { /* RockForceDUO+ */
4847 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4848 PCI_VENDOR_ID_MAINPINE, 0x0400,
4849 0, 0, pbn_b0_2_115200 },
4850 { /* RockForceQUATRO+ */
4851 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4852 PCI_VENDOR_ID_MAINPINE, 0x0500,
4853 0, 0, pbn_b0_4_115200 },
4855 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4856 PCI_VENDOR_ID_MAINPINE, 0x0600,
4857 0, 0, pbn_b0_2_115200 },
4859 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4860 PCI_VENDOR_ID_MAINPINE, 0x0700,
4861 0, 0, pbn_b0_4_115200 },
4862 { /* RockForceOCTO+ */
4863 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4864 PCI_VENDOR_ID_MAINPINE, 0x0800,
4865 0, 0, pbn_b0_8_115200 },
4866 { /* RockForceDUO+ */
4867 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4868 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4869 0, 0, pbn_b0_2_115200 },
4870 { /* RockForceQUARTRO+ */
4871 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4872 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4873 0, 0, pbn_b0_4_115200 },
4874 { /* RockForceOCTO+ */
4875 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4876 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4877 0, 0, pbn_b0_8_115200 },
4879 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4880 PCI_VENDOR_ID_MAINPINE, 0x2000,
4881 0, 0, pbn_b0_1_115200 },
4883 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4884 PCI_VENDOR_ID_MAINPINE, 0x2100,
4885 0, 0, pbn_b0_1_115200 },
4887 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4888 PCI_VENDOR_ID_MAINPINE, 0x2200,
4889 0, 0, pbn_b0_2_115200 },
4891 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4892 PCI_VENDOR_ID_MAINPINE, 0x2300,
4893 0, 0, pbn_b0_2_115200 },
4895 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4896 PCI_VENDOR_ID_MAINPINE, 0x2400,
4897 0, 0, pbn_b0_4_115200 },
4899 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4900 PCI_VENDOR_ID_MAINPINE, 0x2500,
4901 0, 0, pbn_b0_4_115200 },
4903 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4904 PCI_VENDOR_ID_MAINPINE, 0x2600,
4905 0, 0, pbn_b0_8_115200 },
4907 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4908 PCI_VENDOR_ID_MAINPINE, 0x2700,
4909 0, 0, pbn_b0_8_115200 },
4910 { /* IQ Express D1 */
4911 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4912 PCI_VENDOR_ID_MAINPINE, 0x3000,
4913 0, 0, pbn_b0_1_115200 },
4914 { /* IQ Express F1 */
4915 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4916 PCI_VENDOR_ID_MAINPINE, 0x3100,
4917 0, 0, pbn_b0_1_115200 },
4918 { /* IQ Express D2 */
4919 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4920 PCI_VENDOR_ID_MAINPINE, 0x3200,
4921 0, 0, pbn_b0_2_115200 },
4922 { /* IQ Express F2 */
4923 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4924 PCI_VENDOR_ID_MAINPINE, 0x3300,
4925 0, 0, pbn_b0_2_115200 },
4926 { /* IQ Express D4 */
4927 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4928 PCI_VENDOR_ID_MAINPINE, 0x3400,
4929 0, 0, pbn_b0_4_115200 },
4930 { /* IQ Express F4 */
4931 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4932 PCI_VENDOR_ID_MAINPINE, 0x3500,
4933 0, 0, pbn_b0_4_115200 },
4934 { /* IQ Express D8 */
4935 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4936 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4937 0, 0, pbn_b0_8_115200 },
4938 { /* IQ Express F8 */
4939 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4940 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4941 0, 0, pbn_b0_8_115200 },
4945 * PA Semi PA6T-1682M on-chip UART
4947 { PCI_VENDOR_ID_PASEMI, 0xa004,
4948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4952 * National Instruments
4954 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 pbn_b1_bt_4_115200 },
4963 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 pbn_b1_bt_2_115200 },
4966 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968 pbn_b1_bt_4_115200 },
4969 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 pbn_b1_bt_2_115200 },
4972 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980 pbn_b1_bt_4_115200 },
4981 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983 pbn_b1_bt_2_115200 },
4984 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 pbn_b1_bt_4_115200 },
4987 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 pbn_b1_bt_2_115200 },
4990 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5017 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5018 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5028 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5030 { PCI_VENDOR_ID_ADDIDATA,
5031 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5038 { PCI_VENDOR_ID_ADDIDATA,
5039 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5046 { PCI_VENDOR_ID_ADDIDATA,
5047 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5054 { PCI_VENDOR_ID_AMCC,
5055 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5062 { PCI_VENDOR_ID_ADDIDATA,
5063 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5070 { PCI_VENDOR_ID_ADDIDATA,
5071 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5078 { PCI_VENDOR_ID_ADDIDATA,
5079 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5086 { PCI_VENDOR_ID_ADDIDATA,
5087 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5094 { PCI_VENDOR_ID_ADDIDATA,
5095 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5102 { PCI_VENDOR_ID_ADDIDATA,
5103 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5110 { PCI_VENDOR_ID_ADDIDATA,
5111 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5118 { PCI_VENDOR_ID_ADDIDATA,
5119 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5124 pbn_ADDIDATA_PCIe_4_3906250 },
5126 { PCI_VENDOR_ID_ADDIDATA,
5127 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5132 pbn_ADDIDATA_PCIe_2_3906250 },
5134 { PCI_VENDOR_ID_ADDIDATA,
5135 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5140 pbn_ADDIDATA_PCIe_1_3906250 },
5142 { PCI_VENDOR_ID_ADDIDATA,
5143 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5148 pbn_ADDIDATA_PCIe_8_3906250 },
5150 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5151 PCI_VENDOR_ID_IBM, 0x0299,
5152 0, 0, pbn_b0_bt_2_115200 },
5155 * other NetMos 9835 devices are most likely handled by the
5156 * parport_serial driver, check drivers/parport/parport_serial.c
5157 * before adding them here.
5160 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5162 0, 0, pbn_b0_1_115200 },
5164 /* the 9901 is a rebranded 9912 */
5165 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5167 0, 0, pbn_b0_1_115200 },
5169 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5171 0, 0, pbn_b0_1_115200 },
5173 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5175 0, 0, pbn_b0_1_115200 },
5177 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5179 0, 0, pbn_b0_1_115200 },
5181 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5183 0, 0, pbn_NETMOS9900_2s_115200 },
5186 * Best Connectivity and Rosewill PCI Multi I/O cards
5189 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5191 0, 0, pbn_b0_1_115200 },
5193 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5195 0, 0, pbn_b0_bt_2_115200 },
5197 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5199 0, 0, pbn_b0_bt_4_115200 },
5201 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5203 pbn_ce4100_1_115200 },
5208 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5213 * Broadcom TruManage
5215 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5217 pbn_brcm_trumanage },
5220 * AgeStar as-prs2-009
5222 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5223 PCI_ANY_ID, PCI_ANY_ID,
5224 0, 0, pbn_b0_bt_2_115200 },
5227 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5228 * so not listed here.
5230 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5231 PCI_ANY_ID, PCI_ANY_ID,
5232 0, 0, pbn_b0_bt_4_115200 },
5234 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5235 PCI_ANY_ID, PCI_ANY_ID,
5236 0, 0, pbn_b0_bt_2_115200 },
5238 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5239 PCI_ANY_ID, PCI_ANY_ID,
5240 0, 0, pbn_b0_bt_4_115200 },
5242 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5243 PCI_ANY_ID, PCI_ANY_ID,
5244 0, 0, pbn_wch382_2 },
5246 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5247 PCI_ANY_ID, PCI_ANY_ID,
5248 0, 0, pbn_wch384_4 },
5251 * Realtek RealManage
5253 { PCI_VENDOR_ID_REALTEK, 0x816a,
5254 PCI_ANY_ID, PCI_ANY_ID,
5255 0, 0, pbn_b0_1_115200 },
5257 { PCI_VENDOR_ID_REALTEK, 0x816b,
5258 PCI_ANY_ID, PCI_ANY_ID,
5259 0, 0, pbn_b0_1_115200 },
5261 /* Fintek PCI serial cards */
5262 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5263 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5264 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5266 /* MKS Tenta SCOM-080x serial cards */
5267 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5268 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5270 /* Amazon PCI serial device */
5271 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5274 * These entries match devices with class COMMUNICATION_SERIAL,
5275 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5277 { PCI_ANY_ID, PCI_ANY_ID,
5278 PCI_ANY_ID, PCI_ANY_ID,
5279 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5280 0xffff00, pbn_default },
5281 { PCI_ANY_ID, PCI_ANY_ID,
5282 PCI_ANY_ID, PCI_ANY_ID,
5283 PCI_CLASS_COMMUNICATION_MODEM << 8,
5284 0xffff00, pbn_default },
5285 { PCI_ANY_ID, PCI_ANY_ID,
5286 PCI_ANY_ID, PCI_ANY_ID,
5287 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5288 0xffff00, pbn_default },
5292 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5293 pci_channel_state_t state)
5295 struct serial_private *priv = pci_get_drvdata(dev);
5297 if (state == pci_channel_io_perm_failure)
5298 return PCI_ERS_RESULT_DISCONNECT;
5301 pciserial_detach_ports(priv);
5303 pci_disable_device(dev);
5305 return PCI_ERS_RESULT_NEED_RESET;
5308 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5312 rc = pci_enable_device(dev);
5315 return PCI_ERS_RESULT_DISCONNECT;
5317 pci_restore_state(dev);
5318 pci_save_state(dev);
5320 return PCI_ERS_RESULT_RECOVERED;
5323 static void serial8250_io_resume(struct pci_dev *dev)
5325 struct serial_private *priv = pci_get_drvdata(dev);
5326 struct serial_private *new;
5331 new = pciserial_init_ports(dev, priv->board);
5333 pci_set_drvdata(dev, new);
5338 static const struct pci_error_handlers serial8250_err_handler = {
5339 .error_detected = serial8250_io_error_detected,
5340 .slot_reset = serial8250_io_slot_reset,
5341 .resume = serial8250_io_resume,
5344 static struct pci_driver serial_pci_driver = {
5346 .probe = pciserial_init_one,
5347 .remove = pciserial_remove_one,
5349 .pm = &pciserial_pm_ops,
5351 .id_table = serial_pci_tbl,
5352 .err_handler = &serial8250_err_handler,
5355 module_pci_driver(serial_pci_driver);
5357 MODULE_LICENSE("GPL");
5358 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5359 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);