2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
25 #include <asm/byteorder.h>
31 * init function returns:
32 * > 0 - number of ports
33 * = 0 - use board->num_ports
36 struct pci_serial_quirk {
41 int (*probe)(struct pci_dev *dev);
42 int (*init)(struct pci_dev *dev);
43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
45 struct uart_8250_port *, int);
46 void (*exit)(struct pci_dev *dev);
49 #define PCI_NUM_BAR_RESOURCES 6
51 struct serial_private {
54 struct pci_serial_quirk *quirk;
55 const struct pciserial_board *board;
59 static int pci_default_setup(struct serial_private*,
60 const struct pciserial_board*, struct uart_8250_port *, int);
62 static void moan_device(const char *str, struct pci_dev *dev)
66 "Please send the output of lspci -vv, this\n"
67 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 "manufacturer and name of serial board or\n"
69 "modem board to <linux-serial@vger.kernel.org>.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
75 setup_port(struct serial_private *priv, struct uart_8250_port *port,
76 u8 bar, unsigned int offset, int regshift)
78 struct pci_dev *dev = priv->dev;
80 if (bar >= PCI_NUM_BAR_RESOURCES)
83 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
84 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
87 port->port.iotype = UPIO_MEM;
88 port->port.iobase = 0;
89 port->port.mapbase = pci_resource_start(dev, bar) + offset;
90 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
91 port->port.regshift = regshift;
93 port->port.iotype = UPIO_PORT;
94 port->port.iobase = pci_resource_start(dev, bar) + offset;
95 port->port.mapbase = 0;
96 port->port.membase = NULL;
97 port->port.regshift = 0;
103 * ADDI-DATA GmbH communication cards <info@addi-data.com>
105 static int addidata_apci7800_setup(struct serial_private *priv,
106 const struct pciserial_board *board,
107 struct uart_8250_port *port, int idx)
109 unsigned int bar = 0, offset = board->first_offset;
110 bar = FL_GET_BASE(board->flags);
113 offset += idx * board->uart_offset;
114 } else if ((idx >= 2) && (idx < 4)) {
116 offset += ((idx - 2) * board->uart_offset);
117 } else if ((idx >= 4) && (idx < 6)) {
119 offset += ((idx - 4) * board->uart_offset);
120 } else if (idx >= 6) {
122 offset += ((idx - 6) * board->uart_offset);
125 return setup_port(priv, port, bar, offset, board->reg_shift);
129 * AFAVLAB uses a different mixture of BARs and offsets
130 * Not that ugly ;) -- HW
133 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
134 struct uart_8250_port *port, int idx)
136 unsigned int bar, offset = board->first_offset;
138 bar = FL_GET_BASE(board->flags);
143 offset += (idx - 4) * board->uart_offset;
146 return setup_port(priv, port, bar, offset, board->reg_shift);
150 * HP's Remote Management Console. The Diva chip came in several
151 * different versions. N-class, L2000 and A500 have two Diva chips, each
152 * with 3 UARTs (the third UART on the second chip is unused). Superdome
153 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
154 * one Diva chip, but it has been expanded to 5 UARTs.
156 static int pci_hp_diva_init(struct pci_dev *dev)
160 switch (dev->subsystem_device) {
161 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
162 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
163 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
164 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
170 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
173 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
174 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
183 * HP's Diva chip puts the 4th/5th serial port further out, and
184 * some serial ports are supposed to be hidden on certain models.
187 pci_hp_diva_setup(struct serial_private *priv,
188 const struct pciserial_board *board,
189 struct uart_8250_port *port, int idx)
191 unsigned int offset = board->first_offset;
192 unsigned int bar = FL_GET_BASE(board->flags);
194 switch (priv->dev->subsystem_device) {
195 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
199 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 offset += idx * board->uart_offset;
211 return setup_port(priv, port, bar, offset, board->reg_shift);
215 * Added for EKF Intel i960 serial boards
217 static int pci_inteli960ni_init(struct pci_dev *dev)
221 if (!(dev->subsystem_device & 0x1000))
224 /* is firmware started? */
225 pci_read_config_dword(dev, 0x44, &oldval);
226 if (oldval == 0x00001000L) { /* RESET value */
227 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
234 * Some PCI serial cards using the PLX 9050 PCI interface chip require
235 * that the card interrupt be explicitly enabled or disabled. This
236 * seems to be mainly needed on card using the PLX which also use I/O
239 static int pci_plx9050_init(struct pci_dev *dev)
244 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
245 moan_device("no memory in bar 0", dev);
250 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
251 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
254 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
255 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
257 * As the megawolf cards have the int pins active
258 * high, and have 2 UART chips, both ints must be
259 * enabled on the 9050. Also, the UARTS are set in
260 * 16450 mode by default, so we have to enable the
261 * 16C950 'enhanced' mode so that we can use the
266 * enable/disable interrupts
268 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
271 writel(irq_config, p + 0x4c);
274 * Read the register back to ensure that it took effect.
282 static void pci_plx9050_exit(struct pci_dev *dev)
286 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
297 * Read the register back to ensure that it took effect.
304 #define NI8420_INT_ENABLE_REG 0x38
305 #define NI8420_INT_ENABLE_BIT 0x2000
307 static void pci_ni8420_exit(struct pci_dev *dev)
310 unsigned int bar = 0;
312 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
313 moan_device("no memory in bar", dev);
317 p = pci_ioremap_bar(dev, bar);
321 /* Disable the CPU Interrupt */
322 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
323 p + NI8420_INT_ENABLE_REG);
329 #define MITE_IOWBSR1 0xc4
330 #define MITE_IOWCR1 0xf4
331 #define MITE_LCIMR1 0x08
332 #define MITE_LCIMR2 0x10
334 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
336 static void pci_ni8430_exit(struct pci_dev *dev)
339 unsigned int bar = 0;
341 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
342 moan_device("no memory in bar", dev);
346 p = pci_ioremap_bar(dev, bar);
350 /* Disable the CPU Interrupt */
351 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
355 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
357 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
358 struct uart_8250_port *port, int idx)
360 unsigned int bar, offset = board->first_offset;
365 /* first four channels map to 0, 0x100, 0x200, 0x300 */
366 offset += idx * board->uart_offset;
367 } else if (idx < 8) {
368 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
369 offset += idx * board->uart_offset + 0xC00;
370 } else /* we have only 8 ports on PMC-OCTALPRO */
373 return setup_port(priv, port, bar, offset, board->reg_shift);
377 * This does initialization for PMC OCTALPRO cards:
378 * maps the device memory, resets the UARTs (needed, bc
379 * if the module is removed and inserted again, the card
380 * is in the sleep mode) and enables global interrupt.
383 /* global control register offset for SBS PMC-OctalPro */
384 #define OCT_REG_CR_OFF 0x500
386 static int sbs_init(struct pci_dev *dev)
390 p = pci_ioremap_bar(dev, 0);
394 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
395 writeb(0x10, p + OCT_REG_CR_OFF);
397 writeb(0x0, p + OCT_REG_CR_OFF);
399 /* Set bit-2 (INTENABLE) of Control Register */
400 writeb(0x4, p + OCT_REG_CR_OFF);
407 * Disables the global interrupt of PMC-OctalPro
410 static void sbs_exit(struct pci_dev *dev)
414 p = pci_ioremap_bar(dev, 0);
415 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
417 writeb(0, p + OCT_REG_CR_OFF);
422 * SIIG serial cards have an PCI interface chip which also controls
423 * the UART clocking frequency. Each UART can be clocked independently
424 * (except cards equipped with 4 UARTs) and initial clocking settings
425 * are stored in the EEPROM chip. It can cause problems because this
426 * version of serial driver doesn't support differently clocked UART's
427 * on single PCI card. To prevent this, initialization functions set
428 * high frequency clocking for all UART's on given card. It is safe (I
429 * hope) because it doesn't touch EEPROM settings to prevent conflicts
430 * with other OSes (like M$ DOS).
432 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
434 * There is two family of SIIG serial cards with different PCI
435 * interface chip and different configuration methods:
436 * - 10x cards have control registers in IO and/or memory space;
437 * - 20x cards have control registers in standard PCI configuration space.
439 * Note: all 10x cards have PCI device ids 0x10..
440 * all 20x cards have PCI device ids 0x20..
442 * There are also Quartet Serial cards which use Oxford Semiconductor
443 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
445 * Note: some SIIG cards are probed by the parport_serial object.
448 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
449 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
451 static int pci_siig10x_init(struct pci_dev *dev)
456 switch (dev->device & 0xfff8) {
457 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
460 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
463 default: /* 1S1P, 4S */
468 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
472 writew(readw(p + 0x28) & data, p + 0x28);
478 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
479 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
481 static int pci_siig20x_init(struct pci_dev *dev)
485 /* Change clock frequency for the first UART. */
486 pci_read_config_byte(dev, 0x6f, &data);
487 pci_write_config_byte(dev, 0x6f, data & 0xef);
489 /* If this card has 2 UART, we have to do the same with second UART. */
490 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
491 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
492 pci_read_config_byte(dev, 0x73, &data);
493 pci_write_config_byte(dev, 0x73, data & 0xef);
498 static int pci_siig_init(struct pci_dev *dev)
500 unsigned int type = dev->device & 0xff00;
503 return pci_siig10x_init(dev);
504 else if (type == 0x2000)
505 return pci_siig20x_init(dev);
507 moan_device("Unknown SIIG card", dev);
511 static int pci_siig_setup(struct serial_private *priv,
512 const struct pciserial_board *board,
513 struct uart_8250_port *port, int idx)
515 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
519 offset = (idx - 4) * 8;
522 return setup_port(priv, port, bar, offset, 0);
526 * Timedia has an explosion of boards, and to avoid the PCI table from
527 * growing *huge*, we use this function to collapse some 70 entries
528 * in the PCI table into one, for sanity's and compactness's sake.
530 static const unsigned short timedia_single_port[] = {
531 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
534 static const unsigned short timedia_dual_port[] = {
535 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
536 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
537 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
538 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
542 static const unsigned short timedia_quad_port[] = {
543 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
544 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
545 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
549 static const unsigned short timedia_eight_port[] = {
550 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
551 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
554 static const struct timedia_struct {
556 const unsigned short *ids;
558 { 1, timedia_single_port },
559 { 2, timedia_dual_port },
560 { 4, timedia_quad_port },
561 { 8, timedia_eight_port }
565 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
566 * listing them individually, this driver merely grabs them all with
567 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
568 * and should be left free to be claimed by parport_serial instead.
570 static int pci_timedia_probe(struct pci_dev *dev)
573 * Check the third digit of the subdevice ID
574 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
576 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
578 "ignoring Timedia subdevice %04x for parport_serial\n",
579 dev->subsystem_device);
586 static int pci_timedia_init(struct pci_dev *dev)
588 const unsigned short *ids;
591 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
592 ids = timedia_data[i].ids;
593 for (j = 0; ids[j]; j++)
594 if (dev->subsystem_device == ids[j])
595 return timedia_data[i].num;
601 * Timedia/SUNIX uses a mixture of BARs and offsets
602 * Ugh, this is ugly as all hell --- TYT
605 pci_timedia_setup(struct serial_private *priv,
606 const struct pciserial_board *board,
607 struct uart_8250_port *port, int idx)
609 unsigned int bar = 0, offset = board->first_offset;
616 offset = board->uart_offset;
623 offset = board->uart_offset;
632 return setup_port(priv, port, bar, offset, board->reg_shift);
636 * Some Titan cards are also a little weird
639 titan_400l_800l_setup(struct serial_private *priv,
640 const struct pciserial_board *board,
641 struct uart_8250_port *port, int idx)
643 unsigned int bar, offset = board->first_offset;
654 offset = (idx - 2) * board->uart_offset;
657 return setup_port(priv, port, bar, offset, board->reg_shift);
660 static int pci_xircom_init(struct pci_dev *dev)
666 static int pci_ni8420_init(struct pci_dev *dev)
669 unsigned int bar = 0;
671 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
672 moan_device("no memory in bar", dev);
676 p = pci_ioremap_bar(dev, bar);
680 /* Enable CPU Interrupt */
681 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
682 p + NI8420_INT_ENABLE_REG);
688 #define MITE_IOWBSR1_WSIZE 0xa
689 #define MITE_IOWBSR1_WIN_OFFSET 0x800
690 #define MITE_IOWBSR1_WENAB (1 << 7)
691 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
692 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
693 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
695 static int pci_ni8430_init(struct pci_dev *dev)
698 struct pci_bus_region region;
700 unsigned int bar = 0;
702 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
703 moan_device("no memory in bar", dev);
707 p = pci_ioremap_bar(dev, bar);
712 * Set device window address and size in BAR0, while acknowledging that
713 * the resource structure may contain a translated address that differs
714 * from the address the device responds to.
716 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
717 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
718 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
719 writel(device_window, p + MITE_IOWBSR1);
721 /* Set window access to go to RAMSEL IO address space */
722 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
725 /* Enable IO Bus Interrupt 0 */
726 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
728 /* Enable CPU Interrupt */
729 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
735 /* UART Port Control Register */
736 #define NI8430_PORTCON 0x0f
737 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
740 pci_ni8430_setup(struct serial_private *priv,
741 const struct pciserial_board *board,
742 struct uart_8250_port *port, int idx)
744 struct pci_dev *dev = priv->dev;
746 unsigned int bar, offset = board->first_offset;
748 if (idx >= board->num_ports)
751 bar = FL_GET_BASE(board->flags);
752 offset += idx * board->uart_offset;
754 p = pci_ioremap_bar(dev, bar);
758 /* enable the transceiver */
759 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
760 p + offset + NI8430_PORTCON);
764 return setup_port(priv, port, bar, offset, board->reg_shift);
767 static int pci_netmos_9900_setup(struct serial_private *priv,
768 const struct pciserial_board *board,
769 struct uart_8250_port *port, int idx)
773 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
774 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
775 /* netmos apparently orders BARs by datasheet layout, so serial
776 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
780 return setup_port(priv, port, bar, 0, board->reg_shift);
782 return pci_default_setup(priv, board, port, idx);
786 /* the 99xx series comes with a range of device IDs and a variety
789 * 9900 has varying capabilities and can cascade to sub-controllers
790 * (cascading should be purely internal)
791 * 9904 is hardwired with 4 serial ports
792 * 9912 and 9922 are hardwired with 2 serial ports
794 static int pci_netmos_9900_numports(struct pci_dev *dev)
796 unsigned int c = dev->class;
798 unsigned short sub_serports;
805 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
806 /* two possibilities: 0x30ps encodes number of parallel and
807 * serial ports, or 0x1000 indicates *something*. This is not
808 * immediately obvious, since the 2s1p+4s configuration seems
809 * to offer all functionality on functions 0..2, while still
810 * advertising the same function 3 as the 4s+2s1p config.
812 sub_serports = dev->subsystem_device & 0xf;
813 if (sub_serports > 0)
817 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
821 moan_device("unknown NetMos/Mostech program interface", dev);
825 static int pci_netmos_init(struct pci_dev *dev)
827 /* subdevice 0x00PS means <P> parallel, <S> serial */
828 unsigned int num_serial = dev->subsystem_device & 0xf;
830 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
831 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
834 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
835 dev->subsystem_device == 0x0299)
838 switch (dev->device) { /* FALLTHROUGH on all */
839 case PCI_DEVICE_ID_NETMOS_9904:
840 case PCI_DEVICE_ID_NETMOS_9912:
841 case PCI_DEVICE_ID_NETMOS_9922:
842 case PCI_DEVICE_ID_NETMOS_9900:
843 num_serial = pci_netmos_9900_numports(dev);
850 if (num_serial == 0) {
851 moan_device("unknown NetMos/Mostech device", dev);
859 * These chips are available with optionally one parallel port and up to
860 * two serial ports. Unfortunately they all have the same product id.
862 * Basic configuration is done over a region of 32 I/O ports. The base
863 * ioport is called INTA or INTC, depending on docs/other drivers.
865 * The region of the 32 I/O ports is configured in POSIO0R...
869 #define ITE_887x_MISCR 0x9c
870 #define ITE_887x_INTCBAR 0x78
871 #define ITE_887x_UARTBAR 0x7c
872 #define ITE_887x_PS0BAR 0x10
873 #define ITE_887x_POSIO0 0x60
876 #define ITE_887x_IOSIZE 32
877 /* I/O space size (bits 26-24; 8 bytes = 011b) */
878 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
879 /* I/O space size (bits 26-24; 32 bytes = 101b) */
880 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
881 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
882 #define ITE_887x_POSIO_SPEED (3 << 29)
883 /* enable IO_Space bit */
884 #define ITE_887x_POSIO_ENABLE (1 << 31)
886 static int pci_ite887x_init(struct pci_dev *dev)
888 /* inta_addr are the configuration addresses of the ITE */
889 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
892 struct resource *iobase = NULL;
893 u32 miscr, uartbar, ioport;
895 /* search for the base-ioport */
897 while (inta_addr[i] && iobase == NULL) {
898 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
900 if (iobase != NULL) {
901 /* write POSIO0R - speed | size | ioport */
902 pci_write_config_dword(dev, ITE_887x_POSIO0,
903 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
904 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
905 /* write INTCBAR - ioport */
906 pci_write_config_dword(dev, ITE_887x_INTCBAR,
908 ret = inb(inta_addr[i]);
910 /* ioport connected */
913 release_region(iobase->start, ITE_887x_IOSIZE);
920 dev_err(&dev->dev, "ite887x: could not find iobase\n");
924 /* start of undocumented type checking (see parport_pc.c) */
925 type = inb(iobase->start + 0x18) & 0x0f;
928 case 0x2: /* ITE8871 (1P) */
929 case 0xa: /* ITE8875 (1P) */
932 case 0xe: /* ITE8872 (2S1P) */
935 case 0x6: /* ITE8873 (1S) */
938 case 0x8: /* ITE8874 (2S) */
942 moan_device("Unknown ITE887x", dev);
946 /* configure all serial ports */
947 for (i = 0; i < ret; i++) {
948 /* read the I/O port from the device */
949 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
951 ioport &= 0x0000FF00; /* the actual base address */
952 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
953 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
954 ITE_887x_POSIO_IOSIZE_8 | ioport);
956 /* write the ioport to the UARTBAR */
957 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
958 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
959 uartbar |= (ioport << (16 * i)); /* set the ioport */
960 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
962 /* get current config */
963 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
964 /* disable interrupts (UARTx_Routing[3:0]) */
965 miscr &= ~(0xf << (12 - 4 * i));
966 /* activate the UART (UARTx_En) */
967 miscr |= 1 << (23 - i);
968 /* write new config with activated UART */
969 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
973 /* the device has no UARTs if we get here */
974 release_region(iobase->start, ITE_887x_IOSIZE);
980 static void pci_ite887x_exit(struct pci_dev *dev)
983 /* the ioport is bit 0-15 in POSIO0R */
984 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
986 release_region(ioport, ITE_887x_IOSIZE);
990 * EndRun Technologies.
991 * Determine the number of ports available on the device.
993 #define PCI_VENDOR_ID_ENDRUN 0x7401
994 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
996 static int pci_endrun_init(struct pci_dev *dev)
999 unsigned long deviceID;
1000 unsigned int number_uarts = 0;
1002 /* EndRun device is all 0xexxx */
1003 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1004 (dev->device & 0xf000) != 0xe000)
1007 p = pci_iomap(dev, 0, 5);
1011 deviceID = ioread32(p);
1013 if (deviceID == 0x07000200) {
1014 number_uarts = ioread8(p + 4);
1016 "%d ports detected on EndRun PCI Express device\n",
1019 pci_iounmap(dev, p);
1020 return number_uarts;
1024 * Oxford Semiconductor Inc.
1025 * Check that device is part of the Tornado range of devices, then determine
1026 * the number of ports available on the device.
1028 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1031 unsigned long deviceID;
1032 unsigned int number_uarts = 0;
1034 /* OxSemi Tornado devices are all 0xCxxx */
1035 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1036 (dev->device & 0xF000) != 0xC000)
1039 p = pci_iomap(dev, 0, 5);
1043 deviceID = ioread32(p);
1044 /* Tornado device */
1045 if (deviceID == 0x07000200) {
1046 number_uarts = ioread8(p + 4);
1048 "%d ports detected on Oxford PCI Express device\n",
1051 pci_iounmap(dev, p);
1052 return number_uarts;
1055 /* Quatech devices have their own extra interface features */
1057 struct quatech_feature {
1062 #define QPCR_TEST_FOR1 0x3F
1063 #define QPCR_TEST_GET1 0x00
1064 #define QPCR_TEST_FOR2 0x40
1065 #define QPCR_TEST_GET2 0x40
1066 #define QPCR_TEST_FOR3 0x80
1067 #define QPCR_TEST_GET3 0x40
1068 #define QPCR_TEST_FOR4 0xC0
1069 #define QPCR_TEST_GET4 0x80
1071 #define QOPR_CLOCK_X1 0x0000
1072 #define QOPR_CLOCK_X2 0x0001
1073 #define QOPR_CLOCK_X4 0x0002
1074 #define QOPR_CLOCK_X8 0x0003
1075 #define QOPR_CLOCK_RATE_MASK 0x0003
1078 static struct quatech_feature quatech_cards[] = {
1079 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1080 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1081 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1083 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1084 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1085 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1086 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1087 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1088 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1089 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1090 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1091 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1092 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1093 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1094 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1095 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1096 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1097 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1101 static int pci_quatech_amcc(u16 devid)
1103 struct quatech_feature *qf = &quatech_cards[0];
1105 if (qf->devid == devid)
1109 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1113 static int pci_quatech_rqopr(struct uart_8250_port *port)
1115 unsigned long base = port->port.iobase;
1118 LCR = inb(base + UART_LCR);
1119 outb(0xBF, base + UART_LCR);
1120 val = inb(base + UART_SCR);
1121 outb(LCR, base + UART_LCR);
1125 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1127 unsigned long base = port->port.iobase;
1130 LCR = inb(base + UART_LCR);
1131 outb(0xBF, base + UART_LCR);
1132 inb(base + UART_SCR);
1133 outb(qopr, base + UART_SCR);
1134 outb(LCR, base + UART_LCR);
1137 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1139 unsigned long base = port->port.iobase;
1142 LCR = inb(base + UART_LCR);
1143 outb(0xBF, base + UART_LCR);
1144 val = inb(base + UART_SCR);
1145 outb(val | 0x10, base + UART_SCR);
1146 qmcr = inb(base + UART_MCR);
1147 outb(val, base + UART_SCR);
1148 outb(LCR, base + UART_LCR);
1153 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1155 unsigned long base = port->port.iobase;
1158 LCR = inb(base + UART_LCR);
1159 outb(0xBF, base + UART_LCR);
1160 val = inb(base + UART_SCR);
1161 outb(val | 0x10, base + UART_SCR);
1162 outb(qmcr, base + UART_MCR);
1163 outb(val, base + UART_SCR);
1164 outb(LCR, base + UART_LCR);
1167 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1169 unsigned long base = port->port.iobase;
1172 LCR = inb(base + UART_LCR);
1173 outb(0xBF, base + UART_LCR);
1174 val = inb(base + UART_SCR);
1176 outb(0x80, UART_LCR);
1177 if (!(inb(UART_SCR) & 0x20)) {
1178 outb(LCR, base + UART_LCR);
1185 static int pci_quatech_test(struct uart_8250_port *port)
1189 qopr = pci_quatech_rqopr(port);
1190 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1191 reg = pci_quatech_rqopr(port) & 0xC0;
1192 if (reg != QPCR_TEST_GET1)
1194 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1195 reg = pci_quatech_rqopr(port) & 0xC0;
1196 if (reg != QPCR_TEST_GET2)
1198 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1199 reg = pci_quatech_rqopr(port) & 0xC0;
1200 if (reg != QPCR_TEST_GET3)
1202 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1203 reg = pci_quatech_rqopr(port) & 0xC0;
1204 if (reg != QPCR_TEST_GET4)
1207 pci_quatech_wqopr(port, qopr);
1211 static int pci_quatech_clock(struct uart_8250_port *port)
1214 unsigned long clock;
1216 if (pci_quatech_test(port) < 0)
1219 qopr = pci_quatech_rqopr(port);
1221 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1222 reg = pci_quatech_rqopr(port);
1223 if (reg & QOPR_CLOCK_X8) {
1227 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1228 reg = pci_quatech_rqopr(port);
1229 if (!(reg & QOPR_CLOCK_X8)) {
1233 reg &= QOPR_CLOCK_X8;
1234 if (reg == QOPR_CLOCK_X2) {
1236 set = QOPR_CLOCK_X2;
1237 } else if (reg == QOPR_CLOCK_X4) {
1239 set = QOPR_CLOCK_X4;
1240 } else if (reg == QOPR_CLOCK_X8) {
1242 set = QOPR_CLOCK_X8;
1245 set = QOPR_CLOCK_X1;
1247 qopr &= ~QOPR_CLOCK_RATE_MASK;
1251 pci_quatech_wqopr(port, qopr);
1255 static int pci_quatech_rs422(struct uart_8250_port *port)
1260 if (!pci_quatech_has_qmcr(port))
1262 qmcr = pci_quatech_rqmcr(port);
1263 pci_quatech_wqmcr(port, 0xFF);
1264 if (pci_quatech_rqmcr(port))
1266 pci_quatech_wqmcr(port, qmcr);
1270 static int pci_quatech_init(struct pci_dev *dev)
1272 if (pci_quatech_amcc(dev->device)) {
1273 unsigned long base = pci_resource_start(dev, 0);
1277 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1278 tmp = inl(base + 0x3c);
1279 outl(tmp | 0x01000000, base + 0x3c);
1280 outl(tmp &= ~0x01000000, base + 0x3c);
1286 static int pci_quatech_setup(struct serial_private *priv,
1287 const struct pciserial_board *board,
1288 struct uart_8250_port *port, int idx)
1290 /* Needed by pci_quatech calls below */
1291 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1292 /* Set up the clocking */
1293 port->port.uartclk = pci_quatech_clock(port);
1294 /* For now just warn about RS422 */
1295 if (pci_quatech_rs422(port))
1296 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1297 return pci_default_setup(priv, board, port, idx);
1300 static void pci_quatech_exit(struct pci_dev *dev)
1304 static int pci_default_setup(struct serial_private *priv,
1305 const struct pciserial_board *board,
1306 struct uart_8250_port *port, int idx)
1308 unsigned int bar, offset = board->first_offset, maxnr;
1310 bar = FL_GET_BASE(board->flags);
1311 if (board->flags & FL_BASE_BARS)
1314 offset += idx * board->uart_offset;
1316 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1317 (board->reg_shift + 3);
1319 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1322 return setup_port(priv, port, bar, offset, board->reg_shift);
1325 static int pci_pericom_setup(struct serial_private *priv,
1326 const struct pciserial_board *board,
1327 struct uart_8250_port *port, int idx)
1329 unsigned int bar, offset = board->first_offset, maxnr;
1331 bar = FL_GET_BASE(board->flags);
1332 if (board->flags & FL_BASE_BARS)
1335 offset += idx * board->uart_offset;
1340 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1341 (board->reg_shift + 3);
1343 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1346 return setup_port(priv, port, bar, offset, board->reg_shift);
1350 ce4100_serial_setup(struct serial_private *priv,
1351 const struct pciserial_board *board,
1352 struct uart_8250_port *port, int idx)
1356 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1357 port->port.iotype = UPIO_MEM32;
1358 port->port.type = PORT_XSCALE;
1359 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1360 port->port.regshift = 2;
1366 pci_omegapci_setup(struct serial_private *priv,
1367 const struct pciserial_board *board,
1368 struct uart_8250_port *port, int idx)
1370 return setup_port(priv, port, 2, idx * 8, 0);
1374 pci_brcm_trumanage_setup(struct serial_private *priv,
1375 const struct pciserial_board *board,
1376 struct uart_8250_port *port, int idx)
1378 int ret = pci_default_setup(priv, board, port, idx);
1380 port->port.type = PORT_BRCM_TRUMANAGE;
1381 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1385 /* RTS will control by MCR if this bit is 0 */
1386 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1387 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1388 #define FINTEK_RTS_INVERT BIT(5)
1390 /* We should do proper H/W transceiver setting before change to RS485 mode */
1391 static int pci_fintek_rs485_config(struct uart_port *port,
1392 struct serial_rs485 *rs485)
1394 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1396 u8 *index = (u8 *) port->private_data;
1398 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1401 rs485 = &port->rs485;
1402 else if (rs485->flags & SER_RS485_ENABLED)
1403 memset(rs485->padding, 0, sizeof(rs485->padding));
1405 memset(rs485, 0, sizeof(*rs485));
1407 /* F81504/508/512 not support RTS delay before or after send */
1408 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1410 if (rs485->flags & SER_RS485_ENABLED) {
1411 /* Enable RTS H/W control mode */
1412 setting |= FINTEK_RTS_CONTROL_BY_HW;
1414 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1415 /* RTS driving high on TX */
1416 setting &= ~FINTEK_RTS_INVERT;
1418 /* RTS driving low on TX */
1419 setting |= FINTEK_RTS_INVERT;
1422 rs485->delay_rts_after_send = 0;
1423 rs485->delay_rts_before_send = 0;
1425 /* Disable RTS H/W control mode */
1426 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1429 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1431 if (rs485 != &port->rs485)
1432 port->rs485 = *rs485;
1437 static int pci_fintek_setup(struct serial_private *priv,
1438 const struct pciserial_board *board,
1439 struct uart_8250_port *port, int idx)
1441 struct pci_dev *pdev = priv->dev;
1446 config_base = 0x40 + 0x08 * idx;
1448 /* Get the io address from configuration space */
1449 pci_read_config_word(pdev, config_base + 4, &iobase);
1451 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1453 port->port.iotype = UPIO_PORT;
1454 port->port.iobase = iobase;
1455 port->port.rs485_config = pci_fintek_rs485_config;
1457 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1461 /* preserve index in PCI configuration space */
1463 port->port.private_data = data;
1468 static int pci_fintek_init(struct pci_dev *dev)
1470 unsigned long iobase;
1472 resource_size_t bar_data[3];
1474 struct serial_private *priv = pci_get_drvdata(dev);
1475 struct uart_8250_port *port;
1477 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1478 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1479 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1482 switch (dev->device) {
1483 case 0x1104: /* 4 ports */
1484 case 0x1108: /* 8 ports */
1485 max_port = dev->device & 0xff;
1487 case 0x1112: /* 12 ports */
1494 /* Get the io address dispatch from the BIOS */
1495 bar_data[0] = pci_resource_start(dev, 5);
1496 bar_data[1] = pci_resource_start(dev, 4);
1497 bar_data[2] = pci_resource_start(dev, 3);
1499 for (i = 0; i < max_port; ++i) {
1500 /* UART0 configuration offset start from 0x40 */
1501 config_base = 0x40 + 0x08 * i;
1503 /* Calculate Real IO Port */
1504 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1506 /* Enable UART I/O port */
1507 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1509 /* Select 128-byte FIFO and 8x FIFO threshold */
1510 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1513 pci_write_config_byte(dev, config_base + 0x04,
1514 (u8)(iobase & 0xff));
1517 pci_write_config_byte(dev, config_base + 0x05,
1518 (u8)((iobase & 0xff00) >> 8));
1520 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1523 /* re-apply RS232/485 mode when
1524 * pciserial_resume_ports()
1526 port = serial8250_get_port(priv->line[i]);
1527 pci_fintek_rs485_config(&port->port, NULL);
1529 /* First init without port data
1530 * force init to RS232 Mode
1532 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1539 static int skip_tx_en_setup(struct serial_private *priv,
1540 const struct pciserial_board *board,
1541 struct uart_8250_port *port, int idx)
1543 port->port.quirks |= UPQ_NO_TXEN_TEST;
1544 dev_dbg(&priv->dev->dev,
1545 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1546 priv->dev->vendor, priv->dev->device,
1547 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1549 return pci_default_setup(priv, board, port, idx);
1552 static void kt_handle_break(struct uart_port *p)
1554 struct uart_8250_port *up = up_to_u8250p(p);
1556 * On receipt of a BI, serial device in Intel ME (Intel
1557 * management engine) needs to have its fifos cleared for sane
1558 * SOL (Serial Over Lan) output.
1560 serial8250_clear_and_reinit_fifos(up);
1563 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1565 struct uart_8250_port *up = up_to_u8250p(p);
1569 * When the Intel ME (management engine) gets reset its serial
1570 * port registers could return 0 momentarily. Functions like
1571 * serial8250_console_write, read and save the IER, perform
1572 * some operation and then restore it. In order to avoid
1573 * setting IER register inadvertently to 0, if the value read
1574 * is 0, double check with ier value in uart_8250_port and use
1575 * that instead. up->ier should be the same value as what is
1576 * currently configured.
1578 val = inb(p->iobase + offset);
1579 if (offset == UART_IER) {
1586 static int kt_serial_setup(struct serial_private *priv,
1587 const struct pciserial_board *board,
1588 struct uart_8250_port *port, int idx)
1590 port->port.flags |= UPF_BUG_THRE;
1591 port->port.serial_in = kt_serial_in;
1592 port->port.handle_break = kt_handle_break;
1593 return skip_tx_en_setup(priv, board, port, idx);
1596 static int pci_eg20t_init(struct pci_dev *dev)
1598 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1606 pci_wch_ch353_setup(struct serial_private *priv,
1607 const struct pciserial_board *board,
1608 struct uart_8250_port *port, int idx)
1610 port->port.flags |= UPF_FIXED_TYPE;
1611 port->port.type = PORT_16550A;
1612 return pci_default_setup(priv, board, port, idx);
1616 pci_wch_ch355_setup(struct serial_private *priv,
1617 const struct pciserial_board *board,
1618 struct uart_8250_port *port, int idx)
1620 port->port.flags |= UPF_FIXED_TYPE;
1621 port->port.type = PORT_16550A;
1622 return pci_default_setup(priv, board, port, idx);
1626 pci_wch_ch38x_setup(struct serial_private *priv,
1627 const struct pciserial_board *board,
1628 struct uart_8250_port *port, int idx)
1630 port->port.flags |= UPF_FIXED_TYPE;
1631 port->port.type = PORT_16850;
1632 return pci_default_setup(priv, board, port, idx);
1635 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1636 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1637 #define PCI_DEVICE_ID_OCTPRO 0x0001
1638 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1639 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1640 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1641 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1642 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1643 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1644 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1645 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1646 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
1647 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
1648 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1649 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1650 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1651 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1652 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1653 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1654 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1655 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1656 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1657 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1658 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1659 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1660 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1661 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1662 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1663 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1664 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1665 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1666 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1667 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1668 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1669 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1670 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1671 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1672 #define PCI_VENDOR_ID_WCH 0x4348
1673 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1674 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1675 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1676 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1677 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1678 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1679 #define PCI_VENDOR_ID_AGESTAR 0x5372
1680 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1681 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1682 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1684 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1685 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1687 #define PCIE_VENDOR_ID_WCH 0x1c00
1688 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1689 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1690 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1692 #define PCI_VENDOR_ID_PERICOM 0x12D8
1693 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1694 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1695 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1696 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1698 #define PCI_VENDOR_ID_ACCESIO 0x494f
1699 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1700 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1701 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1702 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1703 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1704 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1705 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1706 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1707 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1708 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1709 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1710 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1711 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1712 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1713 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1714 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1715 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1716 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1717 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1718 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1719 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1720 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1721 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1722 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1723 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1724 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1725 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1726 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1727 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1728 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1729 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1730 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1731 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1735 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1736 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1737 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1740 * Master list of serial port init/setup/exit quirks.
1741 * This does not describe the general nature of the port.
1742 * (ie, baud base, number and location of ports, etc)
1744 * This list is ordered alphabetically by vendor then device.
1745 * Specific entries must come before more generic entries.
1747 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1749 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1752 .vendor = PCI_VENDOR_ID_AMCC,
1753 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1754 .subvendor = PCI_ANY_ID,
1755 .subdevice = PCI_ANY_ID,
1756 .setup = addidata_apci7800_setup,
1759 * AFAVLAB cards - these may be called via parport_serial
1760 * It is not clear whether this applies to all products.
1763 .vendor = PCI_VENDOR_ID_AFAVLAB,
1764 .device = PCI_ANY_ID,
1765 .subvendor = PCI_ANY_ID,
1766 .subdevice = PCI_ANY_ID,
1767 .setup = afavlab_setup,
1773 .vendor = PCI_VENDOR_ID_HP,
1774 .device = PCI_DEVICE_ID_HP_DIVA,
1775 .subvendor = PCI_ANY_ID,
1776 .subdevice = PCI_ANY_ID,
1777 .init = pci_hp_diva_init,
1778 .setup = pci_hp_diva_setup,
1784 .vendor = PCI_VENDOR_ID_INTEL,
1785 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1786 .subvendor = 0xe4bf,
1787 .subdevice = PCI_ANY_ID,
1788 .init = pci_inteli960ni_init,
1789 .setup = pci_default_setup,
1792 .vendor = PCI_VENDOR_ID_INTEL,
1793 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1794 .subvendor = PCI_ANY_ID,
1795 .subdevice = PCI_ANY_ID,
1796 .setup = skip_tx_en_setup,
1799 .vendor = PCI_VENDOR_ID_INTEL,
1800 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1801 .subvendor = PCI_ANY_ID,
1802 .subdevice = PCI_ANY_ID,
1803 .setup = skip_tx_en_setup,
1806 .vendor = PCI_VENDOR_ID_INTEL,
1807 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1808 .subvendor = PCI_ANY_ID,
1809 .subdevice = PCI_ANY_ID,
1810 .setup = skip_tx_en_setup,
1813 .vendor = PCI_VENDOR_ID_INTEL,
1814 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1815 .subvendor = PCI_ANY_ID,
1816 .subdevice = PCI_ANY_ID,
1817 .setup = ce4100_serial_setup,
1820 .vendor = PCI_VENDOR_ID_INTEL,
1821 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1822 .subvendor = PCI_ANY_ID,
1823 .subdevice = PCI_ANY_ID,
1824 .setup = kt_serial_setup,
1830 .vendor = PCI_VENDOR_ID_ITE,
1831 .device = PCI_DEVICE_ID_ITE_8872,
1832 .subvendor = PCI_ANY_ID,
1833 .subdevice = PCI_ANY_ID,
1834 .init = pci_ite887x_init,
1835 .setup = pci_default_setup,
1836 .exit = pci_ite887x_exit,
1839 * National Instruments
1842 .vendor = PCI_VENDOR_ID_NI,
1843 .device = PCI_DEVICE_ID_NI_PCI23216,
1844 .subvendor = PCI_ANY_ID,
1845 .subdevice = PCI_ANY_ID,
1846 .init = pci_ni8420_init,
1847 .setup = pci_default_setup,
1848 .exit = pci_ni8420_exit,
1851 .vendor = PCI_VENDOR_ID_NI,
1852 .device = PCI_DEVICE_ID_NI_PCI2328,
1853 .subvendor = PCI_ANY_ID,
1854 .subdevice = PCI_ANY_ID,
1855 .init = pci_ni8420_init,
1856 .setup = pci_default_setup,
1857 .exit = pci_ni8420_exit,
1860 .vendor = PCI_VENDOR_ID_NI,
1861 .device = PCI_DEVICE_ID_NI_PCI2324,
1862 .subvendor = PCI_ANY_ID,
1863 .subdevice = PCI_ANY_ID,
1864 .init = pci_ni8420_init,
1865 .setup = pci_default_setup,
1866 .exit = pci_ni8420_exit,
1869 .vendor = PCI_VENDOR_ID_NI,
1870 .device = PCI_DEVICE_ID_NI_PCI2322,
1871 .subvendor = PCI_ANY_ID,
1872 .subdevice = PCI_ANY_ID,
1873 .init = pci_ni8420_init,
1874 .setup = pci_default_setup,
1875 .exit = pci_ni8420_exit,
1878 .vendor = PCI_VENDOR_ID_NI,
1879 .device = PCI_DEVICE_ID_NI_PCI2324I,
1880 .subvendor = PCI_ANY_ID,
1881 .subdevice = PCI_ANY_ID,
1882 .init = pci_ni8420_init,
1883 .setup = pci_default_setup,
1884 .exit = pci_ni8420_exit,
1887 .vendor = PCI_VENDOR_ID_NI,
1888 .device = PCI_DEVICE_ID_NI_PCI2322I,
1889 .subvendor = PCI_ANY_ID,
1890 .subdevice = PCI_ANY_ID,
1891 .init = pci_ni8420_init,
1892 .setup = pci_default_setup,
1893 .exit = pci_ni8420_exit,
1896 .vendor = PCI_VENDOR_ID_NI,
1897 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1898 .subvendor = PCI_ANY_ID,
1899 .subdevice = PCI_ANY_ID,
1900 .init = pci_ni8420_init,
1901 .setup = pci_default_setup,
1902 .exit = pci_ni8420_exit,
1905 .vendor = PCI_VENDOR_ID_NI,
1906 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1907 .subvendor = PCI_ANY_ID,
1908 .subdevice = PCI_ANY_ID,
1909 .init = pci_ni8420_init,
1910 .setup = pci_default_setup,
1911 .exit = pci_ni8420_exit,
1914 .vendor = PCI_VENDOR_ID_NI,
1915 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1916 .subvendor = PCI_ANY_ID,
1917 .subdevice = PCI_ANY_ID,
1918 .init = pci_ni8420_init,
1919 .setup = pci_default_setup,
1920 .exit = pci_ni8420_exit,
1923 .vendor = PCI_VENDOR_ID_NI,
1924 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1925 .subvendor = PCI_ANY_ID,
1926 .subdevice = PCI_ANY_ID,
1927 .init = pci_ni8420_init,
1928 .setup = pci_default_setup,
1929 .exit = pci_ni8420_exit,
1932 .vendor = PCI_VENDOR_ID_NI,
1933 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1934 .subvendor = PCI_ANY_ID,
1935 .subdevice = PCI_ANY_ID,
1936 .init = pci_ni8420_init,
1937 .setup = pci_default_setup,
1938 .exit = pci_ni8420_exit,
1941 .vendor = PCI_VENDOR_ID_NI,
1942 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1943 .subvendor = PCI_ANY_ID,
1944 .subdevice = PCI_ANY_ID,
1945 .init = pci_ni8420_init,
1946 .setup = pci_default_setup,
1947 .exit = pci_ni8420_exit,
1950 .vendor = PCI_VENDOR_ID_NI,
1951 .device = PCI_ANY_ID,
1952 .subvendor = PCI_ANY_ID,
1953 .subdevice = PCI_ANY_ID,
1954 .init = pci_ni8430_init,
1955 .setup = pci_ni8430_setup,
1956 .exit = pci_ni8430_exit,
1960 .vendor = PCI_VENDOR_ID_QUATECH,
1961 .device = PCI_ANY_ID,
1962 .subvendor = PCI_ANY_ID,
1963 .subdevice = PCI_ANY_ID,
1964 .init = pci_quatech_init,
1965 .setup = pci_quatech_setup,
1966 .exit = pci_quatech_exit,
1972 .vendor = PCI_VENDOR_ID_PANACOM,
1973 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1974 .subvendor = PCI_ANY_ID,
1975 .subdevice = PCI_ANY_ID,
1976 .init = pci_plx9050_init,
1977 .setup = pci_default_setup,
1978 .exit = pci_plx9050_exit,
1981 .vendor = PCI_VENDOR_ID_PANACOM,
1982 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1983 .subvendor = PCI_ANY_ID,
1984 .subdevice = PCI_ANY_ID,
1985 .init = pci_plx9050_init,
1986 .setup = pci_default_setup,
1987 .exit = pci_plx9050_exit,
1990 * Pericom (Only 7954 - It have a offset jump for port 4)
1993 .vendor = PCI_VENDOR_ID_PERICOM,
1994 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
1995 .subvendor = PCI_ANY_ID,
1996 .subdevice = PCI_ANY_ID,
1997 .setup = pci_pericom_setup,
2003 .vendor = PCI_VENDOR_ID_PLX,
2004 .device = PCI_DEVICE_ID_PLX_9050,
2005 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2006 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2007 .init = pci_plx9050_init,
2008 .setup = pci_default_setup,
2009 .exit = pci_plx9050_exit,
2012 .vendor = PCI_VENDOR_ID_PLX,
2013 .device = PCI_DEVICE_ID_PLX_9050,
2014 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2015 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2016 .init = pci_plx9050_init,
2017 .setup = pci_default_setup,
2018 .exit = pci_plx9050_exit,
2021 .vendor = PCI_VENDOR_ID_PLX,
2022 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2023 .subvendor = PCI_VENDOR_ID_PLX,
2024 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2025 .init = pci_plx9050_init,
2026 .setup = pci_default_setup,
2027 .exit = pci_plx9050_exit,
2030 .vendor = PCI_VENDOR_ID_ACCESIO,
2031 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2032 .subvendor = PCI_ANY_ID,
2033 .subdevice = PCI_ANY_ID,
2034 .setup = pci_pericom_setup,
2037 .vendor = PCI_VENDOR_ID_ACCESIO,
2038 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2039 .subvendor = PCI_ANY_ID,
2040 .subdevice = PCI_ANY_ID,
2041 .setup = pci_pericom_setup,
2044 .vendor = PCI_VENDOR_ID_ACCESIO,
2045 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2046 .subvendor = PCI_ANY_ID,
2047 .subdevice = PCI_ANY_ID,
2048 .setup = pci_pericom_setup,
2051 .vendor = PCI_VENDOR_ID_ACCESIO,
2052 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2053 .subvendor = PCI_ANY_ID,
2054 .subdevice = PCI_ANY_ID,
2055 .setup = pci_pericom_setup,
2058 .vendor = PCI_VENDOR_ID_ACCESIO,
2059 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2060 .subvendor = PCI_ANY_ID,
2061 .subdevice = PCI_ANY_ID,
2062 .setup = pci_pericom_setup,
2065 .vendor = PCI_VENDOR_ID_ACCESIO,
2066 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2067 .subvendor = PCI_ANY_ID,
2068 .subdevice = PCI_ANY_ID,
2069 .setup = pci_pericom_setup,
2072 .vendor = PCI_VENDOR_ID_ACCESIO,
2073 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2074 .subvendor = PCI_ANY_ID,
2075 .subdevice = PCI_ANY_ID,
2076 .setup = pci_pericom_setup,
2079 .vendor = PCI_VENDOR_ID_ACCESIO,
2080 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2081 .subvendor = PCI_ANY_ID,
2082 .subdevice = PCI_ANY_ID,
2083 .setup = pci_pericom_setup,
2086 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2087 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2088 .subvendor = PCI_ANY_ID,
2089 .subdevice = PCI_ANY_ID,
2090 .setup = pci_pericom_setup,
2093 .vendor = PCI_VENDOR_ID_ACCESIO,
2094 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2095 .subvendor = PCI_ANY_ID,
2096 .subdevice = PCI_ANY_ID,
2097 .setup = pci_pericom_setup,
2100 .vendor = PCI_VENDOR_ID_ACCESIO,
2101 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2102 .subvendor = PCI_ANY_ID,
2103 .subdevice = PCI_ANY_ID,
2104 .setup = pci_pericom_setup,
2107 .vendor = PCI_VENDOR_ID_ACCESIO,
2108 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2109 .subvendor = PCI_ANY_ID,
2110 .subdevice = PCI_ANY_ID,
2111 .setup = pci_pericom_setup,
2114 .vendor = PCI_VENDOR_ID_ACCESIO,
2115 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2116 .subvendor = PCI_ANY_ID,
2117 .subdevice = PCI_ANY_ID,
2118 .setup = pci_pericom_setup,
2121 .vendor = PCI_VENDOR_ID_ACCESIO,
2122 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2123 .subvendor = PCI_ANY_ID,
2124 .subdevice = PCI_ANY_ID,
2125 .setup = pci_pericom_setup,
2128 .vendor = PCI_VENDOR_ID_ACCESIO,
2129 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2130 .subvendor = PCI_ANY_ID,
2131 .subdevice = PCI_ANY_ID,
2132 .setup = pci_pericom_setup,
2135 * SBS Technologies, Inc., PMC-OCTALPRO 232
2138 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2139 .device = PCI_DEVICE_ID_OCTPRO,
2140 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2141 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2147 * SBS Technologies, Inc., PMC-OCTALPRO 422
2150 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2151 .device = PCI_DEVICE_ID_OCTPRO,
2152 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2153 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2159 * SBS Technologies, Inc., P-Octal 232
2162 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2163 .device = PCI_DEVICE_ID_OCTPRO,
2164 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2165 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2171 * SBS Technologies, Inc., P-Octal 422
2174 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2175 .device = PCI_DEVICE_ID_OCTPRO,
2176 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2177 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2183 * SIIG cards - these may be called via parport_serial
2186 .vendor = PCI_VENDOR_ID_SIIG,
2187 .device = PCI_ANY_ID,
2188 .subvendor = PCI_ANY_ID,
2189 .subdevice = PCI_ANY_ID,
2190 .init = pci_siig_init,
2191 .setup = pci_siig_setup,
2197 .vendor = PCI_VENDOR_ID_TITAN,
2198 .device = PCI_DEVICE_ID_TITAN_400L,
2199 .subvendor = PCI_ANY_ID,
2200 .subdevice = PCI_ANY_ID,
2201 .setup = titan_400l_800l_setup,
2204 .vendor = PCI_VENDOR_ID_TITAN,
2205 .device = PCI_DEVICE_ID_TITAN_800L,
2206 .subvendor = PCI_ANY_ID,
2207 .subdevice = PCI_ANY_ID,
2208 .setup = titan_400l_800l_setup,
2214 .vendor = PCI_VENDOR_ID_TIMEDIA,
2215 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2216 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2217 .subdevice = PCI_ANY_ID,
2218 .probe = pci_timedia_probe,
2219 .init = pci_timedia_init,
2220 .setup = pci_timedia_setup,
2223 .vendor = PCI_VENDOR_ID_TIMEDIA,
2224 .device = PCI_ANY_ID,
2225 .subvendor = PCI_ANY_ID,
2226 .subdevice = PCI_ANY_ID,
2227 .setup = pci_timedia_setup,
2230 * SUNIX (Timedia) cards
2231 * Do not "probe" for these cards as there is at least one combination
2232 * card that should be handled by parport_pc that doesn't match the
2233 * rule in pci_timedia_probe.
2234 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2235 * There are some boards with part number SER5037AL that report
2236 * subdevice ID 0x0002.
2239 .vendor = PCI_VENDOR_ID_SUNIX,
2240 .device = PCI_DEVICE_ID_SUNIX_1999,
2241 .subvendor = PCI_VENDOR_ID_SUNIX,
2242 .subdevice = PCI_ANY_ID,
2243 .init = pci_timedia_init,
2244 .setup = pci_timedia_setup,
2250 .vendor = PCI_VENDOR_ID_XIRCOM,
2251 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2252 .subvendor = PCI_ANY_ID,
2253 .subdevice = PCI_ANY_ID,
2254 .init = pci_xircom_init,
2255 .setup = pci_default_setup,
2258 * Netmos cards - these may be called via parport_serial
2261 .vendor = PCI_VENDOR_ID_NETMOS,
2262 .device = PCI_ANY_ID,
2263 .subvendor = PCI_ANY_ID,
2264 .subdevice = PCI_ANY_ID,
2265 .init = pci_netmos_init,
2266 .setup = pci_netmos_9900_setup,
2269 * EndRun Technologies
2272 .vendor = PCI_VENDOR_ID_ENDRUN,
2273 .device = PCI_ANY_ID,
2274 .subvendor = PCI_ANY_ID,
2275 .subdevice = PCI_ANY_ID,
2276 .init = pci_endrun_init,
2277 .setup = pci_default_setup,
2280 * For Oxford Semiconductor Tornado based devices
2283 .vendor = PCI_VENDOR_ID_OXSEMI,
2284 .device = PCI_ANY_ID,
2285 .subvendor = PCI_ANY_ID,
2286 .subdevice = PCI_ANY_ID,
2287 .init = pci_oxsemi_tornado_init,
2288 .setup = pci_default_setup,
2291 .vendor = PCI_VENDOR_ID_MAINPINE,
2292 .device = PCI_ANY_ID,
2293 .subvendor = PCI_ANY_ID,
2294 .subdevice = PCI_ANY_ID,
2295 .init = pci_oxsemi_tornado_init,
2296 .setup = pci_default_setup,
2299 .vendor = PCI_VENDOR_ID_DIGI,
2300 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2301 .subvendor = PCI_SUBVENDOR_ID_IBM,
2302 .subdevice = PCI_ANY_ID,
2303 .init = pci_oxsemi_tornado_init,
2304 .setup = pci_default_setup,
2307 .vendor = PCI_VENDOR_ID_INTEL,
2309 .subvendor = PCI_ANY_ID,
2310 .subdevice = PCI_ANY_ID,
2311 .init = pci_eg20t_init,
2312 .setup = pci_default_setup,
2315 .vendor = PCI_VENDOR_ID_INTEL,
2317 .subvendor = PCI_ANY_ID,
2318 .subdevice = PCI_ANY_ID,
2319 .init = pci_eg20t_init,
2320 .setup = pci_default_setup,
2323 .vendor = PCI_VENDOR_ID_INTEL,
2325 .subvendor = PCI_ANY_ID,
2326 .subdevice = PCI_ANY_ID,
2327 .init = pci_eg20t_init,
2328 .setup = pci_default_setup,
2331 .vendor = PCI_VENDOR_ID_INTEL,
2333 .subvendor = PCI_ANY_ID,
2334 .subdevice = PCI_ANY_ID,
2335 .init = pci_eg20t_init,
2336 .setup = pci_default_setup,
2341 .subvendor = PCI_ANY_ID,
2342 .subdevice = PCI_ANY_ID,
2343 .init = pci_eg20t_init,
2344 .setup = pci_default_setup,
2349 .subvendor = PCI_ANY_ID,
2350 .subdevice = PCI_ANY_ID,
2351 .init = pci_eg20t_init,
2352 .setup = pci_default_setup,
2357 .subvendor = PCI_ANY_ID,
2358 .subdevice = PCI_ANY_ID,
2359 .init = pci_eg20t_init,
2360 .setup = pci_default_setup,
2365 .subvendor = PCI_ANY_ID,
2366 .subdevice = PCI_ANY_ID,
2367 .init = pci_eg20t_init,
2368 .setup = pci_default_setup,
2373 .subvendor = PCI_ANY_ID,
2374 .subdevice = PCI_ANY_ID,
2375 .init = pci_eg20t_init,
2376 .setup = pci_default_setup,
2379 * Cronyx Omega PCI (PLX-chip based)
2382 .vendor = PCI_VENDOR_ID_PLX,
2383 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2384 .subvendor = PCI_ANY_ID,
2385 .subdevice = PCI_ANY_ID,
2386 .setup = pci_omegapci_setup,
2388 /* WCH CH353 1S1P card (16550 clone) */
2390 .vendor = PCI_VENDOR_ID_WCH,
2391 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2392 .subvendor = PCI_ANY_ID,
2393 .subdevice = PCI_ANY_ID,
2394 .setup = pci_wch_ch353_setup,
2396 /* WCH CH353 2S1P card (16550 clone) */
2398 .vendor = PCI_VENDOR_ID_WCH,
2399 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2400 .subvendor = PCI_ANY_ID,
2401 .subdevice = PCI_ANY_ID,
2402 .setup = pci_wch_ch353_setup,
2404 /* WCH CH353 4S card (16550 clone) */
2406 .vendor = PCI_VENDOR_ID_WCH,
2407 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2408 .subvendor = PCI_ANY_ID,
2409 .subdevice = PCI_ANY_ID,
2410 .setup = pci_wch_ch353_setup,
2412 /* WCH CH353 2S1PF card (16550 clone) */
2414 .vendor = PCI_VENDOR_ID_WCH,
2415 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2416 .subvendor = PCI_ANY_ID,
2417 .subdevice = PCI_ANY_ID,
2418 .setup = pci_wch_ch353_setup,
2420 /* WCH CH352 2S card (16550 clone) */
2422 .vendor = PCI_VENDOR_ID_WCH,
2423 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2424 .subvendor = PCI_ANY_ID,
2425 .subdevice = PCI_ANY_ID,
2426 .setup = pci_wch_ch353_setup,
2428 /* WCH CH355 4S card (16550 clone) */
2430 .vendor = PCI_VENDOR_ID_WCH,
2431 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2432 .subvendor = PCI_ANY_ID,
2433 .subdevice = PCI_ANY_ID,
2434 .setup = pci_wch_ch355_setup,
2436 /* WCH CH382 2S card (16850 clone) */
2438 .vendor = PCIE_VENDOR_ID_WCH,
2439 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2440 .subvendor = PCI_ANY_ID,
2441 .subdevice = PCI_ANY_ID,
2442 .setup = pci_wch_ch38x_setup,
2444 /* WCH CH382 2S1P card (16850 clone) */
2446 .vendor = PCIE_VENDOR_ID_WCH,
2447 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2448 .subvendor = PCI_ANY_ID,
2449 .subdevice = PCI_ANY_ID,
2450 .setup = pci_wch_ch38x_setup,
2452 /* WCH CH384 4S card (16850 clone) */
2454 .vendor = PCIE_VENDOR_ID_WCH,
2455 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2456 .subvendor = PCI_ANY_ID,
2457 .subdevice = PCI_ANY_ID,
2458 .setup = pci_wch_ch38x_setup,
2461 * Broadcom TruManage (NetXtreme)
2464 .vendor = PCI_VENDOR_ID_BROADCOM,
2465 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2466 .subvendor = PCI_ANY_ID,
2467 .subdevice = PCI_ANY_ID,
2468 .setup = pci_brcm_trumanage_setup,
2473 .subvendor = PCI_ANY_ID,
2474 .subdevice = PCI_ANY_ID,
2475 .setup = pci_fintek_setup,
2476 .init = pci_fintek_init,
2481 .subvendor = PCI_ANY_ID,
2482 .subdevice = PCI_ANY_ID,
2483 .setup = pci_fintek_setup,
2484 .init = pci_fintek_init,
2489 .subvendor = PCI_ANY_ID,
2490 .subdevice = PCI_ANY_ID,
2491 .setup = pci_fintek_setup,
2492 .init = pci_fintek_init,
2496 * Default "match everything" terminator entry
2499 .vendor = PCI_ANY_ID,
2500 .device = PCI_ANY_ID,
2501 .subvendor = PCI_ANY_ID,
2502 .subdevice = PCI_ANY_ID,
2503 .setup = pci_default_setup,
2507 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2509 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2512 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2514 struct pci_serial_quirk *quirk;
2516 for (quirk = pci_serial_quirks; ; quirk++)
2517 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2518 quirk_id_matches(quirk->device, dev->device) &&
2519 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2520 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2525 static inline int get_pci_irq(struct pci_dev *dev,
2526 const struct pciserial_board *board)
2528 if (board->flags & FL_NOIRQ)
2535 * This is the configuration table for all of the PCI serial boards
2536 * which we support. It is directly indexed by the pci_board_num_t enum
2537 * value, which is encoded in the pci_device_id PCI probe table's
2538 * driver_data member.
2540 * The makeup of these names are:
2541 * pbn_bn{_bt}_n_baud{_offsetinhex}
2543 * bn = PCI BAR number
2544 * bt = Index using PCI BARs
2545 * n = number of serial ports
2547 * offsetinhex = offset for each sequential port (in hex)
2549 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2551 * Please note: in theory if n = 1, _bt infix should make no difference.
2552 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2554 enum pci_board_num_t {
2648 * Board-specific versions.
2654 pbn_endrun_2_3906250,
2656 pbn_oxsemi_1_4000000,
2657 pbn_oxsemi_2_4000000,
2658 pbn_oxsemi_4_4000000,
2659 pbn_oxsemi_8_4000000,
2671 pbn_ADDIDATA_PCIe_1_3906250,
2672 pbn_ADDIDATA_PCIe_2_3906250,
2673 pbn_ADDIDATA_PCIe_4_3906250,
2674 pbn_ADDIDATA_PCIe_8_3906250,
2675 pbn_ce4100_1_115200,
2677 pbn_NETMOS9900_2s_115200,
2684 pbn_pericom_PI7C9X7951,
2685 pbn_pericom_PI7C9X7952,
2686 pbn_pericom_PI7C9X7954,
2687 pbn_pericom_PI7C9X7958,
2691 * uart_offset - the space between channels
2692 * reg_shift - describes how the UART registers are mapped
2693 * to PCI memory by the card.
2694 * For example IER register on SBS, Inc. PMC-OctPro is located at
2695 * offset 0x10 from the UART base, while UART_IER is defined as 1
2696 * in include/linux/serial_reg.h,
2697 * see first lines of serial_in() and serial_out() in 8250.c
2700 static struct pciserial_board pci_boards[] = {
2704 .base_baud = 115200,
2707 [pbn_b0_1_115200] = {
2710 .base_baud = 115200,
2713 [pbn_b0_2_115200] = {
2716 .base_baud = 115200,
2719 [pbn_b0_4_115200] = {
2722 .base_baud = 115200,
2725 [pbn_b0_5_115200] = {
2728 .base_baud = 115200,
2731 [pbn_b0_8_115200] = {
2734 .base_baud = 115200,
2737 [pbn_b0_1_921600] = {
2740 .base_baud = 921600,
2743 [pbn_b0_2_921600] = {
2746 .base_baud = 921600,
2749 [pbn_b0_4_921600] = {
2752 .base_baud = 921600,
2756 [pbn_b0_2_1130000] = {
2759 .base_baud = 1130000,
2763 [pbn_b0_4_1152000] = {
2766 .base_baud = 1152000,
2770 [pbn_b0_4_1250000] = {
2773 .base_baud = 1250000,
2777 [pbn_b0_2_1843200] = {
2780 .base_baud = 1843200,
2783 [pbn_b0_4_1843200] = {
2786 .base_baud = 1843200,
2790 [pbn_b0_1_4000000] = {
2793 .base_baud = 4000000,
2797 [pbn_b0_bt_1_115200] = {
2798 .flags = FL_BASE0|FL_BASE_BARS,
2800 .base_baud = 115200,
2803 [pbn_b0_bt_2_115200] = {
2804 .flags = FL_BASE0|FL_BASE_BARS,
2806 .base_baud = 115200,
2809 [pbn_b0_bt_4_115200] = {
2810 .flags = FL_BASE0|FL_BASE_BARS,
2812 .base_baud = 115200,
2815 [pbn_b0_bt_8_115200] = {
2816 .flags = FL_BASE0|FL_BASE_BARS,
2818 .base_baud = 115200,
2822 [pbn_b0_bt_1_460800] = {
2823 .flags = FL_BASE0|FL_BASE_BARS,
2825 .base_baud = 460800,
2828 [pbn_b0_bt_2_460800] = {
2829 .flags = FL_BASE0|FL_BASE_BARS,
2831 .base_baud = 460800,
2834 [pbn_b0_bt_4_460800] = {
2835 .flags = FL_BASE0|FL_BASE_BARS,
2837 .base_baud = 460800,
2841 [pbn_b0_bt_1_921600] = {
2842 .flags = FL_BASE0|FL_BASE_BARS,
2844 .base_baud = 921600,
2847 [pbn_b0_bt_2_921600] = {
2848 .flags = FL_BASE0|FL_BASE_BARS,
2850 .base_baud = 921600,
2853 [pbn_b0_bt_4_921600] = {
2854 .flags = FL_BASE0|FL_BASE_BARS,
2856 .base_baud = 921600,
2859 [pbn_b0_bt_8_921600] = {
2860 .flags = FL_BASE0|FL_BASE_BARS,
2862 .base_baud = 921600,
2866 [pbn_b1_1_115200] = {
2869 .base_baud = 115200,
2872 [pbn_b1_2_115200] = {
2875 .base_baud = 115200,
2878 [pbn_b1_4_115200] = {
2881 .base_baud = 115200,
2884 [pbn_b1_8_115200] = {
2887 .base_baud = 115200,
2890 [pbn_b1_16_115200] = {
2893 .base_baud = 115200,
2897 [pbn_b1_1_921600] = {
2900 .base_baud = 921600,
2903 [pbn_b1_2_921600] = {
2906 .base_baud = 921600,
2909 [pbn_b1_4_921600] = {
2912 .base_baud = 921600,
2915 [pbn_b1_8_921600] = {
2918 .base_baud = 921600,
2921 [pbn_b1_2_1250000] = {
2924 .base_baud = 1250000,
2928 [pbn_b1_bt_1_115200] = {
2929 .flags = FL_BASE1|FL_BASE_BARS,
2931 .base_baud = 115200,
2934 [pbn_b1_bt_2_115200] = {
2935 .flags = FL_BASE1|FL_BASE_BARS,
2937 .base_baud = 115200,
2940 [pbn_b1_bt_4_115200] = {
2941 .flags = FL_BASE1|FL_BASE_BARS,
2943 .base_baud = 115200,
2947 [pbn_b1_bt_2_921600] = {
2948 .flags = FL_BASE1|FL_BASE_BARS,
2950 .base_baud = 921600,
2954 [pbn_b1_1_1382400] = {
2957 .base_baud = 1382400,
2960 [pbn_b1_2_1382400] = {
2963 .base_baud = 1382400,
2966 [pbn_b1_4_1382400] = {
2969 .base_baud = 1382400,
2972 [pbn_b1_8_1382400] = {
2975 .base_baud = 1382400,
2979 [pbn_b2_1_115200] = {
2982 .base_baud = 115200,
2985 [pbn_b2_2_115200] = {
2988 .base_baud = 115200,
2991 [pbn_b2_4_115200] = {
2994 .base_baud = 115200,
2997 [pbn_b2_8_115200] = {
3000 .base_baud = 115200,
3004 [pbn_b2_1_460800] = {
3007 .base_baud = 460800,
3010 [pbn_b2_4_460800] = {
3013 .base_baud = 460800,
3016 [pbn_b2_8_460800] = {
3019 .base_baud = 460800,
3022 [pbn_b2_16_460800] = {
3025 .base_baud = 460800,
3029 [pbn_b2_1_921600] = {
3032 .base_baud = 921600,
3035 [pbn_b2_4_921600] = {
3038 .base_baud = 921600,
3041 [pbn_b2_8_921600] = {
3044 .base_baud = 921600,
3048 [pbn_b2_8_1152000] = {
3051 .base_baud = 1152000,
3055 [pbn_b2_bt_1_115200] = {
3056 .flags = FL_BASE2|FL_BASE_BARS,
3058 .base_baud = 115200,
3061 [pbn_b2_bt_2_115200] = {
3062 .flags = FL_BASE2|FL_BASE_BARS,
3064 .base_baud = 115200,
3067 [pbn_b2_bt_4_115200] = {
3068 .flags = FL_BASE2|FL_BASE_BARS,
3070 .base_baud = 115200,
3074 [pbn_b2_bt_2_921600] = {
3075 .flags = FL_BASE2|FL_BASE_BARS,
3077 .base_baud = 921600,
3080 [pbn_b2_bt_4_921600] = {
3081 .flags = FL_BASE2|FL_BASE_BARS,
3083 .base_baud = 921600,
3087 [pbn_b3_2_115200] = {
3090 .base_baud = 115200,
3093 [pbn_b3_4_115200] = {
3096 .base_baud = 115200,
3099 [pbn_b3_8_115200] = {
3102 .base_baud = 115200,
3106 [pbn_b4_bt_2_921600] = {
3109 .base_baud = 921600,
3112 [pbn_b4_bt_4_921600] = {
3115 .base_baud = 921600,
3118 [pbn_b4_bt_8_921600] = {
3121 .base_baud = 921600,
3126 * Entries following this are board-specific.
3135 .base_baud = 921600,
3136 .uart_offset = 0x400,
3140 .flags = FL_BASE2|FL_BASE_BARS,
3142 .base_baud = 921600,
3143 .uart_offset = 0x400,
3147 .flags = FL_BASE2|FL_BASE_BARS,
3149 .base_baud = 921600,
3150 .uart_offset = 0x400,
3154 /* I think this entry is broken - the first_offset looks wrong --rmk */
3155 [pbn_plx_romulus] = {
3158 .base_baud = 921600,
3159 .uart_offset = 8 << 2,
3161 .first_offset = 0x03,
3165 * EndRun Technologies
3166 * Uses the size of PCI Base region 0 to
3167 * signal now many ports are available
3168 * 2 port 952 Uart support
3170 [pbn_endrun_2_3906250] = {
3173 .base_baud = 3906250,
3174 .uart_offset = 0x200,
3175 .first_offset = 0x1000,
3179 * This board uses the size of PCI Base region 0 to
3180 * signal now many ports are available
3183 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3185 .base_baud = 115200,
3188 [pbn_oxsemi_1_4000000] = {
3191 .base_baud = 4000000,
3192 .uart_offset = 0x200,
3193 .first_offset = 0x1000,
3195 [pbn_oxsemi_2_4000000] = {
3198 .base_baud = 4000000,
3199 .uart_offset = 0x200,
3200 .first_offset = 0x1000,
3202 [pbn_oxsemi_4_4000000] = {
3205 .base_baud = 4000000,
3206 .uart_offset = 0x200,
3207 .first_offset = 0x1000,
3209 [pbn_oxsemi_8_4000000] = {
3212 .base_baud = 4000000,
3213 .uart_offset = 0x200,
3214 .first_offset = 0x1000,
3219 * EKF addition for i960 Boards form EKF with serial port.
3222 [pbn_intel_i960] = {
3225 .base_baud = 921600,
3226 .uart_offset = 8 << 2,
3228 .first_offset = 0x10000,
3231 .flags = FL_BASE0|FL_NOIRQ,
3233 .base_baud = 458333,
3236 .first_offset = 0x20178,
3240 * Computone - uses IOMEM.
3242 [pbn_computone_4] = {
3245 .base_baud = 921600,
3246 .uart_offset = 0x40,
3248 .first_offset = 0x200,
3250 [pbn_computone_6] = {
3253 .base_baud = 921600,
3254 .uart_offset = 0x40,
3256 .first_offset = 0x200,
3258 [pbn_computone_8] = {
3261 .base_baud = 921600,
3262 .uart_offset = 0x40,
3264 .first_offset = 0x200,
3269 .base_baud = 460800,
3274 * PA Semi PWRficient PA6T-1682M on-chip UART
3276 [pbn_pasemi_1682M] = {
3279 .base_baud = 8333333,
3282 * National Instruments 843x
3287 .base_baud = 3686400,
3288 .uart_offset = 0x10,
3289 .first_offset = 0x800,
3294 .base_baud = 3686400,
3295 .uart_offset = 0x10,
3296 .first_offset = 0x800,
3301 .base_baud = 3686400,
3302 .uart_offset = 0x10,
3303 .first_offset = 0x800,
3308 .base_baud = 3686400,
3309 .uart_offset = 0x10,
3310 .first_offset = 0x800,
3313 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3315 [pbn_ADDIDATA_PCIe_1_3906250] = {
3318 .base_baud = 3906250,
3319 .uart_offset = 0x200,
3320 .first_offset = 0x1000,
3322 [pbn_ADDIDATA_PCIe_2_3906250] = {
3325 .base_baud = 3906250,
3326 .uart_offset = 0x200,
3327 .first_offset = 0x1000,
3329 [pbn_ADDIDATA_PCIe_4_3906250] = {
3332 .base_baud = 3906250,
3333 .uart_offset = 0x200,
3334 .first_offset = 0x1000,
3336 [pbn_ADDIDATA_PCIe_8_3906250] = {
3339 .base_baud = 3906250,
3340 .uart_offset = 0x200,
3341 .first_offset = 0x1000,
3343 [pbn_ce4100_1_115200] = {
3344 .flags = FL_BASE_BARS,
3346 .base_baud = 921600,
3352 .base_baud = 115200,
3353 .uart_offset = 0x200,
3355 [pbn_NETMOS9900_2s_115200] = {
3358 .base_baud = 115200,
3360 [pbn_brcm_trumanage] = {
3364 .base_baud = 115200,
3369 .base_baud = 115200,
3370 .first_offset = 0x40,
3375 .base_baud = 115200,
3376 .first_offset = 0x40,
3381 .base_baud = 115200,
3382 .first_offset = 0x40,
3387 .base_baud = 115200,
3389 .first_offset = 0xC0,
3394 .base_baud = 115200,
3396 .first_offset = 0xC0,
3399 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3401 [pbn_pericom_PI7C9X7951] = {
3404 .base_baud = 921600,
3407 [pbn_pericom_PI7C9X7952] = {
3410 .base_baud = 921600,
3413 [pbn_pericom_PI7C9X7954] = {
3416 .base_baud = 921600,
3419 [pbn_pericom_PI7C9X7958] = {
3422 .base_baud = 921600,
3427 static const struct pci_device_id blacklist[] = {
3429 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3430 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3431 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3433 /* multi-io cards handled by parport_serial */
3434 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3435 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3436 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3438 /* Moxa Smartio MUE boards handled by 8250_moxa */
3439 { PCI_VDEVICE(MOXA, 0x1024), },
3440 { PCI_VDEVICE(MOXA, 0x1025), },
3441 { PCI_VDEVICE(MOXA, 0x1045), },
3442 { PCI_VDEVICE(MOXA, 0x1144), },
3443 { PCI_VDEVICE(MOXA, 0x1160), },
3444 { PCI_VDEVICE(MOXA, 0x1161), },
3445 { PCI_VDEVICE(MOXA, 0x1182), },
3446 { PCI_VDEVICE(MOXA, 0x1183), },
3447 { PCI_VDEVICE(MOXA, 0x1322), },
3448 { PCI_VDEVICE(MOXA, 0x1342), },
3449 { PCI_VDEVICE(MOXA, 0x1381), },
3450 { PCI_VDEVICE(MOXA, 0x1683), },
3452 /* Intel platforms with MID UART */
3453 { PCI_VDEVICE(INTEL, 0x081b), },
3454 { PCI_VDEVICE(INTEL, 0x081c), },
3455 { PCI_VDEVICE(INTEL, 0x081d), },
3456 { PCI_VDEVICE(INTEL, 0x1191), },
3457 { PCI_VDEVICE(INTEL, 0x19d8), },
3459 /* Intel platforms with DesignWare UART */
3460 { PCI_VDEVICE(INTEL, 0x0936), },
3461 { PCI_VDEVICE(INTEL, 0x0f0a), },
3462 { PCI_VDEVICE(INTEL, 0x0f0c), },
3463 { PCI_VDEVICE(INTEL, 0x228a), },
3464 { PCI_VDEVICE(INTEL, 0x228c), },
3465 { PCI_VDEVICE(INTEL, 0x9ce3), },
3466 { PCI_VDEVICE(INTEL, 0x9ce4), },
3469 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3470 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3473 static int serial_pci_is_class_communication(struct pci_dev *dev)
3476 * If it is not a communications device or the programming
3477 * interface is greater than 6, give up.
3479 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3480 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3481 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3482 (dev->class & 0xff) > 6)
3488 static int serial_pci_is_blacklisted(struct pci_dev *dev)
3490 const struct pci_device_id *bldev;
3493 * Do not access blacklisted devices that are known not to
3494 * feature serial ports or are handled by other modules.
3496 for (bldev = blacklist;
3497 bldev < blacklist + ARRAY_SIZE(blacklist);
3499 if (dev->vendor == bldev->vendor &&
3500 dev->device == bldev->device)
3508 * Given a complete unknown PCI device, try to use some heuristics to
3509 * guess what the configuration might be, based on the pitiful PCI
3510 * serial specs. Returns 0 on success, -ENODEV on failure.
3513 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3515 int num_iomem, num_port, first_port = -1, i;
3518 rc = serial_pci_is_class_communication(dev);
3523 * Should we try to make guesses for multiport serial devices later?
3525 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3528 num_iomem = num_port = 0;
3529 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3530 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3532 if (first_port == -1)
3535 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3540 * If there is 1 or 0 iomem regions, and exactly one port,
3541 * use it. We guess the number of ports based on the IO
3544 if (num_iomem <= 1 && num_port == 1) {
3545 board->flags = first_port;
3546 board->num_ports = pci_resource_len(dev, first_port) / 8;
3551 * Now guess if we've got a board which indexes by BARs.
3552 * Each IO BAR should be 8 bytes, and they should follow
3557 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3558 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3559 pci_resource_len(dev, i) == 8 &&
3560 (first_port == -1 || (first_port + num_port) == i)) {
3562 if (first_port == -1)
3568 board->flags = first_port | FL_BASE_BARS;
3569 board->num_ports = num_port;
3577 serial_pci_matches(const struct pciserial_board *board,
3578 const struct pciserial_board *guessed)
3581 board->num_ports == guessed->num_ports &&
3582 board->base_baud == guessed->base_baud &&
3583 board->uart_offset == guessed->uart_offset &&
3584 board->reg_shift == guessed->reg_shift &&
3585 board->first_offset == guessed->first_offset;
3588 struct serial_private *
3589 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3591 struct uart_8250_port uart;
3592 struct serial_private *priv;
3593 struct pci_serial_quirk *quirk;
3594 int rc, nr_ports, i;
3596 nr_ports = board->num_ports;
3599 * Find an init and setup quirks.
3601 quirk = find_quirk(dev);
3604 * Run the new-style initialization function.
3605 * The initialization function returns:
3607 * 0 - use board->num_ports
3608 * >0 - number of ports
3611 rc = quirk->init(dev);
3620 priv = kzalloc(sizeof(struct serial_private) +
3621 sizeof(unsigned int) * nr_ports,
3624 priv = ERR_PTR(-ENOMEM);
3629 priv->quirk = quirk;
3631 memset(&uart, 0, sizeof(uart));
3632 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3633 uart.port.uartclk = board->base_baud * 16;
3634 uart.port.irq = get_pci_irq(dev, board);
3635 uart.port.dev = &dev->dev;
3637 for (i = 0; i < nr_ports; i++) {
3638 if (quirk->setup(priv, board, &uart, i))
3641 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3642 uart.port.iobase, uart.port.irq, uart.port.iotype);
3644 priv->line[i] = serial8250_register_8250_port(&uart);
3645 if (priv->line[i] < 0) {
3647 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3648 uart.port.iobase, uart.port.irq,
3649 uart.port.iotype, priv->line[i]);
3654 priv->board = board;
3663 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3665 static void pciserial_detach_ports(struct serial_private *priv)
3667 struct pci_serial_quirk *quirk;
3670 for (i = 0; i < priv->nr; i++)
3671 serial8250_unregister_port(priv->line[i]);
3674 * Find the exit quirks.
3676 quirk = find_quirk(priv->dev);
3678 quirk->exit(priv->dev);
3681 void pciserial_remove_ports(struct serial_private *priv)
3683 pciserial_detach_ports(priv);
3686 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3688 void pciserial_suspend_ports(struct serial_private *priv)
3692 for (i = 0; i < priv->nr; i++)
3693 if (priv->line[i] >= 0)
3694 serial8250_suspend_port(priv->line[i]);
3697 * Ensure that every init quirk is properly torn down
3699 if (priv->quirk->exit)
3700 priv->quirk->exit(priv->dev);
3702 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3704 void pciserial_resume_ports(struct serial_private *priv)
3709 * Ensure that the board is correctly configured.
3711 if (priv->quirk->init)
3712 priv->quirk->init(priv->dev);
3714 for (i = 0; i < priv->nr; i++)
3715 if (priv->line[i] >= 0)
3716 serial8250_resume_port(priv->line[i]);
3718 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3721 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3722 * to the arrangement of serial ports on a PCI card.
3725 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3727 struct pci_serial_quirk *quirk;
3728 struct serial_private *priv;
3729 const struct pciserial_board *board;
3730 struct pciserial_board tmp;
3733 quirk = find_quirk(dev);
3735 rc = quirk->probe(dev);
3740 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3741 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3746 board = &pci_boards[ent->driver_data];
3748 rc = serial_pci_is_blacklisted(dev);
3752 rc = pcim_enable_device(dev);
3753 pci_save_state(dev);
3757 if (ent->driver_data == pbn_default) {
3759 * Use a copy of the pci_board entry for this;
3760 * avoid changing entries in the table.
3762 memcpy(&tmp, board, sizeof(struct pciserial_board));
3766 * We matched one of our class entries. Try to
3767 * determine the parameters of this board.
3769 rc = serial_pci_guess_board(dev, &tmp);
3774 * We matched an explicit entry. If we are able to
3775 * detect this boards settings with our heuristic,
3776 * then we no longer need this entry.
3778 memcpy(&tmp, &pci_boards[pbn_default],
3779 sizeof(struct pciserial_board));
3780 rc = serial_pci_guess_board(dev, &tmp);
3781 if (rc == 0 && serial_pci_matches(board, &tmp))
3782 moan_device("Redundant entry in serial pci_table.",
3786 priv = pciserial_init_ports(dev, board);
3788 return PTR_ERR(priv);
3790 pci_set_drvdata(dev, priv);
3794 static void pciserial_remove_one(struct pci_dev *dev)
3796 struct serial_private *priv = pci_get_drvdata(dev);
3798 pciserial_remove_ports(priv);
3801 #ifdef CONFIG_PM_SLEEP
3802 static int pciserial_suspend_one(struct device *dev)
3804 struct pci_dev *pdev = to_pci_dev(dev);
3805 struct serial_private *priv = pci_get_drvdata(pdev);
3808 pciserial_suspend_ports(priv);
3813 static int pciserial_resume_one(struct device *dev)
3815 struct pci_dev *pdev = to_pci_dev(dev);
3816 struct serial_private *priv = pci_get_drvdata(pdev);
3821 * The device may have been disabled. Re-enable it.
3823 err = pci_enable_device(pdev);
3824 /* FIXME: We cannot simply error out here */
3826 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
3827 pciserial_resume_ports(priv);
3833 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
3834 pciserial_resume_one);
3836 static const struct pci_device_id serial_pci_tbl[] = {
3837 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
3838 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
3840 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3841 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3842 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3844 /* Advantech also use 0x3618 and 0xf618 */
3845 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3846 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3848 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3849 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3851 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3852 PCI_SUBVENDOR_ID_CONNECT_TECH,
3853 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3855 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3856 PCI_SUBVENDOR_ID_CONNECT_TECH,
3857 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3859 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3860 PCI_SUBVENDOR_ID_CONNECT_TECH,
3861 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3863 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3864 PCI_SUBVENDOR_ID_CONNECT_TECH,
3865 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3867 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3868 PCI_SUBVENDOR_ID_CONNECT_TECH,
3869 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3871 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3872 PCI_SUBVENDOR_ID_CONNECT_TECH,
3873 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3875 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3876 PCI_SUBVENDOR_ID_CONNECT_TECH,
3877 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3879 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3880 PCI_SUBVENDOR_ID_CONNECT_TECH,
3881 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3883 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3884 PCI_SUBVENDOR_ID_CONNECT_TECH,
3885 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3887 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3888 PCI_SUBVENDOR_ID_CONNECT_TECH,
3889 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3891 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3892 PCI_SUBVENDOR_ID_CONNECT_TECH,
3893 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3895 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3896 PCI_SUBVENDOR_ID_CONNECT_TECH,
3897 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3899 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3900 PCI_SUBVENDOR_ID_CONNECT_TECH,
3901 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3903 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3904 PCI_SUBVENDOR_ID_CONNECT_TECH,
3905 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3907 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3908 PCI_SUBVENDOR_ID_CONNECT_TECH,
3909 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3911 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3912 PCI_SUBVENDOR_ID_CONNECT_TECH,
3913 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3915 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3916 PCI_SUBVENDOR_ID_CONNECT_TECH,
3917 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3919 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3920 PCI_VENDOR_ID_AFAVLAB,
3921 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3923 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3925 pbn_b2_bt_1_115200 },
3926 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3928 pbn_b2_bt_2_115200 },
3929 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3931 pbn_b2_bt_4_115200 },
3932 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3934 pbn_b2_bt_2_115200 },
3935 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3937 pbn_b2_bt_4_115200 },
3938 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3941 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3944 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3948 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3950 pbn_b2_bt_2_115200 },
3951 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953 pbn_b2_bt_2_921600 },
3955 * VScom SPCOM800, from sl@s.pl
3957 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3960 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3963 /* Unknown card - subdevice 0x1584 */
3964 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3966 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3968 /* Unknown card - subdevice 0x1588 */
3969 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3971 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3973 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3974 PCI_SUBVENDOR_ID_KEYSPAN,
3975 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3977 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3984 PCI_VENDOR_ID_ESDGMBH,
3985 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3987 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3988 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3989 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3991 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3992 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3993 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3995 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3996 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3997 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3999 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4000 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4001 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4003 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4004 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4005 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4007 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4008 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4009 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4011 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4012 PCI_SUBVENDOR_ID_EXSYS,
4013 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4016 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4019 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4020 0x10b5, 0x106a, 0, 0,
4023 * EndRun Technologies. PCI express device range.
4024 * EndRun PTP/1588 has 2 Native UARTs.
4026 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4028 pbn_endrun_2_3906250 },
4030 * Quatech cards. These actually have configurable clocks but for
4031 * now we just use the default.
4033 * 100 series are RS232, 200 series RS422,
4035 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4038 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4041 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4044 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4047 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4050 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4053 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4056 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4059 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4062 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4065 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4068 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4071 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4074 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4077 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4080 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4083 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4086 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4089 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4093 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4094 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4097 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4098 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4101 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4103 pbn_b0_bt_2_921600 },
4106 * The below card is a little controversial since it is the
4107 * subject of a PCI vendor/device ID clash. (See
4108 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4109 * For now just used the hex ID 0x950a.
4111 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4112 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4113 0, 0, pbn_b0_2_115200 },
4114 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4115 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4116 0, 0, pbn_b0_2_115200 },
4117 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4120 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4121 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4123 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4126 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128 pbn_b0_bt_2_921600 },
4129 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 * Oxford Semiconductor Inc. Tornado PCI express device range.
4136 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4139 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4142 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4144 pbn_oxsemi_1_4000000 },
4145 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4147 pbn_oxsemi_1_4000000 },
4148 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4151 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4154 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4156 pbn_oxsemi_1_4000000 },
4157 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4159 pbn_oxsemi_1_4000000 },
4160 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4163 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4166 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4169 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4172 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4174 pbn_oxsemi_2_4000000 },
4175 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4177 pbn_oxsemi_2_4000000 },
4178 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4180 pbn_oxsemi_4_4000000 },
4181 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4183 pbn_oxsemi_4_4000000 },
4184 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4186 pbn_oxsemi_8_4000000 },
4187 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189 pbn_oxsemi_8_4000000 },
4190 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4192 pbn_oxsemi_1_4000000 },
4193 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4195 pbn_oxsemi_1_4000000 },
4196 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198 pbn_oxsemi_1_4000000 },
4199 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201 pbn_oxsemi_1_4000000 },
4202 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204 pbn_oxsemi_1_4000000 },
4205 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207 pbn_oxsemi_1_4000000 },
4208 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210 pbn_oxsemi_1_4000000 },
4211 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213 pbn_oxsemi_1_4000000 },
4214 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 pbn_oxsemi_1_4000000 },
4217 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 pbn_oxsemi_1_4000000 },
4220 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222 pbn_oxsemi_1_4000000 },
4223 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225 pbn_oxsemi_1_4000000 },
4226 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 pbn_oxsemi_1_4000000 },
4229 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 pbn_oxsemi_1_4000000 },
4232 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 pbn_oxsemi_1_4000000 },
4235 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237 pbn_oxsemi_1_4000000 },
4238 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240 pbn_oxsemi_1_4000000 },
4241 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243 pbn_oxsemi_1_4000000 },
4244 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246 pbn_oxsemi_1_4000000 },
4247 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249 pbn_oxsemi_1_4000000 },
4250 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252 pbn_oxsemi_1_4000000 },
4253 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255 pbn_oxsemi_1_4000000 },
4256 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 pbn_oxsemi_1_4000000 },
4259 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 pbn_oxsemi_1_4000000 },
4262 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_oxsemi_1_4000000 },
4265 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_oxsemi_1_4000000 },
4269 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4271 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4272 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4273 pbn_oxsemi_1_4000000 },
4274 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4275 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4276 pbn_oxsemi_2_4000000 },
4277 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4278 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4279 pbn_oxsemi_4_4000000 },
4280 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4281 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4282 pbn_oxsemi_8_4000000 },
4285 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4287 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4288 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4289 pbn_oxsemi_2_4000000 },
4292 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4293 * from skokodyn@yahoo.com
4295 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4296 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4298 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4299 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4301 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4302 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4304 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4305 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4309 * Digitan DS560-558, from jimd@esoft.com
4311 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4316 * Titan Electronic cards
4317 * The 400L and 800L have a custom setup quirk.
4319 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4322 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4334 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_b1_bt_2_921600 },
4337 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_b0_bt_4_921600 },
4340 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b0_bt_8_921600 },
4343 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_b4_bt_2_921600 },
4346 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b4_bt_4_921600 },
4349 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_b4_bt_8_921600 },
4352 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4355 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4358 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4361 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363 pbn_oxsemi_1_4000000 },
4364 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366 pbn_oxsemi_2_4000000 },
4367 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369 pbn_oxsemi_4_4000000 },
4370 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372 pbn_oxsemi_8_4000000 },
4373 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375 pbn_oxsemi_2_4000000 },
4376 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378 pbn_oxsemi_2_4000000 },
4379 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381 pbn_b0_bt_2_921600 },
4382 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4385 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4388 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4391 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4395 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4398 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4401 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4404 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 pbn_b2_bt_2_921600 },
4407 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_b2_bt_2_921600 },
4410 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 pbn_b2_bt_2_921600 },
4413 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_b2_bt_4_921600 },
4416 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_b2_bt_4_921600 },
4419 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 pbn_b2_bt_4_921600 },
4422 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 pbn_b0_bt_2_921600 },
4434 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 pbn_b0_bt_2_921600 },
4437 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_b0_bt_2_921600 },
4440 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_b0_bt_4_921600 },
4443 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 pbn_b0_bt_4_921600 },
4446 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_b0_bt_4_921600 },
4449 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_b0_bt_8_921600 },
4452 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_b0_bt_8_921600 },
4455 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_b0_bt_8_921600 },
4460 * Computone devices submitted by Doug McNash dmcnash@computone.com
4462 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4463 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4464 0, 0, pbn_computone_4 },
4465 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4466 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4467 0, 0, pbn_computone_8 },
4468 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4469 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4470 0, 0, pbn_computone_6 },
4472 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4476 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4477 pbn_b0_bt_1_921600 },
4482 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4483 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4484 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4485 pbn_b0_bt_1_921600 },
4487 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4488 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4489 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4490 pbn_b0_bt_1_921600 },
4493 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4495 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_b0_bt_8_115200 },
4498 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_b0_bt_8_115200 },
4502 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 pbn_b0_bt_2_115200 },
4505 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 pbn_b0_bt_2_115200 },
4508 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_b0_bt_2_115200 },
4511 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 pbn_b0_bt_2_115200 },
4514 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 pbn_b0_bt_2_115200 },
4517 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519 pbn_b0_bt_4_460800 },
4520 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522 pbn_b0_bt_4_460800 },
4523 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 pbn_b0_bt_2_460800 },
4526 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528 pbn_b0_bt_2_460800 },
4529 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531 pbn_b0_bt_2_460800 },
4532 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534 pbn_b0_bt_1_115200 },
4535 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537 pbn_b0_bt_1_460800 },
4540 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4541 * Cards are identified by their subsystem vendor IDs, which
4542 * (in hex) match the model number.
4544 * Note that JC140x are RS422/485 cards which require ox950
4545 * ACR = 0x10, and as such are not currently fully supported.
4547 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4548 0x1204, 0x0004, 0, 0,
4550 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4551 0x1208, 0x0004, 0, 0,
4553 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4554 0x1402, 0x0002, 0, 0,
4555 pbn_b0_2_921600 }, */
4556 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4557 0x1404, 0x0004, 0, 0,
4558 pbn_b0_4_921600 }, */
4559 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4560 0x1208, 0x0004, 0, 0,
4563 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4564 0x1204, 0x0004, 0, 0,
4566 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4567 0x1208, 0x0004, 0, 0,
4569 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4570 0x1208, 0x0004, 0, 0,
4573 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4575 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4582 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 * RAStel 2 port modem, gerg@moreton.com.au
4589 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591 pbn_b2_bt_2_115200 },
4594 * EKF addition for i960 Boards form EKF with serial port
4596 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4597 0xE4BF, PCI_ANY_ID, 0, 0,
4601 * Xircom Cardbus/Ethernet combos
4603 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4609 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 * Untested PCI modems, sent in from various folks...
4618 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4620 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4621 0x1048, 0x1500, 0, 0,
4624 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4631 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4632 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4634 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4653 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4654 PCI_ANY_ID, PCI_ANY_ID,
4656 0, pbn_pericom_PI7C9X7951 },
4657 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4658 PCI_ANY_ID, PCI_ANY_ID,
4660 0, pbn_pericom_PI7C9X7952 },
4661 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4662 PCI_ANY_ID, PCI_ANY_ID,
4664 0, pbn_pericom_PI7C9X7954 },
4665 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4666 PCI_ANY_ID, PCI_ANY_ID,
4668 0, pbn_pericom_PI7C9X7958 },
4670 * ACCES I/O Products quad
4672 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 pbn_pericom_PI7C9X7952 },
4675 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677 pbn_pericom_PI7C9X7952 },
4678 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680 pbn_pericom_PI7C9X7954 },
4681 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 pbn_pericom_PI7C9X7954 },
4684 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686 pbn_pericom_PI7C9X7952 },
4687 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689 pbn_pericom_PI7C9X7952 },
4690 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692 pbn_pericom_PI7C9X7954 },
4693 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 pbn_pericom_PI7C9X7954 },
4696 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698 pbn_pericom_PI7C9X7952 },
4699 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 pbn_pericom_PI7C9X7952 },
4702 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 pbn_pericom_PI7C9X7954 },
4705 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_pericom_PI7C9X7954 },
4708 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_pericom_PI7C9X7951 },
4711 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 pbn_pericom_PI7C9X7952 },
4714 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_pericom_PI7C9X7952 },
4717 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_pericom_PI7C9X7954 },
4720 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_pericom_PI7C9X7954 },
4723 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_pericom_PI7C9X7952 },
4726 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_pericom_PI7C9X7954 },
4729 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_pericom_PI7C9X7952 },
4732 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_pericom_PI7C9X7952 },
4735 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_pericom_PI7C9X7954 },
4738 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 pbn_pericom_PI7C9X7954 },
4741 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 pbn_pericom_PI7C9X7952 },
4744 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 pbn_pericom_PI7C9X7954 },
4747 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 pbn_pericom_PI7C9X7954 },
4750 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 pbn_pericom_PI7C9X7958 },
4753 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 pbn_pericom_PI7C9X7958 },
4756 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 pbn_pericom_PI7C9X7954 },
4759 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_pericom_PI7C9X7958 },
4762 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 pbn_pericom_PI7C9X7954 },
4765 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 pbn_pericom_PI7C9X7958 },
4768 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 pbn_pericom_PI7C9X7954 },
4772 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4774 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4781 PCI_ANY_ID, PCI_ANY_ID,
4783 pbn_b1_bt_1_115200 },
4788 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4800 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4803 /* Brainboxes Devices */
4807 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
4808 PCI_ANY_ID, PCI_ANY_ID,
4812 * Brainboxes UC-235/246
4814 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
4815 PCI_ANY_ID, PCI_ANY_ID,
4818 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
4819 PCI_ANY_ID, PCI_ANY_ID,
4823 * Brainboxes UC-253/UC-734
4825 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
4826 PCI_ANY_ID, PCI_ANY_ID,
4830 * Brainboxes UC-260/271/701/756
4832 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
4833 PCI_ANY_ID, PCI_ANY_ID,
4834 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4836 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
4837 PCI_ANY_ID, PCI_ANY_ID,
4838 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4843 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
4844 PCI_ANY_ID, PCI_ANY_ID,
4848 * Brainboxes UC-275/279
4850 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
4851 PCI_ANY_ID, PCI_ANY_ID,
4857 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
4858 PCI_ANY_ID, PCI_ANY_ID,
4861 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
4862 PCI_ANY_ID, PCI_ANY_ID,
4865 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
4866 PCI_ANY_ID, PCI_ANY_ID,
4872 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
4873 PCI_ANY_ID, PCI_ANY_ID,
4879 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
4880 PCI_ANY_ID, PCI_ANY_ID,
4883 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
4884 PCI_ANY_ID, PCI_ANY_ID,
4887 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
4888 PCI_ANY_ID, PCI_ANY_ID,
4892 * Brainboxes UC-320/324
4894 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
4895 PCI_ANY_ID, PCI_ANY_ID,
4901 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
4902 PCI_ANY_ID, PCI_ANY_ID,
4905 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
4906 PCI_ANY_ID, PCI_ANY_ID,
4912 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
4913 PCI_ANY_ID, PCI_ANY_ID,
4916 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
4917 PCI_ANY_ID, PCI_ANY_ID,
4920 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
4921 PCI_ANY_ID, PCI_ANY_ID,
4927 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
4928 PCI_ANY_ID, PCI_ANY_ID,
4934 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
4935 PCI_ANY_ID, PCI_ANY_ID,
4941 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
4942 PCI_ANY_ID, PCI_ANY_ID,
4945 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
4946 PCI_ANY_ID, PCI_ANY_ID,
4949 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
4950 PCI_ANY_ID, PCI_ANY_ID,
4956 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
4957 PCI_ANY_ID, PCI_ANY_ID,
4963 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
4964 PCI_ANY_ID, PCI_ANY_ID,
4967 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
4968 PCI_ANY_ID, PCI_ANY_ID,
4971 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
4972 PCI_ANY_ID, PCI_ANY_ID,
4978 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
4979 PCI_ANY_ID, PCI_ANY_ID,
4982 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
4983 PCI_ANY_ID, PCI_ANY_ID,
4986 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
4987 PCI_ANY_ID, PCI_ANY_ID,
4993 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
4994 PCI_ANY_ID, PCI_ANY_ID,
4997 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
4998 PCI_ANY_ID, PCI_ANY_ID,
5001 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5002 PCI_ANY_ID, PCI_ANY_ID,
5008 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5009 PCI_ANY_ID, PCI_ANY_ID,
5012 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5013 PCI_ANY_ID, PCI_ANY_ID,
5016 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5017 PCI_ANY_ID, PCI_ANY_ID,
5021 * Perle PCI-RAS cards
5023 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5024 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5025 0, 0, pbn_b2_4_921600 },
5026 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5027 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5028 0, 0, pbn_b2_8_921600 },
5031 * Mainpine series cards: Fairly standard layout but fools
5032 * parts of the autodetect in some cases and uses otherwise
5033 * unmatched communications subclasses in the PCI Express case
5036 { /* RockForceDUO */
5037 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5038 PCI_VENDOR_ID_MAINPINE, 0x0200,
5039 0, 0, pbn_b0_2_115200 },
5040 { /* RockForceQUATRO */
5041 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5042 PCI_VENDOR_ID_MAINPINE, 0x0300,
5043 0, 0, pbn_b0_4_115200 },
5044 { /* RockForceDUO+ */
5045 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5046 PCI_VENDOR_ID_MAINPINE, 0x0400,
5047 0, 0, pbn_b0_2_115200 },
5048 { /* RockForceQUATRO+ */
5049 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5050 PCI_VENDOR_ID_MAINPINE, 0x0500,
5051 0, 0, pbn_b0_4_115200 },
5053 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5054 PCI_VENDOR_ID_MAINPINE, 0x0600,
5055 0, 0, pbn_b0_2_115200 },
5057 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5058 PCI_VENDOR_ID_MAINPINE, 0x0700,
5059 0, 0, pbn_b0_4_115200 },
5060 { /* RockForceOCTO+ */
5061 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5062 PCI_VENDOR_ID_MAINPINE, 0x0800,
5063 0, 0, pbn_b0_8_115200 },
5064 { /* RockForceDUO+ */
5065 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5066 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5067 0, 0, pbn_b0_2_115200 },
5068 { /* RockForceQUARTRO+ */
5069 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5070 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5071 0, 0, pbn_b0_4_115200 },
5072 { /* RockForceOCTO+ */
5073 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5074 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5075 0, 0, pbn_b0_8_115200 },
5077 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5078 PCI_VENDOR_ID_MAINPINE, 0x2000,
5079 0, 0, pbn_b0_1_115200 },
5081 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5082 PCI_VENDOR_ID_MAINPINE, 0x2100,
5083 0, 0, pbn_b0_1_115200 },
5085 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5086 PCI_VENDOR_ID_MAINPINE, 0x2200,
5087 0, 0, pbn_b0_2_115200 },
5089 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5090 PCI_VENDOR_ID_MAINPINE, 0x2300,
5091 0, 0, pbn_b0_2_115200 },
5093 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5094 PCI_VENDOR_ID_MAINPINE, 0x2400,
5095 0, 0, pbn_b0_4_115200 },
5097 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5098 PCI_VENDOR_ID_MAINPINE, 0x2500,
5099 0, 0, pbn_b0_4_115200 },
5101 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5102 PCI_VENDOR_ID_MAINPINE, 0x2600,
5103 0, 0, pbn_b0_8_115200 },
5105 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5106 PCI_VENDOR_ID_MAINPINE, 0x2700,
5107 0, 0, pbn_b0_8_115200 },
5108 { /* IQ Express D1 */
5109 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5110 PCI_VENDOR_ID_MAINPINE, 0x3000,
5111 0, 0, pbn_b0_1_115200 },
5112 { /* IQ Express F1 */
5113 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5114 PCI_VENDOR_ID_MAINPINE, 0x3100,
5115 0, 0, pbn_b0_1_115200 },
5116 { /* IQ Express D2 */
5117 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5118 PCI_VENDOR_ID_MAINPINE, 0x3200,
5119 0, 0, pbn_b0_2_115200 },
5120 { /* IQ Express F2 */
5121 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5122 PCI_VENDOR_ID_MAINPINE, 0x3300,
5123 0, 0, pbn_b0_2_115200 },
5124 { /* IQ Express D4 */
5125 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5126 PCI_VENDOR_ID_MAINPINE, 0x3400,
5127 0, 0, pbn_b0_4_115200 },
5128 { /* IQ Express F4 */
5129 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5130 PCI_VENDOR_ID_MAINPINE, 0x3500,
5131 0, 0, pbn_b0_4_115200 },
5132 { /* IQ Express D8 */
5133 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5134 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5135 0, 0, pbn_b0_8_115200 },
5136 { /* IQ Express F8 */
5137 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5138 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5139 0, 0, pbn_b0_8_115200 },
5143 * PA Semi PA6T-1682M on-chip UART
5145 { PCI_VENDOR_ID_PASEMI, 0xa004,
5146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5150 * National Instruments
5152 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5155 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5158 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5160 pbn_b1_bt_4_115200 },
5161 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5163 pbn_b1_bt_2_115200 },
5164 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5166 pbn_b1_bt_4_115200 },
5167 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5169 pbn_b1_bt_2_115200 },
5170 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5173 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5176 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5178 pbn_b1_bt_4_115200 },
5179 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5181 pbn_b1_bt_2_115200 },
5182 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5184 pbn_b1_bt_4_115200 },
5185 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5187 pbn_b1_bt_2_115200 },
5188 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5191 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5194 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5197 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5200 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5203 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5206 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5209 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5212 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5215 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5218 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5221 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5226 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5228 { PCI_VENDOR_ID_ADDIDATA,
5229 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5236 { PCI_VENDOR_ID_ADDIDATA,
5237 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5244 { PCI_VENDOR_ID_ADDIDATA,
5245 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5252 { PCI_VENDOR_ID_AMCC,
5253 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5260 { PCI_VENDOR_ID_ADDIDATA,
5261 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5268 { PCI_VENDOR_ID_ADDIDATA,
5269 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5276 { PCI_VENDOR_ID_ADDIDATA,
5277 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5284 { PCI_VENDOR_ID_ADDIDATA,
5285 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5292 { PCI_VENDOR_ID_ADDIDATA,
5293 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5300 { PCI_VENDOR_ID_ADDIDATA,
5301 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5308 { PCI_VENDOR_ID_ADDIDATA,
5309 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5316 { PCI_VENDOR_ID_ADDIDATA,
5317 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5322 pbn_ADDIDATA_PCIe_4_3906250 },
5324 { PCI_VENDOR_ID_ADDIDATA,
5325 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5330 pbn_ADDIDATA_PCIe_2_3906250 },
5332 { PCI_VENDOR_ID_ADDIDATA,
5333 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5338 pbn_ADDIDATA_PCIe_1_3906250 },
5340 { PCI_VENDOR_ID_ADDIDATA,
5341 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5346 pbn_ADDIDATA_PCIe_8_3906250 },
5348 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5349 PCI_VENDOR_ID_IBM, 0x0299,
5350 0, 0, pbn_b0_bt_2_115200 },
5353 * other NetMos 9835 devices are most likely handled by the
5354 * parport_serial driver, check drivers/parport/parport_serial.c
5355 * before adding them here.
5358 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5360 0, 0, pbn_b0_1_115200 },
5362 /* the 9901 is a rebranded 9912 */
5363 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5365 0, 0, pbn_b0_1_115200 },
5367 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5369 0, 0, pbn_b0_1_115200 },
5371 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5373 0, 0, pbn_b0_1_115200 },
5375 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5377 0, 0, pbn_b0_1_115200 },
5379 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5381 0, 0, pbn_NETMOS9900_2s_115200 },
5384 * Best Connectivity and Rosewill PCI Multi I/O cards
5387 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5389 0, 0, pbn_b0_1_115200 },
5391 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5393 0, 0, pbn_b0_bt_2_115200 },
5395 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5397 0, 0, pbn_b0_bt_4_115200 },
5399 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5401 pbn_ce4100_1_115200 },
5406 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5411 * Broadcom TruManage
5413 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5415 pbn_brcm_trumanage },
5418 * AgeStar as-prs2-009
5420 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5421 PCI_ANY_ID, PCI_ANY_ID,
5422 0, 0, pbn_b0_bt_2_115200 },
5425 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5426 * so not listed here.
5428 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5429 PCI_ANY_ID, PCI_ANY_ID,
5430 0, 0, pbn_b0_bt_4_115200 },
5432 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5433 PCI_ANY_ID, PCI_ANY_ID,
5434 0, 0, pbn_b0_bt_2_115200 },
5436 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5437 PCI_ANY_ID, PCI_ANY_ID,
5438 0, 0, pbn_b0_bt_4_115200 },
5440 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5441 PCI_ANY_ID, PCI_ANY_ID,
5442 0, 0, pbn_wch382_2 },
5444 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5445 PCI_ANY_ID, PCI_ANY_ID,
5446 0, 0, pbn_wch384_4 },
5449 * Realtek RealManage
5451 { PCI_VENDOR_ID_REALTEK, 0x816a,
5452 PCI_ANY_ID, PCI_ANY_ID,
5453 0, 0, pbn_b0_1_115200 },
5455 { PCI_VENDOR_ID_REALTEK, 0x816b,
5456 PCI_ANY_ID, PCI_ANY_ID,
5457 0, 0, pbn_b0_1_115200 },
5459 /* Fintek PCI serial cards */
5460 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5461 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5462 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5464 /* MKS Tenta SCOM-080x serial cards */
5465 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5466 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5468 /* Amazon PCI serial device */
5469 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5472 * These entries match devices with class COMMUNICATION_SERIAL,
5473 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5475 { PCI_ANY_ID, PCI_ANY_ID,
5476 PCI_ANY_ID, PCI_ANY_ID,
5477 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5478 0xffff00, pbn_default },
5479 { PCI_ANY_ID, PCI_ANY_ID,
5480 PCI_ANY_ID, PCI_ANY_ID,
5481 PCI_CLASS_COMMUNICATION_MODEM << 8,
5482 0xffff00, pbn_default },
5483 { PCI_ANY_ID, PCI_ANY_ID,
5484 PCI_ANY_ID, PCI_ANY_ID,
5485 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5486 0xffff00, pbn_default },
5490 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5491 pci_channel_state_t state)
5493 struct serial_private *priv = pci_get_drvdata(dev);
5495 if (state == pci_channel_io_perm_failure)
5496 return PCI_ERS_RESULT_DISCONNECT;
5499 pciserial_detach_ports(priv);
5501 pci_disable_device(dev);
5503 return PCI_ERS_RESULT_NEED_RESET;
5506 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5510 rc = pci_enable_device(dev);
5513 return PCI_ERS_RESULT_DISCONNECT;
5515 pci_restore_state(dev);
5516 pci_save_state(dev);
5518 return PCI_ERS_RESULT_RECOVERED;
5521 static void serial8250_io_resume(struct pci_dev *dev)
5523 struct serial_private *priv = pci_get_drvdata(dev);
5524 struct serial_private *new;
5529 new = pciserial_init_ports(dev, priv->board);
5531 pci_set_drvdata(dev, new);
5536 static const struct pci_error_handlers serial8250_err_handler = {
5537 .error_detected = serial8250_io_error_detected,
5538 .slot_reset = serial8250_io_slot_reset,
5539 .resume = serial8250_io_resume,
5542 static struct pci_driver serial_pci_driver = {
5544 .probe = pciserial_init_one,
5545 .remove = pciserial_remove_one,
5547 .pm = &pciserial_pm_ops,
5549 .id_table = serial_pci_tbl,
5550 .err_handler = &serial8250_err_handler,
5553 module_pci_driver(serial_pci_driver);
5555 MODULE_LICENSE("GPL");
5556 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5557 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);