1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type PCI serial ports.
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/math.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/tty.h>
18 #include <linux/serial_reg.h>
19 #include <linux/serial_core.h>
20 #include <linux/8250_pci.h>
21 #include <linux/bitops.h>
22 #include <linux/bitfield.h>
24 #include <asm/byteorder.h>
28 #include "8250_pcilib.h"
30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32 #define PCI_DEVICE_ID_OCTPRO 0x0001
33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46 #define PCI_DEVICE_ID_TITAN_200I 0x8028
47 #define PCI_DEVICE_ID_TITAN_400I 0x8048
48 #define PCI_DEVICE_ID_TITAN_800I 0x8088
49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
52 #define PCI_DEVICE_ID_TITAN_100E 0xA010
53 #define PCI_DEVICE_ID_TITAN_200E 0xA012
54 #define PCI_DEVICE_ID_TITAN_400E 0xA013
55 #define PCI_DEVICE_ID_TITAN_800E 0xA014
56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
67 #define PCI_VENDOR_ID_WCH 0x4348
68 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
69 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
70 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
71 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
72 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
73 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
74 #define PCI_VENDOR_ID_AGESTAR 0x5372
75 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
76 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
77 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
79 #define PCIE_VENDOR_ID_WCH 0x1c00
80 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
81 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
82 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
83 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
85 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
86 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
87 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027
88 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
89 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046
90 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121
91 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
92 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145
93 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
94 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
95 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
96 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
97 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
98 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323
99 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
100 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343
101 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
102 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
104 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
105 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
106 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
109 * init function returns:
110 * > 0 - number of ports
111 * = 0 - use board->num_ports
114 struct pci_serial_quirk {
119 int (*probe)(struct pci_dev *dev);
120 int (*init)(struct pci_dev *dev);
121 int (*setup)(struct serial_private *,
122 const struct pciserial_board *,
123 struct uart_8250_port *, int);
124 void (*exit)(struct pci_dev *dev);
127 struct f815xxa_data {
132 struct serial_private {
135 struct pci_serial_quirk *quirk;
136 const struct pciserial_board *board;
140 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
142 static const struct pci_device_id pci_use_msi[] = {
143 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
145 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
147 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
149 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
151 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
152 PCI_ANY_ID, PCI_ANY_ID) },
156 static int pci_default_setup(struct serial_private*,
157 const struct pciserial_board*, struct uart_8250_port *, int);
159 static void moan_device(const char *str, struct pci_dev *dev)
162 "Please send the output of lspci -vv, this\n"
163 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
164 "manufacturer and name of serial board or\n"
165 "modem board to <linux-serial@vger.kernel.org>.\n",
166 str, dev->vendor, dev->device,
167 dev->subsystem_vendor, dev->subsystem_device);
171 setup_port(struct serial_private *priv, struct uart_8250_port *port,
172 u8 bar, unsigned int offset, int regshift)
174 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift);
178 * ADDI-DATA GmbH communication cards <info@addi-data.com>
180 static int addidata_apci7800_setup(struct serial_private *priv,
181 const struct pciserial_board *board,
182 struct uart_8250_port *port, int idx)
184 unsigned int bar = 0, offset = board->first_offset;
185 bar = FL_GET_BASE(board->flags);
188 offset += idx * board->uart_offset;
189 } else if ((idx >= 2) && (idx < 4)) {
191 offset += ((idx - 2) * board->uart_offset);
192 } else if ((idx >= 4) && (idx < 6)) {
194 offset += ((idx - 4) * board->uart_offset);
195 } else if (idx >= 6) {
197 offset += ((idx - 6) * board->uart_offset);
200 return setup_port(priv, port, bar, offset, board->reg_shift);
204 * AFAVLAB uses a different mixture of BARs and offsets
205 * Not that ugly ;) -- HW
208 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
209 struct uart_8250_port *port, int idx)
211 unsigned int bar, offset = board->first_offset;
213 bar = FL_GET_BASE(board->flags);
218 offset += (idx - 4) * board->uart_offset;
221 return setup_port(priv, port, bar, offset, board->reg_shift);
225 * HP's Remote Management Console. The Diva chip came in several
226 * different versions. N-class, L2000 and A500 have two Diva chips, each
227 * with 3 UARTs (the third UART on the second chip is unused). Superdome
228 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
229 * one Diva chip, but it has been expanded to 5 UARTs.
231 static int pci_hp_diva_init(struct pci_dev *dev)
235 switch (dev->subsystem_device) {
236 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
237 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
238 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
239 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
242 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
245 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
248 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
249 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
258 * HP's Diva chip puts the 4th/5th serial port further out, and
259 * some serial ports are supposed to be hidden on certain models.
262 pci_hp_diva_setup(struct serial_private *priv,
263 const struct pciserial_board *board,
264 struct uart_8250_port *port, int idx)
266 unsigned int offset = board->first_offset;
267 unsigned int bar = FL_GET_BASE(board->flags);
269 switch (priv->dev->subsystem_device) {
270 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
274 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
284 offset += idx * board->uart_offset;
286 return setup_port(priv, port, bar, offset, board->reg_shift);
290 * Added for EKF Intel i960 serial boards
292 static int pci_inteli960ni_init(struct pci_dev *dev)
296 if (!(dev->subsystem_device & 0x1000))
299 /* is firmware started? */
300 pci_read_config_dword(dev, 0x44, &oldval);
301 if (oldval == 0x00001000L) { /* RESET value */
302 pci_dbg(dev, "Local i960 firmware missing\n");
309 * Some PCI serial cards using the PLX 9050 PCI interface chip require
310 * that the card interrupt be explicitly enabled or disabled. This
311 * seems to be mainly needed on card using the PLX which also use I/O
314 static int pci_plx9050_init(struct pci_dev *dev)
319 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar 0", dev);
325 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
326 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
329 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
330 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
332 * As the megawolf cards have the int pins active
333 * high, and have 2 UART chips, both ints must be
334 * enabled on the 9050. Also, the UARTS are set in
335 * 16450 mode by default, so we have to enable the
336 * 16C950 'enhanced' mode so that we can use the
341 * enable/disable interrupts
343 p = ioremap(pci_resource_start(dev, 0), 0x80);
346 writel(irq_config, p + 0x4c);
349 * Read the register back to ensure that it took effect.
357 static void pci_plx9050_exit(struct pci_dev *dev)
361 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
367 p = ioremap(pci_resource_start(dev, 0), 0x80);
372 * Read the register back to ensure that it took effect.
379 #define NI8420_INT_ENABLE_REG 0x38
380 #define NI8420_INT_ENABLE_BIT 0x2000
382 static void pci_ni8420_exit(struct pci_dev *dev)
385 unsigned int bar = 0;
387 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
388 moan_device("no memory in bar", dev);
392 p = pci_ioremap_bar(dev, bar);
396 /* Disable the CPU Interrupt */
397 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
398 p + NI8420_INT_ENABLE_REG);
404 #define MITE_IOWBSR1 0xc4
405 #define MITE_IOWCR1 0xf4
406 #define MITE_LCIMR1 0x08
407 #define MITE_LCIMR2 0x10
409 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
411 static void pci_ni8430_exit(struct pci_dev *dev)
414 unsigned int bar = 0;
416 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
417 moan_device("no memory in bar", dev);
421 p = pci_ioremap_bar(dev, bar);
425 /* Disable the CPU Interrupt */
426 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
430 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
432 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
433 struct uart_8250_port *port, int idx)
435 unsigned int bar, offset = board->first_offset;
440 /* first four channels map to 0, 0x100, 0x200, 0x300 */
441 offset += idx * board->uart_offset;
442 } else if (idx < 8) {
443 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
444 offset += idx * board->uart_offset + 0xC00;
445 } else /* we have only 8 ports on PMC-OCTALPRO */
448 return setup_port(priv, port, bar, offset, board->reg_shift);
452 * This does initialization for PMC OCTALPRO cards:
453 * maps the device memory, resets the UARTs (needed, bc
454 * if the module is removed and inserted again, the card
455 * is in the sleep mode) and enables global interrupt.
458 /* global control register offset for SBS PMC-OctalPro */
459 #define OCT_REG_CR_OFF 0x500
461 static int sbs_init(struct pci_dev *dev)
465 p = pci_ioremap_bar(dev, 0);
469 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
470 writeb(0x10, p + OCT_REG_CR_OFF);
472 writeb(0x0, p + OCT_REG_CR_OFF);
474 /* Set bit-2 (INTENABLE) of Control Register */
475 writeb(0x4, p + OCT_REG_CR_OFF);
482 * Disables the global interrupt of PMC-OctalPro
485 static void sbs_exit(struct pci_dev *dev)
489 p = pci_ioremap_bar(dev, 0);
490 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
492 writeb(0, p + OCT_REG_CR_OFF);
497 * SIIG serial cards have an PCI interface chip which also controls
498 * the UART clocking frequency. Each UART can be clocked independently
499 * (except cards equipped with 4 UARTs) and initial clocking settings
500 * are stored in the EEPROM chip. It can cause problems because this
501 * version of serial driver doesn't support differently clocked UART's
502 * on single PCI card. To prevent this, initialization functions set
503 * high frequency clocking for all UART's on given card. It is safe (I
504 * hope) because it doesn't touch EEPROM settings to prevent conflicts
505 * with other OSes (like M$ DOS).
507 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
509 * There is two family of SIIG serial cards with different PCI
510 * interface chip and different configuration methods:
511 * - 10x cards have control registers in IO and/or memory space;
512 * - 20x cards have control registers in standard PCI configuration space.
514 * Note: all 10x cards have PCI device ids 0x10..
515 * all 20x cards have PCI device ids 0x20..
517 * There are also Quartet Serial cards which use Oxford Semiconductor
518 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
520 * Note: some SIIG cards are probed by the parport_serial object.
523 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
524 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
526 static int pci_siig10x_init(struct pci_dev *dev)
531 switch (dev->device & 0xfff8) {
532 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
535 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
538 default: /* 1S1P, 4S */
543 p = ioremap(pci_resource_start(dev, 0), 0x80);
547 writew(readw(p + 0x28) & data, p + 0x28);
553 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
554 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
556 static int pci_siig20x_init(struct pci_dev *dev)
560 /* Change clock frequency for the first UART. */
561 pci_read_config_byte(dev, 0x6f, &data);
562 pci_write_config_byte(dev, 0x6f, data & 0xef);
564 /* If this card has 2 UART, we have to do the same with second UART. */
565 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
566 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
567 pci_read_config_byte(dev, 0x73, &data);
568 pci_write_config_byte(dev, 0x73, data & 0xef);
573 static int pci_siig_init(struct pci_dev *dev)
575 unsigned int type = dev->device & 0xff00;
578 return pci_siig10x_init(dev);
580 return pci_siig20x_init(dev);
582 moan_device("Unknown SIIG card", dev);
586 static int pci_siig_setup(struct serial_private *priv,
587 const struct pciserial_board *board,
588 struct uart_8250_port *port, int idx)
590 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
594 offset = (idx - 4) * 8;
597 return setup_port(priv, port, bar, offset, 0);
601 * Timedia has an explosion of boards, and to avoid the PCI table from
602 * growing *huge*, we use this function to collapse some 70 entries
603 * in the PCI table into one, for sanity's and compactness's sake.
605 static const unsigned short timedia_single_port[] = {
606 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
609 static const unsigned short timedia_dual_port[] = {
610 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
611 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
612 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
613 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
617 static const unsigned short timedia_quad_port[] = {
618 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
619 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
620 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
624 static const unsigned short timedia_eight_port[] = {
625 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
626 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
629 static const struct timedia_struct {
631 const unsigned short *ids;
633 { 1, timedia_single_port },
634 { 2, timedia_dual_port },
635 { 4, timedia_quad_port },
636 { 8, timedia_eight_port }
640 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
641 * listing them individually, this driver merely grabs them all with
642 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
643 * and should be left free to be claimed by parport_serial instead.
645 static int pci_timedia_probe(struct pci_dev *dev)
648 * Check the third digit of the subdevice ID
649 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
651 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
652 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
653 dev->subsystem_device);
660 static int pci_timedia_init(struct pci_dev *dev)
662 const unsigned short *ids;
665 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
666 ids = timedia_data[i].ids;
667 for (j = 0; ids[j]; j++)
668 if (dev->subsystem_device == ids[j])
669 return timedia_data[i].num;
675 * Timedia/SUNIX uses a mixture of BARs and offsets
676 * Ugh, this is ugly as all hell --- TYT
679 pci_timedia_setup(struct serial_private *priv,
680 const struct pciserial_board *board,
681 struct uart_8250_port *port, int idx)
683 unsigned int bar = 0, offset = board->first_offset;
690 offset = board->uart_offset;
697 offset = board->uart_offset;
706 return setup_port(priv, port, bar, offset, board->reg_shift);
710 * Some Titan cards are also a little weird
713 titan_400l_800l_setup(struct serial_private *priv,
714 const struct pciserial_board *board,
715 struct uart_8250_port *port, int idx)
717 unsigned int bar, offset = board->first_offset;
728 offset = (idx - 2) * board->uart_offset;
731 return setup_port(priv, port, bar, offset, board->reg_shift);
734 static int pci_xircom_init(struct pci_dev *dev)
740 static int pci_ni8420_init(struct pci_dev *dev)
743 unsigned int bar = 0;
745 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
746 moan_device("no memory in bar", dev);
750 p = pci_ioremap_bar(dev, bar);
754 /* Enable CPU Interrupt */
755 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
756 p + NI8420_INT_ENABLE_REG);
762 #define MITE_IOWBSR1_WSIZE 0xa
763 #define MITE_IOWBSR1_WIN_OFFSET 0x800
764 #define MITE_IOWBSR1_WENAB (1 << 7)
765 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
766 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
767 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
769 static int pci_ni8430_init(struct pci_dev *dev)
772 struct pci_bus_region region;
774 unsigned int bar = 0;
776 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
777 moan_device("no memory in bar", dev);
781 p = pci_ioremap_bar(dev, bar);
786 * Set device window address and size in BAR0, while acknowledging that
787 * the resource structure may contain a translated address that differs
788 * from the address the device responds to.
790 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
791 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
792 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
793 writel(device_window, p + MITE_IOWBSR1);
795 /* Set window access to go to RAMSEL IO address space */
796 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
799 /* Enable IO Bus Interrupt 0 */
800 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
802 /* Enable CPU Interrupt */
803 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
809 /* UART Port Control Register */
810 #define NI8430_PORTCON 0x0f
811 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
814 pci_ni8430_setup(struct serial_private *priv,
815 const struct pciserial_board *board,
816 struct uart_8250_port *port, int idx)
818 struct pci_dev *dev = priv->dev;
820 unsigned int bar, offset = board->first_offset;
822 if (idx >= board->num_ports)
825 bar = FL_GET_BASE(board->flags);
826 offset += idx * board->uart_offset;
828 p = pci_ioremap_bar(dev, bar);
832 /* enable the transceiver */
833 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
834 p + offset + NI8430_PORTCON);
838 return setup_port(priv, port, bar, offset, board->reg_shift);
841 static int pci_netmos_9900_setup(struct serial_private *priv,
842 const struct pciserial_board *board,
843 struct uart_8250_port *port, int idx)
847 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
848 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
849 /* netmos apparently orders BARs by datasheet layout, so serial
850 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
854 return setup_port(priv, port, bar, 0, board->reg_shift);
857 return pci_default_setup(priv, board, port, idx);
860 /* the 99xx series comes with a range of device IDs and a variety
863 * 9900 has varying capabilities and can cascade to sub-controllers
864 * (cascading should be purely internal)
865 * 9904 is hardwired with 4 serial ports
866 * 9912 and 9922 are hardwired with 2 serial ports
868 static int pci_netmos_9900_numports(struct pci_dev *dev)
870 unsigned int c = dev->class;
872 unsigned short sub_serports;
879 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
880 /* two possibilities: 0x30ps encodes number of parallel and
881 * serial ports, or 0x1000 indicates *something*. This is not
882 * immediately obvious, since the 2s1p+4s configuration seems
883 * to offer all functionality on functions 0..2, while still
884 * advertising the same function 3 as the 4s+2s1p config.
886 sub_serports = dev->subsystem_device & 0xf;
887 if (sub_serports > 0)
890 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
894 moan_device("unknown NetMos/Mostech program interface", dev);
898 static int pci_netmos_init(struct pci_dev *dev)
900 /* subdevice 0x00PS means <P> parallel, <S> serial */
901 unsigned int num_serial = dev->subsystem_device & 0xf;
903 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
904 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
907 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
908 dev->subsystem_device == 0x0299)
911 switch (dev->device) { /* FALLTHROUGH on all */
912 case PCI_DEVICE_ID_NETMOS_9904:
913 case PCI_DEVICE_ID_NETMOS_9912:
914 case PCI_DEVICE_ID_NETMOS_9922:
915 case PCI_DEVICE_ID_NETMOS_9900:
916 num_serial = pci_netmos_9900_numports(dev);
923 if (num_serial == 0) {
924 moan_device("unknown NetMos/Mostech device", dev);
932 * These chips are available with optionally one parallel port and up to
933 * two serial ports. Unfortunately they all have the same product id.
935 * Basic configuration is done over a region of 32 I/O ports. The base
936 * ioport is called INTA or INTC, depending on docs/other drivers.
938 * The region of the 32 I/O ports is configured in POSIO0R...
942 #define ITE_887x_MISCR 0x9c
943 #define ITE_887x_INTCBAR 0x78
944 #define ITE_887x_UARTBAR 0x7c
945 #define ITE_887x_PS0BAR 0x10
946 #define ITE_887x_POSIO0 0x60
949 #define ITE_887x_IOSIZE 32
950 /* I/O space size (bits 26-24; 8 bytes = 011b) */
951 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
952 /* I/O space size (bits 26-24; 32 bytes = 101b) */
953 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
954 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
955 #define ITE_887x_POSIO_SPEED (3 << 29)
956 /* enable IO_Space bit */
957 #define ITE_887x_POSIO_ENABLE (1 << 31)
959 /* inta_addr are the configuration addresses of the ITE */
960 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
961 static int pci_ite887x_init(struct pci_dev *dev)
964 struct resource *iobase = NULL;
965 u32 miscr, uartbar, ioport;
967 /* search for the base-ioport */
968 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
969 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
971 if (iobase != NULL) {
972 /* write POSIO0R - speed | size | ioport */
973 pci_write_config_dword(dev, ITE_887x_POSIO0,
974 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
975 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
976 /* write INTCBAR - ioport */
977 pci_write_config_dword(dev, ITE_887x_INTCBAR,
979 ret = inb(inta_addr[i]);
981 /* ioport connected */
984 release_region(iobase->start, ITE_887x_IOSIZE);
988 if (i == ARRAY_SIZE(inta_addr)) {
989 pci_err(dev, "could not find iobase\n");
993 /* start of undocumented type checking (see parport_pc.c) */
994 type = inb(iobase->start + 0x18) & 0x0f;
997 case 0x2: /* ITE8871 (1P) */
998 case 0xa: /* ITE8875 (1P) */
1001 case 0xe: /* ITE8872 (2S1P) */
1004 case 0x6: /* ITE8873 (1S) */
1007 case 0x8: /* ITE8874 (2S) */
1011 moan_device("Unknown ITE887x", dev);
1015 /* configure all serial ports */
1016 for (i = 0; i < ret; i++) {
1017 /* read the I/O port from the device */
1018 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
1020 ioport &= 0x0000FF00; /* the actual base address */
1021 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
1022 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1023 ITE_887x_POSIO_IOSIZE_8 | ioport);
1025 /* write the ioport to the UARTBAR */
1026 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
1027 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
1028 uartbar |= (ioport << (16 * i)); /* set the ioport */
1029 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
1031 /* get current config */
1032 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
1033 /* disable interrupts (UARTx_Routing[3:0]) */
1034 miscr &= ~(0xf << (12 - 4 * i));
1035 /* activate the UART (UARTx_En) */
1036 miscr |= 1 << (23 - i);
1037 /* write new config with activated UART */
1038 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
1042 /* the device has no UARTs if we get here */
1043 release_region(iobase->start, ITE_887x_IOSIZE);
1049 static void pci_ite887x_exit(struct pci_dev *dev)
1052 /* the ioport is bit 0-15 in POSIO0R */
1053 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1055 release_region(ioport, ITE_887x_IOSIZE);
1059 * Oxford Semiconductor Inc.
1060 * Check if an OxSemi device is part of the Tornado range of devices.
1062 #define PCI_VENDOR_ID_ENDRUN 0x7401
1063 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1065 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1067 /* OxSemi Tornado devices are all 0xCxxx */
1068 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1069 (dev->device & 0xf000) != 0xc000)
1072 /* EndRun devices are all 0xExxx */
1073 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1074 (dev->device & 0xf000) != 0xe000)
1081 * Determine the number of ports available on a Tornado device.
1083 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1086 unsigned long deviceID;
1087 unsigned int number_uarts = 0;
1089 if (!pci_oxsemi_tornado_p(dev))
1092 p = pci_iomap(dev, 0, 5);
1096 deviceID = ioread32(p);
1097 /* Tornado device */
1098 if (deviceID == 0x07000200) {
1099 number_uarts = ioread8(p + 4);
1100 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1102 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1103 "EndRun" : "Oxford");
1105 pci_iounmap(dev, p);
1106 return number_uarts;
1109 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1110 #define OXSEMI_TORNADO_TCR_MASK 0xf
1111 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1112 #define OXSEMI_TORNADO_CPR_MIN 0x008
1113 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1116 * Determine the oversampling rate, the clock prescaler, and the clock
1117 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1118 * which is four times the baud base, and the prescaler increments in
1119 * steps of 1/8. Therefore to make calculations on integers we need
1120 * to use a scaled clock rate, which is the baud base multiplied by 32
1121 * (or our assumed UART clock rate multiplied by 2).
1123 * The allowed oversampling rates are from 4 up to 16 inclusive (values
1124 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1125 * values between 1.000 and 63.875 inclusive (operation for values from
1126 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1127 * unsigned 16-bit integer.
1129 * For the most accurate baud rate we use a table of predetermined
1130 * oversampling rates and clock prescalers that records all possible
1131 * products of the two parameters in the range from 4 up to 255 inclusive,
1132 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1133 * by 8. The table is sorted by the decreasing value of the oversampling
1134 * rate and ties are resolved by sorting by the decreasing value of the
1135 * product. This way preference is given to higher oversampling rates.
1137 * We iterate over the table and choose the product of an oversampling
1138 * rate and a clock prescaler that gives the lowest integer division
1139 * result deviation, or if an exact integer divider is found we stop
1140 * looking for it right away. We do some fixup if the resulting clock
1141 * divisor required would be out of its unsigned 16-bit integer range.
1143 * Finally we abuse the supposed fractional part returned to encode the
1144 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1145 * prescaler which will end up in the TCR and CPR/CPR2 registers.
1147 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1151 static u8 p[][2] = {
1152 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1153 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1154 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1155 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1156 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1157 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1158 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1159 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1160 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1161 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1162 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1163 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1164 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1165 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1166 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1167 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1168 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1169 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1170 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1171 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1172 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1173 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1174 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1175 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1176 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1177 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1178 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1179 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1180 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1181 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1182 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1183 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1184 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1185 { 4, 9, }, { 4, 8, },
1187 /* Scale the quotient for comparison to get the fractional part. */
1188 const unsigned int quot_scale = 65536;
1189 unsigned int sclk = port->uartclk * 2;
1190 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1191 unsigned int best_squot;
1198 /* Old custom speed handling. */
1199 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
1200 unsigned int cust_div = port->custom_divisor;
1202 quot = cust_div & UART_DIV_MAX;
1203 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
1204 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
1205 if (cpr < OXSEMI_TORNADO_CPR_MIN)
1206 cpr = OXSEMI_TORNADO_CPR_DEF;
1208 best_squot = quot_scale;
1209 for (i = 0; i < ARRAY_SIZE(p); i++) {
1220 if (srem > spre / 2)
1222 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1229 } else if (squot < best_squot) {
1233 quot = DIV_ROUND_CLOSEST(sdiv, spre);
1236 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1241 while (quot > UART_DIV_MAX) {
1242 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1245 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1249 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1250 cpr = OXSEMI_TORNADO_CPR_MASK;
1255 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1260 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1261 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1262 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1263 * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1264 * has to be written first, followed by CPR2, which occupies the location
1265 * of CKS used with earlier UART designs.
1267 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1270 unsigned int quot_frac)
1272 struct uart_8250_port *up = up_to_u8250p(port);
1273 u8 cpr2 = quot_frac >> 16;
1274 u8 cpr = quot_frac >> 8;
1277 serial_icr_write(up, UART_TCR, tcr);
1278 serial_icr_write(up, UART_CPR, cpr);
1279 serial_icr_write(up, UART_CKS, cpr2);
1280 serial8250_do_set_divisor(port, baud, quot, 0);
1284 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1285 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1287 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1290 struct uart_8250_port *up = up_to_u8250p(port);
1292 up->mcr |= UART_MCR_CLKSEL;
1293 serial8250_do_set_mctrl(port, mctrl);
1297 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1298 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1300 static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1301 const struct pciserial_board *board,
1302 struct uart_8250_port *up, int idx)
1304 struct pci_dev *dev = priv->dev;
1306 if (pci_oxsemi_tornado_p(dev)) {
1307 up->port.flags |= UPF_FULL_PROBE;
1308 up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1309 up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1310 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1313 return pci_default_setup(priv, board, up, idx);
1316 #define QPCR_TEST_FOR1 0x3F
1317 #define QPCR_TEST_GET1 0x00
1318 #define QPCR_TEST_FOR2 0x40
1319 #define QPCR_TEST_GET2 0x40
1320 #define QPCR_TEST_FOR3 0x80
1321 #define QPCR_TEST_GET3 0x40
1322 #define QPCR_TEST_FOR4 0xC0
1323 #define QPCR_TEST_GET4 0x80
1325 #define QOPR_CLOCK_X1 0x0000
1326 #define QOPR_CLOCK_X2 0x0001
1327 #define QOPR_CLOCK_X4 0x0002
1328 #define QOPR_CLOCK_X8 0x0003
1329 #define QOPR_CLOCK_RATE_MASK 0x0003
1331 /* Quatech devices have their own extra interface features */
1332 static struct pci_device_id quatech_cards[] = {
1333 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
1334 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
1335 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1336 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
1337 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1338 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
1339 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
1340 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
1341 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
1342 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
1343 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
1344 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1345 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1346 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1347 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1348 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1349 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1350 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1351 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1355 static int pci_quatech_rqopr(struct uart_8250_port *port)
1357 unsigned long base = port->port.iobase;
1360 LCR = inb(base + UART_LCR);
1361 outb(0xBF, base + UART_LCR);
1362 val = inb(base + UART_SCR);
1363 outb(LCR, base + UART_LCR);
1367 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1369 unsigned long base = port->port.iobase;
1372 LCR = inb(base + UART_LCR);
1373 outb(0xBF, base + UART_LCR);
1374 inb(base + UART_SCR);
1375 outb(qopr, base + UART_SCR);
1376 outb(LCR, base + UART_LCR);
1379 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1381 unsigned long base = port->port.iobase;
1384 LCR = inb(base + UART_LCR);
1385 outb(0xBF, base + UART_LCR);
1386 val = inb(base + UART_SCR);
1387 outb(val | 0x10, base + UART_SCR);
1388 qmcr = inb(base + UART_MCR);
1389 outb(val, base + UART_SCR);
1390 outb(LCR, base + UART_LCR);
1395 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1397 unsigned long base = port->port.iobase;
1400 LCR = inb(base + UART_LCR);
1401 outb(0xBF, base + UART_LCR);
1402 val = inb(base + UART_SCR);
1403 outb(val | 0x10, base + UART_SCR);
1404 outb(qmcr, base + UART_MCR);
1405 outb(val, base + UART_SCR);
1406 outb(LCR, base + UART_LCR);
1409 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1411 unsigned long base = port->port.iobase;
1414 LCR = inb(base + UART_LCR);
1415 outb(0xBF, base + UART_LCR);
1416 val = inb(base + UART_SCR);
1418 outb(0x80, UART_LCR);
1419 if (!(inb(UART_SCR) & 0x20)) {
1420 outb(LCR, base + UART_LCR);
1427 static int pci_quatech_test(struct uart_8250_port *port)
1431 qopr = pci_quatech_rqopr(port);
1432 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1433 reg = pci_quatech_rqopr(port) & 0xC0;
1434 if (reg != QPCR_TEST_GET1)
1436 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1437 reg = pci_quatech_rqopr(port) & 0xC0;
1438 if (reg != QPCR_TEST_GET2)
1440 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1441 reg = pci_quatech_rqopr(port) & 0xC0;
1442 if (reg != QPCR_TEST_GET3)
1444 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1445 reg = pci_quatech_rqopr(port) & 0xC0;
1446 if (reg != QPCR_TEST_GET4)
1449 pci_quatech_wqopr(port, qopr);
1453 static int pci_quatech_clock(struct uart_8250_port *port)
1456 unsigned long clock;
1458 if (pci_quatech_test(port) < 0)
1461 qopr = pci_quatech_rqopr(port);
1463 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1464 reg = pci_quatech_rqopr(port);
1465 if (reg & QOPR_CLOCK_X8) {
1469 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1470 reg = pci_quatech_rqopr(port);
1471 if (!(reg & QOPR_CLOCK_X8)) {
1475 reg &= QOPR_CLOCK_X8;
1476 if (reg == QOPR_CLOCK_X2) {
1478 set = QOPR_CLOCK_X2;
1479 } else if (reg == QOPR_CLOCK_X4) {
1481 set = QOPR_CLOCK_X4;
1482 } else if (reg == QOPR_CLOCK_X8) {
1484 set = QOPR_CLOCK_X8;
1487 set = QOPR_CLOCK_X1;
1489 qopr &= ~QOPR_CLOCK_RATE_MASK;
1493 pci_quatech_wqopr(port, qopr);
1497 static int pci_quatech_rs422(struct uart_8250_port *port)
1502 if (!pci_quatech_has_qmcr(port))
1504 qmcr = pci_quatech_rqmcr(port);
1505 pci_quatech_wqmcr(port, 0xFF);
1506 if (pci_quatech_rqmcr(port))
1508 pci_quatech_wqmcr(port, qmcr);
1512 static int pci_quatech_init(struct pci_dev *dev)
1514 const struct pci_device_id *match;
1517 match = pci_match_id(quatech_cards, dev);
1519 amcc = match->driver_data;
1521 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1524 unsigned long base = pci_resource_start(dev, 0);
1528 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1529 tmp = inl(base + 0x3c);
1530 outl(tmp | 0x01000000, base + 0x3c);
1531 outl(tmp & ~0x01000000, base + 0x3c);
1537 static int pci_quatech_setup(struct serial_private *priv,
1538 const struct pciserial_board *board,
1539 struct uart_8250_port *port, int idx)
1541 /* Needed by pci_quatech calls below */
1542 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1543 /* Set up the clocking */
1544 port->port.uartclk = pci_quatech_clock(port);
1545 /* For now just warn about RS422 */
1546 if (pci_quatech_rs422(port))
1547 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1548 return pci_default_setup(priv, board, port, idx);
1551 static int pci_default_setup(struct serial_private *priv,
1552 const struct pciserial_board *board,
1553 struct uart_8250_port *port, int idx)
1555 unsigned int bar, offset = board->first_offset, maxnr;
1557 bar = FL_GET_BASE(board->flags);
1558 if (board->flags & FL_BASE_BARS)
1561 offset += idx * board->uart_offset;
1563 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1564 (board->reg_shift + 3);
1566 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1569 return setup_port(priv, port, bar, offset, board->reg_shift);
1573 ce4100_serial_setup(struct serial_private *priv,
1574 const struct pciserial_board *board,
1575 struct uart_8250_port *port, int idx)
1579 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1580 port->port.iotype = UPIO_MEM32;
1581 port->port.type = PORT_XSCALE;
1582 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1583 port->port.regshift = 2;
1589 pci_omegapci_setup(struct serial_private *priv,
1590 const struct pciserial_board *board,
1591 struct uart_8250_port *port, int idx)
1593 return setup_port(priv, port, 2, idx * 8, 0);
1597 pci_brcm_trumanage_setup(struct serial_private *priv,
1598 const struct pciserial_board *board,
1599 struct uart_8250_port *port, int idx)
1601 int ret = pci_default_setup(priv, board, port, idx);
1603 port->port.type = PORT_BRCM_TRUMANAGE;
1604 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1608 /* RTS will control by MCR if this bit is 0 */
1609 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1610 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1611 #define FINTEK_RTS_INVERT BIT(5)
1613 /* We should do proper H/W transceiver setting before change to RS485 mode */
1614 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1615 struct serial_rs485 *rs485)
1617 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1619 u8 *index = (u8 *) port->private_data;
1621 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1623 if (rs485->flags & SER_RS485_ENABLED) {
1624 /* Enable RTS H/W control mode */
1625 setting |= FINTEK_RTS_CONTROL_BY_HW;
1627 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1628 /* RTS driving high on TX */
1629 setting &= ~FINTEK_RTS_INVERT;
1631 /* RTS driving low on TX */
1632 setting |= FINTEK_RTS_INVERT;
1635 /* Disable RTS H/W control mode */
1636 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1639 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1644 static const struct serial_rs485 pci_fintek_rs485_supported = {
1645 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
1646 /* F81504/508/512 does not support RTS delay before or after send */
1649 static int pci_fintek_setup(struct serial_private *priv,
1650 const struct pciserial_board *board,
1651 struct uart_8250_port *port, int idx)
1653 struct pci_dev *pdev = priv->dev;
1658 config_base = 0x40 + 0x08 * idx;
1660 /* Get the io address from configuration space */
1661 pci_read_config_word(pdev, config_base + 4, &iobase);
1663 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1665 port->port.iotype = UPIO_PORT;
1666 port->port.iobase = iobase;
1667 port->port.rs485_config = pci_fintek_rs485_config;
1668 port->port.rs485_supported = pci_fintek_rs485_supported;
1670 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1674 /* preserve index in PCI configuration space */
1676 port->port.private_data = data;
1681 static int pci_fintek_init(struct pci_dev *dev)
1683 unsigned long iobase;
1685 resource_size_t bar_data[3];
1687 struct serial_private *priv = pci_get_drvdata(dev);
1689 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1690 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1691 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1694 switch (dev->device) {
1695 case 0x1104: /* 4 ports */
1696 case 0x1108: /* 8 ports */
1697 max_port = dev->device & 0xff;
1699 case 0x1112: /* 12 ports */
1706 /* Get the io address dispatch from the BIOS */
1707 bar_data[0] = pci_resource_start(dev, 5);
1708 bar_data[1] = pci_resource_start(dev, 4);
1709 bar_data[2] = pci_resource_start(dev, 3);
1711 for (i = 0; i < max_port; ++i) {
1712 /* UART0 configuration offset start from 0x40 */
1713 config_base = 0x40 + 0x08 * i;
1715 /* Calculate Real IO Port */
1716 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1718 /* Enable UART I/O port */
1719 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1721 /* Select 128-byte FIFO and 8x FIFO threshold */
1722 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1725 pci_write_config_byte(dev, config_base + 0x04,
1726 (u8)(iobase & 0xff));
1729 pci_write_config_byte(dev, config_base + 0x05,
1730 (u8)((iobase & 0xff00) >> 8));
1732 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1735 /* First init without port data
1736 * force init to RS232 Mode
1738 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1745 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1747 struct f815xxa_data *data = p->private_data;
1748 unsigned long flags;
1750 spin_lock_irqsave(&data->lock, flags);
1751 writeb(value, p->membase + offset);
1752 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1753 spin_unlock_irqrestore(&data->lock, flags);
1756 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1757 const struct pciserial_board *board,
1758 struct uart_8250_port *port, int idx)
1760 struct pci_dev *pdev = priv->dev;
1761 struct f815xxa_data *data;
1763 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1768 spin_lock_init(&data->lock);
1770 port->port.private_data = data;
1771 port->port.iotype = UPIO_MEM;
1772 port->port.flags |= UPF_IOREMAP;
1773 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1774 port->port.serial_out = f815xxa_mem_serial_out;
1779 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1784 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1787 switch (dev->device) {
1788 case 0x1204: /* 4 ports */
1789 case 0x1208: /* 8 ports */
1790 max_port = dev->device & 0xff;
1792 case 0x1212: /* 12 ports */
1799 /* Set to mmio decode */
1800 pci_write_config_byte(dev, 0x209, 0x40);
1802 for (i = 0; i < max_port; ++i) {
1803 /* UART0 configuration offset start from 0x2A0 */
1804 config_base = 0x2A0 + 0x08 * i;
1806 /* Select 128-byte FIFO and 8x FIFO threshold */
1807 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1809 /* Enable UART I/O port */
1810 pci_write_config_byte(dev, config_base + 0, 0x01);
1816 static int skip_tx_en_setup(struct serial_private *priv,
1817 const struct pciserial_board *board,
1818 struct uart_8250_port *port, int idx)
1820 port->port.quirks |= UPQ_NO_TXEN_TEST;
1822 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1823 priv->dev->vendor, priv->dev->device,
1824 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1826 return pci_default_setup(priv, board, port, idx);
1829 static void kt_handle_break(struct uart_port *p)
1831 struct uart_8250_port *up = up_to_u8250p(p);
1833 * On receipt of a BI, serial device in Intel ME (Intel
1834 * management engine) needs to have its fifos cleared for sane
1835 * SOL (Serial Over Lan) output.
1837 serial8250_clear_and_reinit_fifos(up);
1840 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1842 struct uart_8250_port *up = up_to_u8250p(p);
1846 * When the Intel ME (management engine) gets reset its serial
1847 * port registers could return 0 momentarily. Functions like
1848 * serial8250_console_write, read and save the IER, perform
1849 * some operation and then restore it. In order to avoid
1850 * setting IER register inadvertently to 0, if the value read
1851 * is 0, double check with ier value in uart_8250_port and use
1852 * that instead. up->ier should be the same value as what is
1853 * currently configured.
1855 val = inb(p->iobase + offset);
1856 if (offset == UART_IER) {
1863 static int kt_serial_setup(struct serial_private *priv,
1864 const struct pciserial_board *board,
1865 struct uart_8250_port *port, int idx)
1867 port->port.flags |= UPF_BUG_THRE;
1868 port->port.serial_in = kt_serial_in;
1869 port->port.handle_break = kt_handle_break;
1870 return skip_tx_en_setup(priv, board, port, idx);
1873 static int pci_eg20t_init(struct pci_dev *dev)
1875 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1883 pci_wch_ch353_setup(struct serial_private *priv,
1884 const struct pciserial_board *board,
1885 struct uart_8250_port *port, int idx)
1887 port->port.flags |= UPF_FIXED_TYPE;
1888 port->port.type = PORT_16550A;
1889 return pci_default_setup(priv, board, port, idx);
1893 pci_wch_ch355_setup(struct serial_private *priv,
1894 const struct pciserial_board *board,
1895 struct uart_8250_port *port, int idx)
1897 port->port.flags |= UPF_FIXED_TYPE;
1898 port->port.type = PORT_16550A;
1899 return pci_default_setup(priv, board, port, idx);
1903 pci_wch_ch38x_setup(struct serial_private *priv,
1904 const struct pciserial_board *board,
1905 struct uart_8250_port *port, int idx)
1907 port->port.flags |= UPF_FIXED_TYPE;
1908 port->port.type = PORT_16850;
1909 return pci_default_setup(priv, board, port, idx);
1913 #define CH384_XINT_ENABLE_REG 0xEB
1914 #define CH384_XINT_ENABLE_BIT 0x02
1916 static int pci_wch_ch38x_init(struct pci_dev *dev)
1919 unsigned long iobase;
1922 switch (dev->device) {
1923 case 0x3853: /* 8 ports */
1930 iobase = pci_resource_start(dev, 0);
1931 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1936 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1938 unsigned long iobase;
1940 iobase = pci_resource_start(dev, 0);
1941 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1946 pci_sunix_setup(struct serial_private *priv,
1947 const struct pciserial_board *board,
1948 struct uart_8250_port *port, int idx)
1953 port->port.flags |= UPF_FIXED_TYPE;
1954 port->port.type = PORT_SUNIX;
1958 offset = idx * board->uart_offset;
1962 idx = div_s64_rem(idx, 4, &offset);
1963 offset = idx * 64 + offset * board->uart_offset;
1966 return setup_port(priv, port, bar, offset, 0);
1969 #define MOXA_PUART_GPIO_EN 0x09
1970 #define MOXA_PUART_GPIO_OUT 0x0A
1972 #define MOXA_GPIO_PIN2 BIT(2)
1974 #define MOXA_RS232 0x00
1975 #define MOXA_RS422 0x01
1976 #define MOXA_RS485_4W 0x0B
1977 #define MOXA_RS485_2W 0x0F
1978 #define MOXA_UIR_OFFSET 0x04
1979 #define MOXA_EVEN_RS_MASK GENMASK(3, 0)
1980 #define MOXA_ODD_RS_MASK GENMASK(7, 4)
1983 MOXA_SUPP_RS232 = BIT(0),
1984 MOXA_SUPP_RS422 = BIT(1),
1985 MOXA_SUPP_RS485 = BIT(2),
1988 static bool pci_moxa_is_mini_pcie(unsigned short device)
1990 if (device == PCI_DEVICE_ID_MOXA_CP102N ||
1991 device == PCI_DEVICE_ID_MOXA_CP104N ||
1992 device == PCI_DEVICE_ID_MOXA_CP112N ||
1993 device == PCI_DEVICE_ID_MOXA_CP114N ||
1994 device == PCI_DEVICE_ID_MOXA_CP132N ||
1995 device == PCI_DEVICE_ID_MOXA_CP134N)
2001 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)
2003 switch (dev->device & 0x0F00) {
2006 return MOXA_SUPP_RS232;
2008 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2010 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2015 static int pci_moxa_set_interface(const struct pci_dev *dev,
2016 unsigned int port_idx,
2019 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2020 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
2023 val = inb(UIR_addr);
2026 val &= ~MOXA_ODD_RS_MASK;
2027 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
2029 val &= ~MOXA_EVEN_RS_MASK;
2030 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
2032 outb(val, UIR_addr);
2037 static int pci_moxa_init(struct pci_dev *dev)
2039 unsigned short device = dev->device;
2040 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2041 unsigned int num_ports = (device & 0x00F0) >> 4, i;
2042 u8 val, init_mode = MOXA_RS232;
2044 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {
2045 init_mode = MOXA_RS422;
2047 for (i = 0; i < num_ports; ++i)
2048 pci_moxa_set_interface(dev, i, init_mode);
2051 * Enable hardware buffer to prevent break signal output when system boots up.
2052 * This hardware buffer is only supported on Mini PCIe series.
2054 if (pci_moxa_is_mini_pcie(device)) {
2055 /* Set GPIO direction */
2056 val = inb(iobar_addr + MOXA_PUART_GPIO_EN);
2057 val |= MOXA_GPIO_PIN2;
2058 outb(val, iobar_addr + MOXA_PUART_GPIO_EN);
2059 /* Enable low GPIO */
2060 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT);
2061 val &= ~MOXA_GPIO_PIN2;
2062 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT);
2069 pci_moxa_setup(struct serial_private *priv,
2070 const struct pciserial_board *board,
2071 struct uart_8250_port *port, int idx)
2073 unsigned int bar = FL_GET_BASE(board->flags);
2076 if (board->num_ports == 4 && idx == 3)
2077 offset = 7 * board->uart_offset;
2079 offset = idx * board->uart_offset;
2081 return setup_port(priv, port, bar, offset, 0);
2085 * Master list of serial port init/setup/exit quirks.
2086 * This does not describe the general nature of the port.
2087 * (ie, baud base, number and location of ports, etc)
2089 * This list is ordered alphabetically by vendor then device.
2090 * Specific entries must come before more generic entries.
2092 static struct pci_serial_quirk pci_serial_quirks[] = {
2094 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2097 .vendor = PCI_VENDOR_ID_AMCC,
2098 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2099 .subvendor = PCI_ANY_ID,
2100 .subdevice = PCI_ANY_ID,
2101 .setup = addidata_apci7800_setup,
2104 * AFAVLAB cards - these may be called via parport_serial
2105 * It is not clear whether this applies to all products.
2108 .vendor = PCI_VENDOR_ID_AFAVLAB,
2109 .device = PCI_ANY_ID,
2110 .subvendor = PCI_ANY_ID,
2111 .subdevice = PCI_ANY_ID,
2112 .setup = afavlab_setup,
2118 .vendor = PCI_VENDOR_ID_HP,
2119 .device = PCI_DEVICE_ID_HP_DIVA,
2120 .subvendor = PCI_ANY_ID,
2121 .subdevice = PCI_ANY_ID,
2122 .init = pci_hp_diva_init,
2123 .setup = pci_hp_diva_setup,
2126 * HPE PCI serial device
2129 .vendor = PCI_VENDOR_ID_HP_3PAR,
2130 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2131 .subvendor = PCI_ANY_ID,
2132 .subdevice = PCI_ANY_ID,
2133 .setup = pci_hp_diva_setup,
2139 .vendor = PCI_VENDOR_ID_INTEL,
2140 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2141 .subvendor = 0xe4bf,
2142 .subdevice = PCI_ANY_ID,
2143 .init = pci_inteli960ni_init,
2144 .setup = pci_default_setup,
2147 .vendor = PCI_VENDOR_ID_INTEL,
2148 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2149 .subvendor = PCI_ANY_ID,
2150 .subdevice = PCI_ANY_ID,
2151 .setup = skip_tx_en_setup,
2154 .vendor = PCI_VENDOR_ID_INTEL,
2155 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2156 .subvendor = PCI_ANY_ID,
2157 .subdevice = PCI_ANY_ID,
2158 .setup = skip_tx_en_setup,
2161 .vendor = PCI_VENDOR_ID_INTEL,
2162 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2163 .subvendor = PCI_ANY_ID,
2164 .subdevice = PCI_ANY_ID,
2165 .setup = skip_tx_en_setup,
2168 .vendor = PCI_VENDOR_ID_INTEL,
2169 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2170 .subvendor = PCI_ANY_ID,
2171 .subdevice = PCI_ANY_ID,
2172 .setup = ce4100_serial_setup,
2175 .vendor = PCI_VENDOR_ID_INTEL,
2176 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2177 .subvendor = PCI_ANY_ID,
2178 .subdevice = PCI_ANY_ID,
2179 .setup = kt_serial_setup,
2185 .vendor = PCI_VENDOR_ID_ITE,
2186 .device = PCI_DEVICE_ID_ITE_8872,
2187 .subvendor = PCI_ANY_ID,
2188 .subdevice = PCI_ANY_ID,
2189 .init = pci_ite887x_init,
2190 .setup = pci_default_setup,
2191 .exit = pci_ite887x_exit,
2194 * National Instruments
2197 .vendor = PCI_VENDOR_ID_NI,
2198 .device = PCI_DEVICE_ID_NI_PCI23216,
2199 .subvendor = PCI_ANY_ID,
2200 .subdevice = PCI_ANY_ID,
2201 .init = pci_ni8420_init,
2202 .setup = pci_default_setup,
2203 .exit = pci_ni8420_exit,
2206 .vendor = PCI_VENDOR_ID_NI,
2207 .device = PCI_DEVICE_ID_NI_PCI2328,
2208 .subvendor = PCI_ANY_ID,
2209 .subdevice = PCI_ANY_ID,
2210 .init = pci_ni8420_init,
2211 .setup = pci_default_setup,
2212 .exit = pci_ni8420_exit,
2215 .vendor = PCI_VENDOR_ID_NI,
2216 .device = PCI_DEVICE_ID_NI_PCI2324,
2217 .subvendor = PCI_ANY_ID,
2218 .subdevice = PCI_ANY_ID,
2219 .init = pci_ni8420_init,
2220 .setup = pci_default_setup,
2221 .exit = pci_ni8420_exit,
2224 .vendor = PCI_VENDOR_ID_NI,
2225 .device = PCI_DEVICE_ID_NI_PCI2322,
2226 .subvendor = PCI_ANY_ID,
2227 .subdevice = PCI_ANY_ID,
2228 .init = pci_ni8420_init,
2229 .setup = pci_default_setup,
2230 .exit = pci_ni8420_exit,
2233 .vendor = PCI_VENDOR_ID_NI,
2234 .device = PCI_DEVICE_ID_NI_PCI2324I,
2235 .subvendor = PCI_ANY_ID,
2236 .subdevice = PCI_ANY_ID,
2237 .init = pci_ni8420_init,
2238 .setup = pci_default_setup,
2239 .exit = pci_ni8420_exit,
2242 .vendor = PCI_VENDOR_ID_NI,
2243 .device = PCI_DEVICE_ID_NI_PCI2322I,
2244 .subvendor = PCI_ANY_ID,
2245 .subdevice = PCI_ANY_ID,
2246 .init = pci_ni8420_init,
2247 .setup = pci_default_setup,
2248 .exit = pci_ni8420_exit,
2251 .vendor = PCI_VENDOR_ID_NI,
2252 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .init = pci_ni8420_init,
2256 .setup = pci_default_setup,
2257 .exit = pci_ni8420_exit,
2260 .vendor = PCI_VENDOR_ID_NI,
2261 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2262 .subvendor = PCI_ANY_ID,
2263 .subdevice = PCI_ANY_ID,
2264 .init = pci_ni8420_init,
2265 .setup = pci_default_setup,
2266 .exit = pci_ni8420_exit,
2269 .vendor = PCI_VENDOR_ID_NI,
2270 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2271 .subvendor = PCI_ANY_ID,
2272 .subdevice = PCI_ANY_ID,
2273 .init = pci_ni8420_init,
2274 .setup = pci_default_setup,
2275 .exit = pci_ni8420_exit,
2278 .vendor = PCI_VENDOR_ID_NI,
2279 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2280 .subvendor = PCI_ANY_ID,
2281 .subdevice = PCI_ANY_ID,
2282 .init = pci_ni8420_init,
2283 .setup = pci_default_setup,
2284 .exit = pci_ni8420_exit,
2287 .vendor = PCI_VENDOR_ID_NI,
2288 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2289 .subvendor = PCI_ANY_ID,
2290 .subdevice = PCI_ANY_ID,
2291 .init = pci_ni8420_init,
2292 .setup = pci_default_setup,
2293 .exit = pci_ni8420_exit,
2296 .vendor = PCI_VENDOR_ID_NI,
2297 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2298 .subvendor = PCI_ANY_ID,
2299 .subdevice = PCI_ANY_ID,
2300 .init = pci_ni8420_init,
2301 .setup = pci_default_setup,
2302 .exit = pci_ni8420_exit,
2305 .vendor = PCI_VENDOR_ID_NI,
2306 .device = PCI_ANY_ID,
2307 .subvendor = PCI_ANY_ID,
2308 .subdevice = PCI_ANY_ID,
2309 .init = pci_ni8430_init,
2310 .setup = pci_ni8430_setup,
2311 .exit = pci_ni8430_exit,
2315 .vendor = PCI_VENDOR_ID_QUATECH,
2316 .device = PCI_ANY_ID,
2317 .subvendor = PCI_ANY_ID,
2318 .subdevice = PCI_ANY_ID,
2319 .init = pci_quatech_init,
2320 .setup = pci_quatech_setup,
2326 .vendor = PCI_VENDOR_ID_PANACOM,
2327 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2328 .subvendor = PCI_ANY_ID,
2329 .subdevice = PCI_ANY_ID,
2330 .init = pci_plx9050_init,
2331 .setup = pci_default_setup,
2332 .exit = pci_plx9050_exit,
2335 .vendor = PCI_VENDOR_ID_PANACOM,
2336 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2337 .subvendor = PCI_ANY_ID,
2338 .subdevice = PCI_ANY_ID,
2339 .init = pci_plx9050_init,
2340 .setup = pci_default_setup,
2341 .exit = pci_plx9050_exit,
2347 .vendor = PCI_VENDOR_ID_PLX,
2348 .device = PCI_DEVICE_ID_PLX_9050,
2349 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2350 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2351 .init = pci_plx9050_init,
2352 .setup = pci_default_setup,
2353 .exit = pci_plx9050_exit,
2356 .vendor = PCI_VENDOR_ID_PLX,
2357 .device = PCI_DEVICE_ID_PLX_9050,
2358 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2359 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2360 .init = pci_plx9050_init,
2361 .setup = pci_default_setup,
2362 .exit = pci_plx9050_exit,
2365 .vendor = PCI_VENDOR_ID_PLX,
2366 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2367 .subvendor = PCI_VENDOR_ID_PLX,
2368 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2369 .init = pci_plx9050_init,
2370 .setup = pci_default_setup,
2371 .exit = pci_plx9050_exit,
2374 * SBS Technologies, Inc., PMC-OCTALPRO 232
2377 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2378 .device = PCI_DEVICE_ID_OCTPRO,
2379 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2380 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2386 * SBS Technologies, Inc., PMC-OCTALPRO 422
2389 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2390 .device = PCI_DEVICE_ID_OCTPRO,
2391 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2392 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2398 * SBS Technologies, Inc., P-Octal 232
2401 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2402 .device = PCI_DEVICE_ID_OCTPRO,
2403 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2404 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2410 * SBS Technologies, Inc., P-Octal 422
2413 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2414 .device = PCI_DEVICE_ID_OCTPRO,
2415 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2416 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2422 * SIIG cards - these may be called via parport_serial
2425 .vendor = PCI_VENDOR_ID_SIIG,
2426 .device = PCI_ANY_ID,
2427 .subvendor = PCI_ANY_ID,
2428 .subdevice = PCI_ANY_ID,
2429 .init = pci_siig_init,
2430 .setup = pci_siig_setup,
2436 .vendor = PCI_VENDOR_ID_TITAN,
2437 .device = PCI_DEVICE_ID_TITAN_400L,
2438 .subvendor = PCI_ANY_ID,
2439 .subdevice = PCI_ANY_ID,
2440 .setup = titan_400l_800l_setup,
2443 .vendor = PCI_VENDOR_ID_TITAN,
2444 .device = PCI_DEVICE_ID_TITAN_800L,
2445 .subvendor = PCI_ANY_ID,
2446 .subdevice = PCI_ANY_ID,
2447 .setup = titan_400l_800l_setup,
2453 .vendor = PCI_VENDOR_ID_TIMEDIA,
2454 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2455 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2456 .subdevice = PCI_ANY_ID,
2457 .probe = pci_timedia_probe,
2458 .init = pci_timedia_init,
2459 .setup = pci_timedia_setup,
2462 .vendor = PCI_VENDOR_ID_TIMEDIA,
2463 .device = PCI_ANY_ID,
2464 .subvendor = PCI_ANY_ID,
2465 .subdevice = PCI_ANY_ID,
2466 .setup = pci_timedia_setup,
2469 * Sunix PCI serial boards
2472 .vendor = PCI_VENDOR_ID_SUNIX,
2473 .device = PCI_DEVICE_ID_SUNIX_1999,
2474 .subvendor = PCI_VENDOR_ID_SUNIX,
2475 .subdevice = PCI_ANY_ID,
2476 .setup = pci_sunix_setup,
2482 .vendor = PCI_VENDOR_ID_XIRCOM,
2483 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2484 .subvendor = PCI_ANY_ID,
2485 .subdevice = PCI_ANY_ID,
2486 .init = pci_xircom_init,
2487 .setup = pci_default_setup,
2490 * Netmos cards - these may be called via parport_serial
2493 .vendor = PCI_VENDOR_ID_NETMOS,
2494 .device = PCI_ANY_ID,
2495 .subvendor = PCI_ANY_ID,
2496 .subdevice = PCI_ANY_ID,
2497 .init = pci_netmos_init,
2498 .setup = pci_netmos_9900_setup,
2501 * EndRun Technologies
2504 .vendor = PCI_VENDOR_ID_ENDRUN,
2505 .device = PCI_ANY_ID,
2506 .subvendor = PCI_ANY_ID,
2507 .subdevice = PCI_ANY_ID,
2508 .init = pci_oxsemi_tornado_init,
2509 .setup = pci_default_setup,
2512 * For Oxford Semiconductor Tornado based devices
2515 .vendor = PCI_VENDOR_ID_OXSEMI,
2516 .device = PCI_ANY_ID,
2517 .subvendor = PCI_ANY_ID,
2518 .subdevice = PCI_ANY_ID,
2519 .init = pci_oxsemi_tornado_init,
2520 .setup = pci_oxsemi_tornado_setup,
2523 .vendor = PCI_VENDOR_ID_MAINPINE,
2524 .device = PCI_ANY_ID,
2525 .subvendor = PCI_ANY_ID,
2526 .subdevice = PCI_ANY_ID,
2527 .init = pci_oxsemi_tornado_init,
2528 .setup = pci_oxsemi_tornado_setup,
2531 .vendor = PCI_VENDOR_ID_DIGI,
2532 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2533 .subvendor = PCI_SUBVENDOR_ID_IBM,
2534 .subdevice = PCI_ANY_ID,
2535 .init = pci_oxsemi_tornado_init,
2536 .setup = pci_oxsemi_tornado_setup,
2539 * Brainboxes devices - all Oxsemi based
2542 .vendor = PCI_VENDOR_ID_INTASHIELD,
2544 .subvendor = PCI_ANY_ID,
2545 .subdevice = PCI_ANY_ID,
2546 .init = pci_oxsemi_tornado_init,
2547 .setup = pci_oxsemi_tornado_setup,
2550 .vendor = PCI_VENDOR_ID_INTASHIELD,
2552 .subvendor = PCI_ANY_ID,
2553 .subdevice = PCI_ANY_ID,
2554 .init = pci_oxsemi_tornado_init,
2555 .setup = pci_oxsemi_tornado_setup,
2558 .vendor = PCI_VENDOR_ID_INTASHIELD,
2560 .subvendor = PCI_ANY_ID,
2561 .subdevice = PCI_ANY_ID,
2562 .init = pci_oxsemi_tornado_init,
2563 .setup = pci_oxsemi_tornado_setup,
2566 .vendor = PCI_VENDOR_ID_INTASHIELD,
2568 .subvendor = PCI_ANY_ID,
2569 .subdevice = PCI_ANY_ID,
2570 .init = pci_oxsemi_tornado_init,
2571 .setup = pci_oxsemi_tornado_setup,
2574 .vendor = PCI_VENDOR_ID_INTASHIELD,
2576 .subvendor = PCI_ANY_ID,
2577 .subdevice = PCI_ANY_ID,
2578 .init = pci_oxsemi_tornado_init,
2579 .setup = pci_oxsemi_tornado_setup,
2582 .vendor = PCI_VENDOR_ID_INTASHIELD,
2584 .subvendor = PCI_ANY_ID,
2585 .subdevice = PCI_ANY_ID,
2586 .init = pci_oxsemi_tornado_init,
2587 .setup = pci_oxsemi_tornado_setup,
2590 .vendor = PCI_VENDOR_ID_INTASHIELD,
2592 .subvendor = PCI_ANY_ID,
2593 .subdevice = PCI_ANY_ID,
2594 .init = pci_oxsemi_tornado_init,
2595 .setup = pci_oxsemi_tornado_setup,
2598 .vendor = PCI_VENDOR_ID_INTASHIELD,
2600 .subvendor = PCI_ANY_ID,
2601 .subdevice = PCI_ANY_ID,
2602 .init = pci_oxsemi_tornado_init,
2603 .setup = pci_oxsemi_tornado_setup,
2606 .vendor = PCI_VENDOR_ID_INTASHIELD,
2608 .subvendor = PCI_ANY_ID,
2609 .subdevice = PCI_ANY_ID,
2610 .init = pci_oxsemi_tornado_init,
2611 .setup = pci_oxsemi_tornado_setup,
2614 .vendor = PCI_VENDOR_ID_INTASHIELD,
2616 .subvendor = PCI_ANY_ID,
2617 .subdevice = PCI_ANY_ID,
2618 .init = pci_oxsemi_tornado_init,
2619 .setup = pci_oxsemi_tornado_setup,
2622 .vendor = PCI_VENDOR_ID_INTASHIELD,
2624 .subvendor = PCI_ANY_ID,
2625 .subdevice = PCI_ANY_ID,
2626 .init = pci_oxsemi_tornado_init,
2627 .setup = pci_oxsemi_tornado_setup,
2630 .vendor = PCI_VENDOR_ID_INTASHIELD,
2632 .subvendor = PCI_ANY_ID,
2633 .subdevice = PCI_ANY_ID,
2634 .init = pci_oxsemi_tornado_init,
2635 .setup = pci_oxsemi_tornado_setup,
2638 .vendor = PCI_VENDOR_ID_INTASHIELD,
2640 .subvendor = PCI_ANY_ID,
2641 .subdevice = PCI_ANY_ID,
2642 .init = pci_oxsemi_tornado_init,
2643 .setup = pci_oxsemi_tornado_setup,
2646 .vendor = PCI_VENDOR_ID_INTASHIELD,
2648 .subvendor = PCI_ANY_ID,
2649 .subdevice = PCI_ANY_ID,
2650 .init = pci_oxsemi_tornado_init,
2651 .setup = pci_oxsemi_tornado_setup,
2654 .vendor = PCI_VENDOR_ID_INTASHIELD,
2656 .subvendor = PCI_ANY_ID,
2657 .subdevice = PCI_ANY_ID,
2658 .init = pci_oxsemi_tornado_init,
2659 .setup = pci_oxsemi_tornado_setup,
2662 .vendor = PCI_VENDOR_ID_INTASHIELD,
2664 .subvendor = PCI_ANY_ID,
2665 .subdevice = PCI_ANY_ID,
2666 .init = pci_oxsemi_tornado_init,
2667 .setup = pci_oxsemi_tornado_setup,
2670 .vendor = PCI_VENDOR_ID_INTASHIELD,
2672 .subvendor = PCI_ANY_ID,
2673 .subdevice = PCI_ANY_ID,
2674 .init = pci_oxsemi_tornado_init,
2675 .setup = pci_oxsemi_tornado_setup,
2678 .vendor = PCI_VENDOR_ID_INTASHIELD,
2680 .subvendor = PCI_ANY_ID,
2681 .subdevice = PCI_ANY_ID,
2682 .init = pci_oxsemi_tornado_init,
2683 .setup = pci_oxsemi_tornado_setup,
2686 .vendor = PCI_VENDOR_ID_INTEL,
2688 .subvendor = PCI_ANY_ID,
2689 .subdevice = PCI_ANY_ID,
2690 .init = pci_eg20t_init,
2691 .setup = pci_default_setup,
2694 .vendor = PCI_VENDOR_ID_INTEL,
2696 .subvendor = PCI_ANY_ID,
2697 .subdevice = PCI_ANY_ID,
2698 .init = pci_eg20t_init,
2699 .setup = pci_default_setup,
2702 .vendor = PCI_VENDOR_ID_INTEL,
2704 .subvendor = PCI_ANY_ID,
2705 .subdevice = PCI_ANY_ID,
2706 .init = pci_eg20t_init,
2707 .setup = pci_default_setup,
2710 .vendor = PCI_VENDOR_ID_INTEL,
2712 .subvendor = PCI_ANY_ID,
2713 .subdevice = PCI_ANY_ID,
2714 .init = pci_eg20t_init,
2715 .setup = pci_default_setup,
2720 .subvendor = PCI_ANY_ID,
2721 .subdevice = PCI_ANY_ID,
2722 .init = pci_eg20t_init,
2723 .setup = pci_default_setup,
2728 .subvendor = PCI_ANY_ID,
2729 .subdevice = PCI_ANY_ID,
2730 .init = pci_eg20t_init,
2731 .setup = pci_default_setup,
2736 .subvendor = PCI_ANY_ID,
2737 .subdevice = PCI_ANY_ID,
2738 .init = pci_eg20t_init,
2739 .setup = pci_default_setup,
2744 .subvendor = PCI_ANY_ID,
2745 .subdevice = PCI_ANY_ID,
2746 .init = pci_eg20t_init,
2747 .setup = pci_default_setup,
2752 .subvendor = PCI_ANY_ID,
2753 .subdevice = PCI_ANY_ID,
2754 .init = pci_eg20t_init,
2755 .setup = pci_default_setup,
2758 * Cronyx Omega PCI (PLX-chip based)
2761 .vendor = PCI_VENDOR_ID_PLX,
2762 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2763 .subvendor = PCI_ANY_ID,
2764 .subdevice = PCI_ANY_ID,
2765 .setup = pci_omegapci_setup,
2767 /* WCH CH353 1S1P card (16550 clone) */
2769 .vendor = PCI_VENDOR_ID_WCH,
2770 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2771 .subvendor = PCI_ANY_ID,
2772 .subdevice = PCI_ANY_ID,
2773 .setup = pci_wch_ch353_setup,
2775 /* WCH CH353 2S1P card (16550 clone) */
2777 .vendor = PCI_VENDOR_ID_WCH,
2778 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2779 .subvendor = PCI_ANY_ID,
2780 .subdevice = PCI_ANY_ID,
2781 .setup = pci_wch_ch353_setup,
2783 /* WCH CH353 4S card (16550 clone) */
2785 .vendor = PCI_VENDOR_ID_WCH,
2786 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2787 .subvendor = PCI_ANY_ID,
2788 .subdevice = PCI_ANY_ID,
2789 .setup = pci_wch_ch353_setup,
2791 /* WCH CH353 2S1PF card (16550 clone) */
2793 .vendor = PCI_VENDOR_ID_WCH,
2794 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2795 .subvendor = PCI_ANY_ID,
2796 .subdevice = PCI_ANY_ID,
2797 .setup = pci_wch_ch353_setup,
2799 /* WCH CH352 2S card (16550 clone) */
2801 .vendor = PCI_VENDOR_ID_WCH,
2802 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2803 .subvendor = PCI_ANY_ID,
2804 .subdevice = PCI_ANY_ID,
2805 .setup = pci_wch_ch353_setup,
2807 /* WCH CH355 4S card (16550 clone) */
2809 .vendor = PCI_VENDOR_ID_WCH,
2810 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2811 .subvendor = PCI_ANY_ID,
2812 .subdevice = PCI_ANY_ID,
2813 .setup = pci_wch_ch355_setup,
2815 /* WCH CH382 2S card (16850 clone) */
2817 .vendor = PCIE_VENDOR_ID_WCH,
2818 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2819 .subvendor = PCI_ANY_ID,
2820 .subdevice = PCI_ANY_ID,
2821 .setup = pci_wch_ch38x_setup,
2823 /* WCH CH382 2S1P card (16850 clone) */
2825 .vendor = PCIE_VENDOR_ID_WCH,
2826 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2827 .subvendor = PCI_ANY_ID,
2828 .subdevice = PCI_ANY_ID,
2829 .setup = pci_wch_ch38x_setup,
2831 /* WCH CH384 4S card (16850 clone) */
2833 .vendor = PCIE_VENDOR_ID_WCH,
2834 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2835 .subvendor = PCI_ANY_ID,
2836 .subdevice = PCI_ANY_ID,
2837 .setup = pci_wch_ch38x_setup,
2839 /* WCH CH384 8S card (16850 clone) */
2841 .vendor = PCIE_VENDOR_ID_WCH,
2842 .device = PCIE_DEVICE_ID_WCH_CH384_8S,
2843 .subvendor = PCI_ANY_ID,
2844 .subdevice = PCI_ANY_ID,
2845 .init = pci_wch_ch38x_init,
2846 .exit = pci_wch_ch38x_exit,
2847 .setup = pci_wch_ch38x_setup,
2850 * Broadcom TruManage (NetXtreme)
2853 .vendor = PCI_VENDOR_ID_BROADCOM,
2854 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2855 .subvendor = PCI_ANY_ID,
2856 .subdevice = PCI_ANY_ID,
2857 .setup = pci_brcm_trumanage_setup,
2862 .subvendor = PCI_ANY_ID,
2863 .subdevice = PCI_ANY_ID,
2864 .setup = pci_fintek_setup,
2865 .init = pci_fintek_init,
2870 .subvendor = PCI_ANY_ID,
2871 .subdevice = PCI_ANY_ID,
2872 .setup = pci_fintek_setup,
2873 .init = pci_fintek_init,
2878 .subvendor = PCI_ANY_ID,
2879 .subdevice = PCI_ANY_ID,
2880 .setup = pci_fintek_setup,
2881 .init = pci_fintek_init,
2887 .vendor = PCI_VENDOR_ID_MOXA,
2888 .device = PCI_ANY_ID,
2889 .subvendor = PCI_ANY_ID,
2890 .subdevice = PCI_ANY_ID,
2891 .init = pci_moxa_init,
2892 .setup = pci_moxa_setup,
2897 .subvendor = PCI_ANY_ID,
2898 .subdevice = PCI_ANY_ID,
2899 .setup = pci_fintek_f815xxa_setup,
2900 .init = pci_fintek_f815xxa_init,
2905 .subvendor = PCI_ANY_ID,
2906 .subdevice = PCI_ANY_ID,
2907 .setup = pci_fintek_f815xxa_setup,
2908 .init = pci_fintek_f815xxa_init,
2913 .subvendor = PCI_ANY_ID,
2914 .subdevice = PCI_ANY_ID,
2915 .setup = pci_fintek_f815xxa_setup,
2916 .init = pci_fintek_f815xxa_init,
2920 * Default "match everything" terminator entry
2923 .vendor = PCI_ANY_ID,
2924 .device = PCI_ANY_ID,
2925 .subvendor = PCI_ANY_ID,
2926 .subdevice = PCI_ANY_ID,
2927 .setup = pci_default_setup,
2931 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2933 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2936 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2938 struct pci_serial_quirk *quirk;
2940 for (quirk = pci_serial_quirks; ; quirk++)
2941 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2942 quirk_id_matches(quirk->device, dev->device) &&
2943 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2944 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2950 * This is the configuration table for all of the PCI serial boards
2951 * which we support. It is directly indexed by the pci_board_num_t enum
2952 * value, which is encoded in the pci_device_id PCI probe table's
2953 * driver_data member.
2955 * The makeup of these names are:
2956 * pbn_bn{_bt}_n_baud{_offsetinhex}
2958 * bn = PCI BAR number
2959 * bt = Index using PCI BARs
2960 * n = number of serial ports
2962 * offsetinhex = offset for each sequential port (in hex)
2964 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2966 * Please note: in theory if n = 1, _bt infix should make no difference.
2967 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2969 enum pci_board_num_t {
3063 * Board-specific versions.
3070 pbn_oxsemi_1_15625000,
3071 pbn_oxsemi_2_15625000,
3072 pbn_oxsemi_4_15625000,
3073 pbn_oxsemi_8_15625000,
3085 pbn_ADDIDATA_PCIe_1_3906250,
3086 pbn_ADDIDATA_PCIe_2_3906250,
3087 pbn_ADDIDATA_PCIe_4_3906250,
3088 pbn_ADDIDATA_PCIe_8_3906250,
3089 pbn_ce4100_1_115200,
3091 pbn_NETMOS9900_2s_115200,
3107 pbn_titan_1_4000000,
3108 pbn_titan_2_4000000,
3109 pbn_titan_4_4000000,
3110 pbn_titan_8_4000000,
3117 * uart_offset - the space between channels
3118 * reg_shift - describes how the UART registers are mapped
3119 * to PCI memory by the card.
3120 * For example IER register on SBS, Inc. PMC-OctPro is located at
3121 * offset 0x10 from the UART base, while UART_IER is defined as 1
3122 * in include/linux/serial_reg.h,
3123 * see first lines of serial_in() and serial_out() in 8250.c
3126 static struct pciserial_board pci_boards[] = {
3130 .base_baud = 115200,
3133 [pbn_b0_1_115200] = {
3136 .base_baud = 115200,
3139 [pbn_b0_2_115200] = {
3142 .base_baud = 115200,
3145 [pbn_b0_4_115200] = {
3148 .base_baud = 115200,
3151 [pbn_b0_5_115200] = {
3154 .base_baud = 115200,
3157 [pbn_b0_8_115200] = {
3160 .base_baud = 115200,
3163 [pbn_b0_1_921600] = {
3166 .base_baud = 921600,
3169 [pbn_b0_2_921600] = {
3172 .base_baud = 921600,
3175 [pbn_b0_4_921600] = {
3178 .base_baud = 921600,
3182 [pbn_b0_2_1130000] = {
3185 .base_baud = 1130000,
3189 [pbn_b0_4_1152000] = {
3192 .base_baud = 1152000,
3196 [pbn_b0_4_1250000] = {
3199 .base_baud = 1250000,
3203 [pbn_b0_2_1843200] = {
3206 .base_baud = 1843200,
3209 [pbn_b0_4_1843200] = {
3212 .base_baud = 1843200,
3216 [pbn_b0_1_15625000] = {
3219 .base_baud = 15625000,
3223 [pbn_b0_bt_1_115200] = {
3224 .flags = FL_BASE0|FL_BASE_BARS,
3226 .base_baud = 115200,
3229 [pbn_b0_bt_2_115200] = {
3230 .flags = FL_BASE0|FL_BASE_BARS,
3232 .base_baud = 115200,
3235 [pbn_b0_bt_4_115200] = {
3236 .flags = FL_BASE0|FL_BASE_BARS,
3238 .base_baud = 115200,
3241 [pbn_b0_bt_8_115200] = {
3242 .flags = FL_BASE0|FL_BASE_BARS,
3244 .base_baud = 115200,
3248 [pbn_b0_bt_1_460800] = {
3249 .flags = FL_BASE0|FL_BASE_BARS,
3251 .base_baud = 460800,
3254 [pbn_b0_bt_2_460800] = {
3255 .flags = FL_BASE0|FL_BASE_BARS,
3257 .base_baud = 460800,
3260 [pbn_b0_bt_4_460800] = {
3261 .flags = FL_BASE0|FL_BASE_BARS,
3263 .base_baud = 460800,
3267 [pbn_b0_bt_1_921600] = {
3268 .flags = FL_BASE0|FL_BASE_BARS,
3270 .base_baud = 921600,
3273 [pbn_b0_bt_2_921600] = {
3274 .flags = FL_BASE0|FL_BASE_BARS,
3276 .base_baud = 921600,
3279 [pbn_b0_bt_4_921600] = {
3280 .flags = FL_BASE0|FL_BASE_BARS,
3282 .base_baud = 921600,
3285 [pbn_b0_bt_8_921600] = {
3286 .flags = FL_BASE0|FL_BASE_BARS,
3288 .base_baud = 921600,
3292 [pbn_b1_1_115200] = {
3295 .base_baud = 115200,
3298 [pbn_b1_2_115200] = {
3301 .base_baud = 115200,
3304 [pbn_b1_4_115200] = {
3307 .base_baud = 115200,
3310 [pbn_b1_8_115200] = {
3313 .base_baud = 115200,
3316 [pbn_b1_16_115200] = {
3319 .base_baud = 115200,
3323 [pbn_b1_1_921600] = {
3326 .base_baud = 921600,
3329 [pbn_b1_2_921600] = {
3332 .base_baud = 921600,
3335 [pbn_b1_4_921600] = {
3338 .base_baud = 921600,
3341 [pbn_b1_8_921600] = {
3344 .base_baud = 921600,
3347 [pbn_b1_2_1250000] = {
3350 .base_baud = 1250000,
3354 [pbn_b1_bt_1_115200] = {
3355 .flags = FL_BASE1|FL_BASE_BARS,
3357 .base_baud = 115200,
3360 [pbn_b1_bt_2_115200] = {
3361 .flags = FL_BASE1|FL_BASE_BARS,
3363 .base_baud = 115200,
3366 [pbn_b1_bt_4_115200] = {
3367 .flags = FL_BASE1|FL_BASE_BARS,
3369 .base_baud = 115200,
3373 [pbn_b1_bt_2_921600] = {
3374 .flags = FL_BASE1|FL_BASE_BARS,
3376 .base_baud = 921600,
3380 [pbn_b1_1_1382400] = {
3383 .base_baud = 1382400,
3386 [pbn_b1_2_1382400] = {
3389 .base_baud = 1382400,
3392 [pbn_b1_4_1382400] = {
3395 .base_baud = 1382400,
3398 [pbn_b1_8_1382400] = {
3401 .base_baud = 1382400,
3405 [pbn_b2_1_115200] = {
3408 .base_baud = 115200,
3411 [pbn_b2_2_115200] = {
3414 .base_baud = 115200,
3417 [pbn_b2_4_115200] = {
3420 .base_baud = 115200,
3423 [pbn_b2_8_115200] = {
3426 .base_baud = 115200,
3430 [pbn_b2_1_460800] = {
3433 .base_baud = 460800,
3436 [pbn_b2_4_460800] = {
3439 .base_baud = 460800,
3442 [pbn_b2_8_460800] = {
3445 .base_baud = 460800,
3448 [pbn_b2_16_460800] = {
3451 .base_baud = 460800,
3455 [pbn_b2_1_921600] = {
3458 .base_baud = 921600,
3461 [pbn_b2_4_921600] = {
3464 .base_baud = 921600,
3467 [pbn_b2_8_921600] = {
3470 .base_baud = 921600,
3474 [pbn_b2_8_1152000] = {
3477 .base_baud = 1152000,
3481 [pbn_b2_bt_1_115200] = {
3482 .flags = FL_BASE2|FL_BASE_BARS,
3484 .base_baud = 115200,
3487 [pbn_b2_bt_2_115200] = {
3488 .flags = FL_BASE2|FL_BASE_BARS,
3490 .base_baud = 115200,
3493 [pbn_b2_bt_4_115200] = {
3494 .flags = FL_BASE2|FL_BASE_BARS,
3496 .base_baud = 115200,
3500 [pbn_b2_bt_2_921600] = {
3501 .flags = FL_BASE2|FL_BASE_BARS,
3503 .base_baud = 921600,
3506 [pbn_b2_bt_4_921600] = {
3507 .flags = FL_BASE2|FL_BASE_BARS,
3509 .base_baud = 921600,
3513 [pbn_b3_2_115200] = {
3516 .base_baud = 115200,
3519 [pbn_b3_4_115200] = {
3522 .base_baud = 115200,
3525 [pbn_b3_8_115200] = {
3528 .base_baud = 115200,
3532 [pbn_b4_bt_2_921600] = {
3535 .base_baud = 921600,
3538 [pbn_b4_bt_4_921600] = {
3541 .base_baud = 921600,
3544 [pbn_b4_bt_8_921600] = {
3547 .base_baud = 921600,
3552 * Entries following this are board-specific.
3561 .base_baud = 921600,
3562 .uart_offset = 0x400,
3566 .flags = FL_BASE2|FL_BASE_BARS,
3568 .base_baud = 921600,
3569 .uart_offset = 0x400,
3573 .flags = FL_BASE2|FL_BASE_BARS,
3575 .base_baud = 921600,
3576 .uart_offset = 0x400,
3580 /* I think this entry is broken - the first_offset looks wrong --rmk */
3581 [pbn_plx_romulus] = {
3584 .base_baud = 921600,
3585 .uart_offset = 8 << 2,
3587 .first_offset = 0x03,
3591 * This board uses the size of PCI Base region 0 to
3592 * signal now many ports are available
3595 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3597 .base_baud = 115200,
3600 [pbn_oxsemi_1_15625000] = {
3603 .base_baud = 15625000,
3604 .uart_offset = 0x200,
3605 .first_offset = 0x1000,
3607 [pbn_oxsemi_2_15625000] = {
3610 .base_baud = 15625000,
3611 .uart_offset = 0x200,
3612 .first_offset = 0x1000,
3614 [pbn_oxsemi_4_15625000] = {
3617 .base_baud = 15625000,
3618 .uart_offset = 0x200,
3619 .first_offset = 0x1000,
3621 [pbn_oxsemi_8_15625000] = {
3624 .base_baud = 15625000,
3625 .uart_offset = 0x200,
3626 .first_offset = 0x1000,
3631 * EKF addition for i960 Boards form EKF with serial port.
3634 [pbn_intel_i960] = {
3637 .base_baud = 921600,
3638 .uart_offset = 8 << 2,
3640 .first_offset = 0x10000,
3643 .flags = FL_BASE0|FL_NOIRQ,
3645 .base_baud = 458333,
3648 .first_offset = 0x20178,
3652 * Computone - uses IOMEM.
3654 [pbn_computone_4] = {
3657 .base_baud = 921600,
3658 .uart_offset = 0x40,
3660 .first_offset = 0x200,
3662 [pbn_computone_6] = {
3665 .base_baud = 921600,
3666 .uart_offset = 0x40,
3668 .first_offset = 0x200,
3670 [pbn_computone_8] = {
3673 .base_baud = 921600,
3674 .uart_offset = 0x40,
3676 .first_offset = 0x200,
3681 .base_baud = 460800,
3686 * PA Semi PWRficient PA6T-1682M on-chip UART
3688 [pbn_pasemi_1682M] = {
3691 .base_baud = 8333333,
3694 * National Instruments 843x
3699 .base_baud = 3686400,
3700 .uart_offset = 0x10,
3701 .first_offset = 0x800,
3706 .base_baud = 3686400,
3707 .uart_offset = 0x10,
3708 .first_offset = 0x800,
3713 .base_baud = 3686400,
3714 .uart_offset = 0x10,
3715 .first_offset = 0x800,
3720 .base_baud = 3686400,
3721 .uart_offset = 0x10,
3722 .first_offset = 0x800,
3725 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3727 [pbn_ADDIDATA_PCIe_1_3906250] = {
3730 .base_baud = 3906250,
3731 .uart_offset = 0x200,
3732 .first_offset = 0x1000,
3734 [pbn_ADDIDATA_PCIe_2_3906250] = {
3737 .base_baud = 3906250,
3738 .uart_offset = 0x200,
3739 .first_offset = 0x1000,
3741 [pbn_ADDIDATA_PCIe_4_3906250] = {
3744 .base_baud = 3906250,
3745 .uart_offset = 0x200,
3746 .first_offset = 0x1000,
3748 [pbn_ADDIDATA_PCIe_8_3906250] = {
3751 .base_baud = 3906250,
3752 .uart_offset = 0x200,
3753 .first_offset = 0x1000,
3755 [pbn_ce4100_1_115200] = {
3756 .flags = FL_BASE_BARS,
3758 .base_baud = 921600,
3764 .base_baud = 115200,
3765 .uart_offset = 0x200,
3767 [pbn_NETMOS9900_2s_115200] = {
3770 .base_baud = 115200,
3772 [pbn_brcm_trumanage] = {
3776 .base_baud = 115200,
3781 .base_baud = 115200,
3782 .first_offset = 0x40,
3787 .base_baud = 115200,
3788 .first_offset = 0x40,
3793 .base_baud = 115200,
3794 .first_offset = 0x40,
3796 [pbn_fintek_F81504A] = {
3799 .base_baud = 115200,
3801 [pbn_fintek_F81508A] = {
3804 .base_baud = 115200,
3806 [pbn_fintek_F81512A] = {
3809 .base_baud = 115200,
3814 .base_baud = 115200,
3816 .first_offset = 0xC0,
3821 .base_baud = 115200,
3823 .first_offset = 0xC0,
3828 .base_baud = 115200,
3830 .first_offset = 0x00,
3832 [pbn_sunix_pci_1s] = {
3834 .base_baud = 921600,
3837 [pbn_sunix_pci_2s] = {
3839 .base_baud = 921600,
3842 [pbn_sunix_pci_4s] = {
3844 .base_baud = 921600,
3847 [pbn_sunix_pci_8s] = {
3849 .base_baud = 921600,
3852 [pbn_sunix_pci_16s] = {
3854 .base_baud = 921600,
3857 [pbn_titan_1_4000000] = {
3860 .base_baud = 4000000,
3861 .uart_offset = 0x200,
3862 .first_offset = 0x1000,
3864 [pbn_titan_2_4000000] = {
3867 .base_baud = 4000000,
3868 .uart_offset = 0x200,
3869 .first_offset = 0x1000,
3871 [pbn_titan_4_4000000] = {
3874 .base_baud = 4000000,
3875 .uart_offset = 0x200,
3876 .first_offset = 0x1000,
3878 [pbn_titan_8_4000000] = {
3881 .base_baud = 4000000,
3882 .uart_offset = 0x200,
3883 .first_offset = 0x1000,
3888 .base_baud = 921600,
3889 .uart_offset = 0x200,
3894 .base_baud = 921600,
3895 .uart_offset = 0x200,
3900 .base_baud = 921600,
3901 .uart_offset = 0x200,
3905 #define REPORT_CONFIG(option) \
3906 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3907 #define REPORT_8250_CONFIG(option) \
3908 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3909 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3911 static const struct pci_device_id blacklist[] = {
3913 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3914 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3915 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3917 /* multi-io cards handled by parport_serial */
3918 /* WCH CH353 2S1P */
3919 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3920 /* WCH CH353 1S1P */
3921 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3922 /* WCH CH382 2S1P */
3923 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3925 /* Intel platforms with MID UART */
3926 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
3927 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
3928 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
3929 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
3930 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
3931 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
3933 /* Intel platforms with DesignWare UART */
3934 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
3935 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
3936 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
3937 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
3938 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
3939 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
3940 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
3941 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
3942 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
3943 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
3944 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
3945 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
3946 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
3949 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3950 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3952 /* Pericom devices */
3953 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3954 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3956 /* End of the black list */
3960 static int serial_pci_is_class_communication(struct pci_dev *dev)
3963 * If it is not a communications device or the programming
3964 * interface is greater than 6, give up.
3966 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3967 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3968 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3969 (dev->class & 0xff) > 6)
3976 * Given a complete unknown PCI device, try to use some heuristics to
3977 * guess what the configuration might be, based on the pitiful PCI
3978 * serial specs. Returns 0 on success, -ENODEV on failure.
3981 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3983 int num_iomem, num_port, first_port = -1, i;
3986 rc = serial_pci_is_class_communication(dev);
3991 * Should we try to make guesses for multiport serial devices later?
3993 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3996 num_iomem = num_port = 0;
3997 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3998 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4000 if (first_port == -1)
4003 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4008 * If there is 1 or 0 iomem regions, and exactly one port,
4009 * use it. We guess the number of ports based on the IO
4012 if (num_iomem <= 1 && num_port == 1) {
4013 board->flags = first_port;
4014 board->num_ports = pci_resource_len(dev, first_port) / 8;
4019 * Now guess if we've got a board which indexes by BARs.
4020 * Each IO BAR should be 8 bytes, and they should follow
4025 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4026 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4027 pci_resource_len(dev, i) == 8 &&
4028 (first_port == -1 || (first_port + num_port) == i)) {
4030 if (first_port == -1)
4036 board->flags = first_port | FL_BASE_BARS;
4037 board->num_ports = num_port;
4045 serial_pci_matches(const struct pciserial_board *board,
4046 const struct pciserial_board *guessed)
4049 board->num_ports == guessed->num_ports &&
4050 board->base_baud == guessed->base_baud &&
4051 board->uart_offset == guessed->uart_offset &&
4052 board->reg_shift == guessed->reg_shift &&
4053 board->first_offset == guessed->first_offset;
4056 struct serial_private *
4057 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4059 struct uart_8250_port uart;
4060 struct serial_private *priv;
4061 struct pci_serial_quirk *quirk;
4062 int rc, nr_ports, i;
4064 nr_ports = board->num_ports;
4067 * Find an init and setup quirks.
4069 quirk = find_quirk(dev);
4072 * Run the new-style initialization function.
4073 * The initialization function returns:
4075 * 0 - use board->num_ports
4076 * >0 - number of ports
4079 rc = quirk->init(dev);
4088 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL);
4090 priv = ERR_PTR(-ENOMEM);
4095 priv->quirk = quirk;
4097 memset(&uart, 0, sizeof(uart));
4098 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4099 uart.port.uartclk = board->base_baud * 16;
4101 if (board->flags & FL_NOIRQ) {
4104 if (pci_match_id(pci_use_msi, dev)) {
4105 pci_dbg(dev, "Using MSI(-X) interrupts\n");
4106 pci_set_master(dev);
4107 uart.port.flags &= ~UPF_SHARE_IRQ;
4108 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4110 pci_dbg(dev, "Using legacy interrupts\n");
4111 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
4119 uart.port.irq = pci_irq_vector(dev, 0);
4122 uart.port.dev = &dev->dev;
4124 for (i = 0; i < nr_ports; i++) {
4125 if (quirk->setup(priv, board, &uart, i))
4128 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4129 uart.port.iobase, uart.port.irq, uart.port.iotype);
4131 priv->line[i] = serial8250_register_8250_port(&uart);
4132 if (priv->line[i] < 0) {
4134 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4135 uart.port.iobase, uart.port.irq,
4136 uart.port.iotype, priv->line[i]);
4141 priv->board = board;
4150 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4152 static void pciserial_detach_ports(struct serial_private *priv)
4154 struct pci_serial_quirk *quirk;
4157 for (i = 0; i < priv->nr; i++)
4158 serial8250_unregister_port(priv->line[i]);
4161 * Find the exit quirks.
4163 quirk = find_quirk(priv->dev);
4165 quirk->exit(priv->dev);
4168 void pciserial_remove_ports(struct serial_private *priv)
4170 pciserial_detach_ports(priv);
4173 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4175 void pciserial_suspend_ports(struct serial_private *priv)
4179 for (i = 0; i < priv->nr; i++)
4180 if (priv->line[i] >= 0)
4181 serial8250_suspend_port(priv->line[i]);
4184 * Ensure that every init quirk is properly torn down
4186 if (priv->quirk->exit)
4187 priv->quirk->exit(priv->dev);
4189 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4191 void pciserial_resume_ports(struct serial_private *priv)
4196 * Ensure that the board is correctly configured.
4198 if (priv->quirk->init)
4199 priv->quirk->init(priv->dev);
4201 for (i = 0; i < priv->nr; i++)
4202 if (priv->line[i] >= 0)
4203 serial8250_resume_port(priv->line[i]);
4205 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4208 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4209 * to the arrangement of serial ports on a PCI card.
4212 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4214 struct pci_serial_quirk *quirk;
4215 struct serial_private *priv;
4216 const struct pciserial_board *board;
4217 const struct pci_device_id *exclude;
4218 struct pciserial_board tmp;
4221 quirk = find_quirk(dev);
4223 rc = quirk->probe(dev);
4228 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4229 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4233 board = &pci_boards[ent->driver_data];
4235 exclude = pci_match_id(blacklist, dev);
4237 if (exclude->driver_data)
4238 pci_warn(dev, "ignoring port, enable %s to handle\n",
4239 (const char *)exclude->driver_data);
4243 rc = pcim_enable_device(dev);
4244 pci_save_state(dev);
4248 if (ent->driver_data == pbn_default) {
4250 * Use a copy of the pci_board entry for this;
4251 * avoid changing entries in the table.
4253 memcpy(&tmp, board, sizeof(struct pciserial_board));
4257 * We matched one of our class entries. Try to
4258 * determine the parameters of this board.
4260 rc = serial_pci_guess_board(dev, &tmp);
4265 * We matched an explicit entry. If we are able to
4266 * detect this boards settings with our heuristic,
4267 * then we no longer need this entry.
4269 memcpy(&tmp, &pci_boards[pbn_default],
4270 sizeof(struct pciserial_board));
4271 rc = serial_pci_guess_board(dev, &tmp);
4272 if (rc == 0 && serial_pci_matches(board, &tmp))
4273 moan_device("Redundant entry in serial pci_table.",
4277 priv = pciserial_init_ports(dev, board);
4279 return PTR_ERR(priv);
4281 pci_set_drvdata(dev, priv);
4285 static void pciserial_remove_one(struct pci_dev *dev)
4287 struct serial_private *priv = pci_get_drvdata(dev);
4289 pciserial_remove_ports(priv);
4292 #ifdef CONFIG_PM_SLEEP
4293 static int pciserial_suspend_one(struct device *dev)
4295 struct serial_private *priv = dev_get_drvdata(dev);
4298 pciserial_suspend_ports(priv);
4303 static int pciserial_resume_one(struct device *dev)
4305 struct pci_dev *pdev = to_pci_dev(dev);
4306 struct serial_private *priv = pci_get_drvdata(pdev);
4311 * The device may have been disabled. Re-enable it.
4313 err = pci_enable_device(pdev);
4314 /* FIXME: We cannot simply error out here */
4316 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4317 pciserial_resume_ports(priv);
4323 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4324 pciserial_resume_one);
4326 static const struct pci_device_id serial_pci_tbl[] = {
4327 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4328 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4330 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4331 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4332 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4334 /* Advantech also use 0x3618 and 0xf618 */
4335 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4336 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4338 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4339 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4341 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4342 PCI_SUBVENDOR_ID_CONNECT_TECH,
4343 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4345 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4346 PCI_SUBVENDOR_ID_CONNECT_TECH,
4347 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4349 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4350 PCI_SUBVENDOR_ID_CONNECT_TECH,
4351 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4353 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4354 PCI_SUBVENDOR_ID_CONNECT_TECH,
4355 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4357 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4358 PCI_SUBVENDOR_ID_CONNECT_TECH,
4359 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4361 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4362 PCI_SUBVENDOR_ID_CONNECT_TECH,
4363 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4365 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4366 PCI_SUBVENDOR_ID_CONNECT_TECH,
4367 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4369 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4370 PCI_SUBVENDOR_ID_CONNECT_TECH,
4371 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4373 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4374 PCI_SUBVENDOR_ID_CONNECT_TECH,
4375 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4377 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4378 PCI_SUBVENDOR_ID_CONNECT_TECH,
4379 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4381 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4382 PCI_SUBVENDOR_ID_CONNECT_TECH,
4383 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4385 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4386 PCI_SUBVENDOR_ID_CONNECT_TECH,
4387 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4389 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4390 PCI_SUBVENDOR_ID_CONNECT_TECH,
4391 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4393 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4394 PCI_SUBVENDOR_ID_CONNECT_TECH,
4395 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4397 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4398 PCI_SUBVENDOR_ID_CONNECT_TECH,
4399 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4401 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4402 PCI_SUBVENDOR_ID_CONNECT_TECH,
4403 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4405 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4406 PCI_SUBVENDOR_ID_CONNECT_TECH,
4407 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4409 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4410 PCI_VENDOR_ID_AFAVLAB,
4411 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4413 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_b2_bt_1_115200 },
4416 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_b2_bt_2_115200 },
4419 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 pbn_b2_bt_4_115200 },
4422 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 pbn_b2_bt_2_115200 },
4425 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_b2_bt_4_115200 },
4428 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 pbn_b2_bt_2_115200 },
4441 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 pbn_b2_bt_2_921600 },
4445 * VScom SPCOM800, from sl@s.pl
4447 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453 /* Unknown card - subdevice 0x1584 */
4454 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4456 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4458 /* Unknown card - subdevice 0x1588 */
4459 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4461 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4463 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4464 PCI_SUBVENDOR_ID_KEYSPAN,
4465 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4467 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4470 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4473 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4474 PCI_VENDOR_ID_ESDGMBH,
4475 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4477 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4478 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4479 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4481 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4482 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4483 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4485 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4486 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4487 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4489 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4490 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4491 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4493 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4494 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4495 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4497 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4498 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4499 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4501 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4502 PCI_SUBVENDOR_ID_EXSYS,
4503 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4506 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4509 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4510 0x10b5, 0x106a, 0, 0,
4513 * Quatech cards. These actually have configurable clocks but for
4514 * now we just use the default.
4516 * 100 series are RS232, 200 series RS422,
4518 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4576 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4577 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4580 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4581 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4584 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_b0_bt_2_921600 },
4589 * The below card is a little controversial since it is the
4590 * subject of a PCI vendor/device ID clash. (See
4591 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4592 * For now just used the hex ID 0x950a.
4594 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4595 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4596 0, 0, pbn_b0_2_115200 },
4597 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4598 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4599 0, 0, pbn_b0_2_115200 },
4600 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4604 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4606 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_b0_bt_2_921600 },
4612 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 * Oxford Semiconductor Inc. Tornado PCI express device range.
4619 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_b0_1_15625000 },
4622 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_b0_1_15625000 },
4625 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_oxsemi_1_15625000 },
4628 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_oxsemi_1_15625000 },
4631 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_b0_1_15625000 },
4634 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_b0_1_15625000 },
4637 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_oxsemi_1_15625000 },
4640 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_oxsemi_1_15625000 },
4643 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 pbn_b0_1_15625000 },
4646 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_b0_1_15625000 },
4649 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 pbn_b0_1_15625000 },
4652 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 pbn_b0_1_15625000 },
4655 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_oxsemi_2_15625000 },
4658 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 pbn_oxsemi_2_15625000 },
4661 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663 pbn_oxsemi_4_15625000 },
4664 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_oxsemi_4_15625000 },
4667 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_oxsemi_8_15625000 },
4670 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_oxsemi_8_15625000 },
4673 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_oxsemi_1_15625000 },
4676 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_oxsemi_1_15625000 },
4679 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_oxsemi_1_15625000 },
4682 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_oxsemi_1_15625000 },
4685 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_oxsemi_1_15625000 },
4688 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_oxsemi_1_15625000 },
4691 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_oxsemi_1_15625000 },
4694 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_oxsemi_1_15625000 },
4697 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 pbn_oxsemi_1_15625000 },
4700 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 pbn_oxsemi_1_15625000 },
4703 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 pbn_oxsemi_1_15625000 },
4706 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 pbn_oxsemi_1_15625000 },
4709 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_oxsemi_1_15625000 },
4712 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_oxsemi_1_15625000 },
4715 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_oxsemi_1_15625000 },
4718 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_oxsemi_1_15625000 },
4721 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 pbn_oxsemi_1_15625000 },
4724 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_oxsemi_1_15625000 },
4727 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 pbn_oxsemi_1_15625000 },
4730 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 pbn_oxsemi_1_15625000 },
4733 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 pbn_oxsemi_1_15625000 },
4736 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 pbn_oxsemi_1_15625000 },
4739 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 pbn_oxsemi_1_15625000 },
4742 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744 pbn_oxsemi_1_15625000 },
4745 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747 pbn_oxsemi_1_15625000 },
4748 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 pbn_oxsemi_1_15625000 },
4752 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4754 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4755 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4756 pbn_oxsemi_1_15625000 },
4757 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4758 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4759 pbn_oxsemi_2_15625000 },
4760 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4761 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4762 pbn_oxsemi_4_15625000 },
4763 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4764 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4765 pbn_oxsemi_8_15625000 },
4768 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4770 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4771 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4772 pbn_oxsemi_2_15625000 },
4774 * EndRun Technologies. PCI express device range.
4775 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4777 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_oxsemi_2_15625000 },
4782 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4783 * from skokodyn@yahoo.com
4785 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4786 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4788 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4789 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4791 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4792 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4794 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4795 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4799 * Digitan DS560-558, from jimd@esoft.com
4801 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806 * Titan Electronic cards
4807 * The 400L and 800L have a custom setup quirk.
4809 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4812 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4815 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4818 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4821 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4824 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826 pbn_b1_bt_2_921600 },
4827 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829 pbn_b0_bt_4_921600 },
4830 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832 pbn_b0_bt_8_921600 },
4833 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835 pbn_b4_bt_2_921600 },
4836 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838 pbn_b4_bt_4_921600 },
4839 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841 pbn_b4_bt_8_921600 },
4842 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4845 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4848 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853 pbn_titan_1_4000000 },
4854 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4856 pbn_titan_2_4000000 },
4857 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859 pbn_titan_4_4000000 },
4860 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862 pbn_titan_8_4000000 },
4863 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4865 pbn_titan_2_4000000 },
4866 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868 pbn_titan_2_4000000 },
4869 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4871 pbn_b0_bt_2_921600 },
4872 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4881 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 pbn_b2_bt_2_921600 },
4897 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 pbn_b2_bt_2_921600 },
4900 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 pbn_b2_bt_2_921600 },
4903 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_b2_bt_4_921600 },
4906 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_b2_bt_4_921600 },
4909 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 pbn_b2_bt_4_921600 },
4912 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 pbn_b0_bt_2_921600 },
4924 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 pbn_b0_bt_2_921600 },
4927 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929 pbn_b0_bt_2_921600 },
4930 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 pbn_b0_bt_4_921600 },
4933 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935 pbn_b0_bt_4_921600 },
4936 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_b0_bt_4_921600 },
4939 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 pbn_b0_bt_8_921600 },
4942 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_b0_bt_8_921600 },
4945 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 pbn_b0_bt_8_921600 },
4950 * Computone devices submitted by Doug McNash dmcnash@computone.com
4952 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4953 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4954 0, 0, pbn_computone_4 },
4955 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4956 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4957 0, 0, pbn_computone_8 },
4958 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4959 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4960 0, 0, pbn_computone_6 },
4962 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4966 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4967 pbn_b0_bt_1_921600 },
4970 * Sunix PCI serial boards
4972 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4973 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4975 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4976 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4978 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4979 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4981 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4982 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4984 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4985 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4987 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4988 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4990 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4991 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4992 pbn_sunix_pci_16s },
4995 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4997 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 pbn_b0_bt_8_115200 },
5000 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002 pbn_b0_bt_8_115200 },
5004 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5006 pbn_b0_bt_2_115200 },
5007 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5009 pbn_b0_bt_2_115200 },
5010 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5012 pbn_b0_bt_2_115200 },
5013 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5015 pbn_b0_bt_2_115200 },
5016 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5018 pbn_b0_bt_2_115200 },
5019 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5021 pbn_b0_bt_4_460800 },
5022 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5024 pbn_b0_bt_4_460800 },
5025 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5027 pbn_b0_bt_2_460800 },
5028 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5030 pbn_b0_bt_2_460800 },
5031 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5033 pbn_b0_bt_2_460800 },
5034 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5035 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5036 pbn_b0_bt_1_115200 },
5037 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5038 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5039 pbn_b0_bt_1_460800 },
5042 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5043 * Cards are identified by their subsystem vendor IDs, which
5044 * (in hex) match the model number.
5046 * Note that JC140x are RS422/485 cards which require ox950
5047 * ACR = 0x10, and as such are not currently fully supported.
5049 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5050 0x1204, 0x0004, 0, 0,
5052 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5053 0x1208, 0x0004, 0, 0,
5055 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5056 0x1402, 0x0002, 0, 0,
5057 pbn_b0_2_921600 }, */
5058 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5059 0x1404, 0x0004, 0, 0,
5060 pbn_b0_4_921600 }, */
5061 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5062 0x1208, 0x0004, 0, 0,
5065 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5066 0x1204, 0x0004, 0, 0,
5068 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5069 0x1208, 0x0004, 0, 0,
5071 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5072 0x1208, 0x0004, 0, 0,
5075 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5077 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5082 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5084 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5089 * RAStel 2 port modem, gerg@moreton.com.au
5091 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5093 pbn_b2_bt_2_115200 },
5096 * EKF addition for i960 Boards form EKF with serial port
5098 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5099 0xE4BF, PCI_ANY_ID, 0, 0,
5103 * Xircom Cardbus/Ethernet combos
5105 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5109 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5111 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5116 * Untested PCI modems, sent in from various folks...
5120 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5122 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5123 0x1048, 0x1500, 0, 0,
5126 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5133 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5134 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5136 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5139 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5142 /* HPE PCI serial device */
5143 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5147 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5150 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5153 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5157 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5159 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5165 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5166 PCI_ANY_ID, PCI_ANY_ID,
5168 pbn_b1_bt_1_115200 },
5173 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5179 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5185 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5191 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5192 PCI_ANY_ID, PCI_ANY_ID,
5194 pbn_oxsemi_1_15625000 },
5198 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5199 PCI_ANY_ID, PCI_ANY_ID,
5201 pbn_oxsemi_2_15625000 },
5205 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5206 PCI_ANY_ID, PCI_ANY_ID,
5208 pbn_oxsemi_4_15625000 },
5209 /* Brainboxes Devices */
5213 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5214 PCI_ANY_ID, PCI_ANY_ID,
5218 * Brainboxes UC-235/246
5220 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5221 PCI_ANY_ID, PCI_ANY_ID,
5224 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5225 PCI_ANY_ID, PCI_ANY_ID,
5229 * Brainboxes UC-253/UC-734
5231 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5232 PCI_ANY_ID, PCI_ANY_ID,
5236 * Brainboxes UC-260/271/701/756
5238 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5239 PCI_ANY_ID, PCI_ANY_ID,
5240 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5242 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5243 PCI_ANY_ID, PCI_ANY_ID,
5244 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5249 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5250 PCI_ANY_ID, PCI_ANY_ID,
5254 * Brainboxes UC-275/279
5256 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5257 PCI_ANY_ID, PCI_ANY_ID,
5263 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5264 PCI_ANY_ID, PCI_ANY_ID,
5267 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5268 PCI_ANY_ID, PCI_ANY_ID,
5271 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5272 PCI_ANY_ID, PCI_ANY_ID,
5278 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5279 PCI_ANY_ID, PCI_ANY_ID,
5285 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5286 PCI_ANY_ID, PCI_ANY_ID,
5289 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5290 PCI_ANY_ID, PCI_ANY_ID,
5293 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5294 PCI_ANY_ID, PCI_ANY_ID,
5298 * Brainboxes UC-320/324
5300 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5301 PCI_ANY_ID, PCI_ANY_ID,
5307 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5308 PCI_ANY_ID, PCI_ANY_ID,
5311 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5312 PCI_ANY_ID, PCI_ANY_ID,
5318 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5319 PCI_ANY_ID, PCI_ANY_ID,
5322 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5323 PCI_ANY_ID, PCI_ANY_ID,
5326 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5327 PCI_ANY_ID, PCI_ANY_ID,
5333 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5334 PCI_ANY_ID, PCI_ANY_ID,
5340 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5341 PCI_ANY_ID, PCI_ANY_ID,
5347 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5348 PCI_ANY_ID, PCI_ANY_ID,
5351 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5352 PCI_ANY_ID, PCI_ANY_ID,
5355 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5356 PCI_ANY_ID, PCI_ANY_ID,
5362 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5363 PCI_ANY_ID, PCI_ANY_ID,
5369 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5370 PCI_ANY_ID, PCI_ANY_ID,
5373 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5374 PCI_ANY_ID, PCI_ANY_ID,
5377 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5378 PCI_ANY_ID, PCI_ANY_ID,
5384 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5385 PCI_ANY_ID, PCI_ANY_ID,
5388 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5389 PCI_ANY_ID, PCI_ANY_ID,
5392 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5393 PCI_ANY_ID, PCI_ANY_ID,
5399 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5400 PCI_ANY_ID, PCI_ANY_ID,
5403 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5404 PCI_ANY_ID, PCI_ANY_ID,
5407 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5408 PCI_ANY_ID, PCI_ANY_ID,
5414 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5415 PCI_ANY_ID, PCI_ANY_ID,
5418 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5419 PCI_ANY_ID, PCI_ANY_ID,
5422 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5423 PCI_ANY_ID, PCI_ANY_ID,
5429 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5430 PCI_ANY_ID, PCI_ANY_ID,
5433 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5434 PCI_ANY_ID, PCI_ANY_ID,
5436 pbn_oxsemi_2_15625000 },
5438 * Brainboxes PX-235/246
5440 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5441 PCI_ANY_ID, PCI_ANY_ID,
5444 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5445 PCI_ANY_ID, PCI_ANY_ID,
5447 pbn_oxsemi_1_15625000 },
5449 * Brainboxes PX-203/PX-257
5451 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5452 PCI_ANY_ID, PCI_ANY_ID,
5455 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5456 PCI_ANY_ID, PCI_ANY_ID,
5458 pbn_oxsemi_2_15625000 },
5460 * Brainboxes PX-260/PX-701
5462 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5463 PCI_ANY_ID, PCI_ANY_ID,
5465 pbn_oxsemi_4_15625000 },
5467 * Brainboxes PX-275/279
5469 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5470 PCI_ANY_ID, PCI_ANY_ID,
5476 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5477 PCI_ANY_ID, PCI_ANY_ID,
5479 pbn_oxsemi_2_15625000 },
5483 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5484 PCI_ANY_ID, PCI_ANY_ID,
5486 pbn_oxsemi_2_15625000 },
5488 * Brainboxes PX-320/324/PX-376/PX-387
5490 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5491 PCI_ANY_ID, PCI_ANY_ID,
5493 pbn_oxsemi_1_15625000 },
5495 * Brainboxes PX-335/346
5497 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5498 PCI_ANY_ID, PCI_ANY_ID,
5500 pbn_oxsemi_4_15625000 },
5504 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5505 PCI_ANY_ID, PCI_ANY_ID,
5507 pbn_oxsemi_4_15625000 },
5511 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5512 PCI_ANY_ID, PCI_ANY_ID,
5515 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5516 PCI_ANY_ID, PCI_ANY_ID,
5518 pbn_oxsemi_4_15625000 },
5522 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5523 PCI_ANY_ID, PCI_ANY_ID,
5525 pbn_oxsemi_1_15625000 },
5527 * Brainboxes PX-803/PX-857
5529 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5530 PCI_ANY_ID, PCI_ANY_ID,
5533 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5534 PCI_ANY_ID, PCI_ANY_ID,
5536 pbn_oxsemi_2_15625000 },
5537 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5538 PCI_ANY_ID, PCI_ANY_ID,
5540 pbn_oxsemi_2_15625000 },
5544 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5545 PCI_ANY_ID, PCI_ANY_ID,
5548 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5549 PCI_ANY_ID, PCI_ANY_ID,
5551 pbn_oxsemi_4_15625000 },
5553 * Brainboxes PX-835/PX-846
5555 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5556 PCI_ANY_ID, PCI_ANY_ID,
5559 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5560 PCI_ANY_ID, PCI_ANY_ID,
5562 pbn_oxsemi_1_15625000 },
5565 * Perle PCI-RAS cards
5567 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5568 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5569 0, 0, pbn_b2_4_921600 },
5570 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5571 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5572 0, 0, pbn_b2_8_921600 },
5575 * Mainpine series cards: Fairly standard layout but fools
5576 * parts of the autodetect in some cases and uses otherwise
5577 * unmatched communications subclasses in the PCI Express case
5580 { /* RockForceDUO */
5581 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5582 PCI_VENDOR_ID_MAINPINE, 0x0200,
5583 0, 0, pbn_b0_2_115200 },
5584 { /* RockForceQUATRO */
5585 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5586 PCI_VENDOR_ID_MAINPINE, 0x0300,
5587 0, 0, pbn_b0_4_115200 },
5588 { /* RockForceDUO+ */
5589 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5590 PCI_VENDOR_ID_MAINPINE, 0x0400,
5591 0, 0, pbn_b0_2_115200 },
5592 { /* RockForceQUATRO+ */
5593 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5594 PCI_VENDOR_ID_MAINPINE, 0x0500,
5595 0, 0, pbn_b0_4_115200 },
5597 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5598 PCI_VENDOR_ID_MAINPINE, 0x0600,
5599 0, 0, pbn_b0_2_115200 },
5601 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5602 PCI_VENDOR_ID_MAINPINE, 0x0700,
5603 0, 0, pbn_b0_4_115200 },
5604 { /* RockForceOCTO+ */
5605 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5606 PCI_VENDOR_ID_MAINPINE, 0x0800,
5607 0, 0, pbn_b0_8_115200 },
5608 { /* RockForceDUO+ */
5609 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5610 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5611 0, 0, pbn_b0_2_115200 },
5612 { /* RockForceQUARTRO+ */
5613 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5614 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5615 0, 0, pbn_b0_4_115200 },
5616 { /* RockForceOCTO+ */
5617 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5618 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5619 0, 0, pbn_b0_8_115200 },
5621 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5622 PCI_VENDOR_ID_MAINPINE, 0x2000,
5623 0, 0, pbn_b0_1_115200 },
5625 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5626 PCI_VENDOR_ID_MAINPINE, 0x2100,
5627 0, 0, pbn_b0_1_115200 },
5629 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5630 PCI_VENDOR_ID_MAINPINE, 0x2200,
5631 0, 0, pbn_b0_2_115200 },
5633 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5634 PCI_VENDOR_ID_MAINPINE, 0x2300,
5635 0, 0, pbn_b0_2_115200 },
5637 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5638 PCI_VENDOR_ID_MAINPINE, 0x2400,
5639 0, 0, pbn_b0_4_115200 },
5641 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5642 PCI_VENDOR_ID_MAINPINE, 0x2500,
5643 0, 0, pbn_b0_4_115200 },
5645 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5646 PCI_VENDOR_ID_MAINPINE, 0x2600,
5647 0, 0, pbn_b0_8_115200 },
5649 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5650 PCI_VENDOR_ID_MAINPINE, 0x2700,
5651 0, 0, pbn_b0_8_115200 },
5652 { /* IQ Express D1 */
5653 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5654 PCI_VENDOR_ID_MAINPINE, 0x3000,
5655 0, 0, pbn_b0_1_115200 },
5656 { /* IQ Express F1 */
5657 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5658 PCI_VENDOR_ID_MAINPINE, 0x3100,
5659 0, 0, pbn_b0_1_115200 },
5660 { /* IQ Express D2 */
5661 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5662 PCI_VENDOR_ID_MAINPINE, 0x3200,
5663 0, 0, pbn_b0_2_115200 },
5664 { /* IQ Express F2 */
5665 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5666 PCI_VENDOR_ID_MAINPINE, 0x3300,
5667 0, 0, pbn_b0_2_115200 },
5668 { /* IQ Express D4 */
5669 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5670 PCI_VENDOR_ID_MAINPINE, 0x3400,
5671 0, 0, pbn_b0_4_115200 },
5672 { /* IQ Express F4 */
5673 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5674 PCI_VENDOR_ID_MAINPINE, 0x3500,
5675 0, 0, pbn_b0_4_115200 },
5676 { /* IQ Express D8 */
5677 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5678 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5679 0, 0, pbn_b0_8_115200 },
5680 { /* IQ Express F8 */
5681 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5682 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5683 0, 0, pbn_b0_8_115200 },
5687 * PA Semi PA6T-1682M on-chip UART
5689 { PCI_VENDOR_ID_PASEMI, 0xa004,
5690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5694 * National Instruments
5696 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5699 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5702 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5704 pbn_b1_bt_4_115200 },
5705 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5707 pbn_b1_bt_2_115200 },
5708 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5710 pbn_b1_bt_4_115200 },
5711 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5713 pbn_b1_bt_2_115200 },
5714 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5717 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5720 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5722 pbn_b1_bt_4_115200 },
5723 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5725 pbn_b1_bt_2_115200 },
5726 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5728 pbn_b1_bt_4_115200 },
5729 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5731 pbn_b1_bt_2_115200 },
5732 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5735 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5738 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5741 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5744 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5747 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5750 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5753 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5756 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5759 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5762 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5765 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5772 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
5773 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
5774 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
5775 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
5776 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
5777 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
5778 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
5779 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
5780 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
5781 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
5782 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
5783 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
5784 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
5785 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
5786 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
5787 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
5788 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
5789 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
5792 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5794 { PCI_VENDOR_ID_ADDIDATA,
5795 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5802 { PCI_VENDOR_ID_ADDIDATA,
5803 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5810 { PCI_VENDOR_ID_ADDIDATA,
5811 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5818 { PCI_VENDOR_ID_AMCC,
5819 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5826 { PCI_VENDOR_ID_ADDIDATA,
5827 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5834 { PCI_VENDOR_ID_ADDIDATA,
5835 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5842 { PCI_VENDOR_ID_ADDIDATA,
5843 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5850 { PCI_VENDOR_ID_ADDIDATA,
5851 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5858 { PCI_VENDOR_ID_ADDIDATA,
5859 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5866 { PCI_VENDOR_ID_ADDIDATA,
5867 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5874 { PCI_VENDOR_ID_ADDIDATA,
5875 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5882 { PCI_VENDOR_ID_ADDIDATA,
5883 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5888 pbn_ADDIDATA_PCIe_4_3906250 },
5890 { PCI_VENDOR_ID_ADDIDATA,
5891 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5896 pbn_ADDIDATA_PCIe_2_3906250 },
5898 { PCI_VENDOR_ID_ADDIDATA,
5899 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5904 pbn_ADDIDATA_PCIe_1_3906250 },
5906 { PCI_VENDOR_ID_ADDIDATA,
5907 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5912 pbn_ADDIDATA_PCIe_8_3906250 },
5914 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5915 PCI_VENDOR_ID_IBM, 0x0299,
5916 0, 0, pbn_b0_bt_2_115200 },
5919 * other NetMos 9835 devices are most likely handled by the
5920 * parport_serial driver, check drivers/parport/parport_serial.c
5921 * before adding them here.
5924 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5926 0, 0, pbn_b0_1_115200 },
5928 /* the 9901 is a rebranded 9912 */
5929 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5931 0, 0, pbn_b0_1_115200 },
5933 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5935 0, 0, pbn_b0_1_115200 },
5937 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5939 0, 0, pbn_b0_1_115200 },
5941 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5943 0, 0, pbn_b0_1_115200 },
5945 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5947 0, 0, pbn_NETMOS9900_2s_115200 },
5950 * Best Connectivity and Rosewill PCI Multi I/O cards
5953 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5955 0, 0, pbn_b0_1_115200 },
5957 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5959 0, 0, pbn_b0_bt_2_115200 },
5961 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5963 0, 0, pbn_b0_bt_4_115200 },
5966 * ASIX AX99100 PCIe to Multi I/O Controller
5968 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
5970 0, 0, pbn_b0_1_115200 },
5973 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5975 pbn_ce4100_1_115200 },
5980 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5985 * Broadcom TruManage
5987 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5989 pbn_brcm_trumanage },
5992 * AgeStar as-prs2-009
5994 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5995 PCI_ANY_ID, PCI_ANY_ID,
5996 0, 0, pbn_b0_bt_2_115200 },
5999 * WCH CH353 series devices: The 2S1P is handled by parport_serial
6000 * so not listed here.
6002 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
6003 PCI_ANY_ID, PCI_ANY_ID,
6004 0, 0, pbn_b0_bt_4_115200 },
6006 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
6007 PCI_ANY_ID, PCI_ANY_ID,
6008 0, 0, pbn_b0_bt_2_115200 },
6010 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
6011 PCI_ANY_ID, PCI_ANY_ID,
6012 0, 0, pbn_b0_bt_4_115200 },
6014 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
6015 PCI_ANY_ID, PCI_ANY_ID,
6016 0, 0, pbn_wch382_2 },
6018 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
6019 PCI_ANY_ID, PCI_ANY_ID,
6020 0, 0, pbn_wch384_4 },
6022 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
6023 PCI_ANY_ID, PCI_ANY_ID,
6024 0, 0, pbn_wch384_8 },
6026 * Realtek RealManage
6028 { PCI_VENDOR_ID_REALTEK, 0x816a,
6029 PCI_ANY_ID, PCI_ANY_ID,
6030 0, 0, pbn_b0_1_115200 },
6032 { PCI_VENDOR_ID_REALTEK, 0x816b,
6033 PCI_ANY_ID, PCI_ANY_ID,
6034 0, 0, pbn_b0_1_115200 },
6036 /* Fintek PCI serial cards */
6037 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6038 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6039 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6040 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6041 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6042 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6044 /* MKS Tenta SCOM-080x serial cards */
6045 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6046 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6048 /* Amazon PCI serial device */
6049 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6052 * These entries match devices with class COMMUNICATION_SERIAL,
6053 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
6055 { PCI_ANY_ID, PCI_ANY_ID,
6056 PCI_ANY_ID, PCI_ANY_ID,
6057 PCI_CLASS_COMMUNICATION_SERIAL << 8,
6058 0xffff00, pbn_default },
6059 { PCI_ANY_ID, PCI_ANY_ID,
6060 PCI_ANY_ID, PCI_ANY_ID,
6061 PCI_CLASS_COMMUNICATION_MODEM << 8,
6062 0xffff00, pbn_default },
6063 { PCI_ANY_ID, PCI_ANY_ID,
6064 PCI_ANY_ID, PCI_ANY_ID,
6065 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
6066 0xffff00, pbn_default },
6070 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
6071 pci_channel_state_t state)
6073 struct serial_private *priv = pci_get_drvdata(dev);
6075 if (state == pci_channel_io_perm_failure)
6076 return PCI_ERS_RESULT_DISCONNECT;
6079 pciserial_detach_ports(priv);
6081 pci_disable_device(dev);
6083 return PCI_ERS_RESULT_NEED_RESET;
6086 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
6090 rc = pci_enable_device(dev);
6093 return PCI_ERS_RESULT_DISCONNECT;
6095 pci_restore_state(dev);
6096 pci_save_state(dev);
6098 return PCI_ERS_RESULT_RECOVERED;
6101 static void serial8250_io_resume(struct pci_dev *dev)
6103 struct serial_private *priv = pci_get_drvdata(dev);
6104 struct serial_private *new;
6109 new = pciserial_init_ports(dev, priv->board);
6111 pci_set_drvdata(dev, new);
6116 static const struct pci_error_handlers serial8250_err_handler = {
6117 .error_detected = serial8250_io_error_detected,
6118 .slot_reset = serial8250_io_slot_reset,
6119 .resume = serial8250_io_resume,
6122 static struct pci_driver serial_pci_driver = {
6124 .probe = pciserial_init_one,
6125 .remove = pciserial_remove_one,
6127 .pm = &pciserial_pm_ops,
6129 .id_table = serial_pci_tbl,
6130 .err_handler = &serial8250_err_handler,
6133 module_pci_driver(serial_pci_driver);
6135 MODULE_LICENSE("GPL");
6136 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6137 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
6138 MODULE_IMPORT_NS(SERIAL_8250_PCI);