drivers/tty/serial/8250/8250_omap.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * 8250-core based driver for the OMAP internal UART
   4  *
   5  * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Copyright (C) 2014 Sebastian Andrzej Siewior
   8  *
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/device.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/serial_8250.h>
  16 #include <linux/serial_reg.h>
  17 #include <linux/tty_flip.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_gpio.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/delay.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/console.h>
  27 #include <linux/pm_qos.h>
  28 #include <linux/pm_wakeirq.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/sys_soc.h>
  31
  32 #include "8250.h"
  33
  34 #define DEFAULT_CLK_SPEED       48000000
  35
  36 #define UART_ERRATA_i202_MDR1_ACCESS    (1 << 0)
  37 #define OMAP_UART_WER_HAS_TX_WAKEUP     (1 << 1)
  38 #define OMAP_DMA_TX_KICK                (1 << 2)
  39 /*
  40  * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
  41  * The same errata is applicable to AM335x and DRA7x processors too.
  42  */
  43 #define UART_ERRATA_CLOCK_DISABLE       (1 << 3)
  44 #define UART_HAS_EFR2                   BIT(4)
  45 #define UART_HAS_RHR_IT_DIS             BIT(5)
  46 #define UART_RX_TIMEOUT_QUIRK           BIT(6)
  47
  48 #define OMAP_UART_FCR_RX_TRIG           6
  49 #define OMAP_UART_FCR_TX_TRIG           4
  50
  51 /* SCR register bitmasks */
  52 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK       (1 << 7)
  53 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK       (1 << 6)
  54 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  55 #define OMAP_UART_SCR_DMAMODE_MASK              (3 << 1)
  56 #define OMAP_UART_SCR_DMAMODE_1                 (1 << 1)
  57 #define OMAP_UART_SCR_DMAMODE_CTL               (1 << 0)
  58
  59 /* MVR register bitmasks */
  60 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  61 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  62 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  63 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  64 #define OMAP_UART_MVR_MAJ_MASK          0x700
  65 #define OMAP_UART_MVR_MAJ_SHIFT         8
  66 #define OMAP_UART_MVR_MIN_MASK          0x3f
  67
  68 /* SYSC register bitmasks */
  69 #define OMAP_UART_SYSC_SOFTRESET        (1 << 1)
  70
  71 /* SYSS register bitmasks */
  72 #define OMAP_UART_SYSS_RESETDONE        (1 << 0)
  73
  74 #define UART_TI752_TLR_TX       0
  75 #define UART_TI752_TLR_RX       4
  76
  77 #define TRIGGER_TLR_MASK(x)     ((x & 0x3c) >> 2)
  78 #define TRIGGER_FCR_MASK(x)     (x & 3)
  79
  80 /* Enable XON/XOFF flow control on output */
  81 #define OMAP_UART_SW_TX         0x08
  82 /* Enable XON/XOFF flow control on input */
  83 #define OMAP_UART_SW_RX         0x02
  84
  85 #define OMAP_UART_WER_MOD_WKUP  0x7f
  86 #define OMAP_UART_TX_WAKEUP_EN  (1 << 7)
  87
  88 #define TX_TRIGGER      1
  89 #define RX_TRIGGER      48
  90
  91 #define OMAP_UART_TCR_RESTORE(x)        ((x / 4) << 4)
  92 #define OMAP_UART_TCR_HALT(x)           ((x / 4) << 0)
  93
  94 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  95
  96 #define OMAP_UART_REV_46 0x0406
  97 #define OMAP_UART_REV_52 0x0502
  98 #define OMAP_UART_REV_63 0x0603
  99
 100 /* Interrupt Enable Register 2 */
 101 #define UART_OMAP_IER2                  0x1B
 102 #define UART_OMAP_IER2_RHR_IT_DIS       BIT(2)
 103
 104 /* Enhanced features register 2 */
 105 #define UART_OMAP_EFR2                  0x23
 106 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE   BIT(6)
 107
 108 /* RX FIFO occupancy indicator */
 109 #define UART_OMAP_RX_LVL                0x19
 110
 111 struct omap8250_priv {
 112         int line;
 113         u8 habit;
 114         u8 mdr1;
 115         u8 efr;
 116         u8 scr;
 117         u8 wer;
 118         u8 xon;
 119         u8 xoff;
 120         u8 delayed_restore;
 121         u16 quot;
 122
 123         u8 tx_trigger;
 124         u8 rx_trigger;
 125         bool is_suspending;
 126         int wakeirq;
 127         int wakeups_enabled;
 128         u32 latency;
 129         u32 calc_latency;
 130         struct pm_qos_request pm_qos_request;
 131         struct work_struct qos_work;
 132         struct uart_8250_dma omap8250_dma;
 133         spinlock_t rx_dma_lock;
 134         bool rx_dma_broken;
 135         bool throttled;
 136 };
 137
 138 struct omap8250_dma_params {
 139         u32 rx_size;
 140         u8 rx_trigger;
 141         u8 tx_trigger;
 142 };
 143
 144 struct omap8250_platdata {
 145         struct omap8250_dma_params *dma_params;
 146         u8 habit;
 147 };
 148
 149 #ifdef CONFIG_SERIAL_8250_DMA
 150 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
 151 #else
 152 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
 153 #endif
 154
 155 static u32 uart_read(struct uart_8250_port *up, u32 reg)
 156 {
 157         return readl(up->port.membase + (reg << up->port.regshift));
 158 }
 159
 160 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 161 {
 162         struct uart_8250_port *up = up_to_u8250p(port);
 163         struct omap8250_priv *priv = up->port.private_data;
 164         u8 lcr;
 165
 166         serial8250_do_set_mctrl(port, mctrl);
 167
 168         if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
 169                 /*
 170                  * Turn off autoRTS if RTS is lowered and restore autoRTS
 171                  * setting if RTS is raised
 172                  */
 173                 lcr = serial_in(up, UART_LCR);
 174                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 175                 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 176                         priv->efr |= UART_EFR_RTS;
 177                 else
 178                         priv->efr &= ~UART_EFR_RTS;
 179                 serial_out(up, UART_EFR, priv->efr);
 180                 serial_out(up, UART_LCR, lcr);
 181         }
 182 }
 183
 184 /*
 185  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
 186  * The access to uart register after MDR1 Access
 187  * causes UART to corrupt data.
 188  *
 189  * Need a delay =
 190  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 191  * give 10 times as much
 192  */
 193 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
 194                                      struct omap8250_priv *priv)
 195 {
 196         u8 timeout = 255;
 197
 198         serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 199         udelay(2);
 200         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
 201                         UART_FCR_CLEAR_RCVR);
 202         /*
 203          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
 204          * TX_FIFO_E bit is 1.
 205          */
 206         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
 207                                 (UART_LSR_THRE | UART_LSR_DR))) {
 208                 timeout--;
 209                 if (!timeout) {
 210                         /* Should *never* happen. we warn and carry on */
 211                         dev_crit(up->port.dev, "Errata i202: timedout %x\n",
 212                                  serial_in(up, UART_LSR));
 213                         break;
 214                 }
 215                 udelay(1);
 216         }
 217 }
 218
 219 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
 220                                   struct omap8250_priv *priv)
 221 {
 222         unsigned int uartclk = port->uartclk;
 223         unsigned int div_13, div_16;
 224         unsigned int abs_d13, abs_d16;
 225
 226         /*
 227          * Old custom speed handling.
 228          */
 229         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
 230                 priv->quot = port->custom_divisor & UART_DIV_MAX;
 231                 /*
 232                  * I assume that nobody is using this. But hey, if somebody
 233                  * would like to specify the divisor _and_ the mode then the
 234                  * driver is ready and waiting for it.
 235                  */
 236                 if (port->custom_divisor & (1 << 16))
 237                         priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 238                 else
 239                         priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 240                 return;
 241         }
 242         div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
 243         div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
 244
 245         if (!div_13)
 246                 div_13 = 1;
 247         if (!div_16)
 248                 div_16 = 1;
 249
 250         abs_d13 = abs(baud - uartclk / 13 / div_13);
 251         abs_d16 = abs(baud - uartclk / 16 / div_16);
 252
 253         if (abs_d13 >= abs_d16) {
 254                 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 255                 priv->quot = div_16;
 256         } else {
 257                 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 258                 priv->quot = div_13;
 259         }
 260 }
 261
 262 static void omap8250_update_scr(struct uart_8250_port *up,
 263                                 struct omap8250_priv *priv)
 264 {
 265         u8 old_scr;
 266
 267         old_scr = serial_in(up, UART_OMAP_SCR);
 268         if (old_scr == priv->scr)
 269                 return;
 270
 271         /*
 272          * The manual recommends not to enable the DMA mode selector in the SCR
 273          * (instead of the FCR) register _and_ selecting the DMA mode as one
 274          * register write because this may lead to malfunction.
 275          */
 276         if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
 277                 serial_out(up, UART_OMAP_SCR,
 278                            priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
 279         serial_out(up, UART_OMAP_SCR, priv->scr);
 280 }
 281
 282 static void omap8250_update_mdr1(struct uart_8250_port *up,
 283                                  struct omap8250_priv *priv)
 284 {
 285         if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
 286                 omap_8250_mdr1_errataset(up, priv);
 287         else
 288                 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 289 }
 290
 291 static void omap8250_restore_regs(struct uart_8250_port *up)
 292 {
 293         struct omap8250_priv *priv = up->port.private_data;
 294         struct uart_8250_dma    *dma = up->dma;
 295
 296         if (dma && dma->tx_running) {
 297                 /*
 298                  * TCSANOW requests the change to occur immediately however if
 299                  * we have a TX-DMA operation in progress then it has been
 300                  * observed that it might stall and never complete. Therefore we
 301                  * delay DMA completes to prevent this hang from happen.
 302                  */
 303                 priv->delayed_restore = 1;
 304                 return;
 305         }
 306
 307         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 308         serial_out(up, UART_EFR, UART_EFR_ECB);
 309
 310         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 311         serial8250_out_MCR(up, UART_MCR_TCRTLR);
 312         serial_out(up, UART_FCR, up->fcr);
 313
 314         omap8250_update_scr(up, priv);
 315
 316         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 317
 318         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
 319                         OMAP_UART_TCR_HALT(52));
 320         serial_out(up, UART_TI752_TLR,
 321                    TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
 322                    TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
 323
 324         serial_out(up, UART_LCR, 0);
 325
 326         /* drop TCR + TLR access, we setup XON/XOFF later */
 327         serial8250_out_MCR(up, up->mcr);
 328         serial_out(up, UART_IER, up->ier);
 329
 330         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 331         serial_dl_write(up, priv->quot);
 332
 333         serial_out(up, UART_EFR, priv->efr);
 334
 335         /* Configure flow control */
 336         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 337         serial_out(up, UART_XON1, priv->xon);
 338         serial_out(up, UART_XOFF1, priv->xoff);
 339
 340         serial_out(up, UART_LCR, up->lcr);
 341
 342         omap8250_update_mdr1(up, priv);
 343
 344         up->port.ops->set_mctrl(&up->port, up->port.mctrl);
 345
 346         if (up->port.rs485.flags & SER_RS485_ENABLED)
 347                 serial8250_em485_stop_tx(up);
 348 }
 349
 350 /*
 351  * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
 352  * some differences in how we want to handle flow control.
 353  */
 354 static void omap_8250_set_termios(struct uart_port *port,
 355                                   struct ktermios *termios,
 356                                   struct ktermios *old)
 357 {
 358         struct uart_8250_port *up = up_to_u8250p(port);
 359         struct omap8250_priv *priv = up->port.private_data;
 360         unsigned char cval = 0;
 361         unsigned int baud;
 362
 363         switch (termios->c_cflag & CSIZE) {
 364         case CS5:
 365                 cval = UART_LCR_WLEN5;
 366                 break;
 367         case CS6:
 368                 cval = UART_LCR_WLEN6;
 369                 break;
 370         case CS7:
 371                 cval = UART_LCR_WLEN7;
 372                 break;
 373         default:
 374         case CS8:
 375                 cval = UART_LCR_WLEN8;
 376                 break;
 377         }
 378
 379         if (termios->c_cflag & CSTOPB)
 380                 cval |= UART_LCR_STOP;
 381         if (termios->c_cflag & PARENB)
 382                 cval |= UART_LCR_PARITY;
 383         if (!(termios->c_cflag & PARODD))
 384                 cval |= UART_LCR_EPAR;
 385         if (termios->c_cflag & CMSPAR)
 386                 cval |= UART_LCR_SPAR;
 387
 388         /*
 389          * Ask the core to calculate the divisor for us.
 390          */
 391         baud = uart_get_baud_rate(port, termios, old,
 392                                   port->uartclk / 16 / UART_DIV_MAX,
 393                                   port->uartclk / 13);
 394         omap_8250_get_divisor(port, baud, priv);
 395
 396         /*
 397          * Ok, we're now changing the port state. Do it with
 398          * interrupts disabled.
 399          */
 400         pm_runtime_get_sync(port->dev);
 401         spin_lock_irq(&port->lock);
 402
 403         /*
 404          * Update the per-port timeout.
 405          */
 406         uart_update_timeout(port, termios->c_cflag, baud);
 407
 408         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 409         if (termios->c_iflag & INPCK)
 410                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 411         if (termios->c_iflag & (IGNBRK | PARMRK))
 412                 up->port.read_status_mask |= UART_LSR_BI;
 413
 414         /*
 415          * Characters to ignore
 416          */
 417         up->port.ignore_status_mask = 0;
 418         if (termios->c_iflag & IGNPAR)
 419                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 420         if (termios->c_iflag & IGNBRK) {
 421                 up->port.ignore_status_mask |= UART_LSR_BI;
 422                 /*
 423                  * If we're ignoring parity and break indicators,
 424                  * ignore overruns too (for real raw support).
 425                  */
 426                 if (termios->c_iflag & IGNPAR)
 427                         up->port.ignore_status_mask |= UART_LSR_OE;
 428         }
 429
 430         /*
 431          * ignore all characters if CREAD is not set
 432          */
 433         if ((termios->c_cflag & CREAD) == 0)
 434                 up->port.ignore_status_mask |= UART_LSR_DR;
 435
 436         /*
 437          * Modem status interrupts
 438          */
 439         up->ier &= ~UART_IER_MSI;
 440         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 441                 up->ier |= UART_IER_MSI;
 442
 443         up->lcr = cval;
 444         /* Up to here it was mostly serial8250_do_set_termios() */
 445
 446         /*
 447          * We enable TRIG_GRANU for RX and TX and additionally we set
 448          * SCR_TX_EMPTY bit. The result is the following:
 449          * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
 450          * - less than RX_TRIGGER number of bytes will also cause an interrupt
 451          *   once the UART decides that there no new bytes arriving.
 452          * - Once THRE is enabled, the interrupt will be fired once the FIFO is
 453          *   empty - the trigger level is ignored here.
 454          *
 455          * Once DMA is enabled:
 456          * - UART will assert the TX DMA line once there is room for TX_TRIGGER
 457          *   bytes in the TX FIFO. On each assert the DMA engine will move
 458          *   TX_TRIGGER bytes into the FIFO.
 459          * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
 460          *   the FIFO and move RX_TRIGGER bytes.
 461          * This is because threshold and trigger values are the same.
 462          */
 463         up->fcr = UART_FCR_ENABLE_FIFO;
 464         up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
 465         up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
 466
 467         priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
 468                 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
 469
 470         if (up->dma)
 471                 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
 472                         OMAP_UART_SCR_DMAMODE_CTL;
 473
 474         priv->xon = termios->c_cc[VSTART];
 475         priv->xoff = termios->c_cc[VSTOP];
 476
 477         priv->efr = 0;
 478         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
 479
 480         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
 481             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
 482             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
 483                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
 484                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 485                 priv->efr |= UART_EFR_CTS;
 486         } else  if (up->port.flags & UPF_SOFT_FLOW) {
 487                 /*
 488                  * OMAP rx s/w flow control is borked; the transmitter remains
 489                  * stuck off even if rx flow control is subsequently disabled
 490                  */
 491
 492                 /*
 493                  * IXOFF Flag:
 494                  * Enable XON/XOFF flow control on output.
 495                  * Transmit XON1, XOFF1
 496                  */
 497                 if (termios->c_iflag & IXOFF) {
 498                         up->port.status |= UPSTAT_AUTOXOFF;
 499                         priv->efr |= OMAP_UART_SW_TX;
 500                 }
 501         }
 502         omap8250_restore_regs(up);
 503
 504         spin_unlock_irq(&up->port.lock);
 505         pm_runtime_mark_last_busy(port->dev);
 506         pm_runtime_put_autosuspend(port->dev);
 507
 508         /* calculate wakeup latency constraint */
 509         priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
 510         priv->latency = priv->calc_latency;
 511
 512         schedule_work(&priv->qos_work);
 513
 514         /* Don't rewrite B0 */
 515         if (tty_termios_baud_rate(termios))
 516                 tty_termios_encode_baud_rate(termios, baud, baud);
 517 }
 518
 519 /* same as 8250 except that we may have extra flow bits set in EFR */
 520 static void omap_8250_pm(struct uart_port *port, unsigned int state,
 521                          unsigned int oldstate)
 522 {
 523         struct uart_8250_port *up = up_to_u8250p(port);
 524         u8 efr;
 525
 526         pm_runtime_get_sync(port->dev);
 527         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 528         efr = serial_in(up, UART_EFR);
 529         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 530         serial_out(up, UART_LCR, 0);
 531
 532         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 533         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 534         serial_out(up, UART_EFR, efr);
 535         serial_out(up, UART_LCR, 0);
 536
 537         pm_runtime_mark_last_busy(port->dev);
 538         pm_runtime_put_autosuspend(port->dev);
 539 }
 540
 541 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
 542                                               struct omap8250_priv *priv)
 543 {
 544         const struct soc_device_attribute k3_soc_devices[] = {
 545                 { .family = "AM65X",  },
 546                 { .family = "J721E", .revision = "SR1.0" },
 547                 { /* sentinel */ }
 548         };
 549         u32 mvr, scheme;
 550         u16 revision, major, minor;
 551
 552         mvr = uart_read(up, UART_OMAP_MVER);
 553
 554         /* Check revision register scheme */
 555         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
 556
 557         switch (scheme) {
 558         case 0: /* Legacy Scheme: OMAP2/3 */
 559                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
 560                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
 561                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
 562                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
 563                 break;
 564         case 1:
 565                 /* New Scheme: OMAP4+ */
 566                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
 567                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
 568                         OMAP_UART_MVR_MAJ_SHIFT;
 569                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
 570                 break;
 571         default:
 572                 dev_warn(up->port.dev,
 573                          "Unknown revision, defaulting to highest\n");
 574                 /* highest possible revision */
 575                 major = 0xff;
 576                 minor = 0xff;
 577         }
 578         /* normalize revision for the driver */
 579         revision = UART_BUILD_REVISION(major, minor);
 580
 581         switch (revision) {
 582         case OMAP_UART_REV_46:
 583                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
 584                 break;
 585         case OMAP_UART_REV_52:
 586                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 587                                 OMAP_UART_WER_HAS_TX_WAKEUP;
 588                 break;
 589         case OMAP_UART_REV_63:
 590                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 591                         OMAP_UART_WER_HAS_TX_WAKEUP;
 592                 break;
 593         default:
 594                 break;
 595         }
 596
 597         /*
 598          * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
 599          * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
 600          * to enable errata workaround.
 601          */
 602         if (soc_device_match(k3_soc_devices))
 603                 priv->habit &= ~UART_HAS_RHR_IT_DIS;
 604 }
 605
 606 static void omap8250_uart_qos_work(struct work_struct *work)
 607 {
 608         struct omap8250_priv *priv;
 609
 610         priv = container_of(work, struct omap8250_priv, qos_work);
 611         cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
 612 }
 613
 614 #ifdef CONFIG_SERIAL_8250_DMA
 615 static int omap_8250_dma_handle_irq(struct uart_port *port);
 616 #endif
 617
 618 static irqreturn_t omap8250_irq(int irq, void *dev_id)
 619 {
 620         struct uart_port *port = dev_id;
 621         struct omap8250_priv *priv = port->private_data;
 622         struct uart_8250_port *up = up_to_u8250p(port);
 623         unsigned int iir, lsr;
 624         int ret;
 625
 626 #ifdef CONFIG_SERIAL_8250_DMA
 627         if (up->dma) {
 628                 ret = omap_8250_dma_handle_irq(port);
 629                 return IRQ_RETVAL(ret);
 630         }
 631 #endif
 632
 633         serial8250_rpm_get(up);
 634         lsr = serial_port_in(port, UART_LSR);
 635         iir = serial_port_in(port, UART_IIR);
 636         ret = serial8250_handle_irq(port, iir);
 637
 638         /*
 639          * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
 640          * FIFO has been drained, in which case a dummy read of RX FIFO
 641          * is required to clear RX TIMEOUT condition.
 642          */
 643         if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
 644             (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
 645             serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
 646                 serial_port_in(port, UART_RX);
 647         }
 648
 649         /* Stop processing interrupts on input overrun */
 650         if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
 651                 unsigned long delay;
 652
 653                 up->ier = port->serial_in(port, UART_IER);
 654                 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
 655                         port->ops->stop_rx(port);
 656                 } else {
 657                         /* Keep restarting the timer until
 658                          * the input overrun subsides.
 659                          */
 660                         cancel_delayed_work(&up->overrun_backoff);
 661                 }
 662
 663                 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
 664                 schedule_delayed_work(&up->overrun_backoff, delay);
 665         }
 666
 667         serial8250_rpm_put(up);
 668
 669         return IRQ_RETVAL(ret);
 670 }
 671
 672 static int omap_8250_startup(struct uart_port *port)
 673 {
 674         struct uart_8250_port *up = up_to_u8250p(port);
 675         struct omap8250_priv *priv = port->private_data;
 676         int ret;
 677
 678         if (priv->wakeirq) {
 679                 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
 680                 if (ret)
 681                         return ret;
 682         }
 683
 684         pm_runtime_get_sync(port->dev);
 685
 686         up->mcr = 0;
 687         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 688
 689         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 690
 691         up->lsr_saved_flags = 0;
 692         up->msr_saved_flags = 0;
 693
 694         /* Disable DMA for console UART */
 695         if (uart_console(port))
 696                 up->dma = NULL;
 697
 698         if (up->dma) {
 699                 ret = serial8250_request_dma(up);
 700                 if (ret) {
 701                         dev_warn_ratelimited(port->dev,
 702                                              "failed to request DMA\n");
 703                         up->dma = NULL;
 704                 }
 705         }
 706
 707         ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
 708                           dev_name(port->dev), port);
 709         if (ret < 0)
 710                 goto err;
 711
 712         up->ier = UART_IER_RLSI | UART_IER_RDI;
 713         serial_out(up, UART_IER, up->ier);
 714
 715 #ifdef CONFIG_PM
 716         up->capabilities |= UART_CAP_RPM;
 717 #endif
 718
 719         /* Enable module level wake up */
 720         priv->wer = OMAP_UART_WER_MOD_WKUP;
 721         if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
 722                 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
 723         serial_out(up, UART_OMAP_WER, priv->wer);
 724
 725         if (up->dma && !(priv->habit & UART_HAS_EFR2))
 726                 up->dma->rx_dma(up);
 727
 728         pm_runtime_mark_last_busy(port->dev);
 729         pm_runtime_put_autosuspend(port->dev);
 730         return 0;
 731 err:
 732         pm_runtime_mark_last_busy(port->dev);
 733         pm_runtime_put_autosuspend(port->dev);
 734         dev_pm_clear_wake_irq(port->dev);
 735         return ret;
 736 }
 737
 738 static void omap_8250_shutdown(struct uart_port *port)
 739 {
 740         struct uart_8250_port *up = up_to_u8250p(port);
 741         struct omap8250_priv *priv = port->private_data;
 742
 743         flush_work(&priv->qos_work);
 744         if (up->dma)
 745                 omap_8250_rx_dma_flush(up);
 746
 747         pm_runtime_get_sync(port->dev);
 748
 749         serial_out(up, UART_OMAP_WER, 0);
 750         if (priv->habit & UART_HAS_EFR2)
 751                 serial_out(up, UART_OMAP_EFR2, 0x0);
 752
 753         up->ier = 0;
 754         serial_out(up, UART_IER, 0);
 755
 756         if (up->dma)
 757                 serial8250_release_dma(up);
 758
 759         /*
 760          * Disable break condition and FIFOs
 761          */
 762         if (up->lcr & UART_LCR_SBC)
 763                 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
 764         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 765
 766         pm_runtime_mark_last_busy(port->dev);
 767         pm_runtime_put_autosuspend(port->dev);
 768         free_irq(port->irq, port);
 769         dev_pm_clear_wake_irq(port->dev);
 770 }
 771
 772 static void omap_8250_throttle(struct uart_port *port)
 773 {
 774         struct omap8250_priv *priv = port->private_data;
 775         unsigned long flags;
 776
 777         pm_runtime_get_sync(port->dev);
 778
 779         spin_lock_irqsave(&port->lock, flags);
 780         port->ops->stop_rx(port);
 781         priv->throttled = true;
 782         spin_unlock_irqrestore(&port->lock, flags);
 783
 784         pm_runtime_mark_last_busy(port->dev);
 785         pm_runtime_put_autosuspend(port->dev);
 786 }
 787
 788 static void omap_8250_unthrottle(struct uart_port *port)
 789 {
 790         struct omap8250_priv *priv = port->private_data;
 791         struct uart_8250_port *up = up_to_u8250p(port);
 792         unsigned long flags;
 793
 794         pm_runtime_get_sync(port->dev);
 795
 796         spin_lock_irqsave(&port->lock, flags);
 797         priv->throttled = false;
 798         if (up->dma)
 799                 up->dma->rx_dma(up);
 800         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 801         port->read_status_mask |= UART_LSR_DR;
 802         serial_out(up, UART_IER, up->ier);
 803         spin_unlock_irqrestore(&port->lock, flags);
 804
 805         pm_runtime_mark_last_busy(port->dev);
 806         pm_runtime_put_autosuspend(port->dev);
 807 }
 808
 809 #ifdef CONFIG_SERIAL_8250_DMA
 810 static int omap_8250_rx_dma(struct uart_8250_port *p);
 811
 812 /* Must be called while priv->rx_dma_lock is held */
 813 static void __dma_rx_do_complete(struct uart_8250_port *p)
 814 {
 815         struct uart_8250_dma    *dma = p->dma;
 816         struct tty_port         *tty_port = &p->port.state->port;
 817         struct omap8250_priv    *priv = p->port.private_data;
 818         struct dma_chan         *rxchan = dma->rxchan;
 819         dma_cookie_t            cookie;
 820         struct dma_tx_state     state;
 821         int                     count;
 822         int                     ret;
 823         u32                     reg;
 824
 825         if (!dma->rx_running)
 826                 goto out;
 827
 828         cookie = dma->rx_cookie;
 829         dma->rx_running = 0;
 830
 831         /* Re-enable RX FIFO interrupt now that transfer is complete */
 832         if (priv->habit & UART_HAS_RHR_IT_DIS) {
 833                 reg = serial_in(p, UART_OMAP_IER2);
 834                 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
 835                 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
 836         }
 837
 838         dmaengine_tx_status(rxchan, cookie, &state);
 839
 840         count = dma->rx_size - state.residue + state.in_flight_bytes;
 841         if (count < dma->rx_size) {
 842                 dmaengine_terminate_async(rxchan);
 843
 844                 /*
 845                  * Poll for teardown to complete which guarantees in
 846                  * flight data is drained.
 847                  */
 848                 if (state.in_flight_bytes) {
 849                         int poll_count = 25;
 850
 851                         while (dmaengine_tx_status(rxchan, cookie, NULL) &&
 852                                poll_count--)
 853                                 cpu_relax();
 854
 855                         if (poll_count == -1)
 856                                 dev_err(p->port.dev, "teardown incomplete\n");
 857                 }
 858         }
 859         if (!count)
 860                 goto out;
 861         ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
 862
 863         p->port.icount.rx += ret;
 864         p->port.icount.buf_overrun += count - ret;
 865 out:
 866
 867         tty_flip_buffer_push(tty_port);
 868 }
 869
 870 static void __dma_rx_complete(void *param)
 871 {
 872         struct uart_8250_port *p = param;
 873         struct omap8250_priv *priv = p->port.private_data;
 874         struct uart_8250_dma *dma = p->dma;
 875         struct dma_tx_state     state;
 876         unsigned long flags;
 877
 878         spin_lock_irqsave(&p->port.lock, flags);
 879
 880         /*
 881          * If the tx status is not DMA_COMPLETE, then this is a delayed
 882          * completion callback. A previous RX timeout flush would have
 883          * already pushed the data, so exit.
 884          */
 885         if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
 886                         DMA_COMPLETE) {
 887                 spin_unlock_irqrestore(&p->port.lock, flags);
 888                 return;
 889         }
 890         __dma_rx_do_complete(p);
 891         if (!priv->throttled) {
 892                 p->ier |= UART_IER_RLSI | UART_IER_RDI;
 893                 serial_out(p, UART_IER, p->ier);
 894                 if (!(priv->habit & UART_HAS_EFR2))
 895                         omap_8250_rx_dma(p);
 896         }
 897
 898         spin_unlock_irqrestore(&p->port.lock, flags);
 899 }
 900
 901 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
 902 {
 903         struct omap8250_priv    *priv = p->port.private_data;
 904         struct uart_8250_dma    *dma = p->dma;
 905         struct dma_tx_state     state;
 906         unsigned long           flags;
 907         int ret;
 908
 909         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 910
 911         if (!dma->rx_running) {
 912                 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 913                 return;
 914         }
 915
 916         ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
 917         if (ret == DMA_IN_PROGRESS) {
 918                 ret = dmaengine_pause(dma->rxchan);
 919                 if (WARN_ON_ONCE(ret))
 920                         priv->rx_dma_broken = true;
 921         }
 922         __dma_rx_do_complete(p);
 923         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 924 }
 925
 926 static int omap_8250_rx_dma(struct uart_8250_port *p)
 927 {
 928         struct omap8250_priv            *priv = p->port.private_data;
 929         struct uart_8250_dma            *dma = p->dma;
 930         int                             err = 0;
 931         struct dma_async_tx_descriptor  *desc;
 932         unsigned long                   flags;
 933         u32                             reg;
 934
 935         if (priv->rx_dma_broken)
 936                 return -EINVAL;
 937
 938         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 939
 940         if (dma->rx_running) {
 941                 enum dma_status state;
 942
 943                 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
 944                 if (state == DMA_COMPLETE) {
 945                         /*
 946                          * Disable RX interrupts to allow RX DMA completion
 947                          * callback to run.
 948                          */
 949                         p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 950                         serial_out(p, UART_IER, p->ier);
 951                 }
 952                 goto out;
 953         }
 954
 955         desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
 956                                            dma->rx_size, DMA_DEV_TO_MEM,
 957                                            DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 958         if (!desc) {
 959                 err = -EBUSY;
 960                 goto out;
 961         }
 962
 963         dma->rx_running = 1;
 964         desc->callback = __dma_rx_complete;
 965         desc->callback_param = p;
 966
 967         dma->rx_cookie = dmaengine_submit(desc);
 968
 969         /*
 970          * Disable RX FIFO interrupt while RX DMA is enabled, else
 971          * spurious interrupt may be raised when data is in the RX FIFO
 972          * but is yet to be drained by DMA.
 973          */
 974         if (priv->habit & UART_HAS_RHR_IT_DIS) {
 975                 reg = serial_in(p, UART_OMAP_IER2);
 976                 reg |= UART_OMAP_IER2_RHR_IT_DIS;
 977                 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
 978         }
 979
 980         dma_async_issue_pending(dma->rxchan);
 981 out:
 982         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 983         return err;
 984 }
 985
 986 static int omap_8250_tx_dma(struct uart_8250_port *p);
 987
 988 static void omap_8250_dma_tx_complete(void *param)
 989 {
 990         struct uart_8250_port   *p = param;
 991         struct uart_8250_dma    *dma = p->dma;
 992         struct circ_buf         *xmit = &p->port.state->xmit;
 993         unsigned long           flags;
 994         bool                    en_thri = false;
 995         struct omap8250_priv    *priv = p->port.private_data;
 996
 997         dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
 998                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 999
1000         spin_lock_irqsave(&p->port.lock, flags);
1001
1002         dma->tx_running = 0;
1003
1004         xmit->tail += dma->tx_size;
1005         xmit->tail &= UART_XMIT_SIZE - 1;
1006         p->port.icount.tx += dma->tx_size;
1007
1008         if (priv->delayed_restore) {
1009                 priv->delayed_restore = 0;
1010                 omap8250_restore_regs(p);
1011         }
1012
1013         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1014                 uart_write_wakeup(&p->port);
1015
1016         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1017                 int ret;
1018
1019                 ret = omap_8250_tx_dma(p);
1020                 if (ret)
1021                         en_thri = true;
1022         } else if (p->capabilities & UART_CAP_RPM) {
1023                 en_thri = true;
1024         }
1025
1026         if (en_thri) {
1027                 dma->tx_err = 1;
1028                 serial8250_set_THRI(p);
1029         }
1030
1031         spin_unlock_irqrestore(&p->port.lock, flags);
1032 }
1033
1034 static int omap_8250_tx_dma(struct uart_8250_port *p)
1035 {
1036         struct uart_8250_dma            *dma = p->dma;
1037         struct omap8250_priv            *priv = p->port.private_data;
1038         struct circ_buf                 *xmit = &p->port.state->xmit;
1039         struct dma_async_tx_descriptor  *desc;
1040         unsigned int    skip_byte = 0;
1041         int ret;
1042
1043         if (dma->tx_running)
1044                 return 0;
1045         if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1046
1047                 /*
1048                  * Even if no data, we need to return an error for the two cases
1049                  * below so serial8250_tx_chars() is invoked and properly clears
1050                  * THRI and/or runtime suspend.
1051                  */
1052                 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1053                         ret = -EBUSY;
1054                         goto err;
1055                 }
1056                 serial8250_clear_THRI(p);
1057                 return 0;
1058         }
1059
1060         dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1061         if (priv->habit & OMAP_DMA_TX_KICK) {
1062                 u8 tx_lvl;
1063
1064                 /*
1065                  * We need to put the first byte into the FIFO in order to start
1066                  * the DMA transfer. For transfers smaller than four bytes we
1067                  * don't bother doing DMA at all. It seem not matter if there
1068                  * are still bytes in the FIFO from the last transfer (in case
1069                  * we got here directly from omap_8250_dma_tx_complete()). Bytes
1070                  * leaving the FIFO seem not to trigger the DMA transfer. It is
1071                  * really the byte that we put into the FIFO.
1072                  * If the FIFO is already full then we most likely got here from
1073                  * omap_8250_dma_tx_complete(). And this means the DMA engine
1074                  * just completed its work. We don't have to wait the complete
1075                  * 86us at 115200,8n1 but around 60us (not to mention lower
1076                  * baudrates). So in that case we take the interrupt and try
1077                  * again with an empty FIFO.
1078                  */
1079                 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1080                 if (tx_lvl == p->tx_loadsz) {
1081                         ret = -EBUSY;
1082                         goto err;
1083                 }
1084                 if (dma->tx_size < 4) {
1085                         ret = -EINVAL;
1086                         goto err;
1087                 }
1088                 skip_byte = 1;
1089         }
1090
1091         desc = dmaengine_prep_slave_single(dma->txchan,
1092                         dma->tx_addr + xmit->tail + skip_byte,
1093                         dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1094                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1095         if (!desc) {
1096                 ret = -EBUSY;
1097                 goto err;
1098         }
1099
1100         dma->tx_running = 1;
1101
1102         desc->callback = omap_8250_dma_tx_complete;
1103         desc->callback_param = p;
1104
1105         dma->tx_cookie = dmaengine_submit(desc);
1106
1107         dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1108                                    UART_XMIT_SIZE, DMA_TO_DEVICE);
1109
1110         dma_async_issue_pending(dma->txchan);
1111         if (dma->tx_err)
1112                 dma->tx_err = 0;
1113
1114         serial8250_clear_THRI(p);
1115         if (skip_byte)
1116                 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1117         return 0;
1118 err:
1119         dma->tx_err = 1;
1120         return ret;
1121 }
1122
1123 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1124 {
1125         switch (iir & 0x3f) {
1126         case UART_IIR_RLSI:
1127         case UART_IIR_RX_TIMEOUT:
1128         case UART_IIR_RDI:
1129                 omap_8250_rx_dma_flush(up);
1130                 return true;
1131         }
1132         return omap_8250_rx_dma(up);
1133 }
1134
1135 static unsigned char omap_8250_handle_rx_dma(struct uart_8250_port *up,
1136                                              u8 iir, unsigned char status)
1137 {
1138         if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1139             (iir & UART_IIR_RDI)) {
1140                 if (handle_rx_dma(up, iir)) {
1141                         status = serial8250_rx_chars(up, status);
1142                         omap_8250_rx_dma(up);
1143                 }
1144         }
1145
1146         return status;
1147 }
1148
1149 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1150                                      unsigned char status)
1151 {
1152         /*
1153          * Queue a new transfer if FIFO has data.
1154          */
1155         if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1156             (up->ier & UART_IER_RDI)) {
1157                 omap_8250_rx_dma(up);
1158                 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1159         } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1160                 /*
1161                  * Disable RX timeout, read IIR to clear
1162                  * current timeout condition, clear EFR2 to
1163                  * periodic timeouts, re-enable interrupts.
1164                  */
1165                 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1166                 serial_out(up, UART_IER, up->ier);
1167                 omap_8250_rx_dma_flush(up);
1168                 serial_in(up, UART_IIR);
1169                 serial_out(up, UART_OMAP_EFR2, 0x0);
1170                 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1171                 serial_out(up, UART_IER, up->ier);
1172         }
1173 }
1174
1175 /*
1176  * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1177  * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1178  * use the default routine in the non-DMA case and this one for with DMA.
1179  */
1180 static int omap_8250_dma_handle_irq(struct uart_port *port)
1181 {
1182         struct uart_8250_port *up = up_to_u8250p(port);
1183         struct omap8250_priv *priv = up->port.private_data;
1184         unsigned char status;
1185         unsigned long flags;
1186         u8 iir;
1187
1188         serial8250_rpm_get(up);
1189
1190         iir = serial_port_in(port, UART_IIR);
1191         if (iir & UART_IIR_NO_INT) {
1192                 serial8250_rpm_put(up);
1193                 return IRQ_HANDLED;
1194         }
1195
1196         spin_lock_irqsave(&port->lock, flags);
1197
1198         status = serial_port_in(port, UART_LSR);
1199
1200         if (priv->habit & UART_HAS_EFR2)
1201                 am654_8250_handle_rx_dma(up, iir, status);
1202         else
1203                 status = omap_8250_handle_rx_dma(up, iir, status);
1204
1205         serial8250_modem_status(up);
1206         if (status & UART_LSR_THRE && up->dma->tx_err) {
1207                 if (uart_tx_stopped(&up->port) ||
1208                     uart_circ_empty(&up->port.state->xmit)) {
1209                         up->dma->tx_err = 0;
1210                         serial8250_tx_chars(up);
1211                 } else  {
1212                         /*
1213                          * try again due to an earlier failer which
1214                          * might have been resolved by now.
1215                          */
1216                         if (omap_8250_tx_dma(up))
1217                                 serial8250_tx_chars(up);
1218                 }
1219         }
1220
1221         uart_unlock_and_check_sysrq(port, flags);
1222         serial8250_rpm_put(up);
1223         return 1;
1224 }
1225
1226 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1227 {
1228         return false;
1229 }
1230
1231 #else
1232
1233 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1234 {
1235         return -EINVAL;
1236 }
1237 #endif
1238
1239 static int omap8250_no_handle_irq(struct uart_port *port)
1240 {
1241         /* IRQ has not been requested but handling irq? */
1242         WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1243         return 0;
1244 }
1245
1246 static struct omap8250_dma_params am654_dma = {
1247         .rx_size = SZ_2K,
1248         .rx_trigger = 1,
1249         .tx_trigger = TX_TRIGGER,
1250 };
1251
1252 static struct omap8250_dma_params am33xx_dma = {
1253         .rx_size = RX_TRIGGER,
1254         .rx_trigger = RX_TRIGGER,
1255         .tx_trigger = TX_TRIGGER,
1256 };
1257
1258 static struct omap8250_platdata am654_platdata = {
1259         .dma_params     = &am654_dma,
1260         .habit          = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1261                           UART_RX_TIMEOUT_QUIRK,
1262 };
1263
1264 static struct omap8250_platdata am33xx_platdata = {
1265         .dma_params     = &am33xx_dma,
1266         .habit          = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1267 };
1268
1269 static struct omap8250_platdata omap4_platdata = {
1270         .dma_params     = &am33xx_dma,
1271         .habit          = UART_ERRATA_CLOCK_DISABLE,
1272 };
1273
1274 static const struct of_device_id omap8250_dt_ids[] = {
1275         { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1276         { .compatible = "ti,omap2-uart" },
1277         { .compatible = "ti,omap3-uart" },
1278         { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1279         { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1280         { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1281         { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1282         {},
1283 };
1284 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1285
1286 static int omap8250_probe(struct platform_device *pdev)
1287 {
1288         struct device_node *np = pdev->dev.of_node;
1289         struct omap8250_priv *priv;
1290         const struct omap8250_platdata *pdata;
1291         struct uart_8250_port up;
1292         struct resource *regs;
1293         void __iomem *membase;
1294         int irq, ret;
1295
1296         irq = platform_get_irq(pdev, 0);
1297         if (irq < 0)
1298                 return irq;
1299
1300         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1301         if (!regs) {
1302                 dev_err(&pdev->dev, "missing registers\n");
1303                 return -EINVAL;
1304         }
1305
1306         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1307         if (!priv)
1308                 return -ENOMEM;
1309
1310         membase = devm_ioremap(&pdev->dev, regs->start,
1311                                        resource_size(regs));
1312         if (!membase)
1313                 return -ENODEV;
1314
1315         memset(&up, 0, sizeof(up));
1316         up.port.dev = &pdev->dev;
1317         up.port.mapbase = regs->start;
1318         up.port.membase = membase;
1319         up.port.irq = irq;
1320         /*
1321          * It claims to be 16C750 compatible however it is a little different.
1322          * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1323          * have) is enabled via EFR instead of MCR. The type is set here 8250
1324          * just to get things going. UNKNOWN does not work for a few reasons and
1325          * we don't need our own type since we don't use 8250's set_termios()
1326          * or pm callback.
1327          */
1328         up.port.type = PORT_8250;
1329         up.port.iotype = UPIO_MEM;
1330         up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1331                 UPF_HARD_FLOW;
1332         up.port.private_data = priv;
1333
1334         up.port.regshift = 2;
1335         up.port.fifosize = 64;
1336         up.tx_loadsz = 64;
1337         up.capabilities = UART_CAP_FIFO;
1338 #ifdef CONFIG_PM
1339         /*
1340          * Runtime PM is mostly transparent. However to do it right we need to a
1341          * TX empty interrupt before we can put the device to auto idle. So if
1342          * PM is not enabled we don't add that flag and can spare that one extra
1343          * interrupt in the TX path.
1344          */
1345         up.capabilities |= UART_CAP_RPM;
1346 #endif
1347         up.port.set_termios = omap_8250_set_termios;
1348         up.port.set_mctrl = omap8250_set_mctrl;
1349         up.port.pm = omap_8250_pm;
1350         up.port.startup = omap_8250_startup;
1351         up.port.shutdown = omap_8250_shutdown;
1352         up.port.throttle = omap_8250_throttle;
1353         up.port.unthrottle = omap_8250_unthrottle;
1354         up.port.rs485_config = serial8250_em485_config;
1355         up.rs485_start_tx = serial8250_em485_start_tx;
1356         up.rs485_stop_tx = serial8250_em485_stop_tx;
1357         up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1358
1359         ret = of_alias_get_id(np, "serial");
1360         if (ret < 0) {
1361                 dev_err(&pdev->dev, "failed to get alias\n");
1362                 return ret;
1363         }
1364         up.port.line = ret;
1365
1366         if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1367                 struct clk *clk;
1368
1369                 clk = devm_clk_get(&pdev->dev, NULL);
1370                 if (IS_ERR(clk)) {
1371                         if (PTR_ERR(clk) == -EPROBE_DEFER)
1372                                 return -EPROBE_DEFER;
1373                 } else {
1374                         up.port.uartclk = clk_get_rate(clk);
1375                 }
1376         }
1377
1378         if (of_property_read_u32(np, "overrun-throttle-ms",
1379                                  &up.overrun_backoff_time_ms) != 0)
1380                 up.overrun_backoff_time_ms = 0;
1381
1382         priv->wakeirq = irq_of_parse_and_map(np, 1);
1383
1384         pdata = of_device_get_match_data(&pdev->dev);
1385         if (pdata)
1386                 priv->habit |= pdata->habit;
1387
1388         if (!up.port.uartclk) {
1389                 up.port.uartclk = DEFAULT_CLK_SPEED;
1390                 dev_warn(&pdev->dev,
1391                          "No clock speed specified: using default: %d\n",
1392                          DEFAULT_CLK_SPEED);
1393         }
1394
1395         priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1396         priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1397         cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1398         INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1399
1400         spin_lock_init(&priv->rx_dma_lock);
1401
1402         device_init_wakeup(&pdev->dev, true);
1403         pm_runtime_enable(&pdev->dev);
1404         pm_runtime_use_autosuspend(&pdev->dev);
1405
1406         /*
1407          * Disable runtime PM until autosuspend delay unless specifically
1408          * enabled by the user via sysfs. This is the historic way to
1409          * prevent an unsafe default policy with lossy characters on wake-up.
1410          * For serdev devices this is not needed, the policy can be managed by
1411          * the serdev driver.
1412          */
1413         if (!of_get_available_child_count(pdev->dev.of_node))
1414                 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1415
1416         pm_runtime_irq_safe(&pdev->dev);
1417
1418         pm_runtime_get_sync(&pdev->dev);
1419
1420         omap_serial_fill_features_erratas(&up, priv);
1421         up.port.handle_irq = omap8250_no_handle_irq;
1422         priv->rx_trigger = RX_TRIGGER;
1423         priv->tx_trigger = TX_TRIGGER;
1424 #ifdef CONFIG_SERIAL_8250_DMA
1425         /*
1426          * Oh DMA support. If there are no DMA properties in the DT then
1427          * we will fall back to a generic DMA channel which does not
1428          * really work here. To ensure that we do not get a generic DMA
1429          * channel assigned, we have the the_no_dma_filter_fn() here.
1430          * To avoid "failed to request DMA" messages we check for DMA
1431          * properties in DT.
1432          */
1433         ret = of_property_count_strings(np, "dma-names");
1434         if (ret == 2) {
1435                 struct omap8250_dma_params *dma_params = NULL;
1436
1437                 up.dma = &priv->omap8250_dma;
1438                 up.dma->fn = the_no_dma_filter_fn;
1439                 up.dma->tx_dma = omap_8250_tx_dma;
1440                 up.dma->rx_dma = omap_8250_rx_dma;
1441                 if (pdata)
1442                         dma_params = pdata->dma_params;
1443
1444                 if (dma_params) {
1445                         up.dma->rx_size = dma_params->rx_size;
1446                         up.dma->rxconf.src_maxburst = dma_params->rx_trigger;
1447                         up.dma->txconf.dst_maxburst = dma_params->tx_trigger;
1448                         priv->rx_trigger = dma_params->rx_trigger;
1449                         priv->tx_trigger = dma_params->tx_trigger;
1450                 } else {
1451                         up.dma->rx_size = RX_TRIGGER;
1452                         up.dma->rxconf.src_maxburst = RX_TRIGGER;
1453                         up.dma->txconf.dst_maxburst = TX_TRIGGER;
1454                 }
1455         }
1456 #endif
1457         ret = serial8250_register_8250_port(&up);
1458         if (ret < 0) {
1459                 dev_err(&pdev->dev, "unable to register 8250 port\n");
1460                 goto err;
1461         }
1462         priv->line = ret;
1463         platform_set_drvdata(pdev, priv);
1464         pm_runtime_mark_last_busy(&pdev->dev);
1465         pm_runtime_put_autosuspend(&pdev->dev);
1466         return 0;
1467 err:
1468         pm_runtime_dont_use_autosuspend(&pdev->dev);
1469         pm_runtime_put_sync(&pdev->dev);
1470         pm_runtime_disable(&pdev->dev);
1471         return ret;
1472 }
1473
1474 static int omap8250_remove(struct platform_device *pdev)
1475 {
1476         struct omap8250_priv *priv = platform_get_drvdata(pdev);
1477
1478         pm_runtime_dont_use_autosuspend(&pdev->dev);
1479         pm_runtime_put_sync(&pdev->dev);
1480         pm_runtime_disable(&pdev->dev);
1481         serial8250_unregister_port(priv->line);
1482         cpu_latency_qos_remove_request(&priv->pm_qos_request);
1483         device_init_wakeup(&pdev->dev, false);
1484         return 0;
1485 }
1486
1487 #ifdef CONFIG_PM_SLEEP
1488 static int omap8250_prepare(struct device *dev)
1489 {
1490         struct omap8250_priv *priv = dev_get_drvdata(dev);
1491
1492         if (!priv)
1493                 return 0;
1494         priv->is_suspending = true;
1495         return 0;
1496 }
1497
1498 static void omap8250_complete(struct device *dev)
1499 {
1500         struct omap8250_priv *priv = dev_get_drvdata(dev);
1501
1502         if (!priv)
1503                 return;
1504         priv->is_suspending = false;
1505 }
1506
1507 static int omap8250_suspend(struct device *dev)
1508 {
1509         struct omap8250_priv *priv = dev_get_drvdata(dev);
1510         struct uart_8250_port *up = serial8250_get_port(priv->line);
1511
1512         serial8250_suspend_port(priv->line);
1513
1514         pm_runtime_get_sync(dev);
1515         if (!device_may_wakeup(dev))
1516                 priv->wer = 0;
1517         serial_out(up, UART_OMAP_WER, priv->wer);
1518         pm_runtime_mark_last_busy(dev);
1519         pm_runtime_put_autosuspend(dev);
1520
1521         flush_work(&priv->qos_work);
1522         return 0;
1523 }
1524
1525 static int omap8250_resume(struct device *dev)
1526 {
1527         struct omap8250_priv *priv = dev_get_drvdata(dev);
1528
1529         serial8250_resume_port(priv->line);
1530         return 0;
1531 }
1532 #else
1533 #define omap8250_prepare NULL
1534 #define omap8250_complete NULL
1535 #endif
1536
1537 #ifdef CONFIG_PM
1538 static int omap8250_lost_context(struct uart_8250_port *up)
1539 {
1540         u32 val;
1541
1542         val = serial_in(up, UART_OMAP_SCR);
1543         /*
1544          * If we lose context, then SCR is set to its reset value of zero.
1545          * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1546          * among other bits, to never set the register back to zero again.
1547          */
1548         if (!val)
1549                 return 1;
1550         return 0;
1551 }
1552
1553 /* TODO: in future, this should happen via API in drivers/reset/ */
1554 static int omap8250_soft_reset(struct device *dev)
1555 {
1556         struct omap8250_priv *priv = dev_get_drvdata(dev);
1557         struct uart_8250_port *up = serial8250_get_port(priv->line);
1558         int timeout = 100;
1559         int sysc;
1560         int syss;
1561
1562         /*
1563          * At least on omap4, unused uarts may not idle after reset without
1564          * a basic scr dma configuration even with no dma in use. The
1565          * module clkctrl status bits will be 1 instead of 3 blocking idle
1566          * for the whole clockdomain. The softreset below will clear scr,
1567          * and we restore it on resume so this is safe to do on all SoCs
1568          * needing omap8250_soft_reset() quirk. Do it in two writes as
1569          * recommended in the comment for omap8250_update_scr().
1570          */
1571         serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1572         serial_out(up, UART_OMAP_SCR,
1573                    OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1574
1575         sysc = serial_in(up, UART_OMAP_SYSC);
1576
1577         /* softreset the UART */
1578         sysc |= OMAP_UART_SYSC_SOFTRESET;
1579         serial_out(up, UART_OMAP_SYSC, sysc);
1580
1581         /* By experiments, 1us enough for reset complete on AM335x */
1582         do {
1583                 udelay(1);
1584                 syss = serial_in(up, UART_OMAP_SYSS);
1585         } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1586
1587         if (!timeout) {
1588                 dev_err(dev, "timed out waiting for reset done\n");
1589                 return -ETIMEDOUT;
1590         }
1591
1592         return 0;
1593 }
1594
1595 static int omap8250_runtime_suspend(struct device *dev)
1596 {
1597         struct omap8250_priv *priv = dev_get_drvdata(dev);
1598         struct uart_8250_port *up;
1599
1600         /* In case runtime-pm tries this before we are setup */
1601         if (!priv)
1602                 return 0;
1603
1604         up = serial8250_get_port(priv->line);
1605         /*
1606          * When using 'no_console_suspend', the console UART must not be
1607          * suspended. Since driver suspend is managed by runtime suspend,
1608          * preventing runtime suspend (by returning error) will keep device
1609          * active during suspend.
1610          */
1611         if (priv->is_suspending && !console_suspend_enabled) {
1612                 if (uart_console(&up->port))
1613                         return -EBUSY;
1614         }
1615
1616         if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1617                 int ret;
1618
1619                 ret = omap8250_soft_reset(dev);
1620                 if (ret)
1621                         return ret;
1622
1623                 /* Restore to UART mode after reset (for wakeup) */
1624                 omap8250_update_mdr1(up, priv);
1625                 /* Restore wakeup enable register */
1626                 serial_out(up, UART_OMAP_WER, priv->wer);
1627         }
1628
1629         if (up->dma && up->dma->rxchan)
1630                 omap_8250_rx_dma_flush(up);
1631
1632         priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1633         schedule_work(&priv->qos_work);
1634
1635         return 0;
1636 }
1637
1638 static int omap8250_runtime_resume(struct device *dev)
1639 {
1640         struct omap8250_priv *priv = dev_get_drvdata(dev);
1641         struct uart_8250_port *up;
1642
1643         /* In case runtime-pm tries this before we are setup */
1644         if (!priv)
1645                 return 0;
1646
1647         up = serial8250_get_port(priv->line);
1648
1649         if (omap8250_lost_context(up))
1650                 omap8250_restore_regs(up);
1651
1652         if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2))
1653                 omap_8250_rx_dma(up);
1654
1655         priv->latency = priv->calc_latency;
1656         schedule_work(&priv->qos_work);
1657         return 0;
1658 }
1659 #endif
1660
1661 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1662 static int __init omap8250_console_fixup(void)
1663 {
1664         char *omap_str;
1665         char *options;
1666         u8 idx;
1667
1668         if (strstr(boot_command_line, "console=ttyS"))
1669                 /* user set a ttyS based name for the console */
1670                 return 0;
1671
1672         omap_str = strstr(boot_command_line, "console=ttyO");
1673         if (!omap_str)
1674                 /* user did not set ttyO based console, so we don't care */
1675                 return 0;
1676
1677         omap_str += 12;
1678         if ('0' <= *omap_str && *omap_str <= '9')
1679                 idx = *omap_str - '0';
1680         else
1681                 return 0;
1682
1683         omap_str++;
1684         if (omap_str[0] == ',') {
1685                 omap_str++;
1686                 options = omap_str;
1687         } else {
1688                 options = NULL;
1689         }
1690
1691         add_preferred_console("ttyS", idx, options);
1692         pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1693                idx, idx);
1694         pr_err("This ensures that you still see kernel messages. Please\n");
1695         pr_err("update your kernel commandline.\n");
1696         return 0;
1697 }
1698 console_initcall(omap8250_console_fixup);
1699 #endif
1700
1701 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1702         SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1703         SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1704                            omap8250_runtime_resume, NULL)
1705         .prepare        = omap8250_prepare,
1706         .complete       = omap8250_complete,
1707 };
1708
1709 static struct platform_driver omap8250_platform_driver = {
1710         .driver = {
1711                 .name           = "omap8250",
1712                 .pm             = &omap8250_dev_pm_ops,
1713                 .of_match_table = omap8250_dt_ids,
1714         },
1715         .probe                  = omap8250_probe,
1716         .remove                 = omap8250_remove,
1717 };
1718 module_platform_driver(omap8250_platform_driver);
1719
1720 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1721 MODULE_DESCRIPTION("OMAP 8250 Driver");
1722 MODULE_LICENSE("GPL v2");