2 * 8250-core based driver for the OMAP internal UART
4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 * Copyright (C) 2014 Sebastian Andrzej Siewior
10 #include <linux/device.h>
12 #include <linux/module.h>
13 #include <linux/serial_8250.h>
14 #include <linux/serial_reg.h>
15 #include <linux/tty_flip.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_irq.h>
22 #include <linux/delay.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/console.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_wakeirq.h>
27 #include <linux/dma-mapping.h>
31 #define DEFAULT_CLK_SPEED 48000000
33 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
34 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
35 #define OMAP_DMA_TX_KICK (1 << 2)
37 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
38 * The same errata is applicable to AM335x and DRA7x processors too.
40 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
42 #define OMAP_UART_FCR_RX_TRIG 6
43 #define OMAP_UART_FCR_TX_TRIG 4
45 /* SCR register bitmasks */
46 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
47 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
48 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
49 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
50 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
51 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
53 /* MVR register bitmasks */
54 #define OMAP_UART_MVR_SCHEME_SHIFT 30
55 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
56 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
57 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
58 #define OMAP_UART_MVR_MAJ_MASK 0x700
59 #define OMAP_UART_MVR_MAJ_SHIFT 8
60 #define OMAP_UART_MVR_MIN_MASK 0x3f
62 /* SYSC register bitmasks */
63 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
65 /* SYSS register bitmasks */
66 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
68 #define UART_TI752_TLR_TX 0
69 #define UART_TI752_TLR_RX 4
71 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
72 #define TRIGGER_FCR_MASK(x) (x & 3)
74 /* Enable XON/XOFF flow control on output */
75 #define OMAP_UART_SW_TX 0x08
76 /* Enable XON/XOFF flow control on input */
77 #define OMAP_UART_SW_RX 0x02
79 #define OMAP_UART_WER_MOD_WKUP 0x7f
80 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
85 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
86 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
88 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
90 #define OMAP_UART_REV_46 0x0406
91 #define OMAP_UART_REV_52 0x0502
92 #define OMAP_UART_REV_63 0x0603
94 struct omap8250_priv {
111 struct pm_qos_request pm_qos_request;
112 struct work_struct qos_work;
113 struct uart_8250_dma omap8250_dma;
114 spinlock_t rx_dma_lock;
118 #ifdef CONFIG_SERIAL_8250_DMA
119 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
121 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
124 static u32 uart_read(struct uart_8250_port *up, u32 reg)
126 return readl(up->port.membase + (reg << up->port.regshift));
129 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
131 struct uart_8250_port *up = up_to_u8250p(port);
132 struct omap8250_priv *priv = up->port.private_data;
135 serial8250_do_set_mctrl(port, mctrl);
138 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
141 lcr = serial_in(up, UART_LCR);
142 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
143 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
144 priv->efr |= UART_EFR_RTS;
146 priv->efr &= ~UART_EFR_RTS;
147 serial_out(up, UART_EFR, priv->efr);
148 serial_out(up, UART_LCR, lcr);
152 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
153 * The access to uart register after MDR1 Access
154 * causes UART to corrupt data.
157 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
158 * give 10 times as much
160 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
161 struct omap8250_priv *priv)
163 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
165 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
166 UART_FCR_CLEAR_RCVR);
169 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
170 struct omap8250_priv *priv)
172 unsigned int uartclk = port->uartclk;
173 unsigned int div_13, div_16;
174 unsigned int abs_d13, abs_d16;
177 * Old custom speed handling.
179 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
180 priv->quot = port->custom_divisor & 0xffff;
182 * I assume that nobody is using this. But hey, if somebody
183 * would like to specify the divisor _and_ the mode then the
184 * driver is ready and waiting for it.
186 if (port->custom_divisor & (1 << 16))
187 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
189 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
192 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
193 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
200 abs_d13 = abs(baud - uartclk / 13 / div_13);
201 abs_d16 = abs(baud - uartclk / 16 / div_16);
203 if (abs_d13 >= abs_d16) {
204 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
207 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
212 static void omap8250_update_scr(struct uart_8250_port *up,
213 struct omap8250_priv *priv)
217 old_scr = serial_in(up, UART_OMAP_SCR);
218 if (old_scr == priv->scr)
222 * The manual recommends not to enable the DMA mode selector in the SCR
223 * (instead of the FCR) register _and_ selecting the DMA mode as one
224 * register write because this may lead to malfunction.
226 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
227 serial_out(up, UART_OMAP_SCR,
228 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
229 serial_out(up, UART_OMAP_SCR, priv->scr);
232 static void omap8250_update_mdr1(struct uart_8250_port *up,
233 struct omap8250_priv *priv)
235 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
236 omap_8250_mdr1_errataset(up, priv);
238 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
241 static void omap8250_restore_regs(struct uart_8250_port *up)
243 struct omap8250_priv *priv = up->port.private_data;
244 struct uart_8250_dma *dma = up->dma;
245 u8 mcr = serial8250_in_MCR(up);
247 if (dma && dma->tx_running) {
249 * TCSANOW requests the change to occur immediately however if
250 * we have a TX-DMA operation in progress then it has been
251 * observed that it might stall and never complete. Therefore we
252 * delay DMA completes to prevent this hang from happen.
254 priv->delayed_restore = 1;
258 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
259 serial_out(up, UART_EFR, UART_EFR_ECB);
261 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
262 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
263 serial_out(up, UART_FCR, up->fcr);
265 omap8250_update_scr(up, priv);
267 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
269 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
270 OMAP_UART_TCR_HALT(52));
271 serial_out(up, UART_TI752_TLR,
272 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
273 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
275 serial_out(up, UART_LCR, 0);
277 /* drop TCR + TLR access, we setup XON/XOFF later */
278 serial8250_out_MCR(up, mcr);
280 serial_out(up, UART_IER, up->ier);
282 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
283 serial_dl_write(up, priv->quot);
285 serial_out(up, UART_EFR, priv->efr);
287 /* Configure flow control */
288 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
289 serial_out(up, UART_XON1, priv->xon);
290 serial_out(up, UART_XOFF1, priv->xoff);
292 serial_out(up, UART_LCR, up->lcr);
294 omap8250_update_mdr1(up, priv);
296 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
300 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
301 * some differences in how we want to handle flow control.
303 static void omap_8250_set_termios(struct uart_port *port,
304 struct ktermios *termios,
305 struct ktermios *old)
307 struct uart_8250_port *up = up_to_u8250p(port);
308 struct omap8250_priv *priv = up->port.private_data;
309 unsigned char cval = 0;
312 switch (termios->c_cflag & CSIZE) {
314 cval = UART_LCR_WLEN5;
317 cval = UART_LCR_WLEN6;
320 cval = UART_LCR_WLEN7;
324 cval = UART_LCR_WLEN8;
328 if (termios->c_cflag & CSTOPB)
329 cval |= UART_LCR_STOP;
330 if (termios->c_cflag & PARENB)
331 cval |= UART_LCR_PARITY;
332 if (!(termios->c_cflag & PARODD))
333 cval |= UART_LCR_EPAR;
334 if (termios->c_cflag & CMSPAR)
335 cval |= UART_LCR_SPAR;
338 * Ask the core to calculate the divisor for us.
340 baud = uart_get_baud_rate(port, termios, old,
341 port->uartclk / 16 / 0xffff,
343 omap_8250_get_divisor(port, baud, priv);
346 * Ok, we're now changing the port state. Do it with
347 * interrupts disabled.
349 pm_runtime_get_sync(port->dev);
350 spin_lock_irq(&port->lock);
353 * Update the per-port timeout.
355 uart_update_timeout(port, termios->c_cflag, baud);
357 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
358 if (termios->c_iflag & INPCK)
359 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
360 if (termios->c_iflag & (IGNBRK | PARMRK))
361 up->port.read_status_mask |= UART_LSR_BI;
364 * Characters to ignore
366 up->port.ignore_status_mask = 0;
367 if (termios->c_iflag & IGNPAR)
368 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
369 if (termios->c_iflag & IGNBRK) {
370 up->port.ignore_status_mask |= UART_LSR_BI;
372 * If we're ignoring parity and break indicators,
373 * ignore overruns too (for real raw support).
375 if (termios->c_iflag & IGNPAR)
376 up->port.ignore_status_mask |= UART_LSR_OE;
380 * ignore all characters if CREAD is not set
382 if ((termios->c_cflag & CREAD) == 0)
383 up->port.ignore_status_mask |= UART_LSR_DR;
386 * Modem status interrupts
388 up->ier &= ~UART_IER_MSI;
389 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
390 up->ier |= UART_IER_MSI;
393 /* Up to here it was mostly serial8250_do_set_termios() */
396 * We enable TRIG_GRANU for RX and TX and additionaly we set
397 * SCR_TX_EMPTY bit. The result is the following:
398 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
399 * - less than RX_TRIGGER number of bytes will also cause an interrupt
400 * once the UART decides that there no new bytes arriving.
401 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
402 * empty - the trigger level is ignored here.
404 * Once DMA is enabled:
405 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
406 * bytes in the TX FIFO. On each assert the DMA engine will move
407 * TX_TRIGGER bytes into the FIFO.
408 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
409 * the FIFO and move RX_TRIGGER bytes.
410 * This is because threshold and trigger values are the same.
412 up->fcr = UART_FCR_ENABLE_FIFO;
413 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
414 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
416 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
417 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
420 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
421 OMAP_UART_SCR_DMAMODE_CTL;
423 priv->xon = termios->c_cc[VSTART];
424 priv->xoff = termios->c_cc[VSTOP];
427 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
429 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
430 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
431 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
432 priv->efr |= UART_EFR_CTS;
433 } else if (up->port.flags & UPF_SOFT_FLOW) {
435 * OMAP rx s/w flow control is borked; the transmitter remains
436 * stuck off even if rx flow control is subsequently disabled
441 * Enable XON/XOFF flow control on output.
442 * Transmit XON1, XOFF1
444 if (termios->c_iflag & IXOFF) {
445 up->port.status |= UPSTAT_AUTOXOFF;
446 priv->efr |= OMAP_UART_SW_TX;
449 omap8250_restore_regs(up);
451 spin_unlock_irq(&up->port.lock);
452 pm_runtime_mark_last_busy(port->dev);
453 pm_runtime_put_autosuspend(port->dev);
455 /* calculate wakeup latency constraint */
456 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
457 priv->latency = priv->calc_latency;
459 schedule_work(&priv->qos_work);
461 /* Don't rewrite B0 */
462 if (tty_termios_baud_rate(termios))
463 tty_termios_encode_baud_rate(termios, baud, baud);
466 /* same as 8250 except that we may have extra flow bits set in EFR */
467 static void omap_8250_pm(struct uart_port *port, unsigned int state,
468 unsigned int oldstate)
470 struct uart_8250_port *up = up_to_u8250p(port);
473 pm_runtime_get_sync(port->dev);
474 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
475 efr = serial_in(up, UART_EFR);
476 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
477 serial_out(up, UART_LCR, 0);
479 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
480 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
481 serial_out(up, UART_EFR, efr);
482 serial_out(up, UART_LCR, 0);
484 pm_runtime_mark_last_busy(port->dev);
485 pm_runtime_put_autosuspend(port->dev);
488 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
489 struct omap8250_priv *priv)
492 u16 revision, major, minor;
494 mvr = uart_read(up, UART_OMAP_MVER);
496 /* Check revision register scheme */
497 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
500 case 0: /* Legacy Scheme: OMAP2/3 */
501 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
502 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
503 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
504 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
507 /* New Scheme: OMAP4+ */
508 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
509 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
510 OMAP_UART_MVR_MAJ_SHIFT;
511 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
514 dev_warn(up->port.dev,
515 "Unknown revision, defaulting to highest\n");
516 /* highest possible revision */
520 /* normalize revision for the driver */
521 revision = UART_BUILD_REVISION(major, minor);
524 case OMAP_UART_REV_46:
525 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
527 case OMAP_UART_REV_52:
528 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
529 OMAP_UART_WER_HAS_TX_WAKEUP;
531 case OMAP_UART_REV_63:
532 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
533 OMAP_UART_WER_HAS_TX_WAKEUP;
540 static void omap8250_uart_qos_work(struct work_struct *work)
542 struct omap8250_priv *priv;
544 priv = container_of(work, struct omap8250_priv, qos_work);
545 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
548 #ifdef CONFIG_SERIAL_8250_DMA
549 static int omap_8250_dma_handle_irq(struct uart_port *port);
552 static irqreturn_t omap8250_irq(int irq, void *dev_id)
554 struct uart_port *port = dev_id;
555 struct uart_8250_port *up = up_to_u8250p(port);
559 #ifdef CONFIG_SERIAL_8250_DMA
561 ret = omap_8250_dma_handle_irq(port);
562 return IRQ_RETVAL(ret);
566 serial8250_rpm_get(up);
567 iir = serial_port_in(port, UART_IIR);
568 ret = serial8250_handle_irq(port, iir);
569 serial8250_rpm_put(up);
571 return IRQ_RETVAL(ret);
574 static int omap_8250_startup(struct uart_port *port)
576 struct uart_8250_port *up = up_to_u8250p(port);
577 struct omap8250_priv *priv = port->private_data;
581 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
586 pm_runtime_get_sync(port->dev);
588 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
590 serial_out(up, UART_LCR, UART_LCR_WLEN8);
592 up->lsr_saved_flags = 0;
593 up->msr_saved_flags = 0;
595 /* Disable DMA for console UART */
596 if (uart_console(port))
600 ret = serial8250_request_dma(up);
602 dev_warn_ratelimited(port->dev,
603 "failed to request DMA\n");
608 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
609 dev_name(port->dev), port);
613 up->ier = UART_IER_RLSI | UART_IER_RDI;
614 serial_out(up, UART_IER, up->ier);
617 up->capabilities |= UART_CAP_RPM;
620 /* Enable module level wake up */
621 priv->wer = OMAP_UART_WER_MOD_WKUP;
622 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
623 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
624 serial_out(up, UART_OMAP_WER, priv->wer);
629 pm_runtime_mark_last_busy(port->dev);
630 pm_runtime_put_autosuspend(port->dev);
633 pm_runtime_mark_last_busy(port->dev);
634 pm_runtime_put_autosuspend(port->dev);
635 dev_pm_clear_wake_irq(port->dev);
639 static void omap_8250_shutdown(struct uart_port *port)
641 struct uart_8250_port *up = up_to_u8250p(port);
642 struct omap8250_priv *priv = port->private_data;
644 flush_work(&priv->qos_work);
646 omap_8250_rx_dma_flush(up);
648 pm_runtime_get_sync(port->dev);
650 serial_out(up, UART_OMAP_WER, 0);
653 serial_out(up, UART_IER, 0);
656 serial8250_release_dma(up);
659 * Disable break condition and FIFOs
661 if (up->lcr & UART_LCR_SBC)
662 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
663 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
665 pm_runtime_mark_last_busy(port->dev);
666 pm_runtime_put_autosuspend(port->dev);
667 free_irq(port->irq, port);
668 dev_pm_clear_wake_irq(port->dev);
671 static void omap_8250_throttle(struct uart_port *port)
673 struct uart_8250_port *up = up_to_u8250p(port);
676 pm_runtime_get_sync(port->dev);
678 spin_lock_irqsave(&port->lock, flags);
679 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
680 serial_out(up, UART_IER, up->ier);
681 spin_unlock_irqrestore(&port->lock, flags);
683 pm_runtime_mark_last_busy(port->dev);
684 pm_runtime_put_autosuspend(port->dev);
687 static int omap_8250_rs485_config(struct uart_port *port,
688 struct serial_rs485 *rs485)
690 struct uart_8250_port *up = up_to_u8250p(port);
692 /* Clamp the delays to [0, 100ms] */
693 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
694 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
696 port->rs485 = *rs485;
699 * Both serial8250_em485_init and serial8250_em485_destroy
702 if (rs485->flags & SER_RS485_ENABLED) {
703 int ret = serial8250_em485_init(up);
706 rs485->flags &= ~SER_RS485_ENABLED;
707 port->rs485.flags &= ~SER_RS485_ENABLED;
712 serial8250_em485_destroy(up);
717 static void omap_8250_unthrottle(struct uart_port *port)
719 struct uart_8250_port *up = up_to_u8250p(port);
722 pm_runtime_get_sync(port->dev);
724 spin_lock_irqsave(&port->lock, flags);
725 up->ier |= UART_IER_RLSI | UART_IER_RDI;
726 serial_out(up, UART_IER, up->ier);
727 spin_unlock_irqrestore(&port->lock, flags);
729 pm_runtime_mark_last_busy(port->dev);
730 pm_runtime_put_autosuspend(port->dev);
733 #ifdef CONFIG_SERIAL_8250_DMA
734 static int omap_8250_rx_dma(struct uart_8250_port *p);
736 static void __dma_rx_do_complete(struct uart_8250_port *p)
738 struct omap8250_priv *priv = p->port.private_data;
739 struct uart_8250_dma *dma = p->dma;
740 struct tty_port *tty_port = &p->port.state->port;
741 struct dma_tx_state state;
746 spin_lock_irqsave(&priv->rx_dma_lock, flags);
748 if (!dma->rx_running)
752 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
754 count = dma->rx_size - state.residue;
755 if (count < dma->rx_size)
756 dmaengine_terminate_async(dma->rxchan);
759 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
761 p->port.icount.rx += ret;
762 p->port.icount.buf_overrun += count - ret;
764 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
766 tty_flip_buffer_push(tty_port);
769 static void __dma_rx_complete(void *param)
771 struct uart_8250_port *p = param;
772 struct uart_8250_dma *dma = p->dma;
773 struct dma_tx_state state;
776 spin_lock_irqsave(&p->port.lock, flags);
779 * If the tx status is not DMA_COMPLETE, then this is a delayed
780 * completion callback. A previous RX timeout flush would have
781 * already pushed the data, so exit.
783 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
785 spin_unlock_irqrestore(&p->port.lock, flags);
788 __dma_rx_do_complete(p);
791 spin_unlock_irqrestore(&p->port.lock, flags);
794 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
796 struct omap8250_priv *priv = p->port.private_data;
797 struct uart_8250_dma *dma = p->dma;
798 struct dma_tx_state state;
802 spin_lock_irqsave(&priv->rx_dma_lock, flags);
804 if (!dma->rx_running) {
805 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
809 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
810 if (ret == DMA_IN_PROGRESS) {
811 ret = dmaengine_pause(dma->rxchan);
812 if (WARN_ON_ONCE(ret))
813 priv->rx_dma_broken = true;
815 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
817 __dma_rx_do_complete(p);
820 static int omap_8250_rx_dma(struct uart_8250_port *p)
822 struct omap8250_priv *priv = p->port.private_data;
823 struct uart_8250_dma *dma = p->dma;
825 struct dma_async_tx_descriptor *desc;
828 if (priv->rx_dma_broken)
831 spin_lock_irqsave(&priv->rx_dma_lock, flags);
836 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
837 dma->rx_size, DMA_DEV_TO_MEM,
838 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
845 desc->callback = __dma_rx_complete;
846 desc->callback_param = p;
848 dma->rx_cookie = dmaengine_submit(desc);
850 dma_async_issue_pending(dma->rxchan);
852 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
856 static int omap_8250_tx_dma(struct uart_8250_port *p);
858 static void omap_8250_dma_tx_complete(void *param)
860 struct uart_8250_port *p = param;
861 struct uart_8250_dma *dma = p->dma;
862 struct circ_buf *xmit = &p->port.state->xmit;
864 bool en_thri = false;
865 struct omap8250_priv *priv = p->port.private_data;
867 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
868 UART_XMIT_SIZE, DMA_TO_DEVICE);
870 spin_lock_irqsave(&p->port.lock, flags);
874 xmit->tail += dma->tx_size;
875 xmit->tail &= UART_XMIT_SIZE - 1;
876 p->port.icount.tx += dma->tx_size;
878 if (priv->delayed_restore) {
879 priv->delayed_restore = 0;
880 omap8250_restore_regs(p);
883 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
884 uart_write_wakeup(&p->port);
886 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
889 ret = omap_8250_tx_dma(p);
893 } else if (p->capabilities & UART_CAP_RPM) {
899 p->ier |= UART_IER_THRI;
900 serial_port_out(&p->port, UART_IER, p->ier);
903 spin_unlock_irqrestore(&p->port.lock, flags);
906 static int omap_8250_tx_dma(struct uart_8250_port *p)
908 struct uart_8250_dma *dma = p->dma;
909 struct omap8250_priv *priv = p->port.private_data;
910 struct circ_buf *xmit = &p->port.state->xmit;
911 struct dma_async_tx_descriptor *desc;
912 unsigned int skip_byte = 0;
917 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
920 * Even if no data, we need to return an error for the two cases
921 * below so serial8250_tx_chars() is invoked and properly clears
922 * THRI and/or runtime suspend.
924 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
928 if (p->ier & UART_IER_THRI) {
929 p->ier &= ~UART_IER_THRI;
930 serial_out(p, UART_IER, p->ier);
935 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
936 if (priv->habit & OMAP_DMA_TX_KICK) {
940 * We need to put the first byte into the FIFO in order to start
941 * the DMA transfer. For transfers smaller than four bytes we
942 * don't bother doing DMA at all. It seem not matter if there
943 * are still bytes in the FIFO from the last transfer (in case
944 * we got here directly from omap_8250_dma_tx_complete()). Bytes
945 * leaving the FIFO seem not to trigger the DMA transfer. It is
946 * really the byte that we put into the FIFO.
947 * If the FIFO is already full then we most likely got here from
948 * omap_8250_dma_tx_complete(). And this means the DMA engine
949 * just completed its work. We don't have to wait the complete
950 * 86us at 115200,8n1 but around 60us (not to mention lower
951 * baudrates). So in that case we take the interrupt and try
952 * again with an empty FIFO.
954 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
955 if (tx_lvl == p->tx_loadsz) {
959 if (dma->tx_size < 4) {
966 desc = dmaengine_prep_slave_single(dma->txchan,
967 dma->tx_addr + xmit->tail + skip_byte,
968 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
969 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
977 desc->callback = omap_8250_dma_tx_complete;
978 desc->callback_param = p;
980 dma->tx_cookie = dmaengine_submit(desc);
982 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
983 UART_XMIT_SIZE, DMA_TO_DEVICE);
985 dma_async_issue_pending(dma->txchan);
989 if (p->ier & UART_IER_THRI) {
990 p->ier &= ~UART_IER_THRI;
991 serial_out(p, UART_IER, p->ier);
994 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1001 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1003 switch (iir & 0x3f) {
1005 case UART_IIR_RX_TIMEOUT:
1007 omap_8250_rx_dma_flush(up);
1010 return omap_8250_rx_dma(up);
1014 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1015 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1016 * use the default routine in the non-DMA case and this one for with DMA.
1018 static int omap_8250_dma_handle_irq(struct uart_port *port)
1020 struct uart_8250_port *up = up_to_u8250p(port);
1021 unsigned char status;
1022 unsigned long flags;
1025 serial8250_rpm_get(up);
1027 iir = serial_port_in(port, UART_IIR);
1028 if (iir & UART_IIR_NO_INT) {
1029 serial8250_rpm_put(up);
1033 spin_lock_irqsave(&port->lock, flags);
1035 status = serial_port_in(port, UART_LSR);
1037 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1038 if (handle_rx_dma(up, iir)) {
1039 status = serial8250_rx_chars(up, status);
1040 omap_8250_rx_dma(up);
1043 serial8250_modem_status(up);
1044 if (status & UART_LSR_THRE && up->dma->tx_err) {
1045 if (uart_tx_stopped(&up->port) ||
1046 uart_circ_empty(&up->port.state->xmit)) {
1047 up->dma->tx_err = 0;
1048 serial8250_tx_chars(up);
1051 * try again due to an earlier failer which
1052 * might have been resolved by now.
1054 if (omap_8250_tx_dma(up))
1055 serial8250_tx_chars(up);
1059 spin_unlock_irqrestore(&port->lock, flags);
1060 serial8250_rpm_put(up);
1064 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1071 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1077 static int omap8250_no_handle_irq(struct uart_port *port)
1079 /* IRQ has not been requested but handling irq? */
1080 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1084 static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE;
1085 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1086 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1088 static const struct of_device_id omap8250_dt_ids[] = {
1089 { .compatible = "ti,omap2-uart" },
1090 { .compatible = "ti,omap3-uart" },
1091 { .compatible = "ti,omap4-uart", .data = &omap4_habit, },
1092 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1093 { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1094 { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1097 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1099 static int omap8250_probe(struct platform_device *pdev)
1101 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1103 struct omap8250_priv *priv;
1104 struct uart_8250_port up;
1106 void __iomem *membase;
1108 if (!regs || !irq) {
1109 dev_err(&pdev->dev, "missing registers or irq\n");
1113 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1117 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1118 resource_size(regs));
1122 memset(&up, 0, sizeof(up));
1123 up.port.dev = &pdev->dev;
1124 up.port.mapbase = regs->start;
1125 up.port.membase = membase;
1126 up.port.irq = irq->start;
1128 * It claims to be 16C750 compatible however it is a little different.
1129 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1130 * have) is enabled via EFR instead of MCR. The type is set here 8250
1131 * just to get things going. UNKNOWN does not work for a few reasons and
1132 * we don't need our own type since we don't use 8250's set_termios()
1135 up.port.type = PORT_8250;
1136 up.port.iotype = UPIO_MEM;
1137 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1139 up.port.private_data = priv;
1141 up.port.regshift = 2;
1142 up.port.fifosize = 64;
1144 up.capabilities = UART_CAP_FIFO;
1147 * Runtime PM is mostly transparent. However to do it right we need to a
1148 * TX empty interrupt before we can put the device to auto idle. So if
1149 * PM is not enabled we don't add that flag and can spare that one extra
1150 * interrupt in the TX path.
1152 up.capabilities |= UART_CAP_RPM;
1154 up.port.set_termios = omap_8250_set_termios;
1155 up.port.set_mctrl = omap8250_set_mctrl;
1156 up.port.pm = omap_8250_pm;
1157 up.port.startup = omap_8250_startup;
1158 up.port.shutdown = omap_8250_shutdown;
1159 up.port.throttle = omap_8250_throttle;
1160 up.port.unthrottle = omap_8250_unthrottle;
1161 up.port.rs485_config = omap_8250_rs485_config;
1163 if (pdev->dev.of_node) {
1164 const struct of_device_id *id;
1166 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1168 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1170 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1172 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1174 priv->habit |= *(u8 *)id->data;
1179 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1184 if (!up.port.uartclk) {
1185 up.port.uartclk = DEFAULT_CLK_SPEED;
1186 dev_warn(&pdev->dev,
1187 "No clock speed specified: using default: %d\n",
1191 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1192 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1193 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1195 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1197 spin_lock_init(&priv->rx_dma_lock);
1199 device_init_wakeup(&pdev->dev, true);
1200 pm_runtime_enable(&pdev->dev);
1201 pm_runtime_use_autosuspend(&pdev->dev);
1202 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1204 pm_runtime_irq_safe(&pdev->dev);
1206 pm_runtime_get_sync(&pdev->dev);
1208 omap_serial_fill_features_erratas(&up, priv);
1209 up.port.handle_irq = omap8250_no_handle_irq;
1210 #ifdef CONFIG_SERIAL_8250_DMA
1211 if (pdev->dev.of_node) {
1213 * Oh DMA support. If there are no DMA properties in the DT then
1214 * we will fall back to a generic DMA channel which does not
1215 * really work here. To ensure that we do not get a generic DMA
1216 * channel assigned, we have the the_no_dma_filter_fn() here.
1217 * To avoid "failed to request DMA" messages we check for DMA
1220 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1222 up.dma = &priv->omap8250_dma;
1223 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1224 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1225 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1226 priv->omap8250_dma.rx_size = RX_TRIGGER;
1227 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1228 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1232 ret = serial8250_register_8250_port(&up);
1234 dev_err(&pdev->dev, "unable to register 8250 port\n");
1238 platform_set_drvdata(pdev, priv);
1239 pm_runtime_mark_last_busy(&pdev->dev);
1240 pm_runtime_put_autosuspend(&pdev->dev);
1243 pm_runtime_dont_use_autosuspend(&pdev->dev);
1244 pm_runtime_put_sync(&pdev->dev);
1245 pm_runtime_disable(&pdev->dev);
1249 static int omap8250_remove(struct platform_device *pdev)
1251 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1253 pm_runtime_dont_use_autosuspend(&pdev->dev);
1254 pm_runtime_put_sync(&pdev->dev);
1255 flush_work(&priv->qos_work);
1256 pm_runtime_disable(&pdev->dev);
1257 serial8250_unregister_port(priv->line);
1258 pm_qos_remove_request(&priv->pm_qos_request);
1259 device_init_wakeup(&pdev->dev, false);
1263 #ifdef CONFIG_PM_SLEEP
1264 static int omap8250_prepare(struct device *dev)
1266 struct omap8250_priv *priv = dev_get_drvdata(dev);
1270 priv->is_suspending = true;
1274 static void omap8250_complete(struct device *dev)
1276 struct omap8250_priv *priv = dev_get_drvdata(dev);
1280 priv->is_suspending = false;
1283 static int omap8250_suspend(struct device *dev)
1285 struct omap8250_priv *priv = dev_get_drvdata(dev);
1287 serial8250_suspend_port(priv->line);
1288 flush_work(&priv->qos_work);
1292 static int omap8250_resume(struct device *dev)
1294 struct omap8250_priv *priv = dev_get_drvdata(dev);
1296 serial8250_resume_port(priv->line);
1300 #define omap8250_prepare NULL
1301 #define omap8250_complete NULL
1305 static int omap8250_lost_context(struct uart_8250_port *up)
1309 val = serial_in(up, UART_OMAP_SCR);
1311 * If we lose context, then SCR is set to its reset value of zero.
1312 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1313 * among other bits, to never set the register back to zero again.
1320 /* TODO: in future, this should happen via API in drivers/reset/ */
1321 static int omap8250_soft_reset(struct device *dev)
1323 struct omap8250_priv *priv = dev_get_drvdata(dev);
1324 struct uart_8250_port *up = serial8250_get_port(priv->line);
1330 * At least on omap4, unused uarts may not idle after reset without
1331 * a basic scr dma configuration even with no dma in use. The
1332 * module clkctrl status bits will be 1 instead of 3 blocking idle
1333 * for the whole clockdomain. The softreset below will clear scr,
1334 * and we restore it on resume so this is safe to do on all SoCs
1335 * needing omap8250_soft_reset() quirk. Do it in two writes as
1336 * recommended in the comment for omap8250_update_scr().
1338 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1339 serial_out(up, UART_OMAP_SCR,
1340 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1342 sysc = serial_in(up, UART_OMAP_SYSC);
1344 /* softreset the UART */
1345 sysc |= OMAP_UART_SYSC_SOFTRESET;
1346 serial_out(up, UART_OMAP_SYSC, sysc);
1348 /* By experiments, 1us enough for reset complete on AM335x */
1351 syss = serial_in(up, UART_OMAP_SYSS);
1352 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1355 dev_err(dev, "timed out waiting for reset done\n");
1362 static int omap8250_runtime_suspend(struct device *dev)
1364 struct omap8250_priv *priv = dev_get_drvdata(dev);
1365 struct uart_8250_port *up;
1367 /* In case runtime-pm tries this before we are setup */
1371 up = serial8250_get_port(priv->line);
1373 * When using 'no_console_suspend', the console UART must not be
1374 * suspended. Since driver suspend is managed by runtime suspend,
1375 * preventing runtime suspend (by returning error) will keep device
1376 * active during suspend.
1378 if (priv->is_suspending && !console_suspend_enabled) {
1379 if (uart_console(&up->port))
1383 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1386 ret = omap8250_soft_reset(dev);
1390 /* Restore to UART mode after reset (for wakeup) */
1391 omap8250_update_mdr1(up, priv);
1394 if (up->dma && up->dma->rxchan)
1395 omap_8250_rx_dma_flush(up);
1397 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1398 schedule_work(&priv->qos_work);
1403 static int omap8250_runtime_resume(struct device *dev)
1405 struct omap8250_priv *priv = dev_get_drvdata(dev);
1406 struct uart_8250_port *up;
1408 /* In case runtime-pm tries this before we are setup */
1412 up = serial8250_get_port(priv->line);
1414 if (omap8250_lost_context(up))
1415 omap8250_restore_regs(up);
1417 if (up->dma && up->dma->rxchan)
1418 omap_8250_rx_dma(up);
1420 priv->latency = priv->calc_latency;
1421 schedule_work(&priv->qos_work);
1426 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1427 static int __init omap8250_console_fixup(void)
1433 if (strstr(boot_command_line, "console=ttyS"))
1434 /* user set a ttyS based name for the console */
1437 omap_str = strstr(boot_command_line, "console=ttyO");
1439 /* user did not set ttyO based console, so we don't care */
1443 if ('0' <= *omap_str && *omap_str <= '9')
1444 idx = *omap_str - '0';
1449 if (omap_str[0] == ',') {
1456 add_preferred_console("ttyS", idx, options);
1457 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1459 pr_err("This ensures that you still see kernel messages. Please\n");
1460 pr_err("update your kernel commandline.\n");
1463 console_initcall(omap8250_console_fixup);
1466 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1467 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1468 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1469 omap8250_runtime_resume, NULL)
1470 .prepare = omap8250_prepare,
1471 .complete = omap8250_complete,
1474 static struct platform_driver omap8250_platform_driver = {
1477 .pm = &omap8250_dev_pm_ops,
1478 .of_match_table = omap8250_dt_ids,
1480 .probe = omap8250_probe,
1481 .remove = omap8250_remove,
1483 module_platform_driver(omap8250_platform_driver);
1485 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1486 MODULE_DESCRIPTION("OMAP 8250 Driver");
1487 MODULE_LICENSE("GPL v2");