2 * 8250-core based driver for the OMAP internal UART
4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 * Copyright (C) 2014 Sebastian Andrzej Siewior
10 #include <linux/device.h>
12 #include <linux/module.h>
13 #include <linux/serial_8250.h>
14 #include <linux/serial_reg.h>
15 #include <linux/tty_flip.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_irq.h>
22 #include <linux/delay.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/console.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_wakeirq.h>
27 #include <linux/dma-mapping.h>
31 #define DEFAULT_CLK_SPEED 48000000
33 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
34 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
35 #define OMAP_DMA_TX_KICK (1 << 2)
37 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
38 * The same errata is applicable to AM335x and DRA7x processors too.
40 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
42 #define OMAP_UART_FCR_RX_TRIG 6
43 #define OMAP_UART_FCR_TX_TRIG 4
45 /* SCR register bitmasks */
46 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
47 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
48 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
49 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
50 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
51 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
53 /* MVR register bitmasks */
54 #define OMAP_UART_MVR_SCHEME_SHIFT 30
55 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
56 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
57 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
58 #define OMAP_UART_MVR_MAJ_MASK 0x700
59 #define OMAP_UART_MVR_MAJ_SHIFT 8
60 #define OMAP_UART_MVR_MIN_MASK 0x3f
62 /* SYSC register bitmasks */
63 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
65 /* SYSS register bitmasks */
66 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
68 #define UART_TI752_TLR_TX 0
69 #define UART_TI752_TLR_RX 4
71 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
72 #define TRIGGER_FCR_MASK(x) (x & 3)
74 /* Enable XON/XOFF flow control on output */
75 #define OMAP_UART_SW_TX 0x08
76 /* Enable XON/XOFF flow control on input */
77 #define OMAP_UART_SW_RX 0x02
79 #define OMAP_UART_WER_MOD_WKUP 0x7f
80 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
85 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
86 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
88 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
90 #define OMAP_UART_REV_46 0x0406
91 #define OMAP_UART_REV_52 0x0502
92 #define OMAP_UART_REV_63 0x0603
94 struct omap8250_priv {
111 struct pm_qos_request pm_qos_request;
112 struct work_struct qos_work;
113 struct uart_8250_dma omap8250_dma;
114 spinlock_t rx_dma_lock;
118 #ifdef CONFIG_SERIAL_8250_DMA
119 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
121 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
124 static u32 uart_read(struct uart_8250_port *up, u32 reg)
126 return readl(up->port.membase + (reg << up->port.regshift));
129 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
131 struct uart_8250_port *up = up_to_u8250p(port);
132 struct omap8250_priv *priv = up->port.private_data;
135 serial8250_do_set_mctrl(port, mctrl);
138 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
141 lcr = serial_in(up, UART_LCR);
142 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
143 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
144 priv->efr |= UART_EFR_RTS;
146 priv->efr &= ~UART_EFR_RTS;
147 serial_out(up, UART_EFR, priv->efr);
148 serial_out(up, UART_LCR, lcr);
152 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
153 * The access to uart register after MDR1 Access
154 * causes UART to corrupt data.
157 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
158 * give 10 times as much
160 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
161 struct omap8250_priv *priv)
165 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
167 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
168 UART_FCR_CLEAR_RCVR);
170 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
171 * TX_FIFO_E bit is 1.
173 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
174 (UART_LSR_THRE | UART_LSR_DR))) {
177 /* Should *never* happen. we warn and carry on */
178 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
179 serial_in(up, UART_LSR));
186 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
187 struct omap8250_priv *priv)
189 unsigned int uartclk = port->uartclk;
190 unsigned int div_13, div_16;
191 unsigned int abs_d13, abs_d16;
194 * Old custom speed handling.
196 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
197 priv->quot = port->custom_divisor & 0xffff;
199 * I assume that nobody is using this. But hey, if somebody
200 * would like to specify the divisor _and_ the mode then the
201 * driver is ready and waiting for it.
203 if (port->custom_divisor & (1 << 16))
204 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
206 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
209 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
210 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
217 abs_d13 = abs(baud - uartclk / 13 / div_13);
218 abs_d16 = abs(baud - uartclk / 16 / div_16);
220 if (abs_d13 >= abs_d16) {
221 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
224 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
229 static void omap8250_update_scr(struct uart_8250_port *up,
230 struct omap8250_priv *priv)
234 old_scr = serial_in(up, UART_OMAP_SCR);
235 if (old_scr == priv->scr)
239 * The manual recommends not to enable the DMA mode selector in the SCR
240 * (instead of the FCR) register _and_ selecting the DMA mode as one
241 * register write because this may lead to malfunction.
243 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
244 serial_out(up, UART_OMAP_SCR,
245 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
246 serial_out(up, UART_OMAP_SCR, priv->scr);
249 static void omap8250_update_mdr1(struct uart_8250_port *up,
250 struct omap8250_priv *priv)
252 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
253 omap_8250_mdr1_errataset(up, priv);
255 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
258 static void omap8250_restore_regs(struct uart_8250_port *up)
260 struct omap8250_priv *priv = up->port.private_data;
261 struct uart_8250_dma *dma = up->dma;
263 if (dma && dma->tx_running) {
265 * TCSANOW requests the change to occur immediately however if
266 * we have a TX-DMA operation in progress then it has been
267 * observed that it might stall and never complete. Therefore we
268 * delay DMA completes to prevent this hang from happen.
270 priv->delayed_restore = 1;
274 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
275 serial_out(up, UART_EFR, UART_EFR_ECB);
277 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
278 serial8250_out_MCR(up, UART_MCR_TCRTLR);
279 serial_out(up, UART_FCR, up->fcr);
281 omap8250_update_scr(up, priv);
283 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
285 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
286 OMAP_UART_TCR_HALT(52));
287 serial_out(up, UART_TI752_TLR,
288 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
289 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
291 serial_out(up, UART_LCR, 0);
293 /* drop TCR + TLR access, we setup XON/XOFF later */
294 serial8250_out_MCR(up, up->mcr);
295 serial_out(up, UART_IER, up->ier);
297 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
298 serial_dl_write(up, priv->quot);
300 serial_out(up, UART_EFR, priv->efr);
302 /* Configure flow control */
303 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
304 serial_out(up, UART_XON1, priv->xon);
305 serial_out(up, UART_XOFF1, priv->xoff);
307 serial_out(up, UART_LCR, up->lcr);
309 omap8250_update_mdr1(up, priv);
311 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
315 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
316 * some differences in how we want to handle flow control.
318 static void omap_8250_set_termios(struct uart_port *port,
319 struct ktermios *termios,
320 struct ktermios *old)
322 struct uart_8250_port *up = up_to_u8250p(port);
323 struct omap8250_priv *priv = up->port.private_data;
324 unsigned char cval = 0;
327 switch (termios->c_cflag & CSIZE) {
329 cval = UART_LCR_WLEN5;
332 cval = UART_LCR_WLEN6;
335 cval = UART_LCR_WLEN7;
339 cval = UART_LCR_WLEN8;
343 if (termios->c_cflag & CSTOPB)
344 cval |= UART_LCR_STOP;
345 if (termios->c_cflag & PARENB)
346 cval |= UART_LCR_PARITY;
347 if (!(termios->c_cflag & PARODD))
348 cval |= UART_LCR_EPAR;
349 if (termios->c_cflag & CMSPAR)
350 cval |= UART_LCR_SPAR;
353 * Ask the core to calculate the divisor for us.
355 baud = uart_get_baud_rate(port, termios, old,
356 port->uartclk / 16 / 0xffff,
358 omap_8250_get_divisor(port, baud, priv);
361 * Ok, we're now changing the port state. Do it with
362 * interrupts disabled.
364 pm_runtime_get_sync(port->dev);
365 spin_lock_irq(&port->lock);
368 * Update the per-port timeout.
370 uart_update_timeout(port, termios->c_cflag, baud);
372 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
373 if (termios->c_iflag & INPCK)
374 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
375 if (termios->c_iflag & (IGNBRK | PARMRK))
376 up->port.read_status_mask |= UART_LSR_BI;
379 * Characters to ignore
381 up->port.ignore_status_mask = 0;
382 if (termios->c_iflag & IGNPAR)
383 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
384 if (termios->c_iflag & IGNBRK) {
385 up->port.ignore_status_mask |= UART_LSR_BI;
387 * If we're ignoring parity and break indicators,
388 * ignore overruns too (for real raw support).
390 if (termios->c_iflag & IGNPAR)
391 up->port.ignore_status_mask |= UART_LSR_OE;
395 * ignore all characters if CREAD is not set
397 if ((termios->c_cflag & CREAD) == 0)
398 up->port.ignore_status_mask |= UART_LSR_DR;
401 * Modem status interrupts
403 up->ier &= ~UART_IER_MSI;
404 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
405 up->ier |= UART_IER_MSI;
408 /* Up to here it was mostly serial8250_do_set_termios() */
411 * We enable TRIG_GRANU for RX and TX and additionaly we set
412 * SCR_TX_EMPTY bit. The result is the following:
413 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
414 * - less than RX_TRIGGER number of bytes will also cause an interrupt
415 * once the UART decides that there no new bytes arriving.
416 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
417 * empty - the trigger level is ignored here.
419 * Once DMA is enabled:
420 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
421 * bytes in the TX FIFO. On each assert the DMA engine will move
422 * TX_TRIGGER bytes into the FIFO.
423 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
424 * the FIFO and move RX_TRIGGER bytes.
425 * This is because threshold and trigger values are the same.
427 up->fcr = UART_FCR_ENABLE_FIFO;
428 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
429 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
431 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
432 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
435 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
436 OMAP_UART_SCR_DMAMODE_CTL;
438 priv->xon = termios->c_cc[VSTART];
439 priv->xoff = termios->c_cc[VSTOP];
442 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
444 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
445 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
446 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
447 priv->efr |= UART_EFR_CTS;
448 } else if (up->port.flags & UPF_SOFT_FLOW) {
450 * OMAP rx s/w flow control is borked; the transmitter remains
451 * stuck off even if rx flow control is subsequently disabled
456 * Enable XON/XOFF flow control on output.
457 * Transmit XON1, XOFF1
459 if (termios->c_iflag & IXOFF) {
460 up->port.status |= UPSTAT_AUTOXOFF;
461 priv->efr |= OMAP_UART_SW_TX;
464 omap8250_restore_regs(up);
466 spin_unlock_irq(&up->port.lock);
467 pm_runtime_mark_last_busy(port->dev);
468 pm_runtime_put_autosuspend(port->dev);
470 /* calculate wakeup latency constraint */
471 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
472 priv->latency = priv->calc_latency;
474 schedule_work(&priv->qos_work);
476 /* Don't rewrite B0 */
477 if (tty_termios_baud_rate(termios))
478 tty_termios_encode_baud_rate(termios, baud, baud);
481 /* same as 8250 except that we may have extra flow bits set in EFR */
482 static void omap_8250_pm(struct uart_port *port, unsigned int state,
483 unsigned int oldstate)
485 struct uart_8250_port *up = up_to_u8250p(port);
488 pm_runtime_get_sync(port->dev);
489 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
490 efr = serial_in(up, UART_EFR);
491 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
492 serial_out(up, UART_LCR, 0);
494 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
495 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
496 serial_out(up, UART_EFR, efr);
497 serial_out(up, UART_LCR, 0);
499 pm_runtime_mark_last_busy(port->dev);
500 pm_runtime_put_autosuspend(port->dev);
503 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
504 struct omap8250_priv *priv)
507 u16 revision, major, minor;
509 mvr = uart_read(up, UART_OMAP_MVER);
511 /* Check revision register scheme */
512 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
515 case 0: /* Legacy Scheme: OMAP2/3 */
516 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
517 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
518 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
519 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
522 /* New Scheme: OMAP4+ */
523 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
524 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
525 OMAP_UART_MVR_MAJ_SHIFT;
526 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
529 dev_warn(up->port.dev,
530 "Unknown revision, defaulting to highest\n");
531 /* highest possible revision */
535 /* normalize revision for the driver */
536 revision = UART_BUILD_REVISION(major, minor);
539 case OMAP_UART_REV_46:
540 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
542 case OMAP_UART_REV_52:
543 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
544 OMAP_UART_WER_HAS_TX_WAKEUP;
546 case OMAP_UART_REV_63:
547 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
548 OMAP_UART_WER_HAS_TX_WAKEUP;
555 static void omap8250_uart_qos_work(struct work_struct *work)
557 struct omap8250_priv *priv;
559 priv = container_of(work, struct omap8250_priv, qos_work);
560 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
563 #ifdef CONFIG_SERIAL_8250_DMA
564 static int omap_8250_dma_handle_irq(struct uart_port *port);
567 static irqreturn_t omap8250_irq(int irq, void *dev_id)
569 struct uart_port *port = dev_id;
570 struct uart_8250_port *up = up_to_u8250p(port);
574 #ifdef CONFIG_SERIAL_8250_DMA
576 ret = omap_8250_dma_handle_irq(port);
577 return IRQ_RETVAL(ret);
581 serial8250_rpm_get(up);
582 iir = serial_port_in(port, UART_IIR);
583 ret = serial8250_handle_irq(port, iir);
584 serial8250_rpm_put(up);
586 return IRQ_RETVAL(ret);
589 static int omap_8250_startup(struct uart_port *port)
591 struct uart_8250_port *up = up_to_u8250p(port);
592 struct omap8250_priv *priv = port->private_data;
596 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
601 pm_runtime_get_sync(port->dev);
604 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
606 serial_out(up, UART_LCR, UART_LCR_WLEN8);
608 up->lsr_saved_flags = 0;
609 up->msr_saved_flags = 0;
611 /* Disable DMA for console UART */
612 if (uart_console(port))
616 ret = serial8250_request_dma(up);
618 dev_warn_ratelimited(port->dev,
619 "failed to request DMA\n");
624 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
625 dev_name(port->dev), port);
629 up->ier = UART_IER_RLSI | UART_IER_RDI;
630 serial_out(up, UART_IER, up->ier);
633 up->capabilities |= UART_CAP_RPM;
636 /* Enable module level wake up */
637 priv->wer = OMAP_UART_WER_MOD_WKUP;
638 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
639 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
640 serial_out(up, UART_OMAP_WER, priv->wer);
645 pm_runtime_mark_last_busy(port->dev);
646 pm_runtime_put_autosuspend(port->dev);
649 pm_runtime_mark_last_busy(port->dev);
650 pm_runtime_put_autosuspend(port->dev);
651 dev_pm_clear_wake_irq(port->dev);
655 static void omap_8250_shutdown(struct uart_port *port)
657 struct uart_8250_port *up = up_to_u8250p(port);
658 struct omap8250_priv *priv = port->private_data;
660 flush_work(&priv->qos_work);
662 omap_8250_rx_dma_flush(up);
664 pm_runtime_get_sync(port->dev);
666 serial_out(up, UART_OMAP_WER, 0);
669 serial_out(up, UART_IER, 0);
672 serial8250_release_dma(up);
675 * Disable break condition and FIFOs
677 if (up->lcr & UART_LCR_SBC)
678 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
679 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
681 pm_runtime_mark_last_busy(port->dev);
682 pm_runtime_put_autosuspend(port->dev);
683 free_irq(port->irq, port);
684 dev_pm_clear_wake_irq(port->dev);
687 static void omap_8250_throttle(struct uart_port *port)
689 struct uart_8250_port *up = up_to_u8250p(port);
692 pm_runtime_get_sync(port->dev);
694 spin_lock_irqsave(&port->lock, flags);
695 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
696 serial_out(up, UART_IER, up->ier);
697 spin_unlock_irqrestore(&port->lock, flags);
699 pm_runtime_mark_last_busy(port->dev);
700 pm_runtime_put_autosuspend(port->dev);
703 static int omap_8250_rs485_config(struct uart_port *port,
704 struct serial_rs485 *rs485)
706 struct uart_8250_port *up = up_to_u8250p(port);
708 /* Clamp the delays to [0, 100ms] */
709 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
710 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
712 port->rs485 = *rs485;
715 * Both serial8250_em485_init and serial8250_em485_destroy
718 if (rs485->flags & SER_RS485_ENABLED) {
719 int ret = serial8250_em485_init(up);
722 rs485->flags &= ~SER_RS485_ENABLED;
723 port->rs485.flags &= ~SER_RS485_ENABLED;
728 serial8250_em485_destroy(up);
733 static void omap_8250_unthrottle(struct uart_port *port)
735 struct uart_8250_port *up = up_to_u8250p(port);
738 pm_runtime_get_sync(port->dev);
740 spin_lock_irqsave(&port->lock, flags);
741 up->ier |= UART_IER_RLSI | UART_IER_RDI;
742 serial_out(up, UART_IER, up->ier);
743 spin_unlock_irqrestore(&port->lock, flags);
745 pm_runtime_mark_last_busy(port->dev);
746 pm_runtime_put_autosuspend(port->dev);
749 #ifdef CONFIG_SERIAL_8250_DMA
750 static int omap_8250_rx_dma(struct uart_8250_port *p);
752 static void __dma_rx_do_complete(struct uart_8250_port *p)
754 struct omap8250_priv *priv = p->port.private_data;
755 struct uart_8250_dma *dma = p->dma;
756 struct tty_port *tty_port = &p->port.state->port;
757 struct dma_tx_state state;
762 spin_lock_irqsave(&priv->rx_dma_lock, flags);
764 if (!dma->rx_running)
768 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
770 count = dma->rx_size - state.residue;
771 if (count < dma->rx_size)
772 dmaengine_terminate_async(dma->rxchan);
775 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
777 p->port.icount.rx += ret;
778 p->port.icount.buf_overrun += count - ret;
780 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
782 tty_flip_buffer_push(tty_port);
785 static void __dma_rx_complete(void *param)
787 __dma_rx_do_complete(param);
788 omap_8250_rx_dma(param);
791 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
793 struct omap8250_priv *priv = p->port.private_data;
794 struct uart_8250_dma *dma = p->dma;
798 spin_lock_irqsave(&priv->rx_dma_lock, flags);
800 if (!dma->rx_running) {
801 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
805 ret = dmaengine_pause(dma->rxchan);
806 if (WARN_ON_ONCE(ret))
807 priv->rx_dma_broken = true;
809 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
811 __dma_rx_do_complete(p);
814 static int omap_8250_rx_dma(struct uart_8250_port *p)
816 struct omap8250_priv *priv = p->port.private_data;
817 struct uart_8250_dma *dma = p->dma;
819 struct dma_async_tx_descriptor *desc;
822 if (priv->rx_dma_broken)
825 spin_lock_irqsave(&priv->rx_dma_lock, flags);
830 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
831 dma->rx_size, DMA_DEV_TO_MEM,
832 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
839 desc->callback = __dma_rx_complete;
840 desc->callback_param = p;
842 dma->rx_cookie = dmaengine_submit(desc);
844 dma_async_issue_pending(dma->rxchan);
846 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
850 static int omap_8250_tx_dma(struct uart_8250_port *p);
852 static void omap_8250_dma_tx_complete(void *param)
854 struct uart_8250_port *p = param;
855 struct uart_8250_dma *dma = p->dma;
856 struct circ_buf *xmit = &p->port.state->xmit;
858 bool en_thri = false;
859 struct omap8250_priv *priv = p->port.private_data;
861 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
862 UART_XMIT_SIZE, DMA_TO_DEVICE);
864 spin_lock_irqsave(&p->port.lock, flags);
868 xmit->tail += dma->tx_size;
869 xmit->tail &= UART_XMIT_SIZE - 1;
870 p->port.icount.tx += dma->tx_size;
872 if (priv->delayed_restore) {
873 priv->delayed_restore = 0;
874 omap8250_restore_regs(p);
877 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
878 uart_write_wakeup(&p->port);
880 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
883 ret = omap_8250_tx_dma(p);
887 } else if (p->capabilities & UART_CAP_RPM) {
893 p->ier |= UART_IER_THRI;
894 serial_port_out(&p->port, UART_IER, p->ier);
897 spin_unlock_irqrestore(&p->port.lock, flags);
900 static int omap_8250_tx_dma(struct uart_8250_port *p)
902 struct uart_8250_dma *dma = p->dma;
903 struct omap8250_priv *priv = p->port.private_data;
904 struct circ_buf *xmit = &p->port.state->xmit;
905 struct dma_async_tx_descriptor *desc;
906 unsigned int skip_byte = 0;
911 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
914 * Even if no data, we need to return an error for the two cases
915 * below so serial8250_tx_chars() is invoked and properly clears
916 * THRI and/or runtime suspend.
918 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
922 if (p->ier & UART_IER_THRI) {
923 p->ier &= ~UART_IER_THRI;
924 serial_out(p, UART_IER, p->ier);
929 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
930 if (priv->habit & OMAP_DMA_TX_KICK) {
934 * We need to put the first byte into the FIFO in order to start
935 * the DMA transfer. For transfers smaller than four bytes we
936 * don't bother doing DMA at all. It seem not matter if there
937 * are still bytes in the FIFO from the last transfer (in case
938 * we got here directly from omap_8250_dma_tx_complete()). Bytes
939 * leaving the FIFO seem not to trigger the DMA transfer. It is
940 * really the byte that we put into the FIFO.
941 * If the FIFO is already full then we most likely got here from
942 * omap_8250_dma_tx_complete(). And this means the DMA engine
943 * just completed its work. We don't have to wait the complete
944 * 86us at 115200,8n1 but around 60us (not to mention lower
945 * baudrates). So in that case we take the interrupt and try
946 * again with an empty FIFO.
948 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
949 if (tx_lvl == p->tx_loadsz) {
953 if (dma->tx_size < 4) {
960 desc = dmaengine_prep_slave_single(dma->txchan,
961 dma->tx_addr + xmit->tail + skip_byte,
962 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
963 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
971 desc->callback = omap_8250_dma_tx_complete;
972 desc->callback_param = p;
974 dma->tx_cookie = dmaengine_submit(desc);
976 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
977 UART_XMIT_SIZE, DMA_TO_DEVICE);
979 dma_async_issue_pending(dma->txchan);
983 if (p->ier & UART_IER_THRI) {
984 p->ier &= ~UART_IER_THRI;
985 serial_out(p, UART_IER, p->ier);
988 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
995 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
997 switch (iir & 0x3f) {
999 case UART_IIR_RX_TIMEOUT:
1001 omap_8250_rx_dma_flush(up);
1004 return omap_8250_rx_dma(up);
1008 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1009 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1010 * use the default routine in the non-DMA case and this one for with DMA.
1012 static int omap_8250_dma_handle_irq(struct uart_port *port)
1014 struct uart_8250_port *up = up_to_u8250p(port);
1015 unsigned char status;
1016 unsigned long flags;
1019 serial8250_rpm_get(up);
1021 iir = serial_port_in(port, UART_IIR);
1022 if (iir & UART_IIR_NO_INT) {
1023 serial8250_rpm_put(up);
1027 spin_lock_irqsave(&port->lock, flags);
1029 status = serial_port_in(port, UART_LSR);
1031 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1032 if (handle_rx_dma(up, iir)) {
1033 status = serial8250_rx_chars(up, status);
1034 omap_8250_rx_dma(up);
1037 serial8250_modem_status(up);
1038 if (status & UART_LSR_THRE && up->dma->tx_err) {
1039 if (uart_tx_stopped(&up->port) ||
1040 uart_circ_empty(&up->port.state->xmit)) {
1041 up->dma->tx_err = 0;
1042 serial8250_tx_chars(up);
1045 * try again due to an earlier failer which
1046 * might have been resolved by now.
1048 if (omap_8250_tx_dma(up))
1049 serial8250_tx_chars(up);
1053 spin_unlock_irqrestore(&port->lock, flags);
1054 serial8250_rpm_put(up);
1058 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1065 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1071 static int omap8250_no_handle_irq(struct uart_port *port)
1073 /* IRQ has not been requested but handling irq? */
1074 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1078 static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE;
1079 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1080 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1082 static const struct of_device_id omap8250_dt_ids[] = {
1083 { .compatible = "ti,omap2-uart" },
1084 { .compatible = "ti,omap3-uart" },
1085 { .compatible = "ti,omap4-uart", .data = &omap4_habit, },
1086 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1087 { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1088 { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1091 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1093 static int omap8250_probe(struct platform_device *pdev)
1095 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1096 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1097 struct omap8250_priv *priv;
1098 struct uart_8250_port up;
1100 void __iomem *membase;
1102 if (!regs || !irq) {
1103 dev_err(&pdev->dev, "missing registers or irq\n");
1107 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1111 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1112 resource_size(regs));
1116 memset(&up, 0, sizeof(up));
1117 up.port.dev = &pdev->dev;
1118 up.port.mapbase = regs->start;
1119 up.port.membase = membase;
1120 up.port.irq = irq->start;
1122 * It claims to be 16C750 compatible however it is a little different.
1123 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1124 * have) is enabled via EFR instead of MCR. The type is set here 8250
1125 * just to get things going. UNKNOWN does not work for a few reasons and
1126 * we don't need our own type since we don't use 8250's set_termios()
1129 up.port.type = PORT_8250;
1130 up.port.iotype = UPIO_MEM;
1131 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1133 up.port.private_data = priv;
1135 up.port.regshift = 2;
1136 up.port.fifosize = 64;
1138 up.capabilities = UART_CAP_FIFO;
1141 * Runtime PM is mostly transparent. However to do it right we need to a
1142 * TX empty interrupt before we can put the device to auto idle. So if
1143 * PM is not enabled we don't add that flag and can spare that one extra
1144 * interrupt in the TX path.
1146 up.capabilities |= UART_CAP_RPM;
1148 up.port.set_termios = omap_8250_set_termios;
1149 up.port.set_mctrl = omap8250_set_mctrl;
1150 up.port.pm = omap_8250_pm;
1151 up.port.startup = omap_8250_startup;
1152 up.port.shutdown = omap_8250_shutdown;
1153 up.port.throttle = omap_8250_throttle;
1154 up.port.unthrottle = omap_8250_unthrottle;
1155 up.port.rs485_config = omap_8250_rs485_config;
1157 if (pdev->dev.of_node) {
1158 const struct of_device_id *id;
1160 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1162 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1164 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1166 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1168 priv->habit |= *(u8 *)id->data;
1173 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1178 if (!up.port.uartclk) {
1179 up.port.uartclk = DEFAULT_CLK_SPEED;
1180 dev_warn(&pdev->dev,
1181 "No clock speed specified: using default: %d\n",
1185 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1186 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1187 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1189 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1191 spin_lock_init(&priv->rx_dma_lock);
1193 device_init_wakeup(&pdev->dev, true);
1194 pm_runtime_enable(&pdev->dev);
1195 pm_runtime_use_autosuspend(&pdev->dev);
1196 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1198 pm_runtime_irq_safe(&pdev->dev);
1200 pm_runtime_get_sync(&pdev->dev);
1202 omap_serial_fill_features_erratas(&up, priv);
1203 up.port.handle_irq = omap8250_no_handle_irq;
1204 #ifdef CONFIG_SERIAL_8250_DMA
1205 if (pdev->dev.of_node) {
1207 * Oh DMA support. If there are no DMA properties in the DT then
1208 * we will fall back to a generic DMA channel which does not
1209 * really work here. To ensure that we do not get a generic DMA
1210 * channel assigned, we have the the_no_dma_filter_fn() here.
1211 * To avoid "failed to request DMA" messages we check for DMA
1214 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1216 up.dma = &priv->omap8250_dma;
1217 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1218 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1219 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1220 priv->omap8250_dma.rx_size = RX_TRIGGER;
1221 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1222 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1224 * pause is currently not supported atleast on omap-sdma
1225 * and edma on most earlier kernels.
1227 priv->rx_dma_broken = true;
1231 ret = serial8250_register_8250_port(&up);
1233 dev_err(&pdev->dev, "unable to register 8250 port\n");
1237 platform_set_drvdata(pdev, priv);
1238 pm_runtime_mark_last_busy(&pdev->dev);
1239 pm_runtime_put_autosuspend(&pdev->dev);
1242 pm_runtime_dont_use_autosuspend(&pdev->dev);
1243 pm_runtime_put_sync(&pdev->dev);
1244 pm_runtime_disable(&pdev->dev);
1248 static int omap8250_remove(struct platform_device *pdev)
1250 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1252 pm_runtime_dont_use_autosuspend(&pdev->dev);
1253 pm_runtime_put_sync(&pdev->dev);
1254 pm_runtime_disable(&pdev->dev);
1255 serial8250_unregister_port(priv->line);
1256 pm_qos_remove_request(&priv->pm_qos_request);
1257 device_init_wakeup(&pdev->dev, false);
1261 #ifdef CONFIG_PM_SLEEP
1262 static int omap8250_prepare(struct device *dev)
1264 struct omap8250_priv *priv = dev_get_drvdata(dev);
1268 priv->is_suspending = true;
1272 static void omap8250_complete(struct device *dev)
1274 struct omap8250_priv *priv = dev_get_drvdata(dev);
1278 priv->is_suspending = false;
1281 static int omap8250_suspend(struct device *dev)
1283 struct omap8250_priv *priv = dev_get_drvdata(dev);
1285 serial8250_suspend_port(priv->line);
1286 flush_work(&priv->qos_work);
1290 static int omap8250_resume(struct device *dev)
1292 struct omap8250_priv *priv = dev_get_drvdata(dev);
1294 serial8250_resume_port(priv->line);
1298 #define omap8250_prepare NULL
1299 #define omap8250_complete NULL
1303 static int omap8250_lost_context(struct uart_8250_port *up)
1307 val = serial_in(up, UART_OMAP_SCR);
1309 * If we lose context, then SCR is set to its reset value of zero.
1310 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1311 * among other bits, to never set the register back to zero again.
1318 /* TODO: in future, this should happen via API in drivers/reset/ */
1319 static int omap8250_soft_reset(struct device *dev)
1321 struct omap8250_priv *priv = dev_get_drvdata(dev);
1322 struct uart_8250_port *up = serial8250_get_port(priv->line);
1328 * At least on omap4, unused uarts may not idle after reset without
1329 * a basic scr dma configuration even with no dma in use. The
1330 * module clkctrl status bits will be 1 instead of 3 blocking idle
1331 * for the whole clockdomain. The softreset below will clear scr,
1332 * and we restore it on resume so this is safe to do on all SoCs
1333 * needing omap8250_soft_reset() quirk. Do it in two writes as
1334 * recommended in the comment for omap8250_update_scr().
1336 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1337 serial_out(up, UART_OMAP_SCR,
1338 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1340 sysc = serial_in(up, UART_OMAP_SYSC);
1342 /* softreset the UART */
1343 sysc |= OMAP_UART_SYSC_SOFTRESET;
1344 serial_out(up, UART_OMAP_SYSC, sysc);
1346 /* By experiments, 1us enough for reset complete on AM335x */
1349 syss = serial_in(up, UART_OMAP_SYSS);
1350 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1353 dev_err(dev, "timed out waiting for reset done\n");
1360 static int omap8250_runtime_suspend(struct device *dev)
1362 struct omap8250_priv *priv = dev_get_drvdata(dev);
1363 struct uart_8250_port *up;
1365 /* In case runtime-pm tries this before we are setup */
1369 up = serial8250_get_port(priv->line);
1371 * When using 'no_console_suspend', the console UART must not be
1372 * suspended. Since driver suspend is managed by runtime suspend,
1373 * preventing runtime suspend (by returning error) will keep device
1374 * active during suspend.
1376 if (priv->is_suspending && !console_suspend_enabled) {
1377 if (uart_console(&up->port))
1381 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1384 ret = omap8250_soft_reset(dev);
1388 /* Restore to UART mode after reset (for wakeup) */
1389 omap8250_update_mdr1(up, priv);
1392 if (up->dma && up->dma->rxchan)
1393 omap_8250_rx_dma_flush(up);
1395 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1396 schedule_work(&priv->qos_work);
1401 static int omap8250_runtime_resume(struct device *dev)
1403 struct omap8250_priv *priv = dev_get_drvdata(dev);
1404 struct uart_8250_port *up;
1406 /* In case runtime-pm tries this before we are setup */
1410 up = serial8250_get_port(priv->line);
1412 if (omap8250_lost_context(up))
1413 omap8250_restore_regs(up);
1415 if (up->dma && up->dma->rxchan)
1416 omap_8250_rx_dma(up);
1418 priv->latency = priv->calc_latency;
1419 schedule_work(&priv->qos_work);
1424 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1425 static int __init omap8250_console_fixup(void)
1431 if (strstr(boot_command_line, "console=ttyS"))
1432 /* user set a ttyS based name for the console */
1435 omap_str = strstr(boot_command_line, "console=ttyO");
1437 /* user did not set ttyO based console, so we don't care */
1441 if ('0' <= *omap_str && *omap_str <= '9')
1442 idx = *omap_str - '0';
1447 if (omap_str[0] == ',') {
1454 add_preferred_console("ttyS", idx, options);
1455 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1457 pr_err("This ensures that you still see kernel messages. Please\n");
1458 pr_err("update your kernel commandline.\n");
1461 console_initcall(omap8250_console_fixup);
1464 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1465 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1466 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1467 omap8250_runtime_resume, NULL)
1468 .prepare = omap8250_prepare,
1469 .complete = omap8250_complete,
1472 static struct platform_driver omap8250_platform_driver = {
1475 .pm = &omap8250_dev_pm_ops,
1476 .of_match_table = omap8250_dt_ids,
1478 .probe = omap8250_probe,
1479 .remove = omap8250_remove,
1481 module_platform_driver(omap8250_platform_driver);
1483 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1484 MODULE_DESCRIPTION("OMAP 8250 Driver");
1485 MODULE_LICENSE("GPL v2");